A high-precision digital-to-analog converter

Abstract

The present invention belongs to the technical field of digital-to-analog converters, and specifically relates to a high-precision digital-to-analog converter. The present invention includes a DAC main body, a DAC weight error sampling, holding, and comparison module, a calibration logic controller, an error successive approximation logic controller, a weight error calculator, a weight error register, a first mode switching switch and a second mode switching switch, and a weight error accumulator. The calibration logic controller has a built-in timing logic for controlling the DAC weight error calibration. When the input error correction instruction is high, the DAC main body, the DAC weight error sampling, holding, and comparison module, the error successive approximation logic controller, the weight error calculator, and the weight error register are controlled to work in coordination according to a set process, and the auxiliary DAC is used to compensate for the nonlinear error of the main DAC. The automatic nonlinear correction function integrated in the present invention can be automatically completed by the host initiating a correction enable command.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital-to-analog converters, and in particular relates to a high-precision digital-to-analog converter. Background Art

[0002] A digital-to-analog converter (DAC) converts digital signals into analog output signals. Based on their implementation principles, they can be categorized as resistive DACs and current DACs. Resistive DACs are further categorized as R-String DACs, R-2R DACs, and Segmented R-2R DACs. DACs in integrated circuits mostly use polycrystalline resistors. If the resistors are large enough and the layout is carefully planned, a polycrystalline resistor DAC can achieve 12-bit accuracy. However, due to process tolerances and the effects of resistor bias, achieving better than 14-bit accuracy is difficult simply by optimizing the structure and layout of a resistive DAC. To further improve the accuracy of a resistive DAC, nonlinear calibration techniques are required. Summary of the Invention

[0003] To solve the above problems, the present invention proposes a high-precision DAC which integrates a nonlinear automatic correction algorithm and adopts a master-slave DAC architecture. The master DAC is the main body of the DAC and the slave DAC is used to correct the nonlinearity of the master DAC.

[0004] The technical solution of the present invention is:

[0005] A high-precision digital-to-analog converter comprises a DAC body, a DAC weight error sampling, holding and comparison module, a calibration logic controller, an error successive approximation logic controller, a weight error calculator, a weight error register, a first mode switch and a second mode switch, and a weight error accumulator; the first mode switch and the second mode switch are two-to-one selectors, and the enable signals are both error correction instructions, wherein the 0 input terminal of the first mode switch is connected to external input data, the 1 input terminal of the first mode switch is connected to the output of the calibration logic controller, the output of the first mode switch is connected to one input terminal of the DAC body, and the input of the calibration logic controller is connected to the error correction instruction; the other input terminal of the DAC body is connected to the second mode switch. The output of the switching switch is connected, the 0 input terminal of the second mode switching switch is connected to the output of the weight error accumulator, and the 1 input of the second mode switching switch is connected to the output of the error successive approximation logic controller; the input of the weight error accumulator is the output of the weight error register and external input data, the input of the weight error register is the output of the calibration logic controller and the output of the weight error calculator, the input of the weight error calculator is the output of the calibration logic controller and the output of the error successive approximation logic controller, the input of the error successive approximation logic controller is the output of the calibration logic controller and the output of the DAC weight error sampling, holding and comparison module, the input of the DAC weight error sampling, holding and comparison module is the output of the DAC body, and the DAC body outputs the digital-to-analog conversion result;

[0006] The DAC body includes a main DAC, an auxiliary DAC, and an attenuator, wherein the input of the main DAC is connected to the output of the first mode switch, the input of the auxiliary DAC is connected to the output of the second mode switch, and the output of the auxiliary DAC is superimposed with the output of the main DAC after passing through the attenuator to obtain a digital-to-analog conversion result; when the error correction instruction is pulled high, the code value selection of the main DAC is provided by the calibration logic controller, and the code value of the auxiliary DAC is provided by the error successive approximation logic controller; when the error correction instruction is pulled low, the code value of the main DAC is provided by external input data, and the code value of the auxiliary DAC is provided by the weighted error accumulator; wherein the auxiliary DAC is used to compensate for the nonlinear error of the main DAC;

[0007] The DAC weight error sampling, holding and comparison module includes a two-to-one multiplexing switch, a weight difference holder and a weight error comparator, wherein the enable signal of the two-to-one multiplexing switch is the output of the calibration logic controller, the fixed end of the two-to-one multiplexing switch is connected to the output of the DAC body, the first active end of the two-to-one multiplexing switch is connected to the positive input end of the weight error comparator through the weight difference holder, the second active end of the two-to-one multiplexing switch is connected to the negative input end of the weight error comparator, and the output end of the weight error comparator is the output end of the DAC weight error sampling, holding and comparison module.

[0008] Furthermore, the calibration logic controller has a built-in timing logic for controlling the DAC weight error calibration. When the input error correction instruction is high, the DAC main body, DAC weight error sampling and holding and comparison module, error successive approximation logic controller, weight error calculator, and weight error register are controlled to work together according to the set process to obtain the weight and mutual exclusion weight difference of each bit of the main DAC, and calculate the weight error of the main DAC through the weight error calculator, and then store the weight error in the weight error register; the definition of the weight and mutual exclusion weight is that for the i-th bit of the main DAC, its weight refers to the output Vm(i) of the DAC with the i-th bit set to 1, and the mutual exclusion weight refers to the output Vmr(i) of the DAC with all low bits less than i set to 1.

[0009] Furthermore, the timing logic of the DAC weight error calibration is used to store the difference between the weight of the main DAC and the mutually exclusive weight, and cooperate with the error successive approximation logic controller and the auxiliary DAC to complete the search and storage of the difference. The specific implementation method is: for the i-th bit of the main DAC, first sample and hold the weight error of the i-th bit, the calibration logic controller connects the two-to-one multiplexing switch to the first active end, and controls the i-th bit of the main DAC to be set to 1, the weight difference holder stores the weight output voltage value Vm(i) of the main DAC, and then the calibration logic controller sets the 0th to i-1th bits of the main DAC to 1, the weight difference holder then stores the mutually exclusive weight output voltage value Vmr(i) output by the main DAC, and the weight difference holder stores the difference Vm(i)-Vmr(i) of the two samples to a storage medium or register; the weight error search process is that the calibration logic controller connects the two-to-one multiplexing switch to the second active end, the error successive approximation logic controller, the auxiliary DAC, and the weight error comparator constitute a SAR ADC, and converts Vm(i)-Vmr(i) into digital code value ΔVm(i) through binary search algorithm and stores it in the register.

[0010] Furthermore, the weight error calculator calculates the weight error in such a way that the weight error Weight_err(i) of the i-th bit is:

[0011]

[0012] Among them, N M is the bit width of the main DAC.

[0013] The beneficial effects of the present invention are as follows: the automatic nonlinear correction function integrated in the present invention can be automatically completed by simply initiating a correction enable command by the host. It can be performed not only in the CP and FT test stages, but also in the UT, ST, and any stage of the product life cycle. It can eliminate to the greatest extent the impact of engineering problems such as packaging stress, single board stress, and chip aging on the DAC. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is the main structure of the DAC of the present invention.

[0015] Figure 2 This is the structure of the DAC body in the embodiment.

[0016] Figure 3 4 is the structure of the DAC weight error sampling, holding and comparison module in the embodiment.

[0017] Figure 4 This is the structure of the preamplifier in the embodiment.

[0018] Figure 5 This is a flow chart of the SAR logic searching for the difference between a certain 1-bit weight of the main DAC and the mutually exclusive weight in the embodiment.

[0019] Figure 6 This is a complete flowchart for searching all bit weight differences of the main DAC in the embodiment.

[0020] Figure 7 This is a schematic diagram of the performance comparison and verification before and after DAC nonlinear error calibration. DETAILED DESCRIPTION

[0021] The technical solution of the present invention is further described in detail below with reference to the accompanying drawings and embodiments:

[0022] like Figure 1 As shown in the figure, 100 represents the entire DAC solution, which includes: DAC body 200, DAC weight error sampling, holding and comparison module 300, correction logic 106, error successive approximation (SAR) logic 103, weight error calculator 104, weight error register 105, mode switching switches 101 and 102, and weight error accumulator 107.

[0023] Figure 1The DAC main body 200 in the embodiment includes: a main DAC 201, an auxiliary DAC 202, a scale factor 203, and an adder 204. A feature of the DAC main body 200 is that the auxiliary DAC is used to compensate for the nonlinear errors of the main DAC. The auxiliary DAC's accuracy is designed to be significantly lower than that of the main DAC, and the auxiliary DAC's output undergoes a K-fold scale factor 203 before being superimposed 204 with the main DAC's output to form a final, high-precision, effective output. The scale factor K must be designed to balance the auxiliary DAC's calibration range and equivalent output accuracy. The range must ensure that it can cover the total nonlinear errors of the main DAC. The auxiliary DAC's equivalent output accuracy is defined as the product of the auxiliary DAC's resolution and the scale factor K, ensuring that the equivalent output accuracy is at least twice that of the main DAC. Another feature of the DAC main body 200 is that the main DAC can be either a resistive or current-type DAC, and the auxiliary DAC can be either a resistive or current-type DAC.

[0024] Figure 1 The DAC weight error sampling, holding and comparison module 300 includes: a two-choice multiplexing switch 303, a weight difference holder 301, and a weight error comparator 302. The module 300 acts as an actuator in calibrating the main DAC weight error. Its main function is to store the difference between the main DAC weight and the mutually exclusive weight, and to cooperate with the SAR LOGIC and the auxiliary DAC to complete the search and storage of the difference. Taking the process of searching the weight error of the i-th bit of the main DAC as an example, the first step is to sample and hold the weight error of the i-th bit. The calibration logic controller 106 first connects the MUX switch 301 to the A path and controls the i-th bit of the main DAC to be set to 1. The weight difference holder 301 stores the weight output voltage value V of the main DAC. m (i) Then the calibration logic controller sets bits 0 to i-1 of the main DAC to 1, and the weight difference holder 301 stores the mutually exclusive weighted output voltage value V output by the main DAC. mr (i) The weight difference holder 301 stores the difference V between the two samples. m (i)-V mr (i) Store in a storage medium or register; The second step is weight error search, the calibration logic controller 106 connects the MUX switch 301 to the B path, the SAR logic 103, the auxiliary DAC 202, and the comparator 302 form a SAR ADC, and uses the binary search algorithm to find W m (i)-W mr (i) Convert to digital code value ΔV m (i) and store it in the register. If the bit width of the main DAC is N M bits, the above search process must be repeated at most N times Mtimes, until the difference search of all bits of the main DAC is traversed. Module 300 can be implemented in the analog domain or in the digital domain; if implemented in the analog domain, the MUX switch 303 is an analog transmission switch, the weight difference holder 301 can be implemented by a capacitor, and the comparator 302 is an analog comparator; if implemented in the digital domain, an ADC will be added to the front stage of the MUX to digitize the weight error, the sampling and holding module 301 is a digital register, and the comparator 302 is also a digital comparator. The definition of weight and mutually exclusive weight is: for the i-th bit of the main DAC, its weight refers to the output V of the DAC with the i-th bit set to 1. m (i), mutually exclusive weight means that all low bits less than i are set to 1 DAC output V mr (i).

[0025] Figure 1 The nonlinear calibration logic controller 106 integrates the timing logic for controlling the DAC weight error calibration. As long as the host issues an error correction instruction (Cali_EN is pulled high), the correction logic 106 will control the collaborative work of modules such as DAC200, weight error sampling and holding and comparison module 300, successive approximation logic SAR logic 103 according to the designed process, search for the difference between the weight of each bit of the main DAC and the mutually exclusive weight, and then control the ASIC-based weight error calculator 104 to calculate the weight error of the main DAC and store it in the weight error register 105.

[0026] Figure 1 The SAR logic 103 integrates a binary search logic to search for the difference between the weight of each bit of the main DAC and the mutually exclusive weight, and sends the searched binary code to the weight error calculator 104. The working principle of the SAR logic is: Assuming that the auxiliary DAC bit width is N A -bits, taking the search for the difference between the weight of the i-th bit of the main DAC and the mutually exclusive weight as an example, the difference ΔV between the weight of the i-th bit of the main DAC and the mutually exclusive weight is stored in 301 m After (i), 303 switches to channel B, and the SAR logic starts searching from the highest bit of the auxiliary DAC. A Set the bit to 1 and then observe the output of the comparator; if the comparator outputs 1, then the Nth A bit remains at 1, and N A -1 bit is set to 1; if the comparator outputs 0, the Nth A bit is set to 0, and N A -1 bit is set to 1; then observe the comparator output to determine the Nth A -1bit status and N A-2 bit is set to 1, and the above process is repeated until all bits of the auxiliary DAC are traversed and the N bits obtained are searched. A The bits code value is the difference ΔW between the main DAC weight and the mutual exclusion weight obtained by the auxiliary DAC search. m (i).

[0027] Figure 1 The weight error calculator 104 calculates the difference ΔW between the main DAC weight and the mutual exclusion weight. m (i) sequence (1≤i≤N M ), calculate the weight error Weight_err(i) of each bit of the main DAC according to the core algorithm of AISC. The calculation algorithm of the weight error Weight_err(i) of the i-th bit is:

[0028]

[0029] This formula can be used to calculate the weight error of each bit of the main DAC. The algorithm can be integrated into the AISC or embedded in the MCU code.

[0030] Figure 1 The weight error register is a bit width N A bits, depth N M The stack (FIFO) of bits sequentially stores the main DAC weight error Weight_err sequence calculated in step

[00010] .

[0031] Figure 1 The mode selection switches 101 and 102 are two-to-one digital multiplexers, 101 is N M bits MUX, 102 is N A When the calibration enable Cali_EN is pulled high, the code value selection of the main DAC is given by the calibration logic controller, and the code value of the auxiliary DAC is provided by the SAR logic module; when Cali_EN is pulled low, the code value of the main DAC is provided by the host, and the code value of the auxiliary DAC is provided by the weight error accumulator 107.

[0032] The function of the weighted error accumulator 107 is to calculate the given main DAC code value DATA_IN <N M :1>, the total error code value C that the main DAC needs to compensate A and sends the code value to the data bit DA of the auxiliary DAC <N A :1>, the auxiliary DAC converts the digital error compensation code value into analog value and adds it to the DAC output. When the main DAC input code value is DATA_IN <N M :1>, the total error code value C that needs to be compensatedA The calculation formula of reference formula (2) is to convert DATA_IN <N M :1> For code values of 1 in the sequence, the corresponding values of the weight error register are superimposed. The compensation code value CA is a binary code, and its bit width is the same as that of the auxiliary DAC, i.e. N A bit.

[0033]

[0034] In the formula Weight_err Represents the storage value of the register in the ith group of the FIFO index address. Under a given code value of the main DAC, the total DAC output expression after weight error compensation is shown in Equation (3), where k is the scale attenuation factor of the main DAC.

[0035]

[0036] Figure 1 The main body 200 of the DAC can be an R-DAC or a current mirror DAC, and the R-DAC can include an R-String, R-2R, or Segmented R-2R DAC.

[0037] Example

[0038] In this example, if Figure 2 As shown, the DAC is a Segmented R-2R DAC structure, and the DAC body includes: a main DAC 201, an auxiliary DAC 202, and a scale reduction resistor 203. The main DAC 201 is an N M bits Segmented R-2R DAC, its low L M bits is R-2R DAC, high N M -L M bits is the thermometer code R-DAC, if L M =N M , the main DAC degenerates into an R-2R DAC structure. According to the existing process performance, such as 180nm process, the Segmented R-2R DAC does not introduce a calibration algorithm, and can achieve 12-bit effective bits by optimizing the layout matching alone. To achieve higher precision, such as a 14-bit to 20-bit DAC, a nonlinear calibration algorithm must be introduced. This embodiment also introduces N A Auxiliary DAC 202 has two functions: first, to search for nonlinear errors in the main DAC during nonlinearity calibration; second, to add the compensation for the corresponding code value to the DAC output, VDAC, during normal main DAC transcoding to eliminate nonlinear errors. The auxiliary DAC can also be a segmented R-2RDAC, whose accuracy can be significantly lower than that of the main DAC, depending on the nonlinearity of the main DAC. Generally, if the main DAC has a 16-bit bit width, an auxiliary DAC with a bit width of approximately 9 bits will meet the requirement. The main function of the scaling resistor 203 is to attenuate the range of the auxiliary DAC to improve the equivalent output accuracy of the auxiliary DAC 202, ensuring that the equivalent output accuracy of the auxiliary DAC is higher than that of the main DAC. For example, if the auxiliary DAC has a 9-bit bit width and the scaling resistor 203 has an equivalent attenuation factor of 128, the equivalent output accuracy of the auxiliary DAC, VDAC, is approximately 17 bits. The design of the scale-down resistor 203 also needs to take the calibration range into consideration. The larger the resistance value, the higher the accuracy of the auxiliary DAC equivalent output, and the smaller the supported calibration range.

[0039] The DAC weight error sample-and-hold and comparison module 300 plays a key role in weight error search. It has two functions: first, it samples and holds the difference between the output of the main DAC corresponding to weight position 1 and the output of the mutually exclusive weight position 1; second, it forms a SAR ADC with the auxiliary DAC 202 and SAR logic 103 to quantize the difference in the difference sampler and hold. The DAC weight error sample-and-hold and comparison module 300 can be implemented using either analog or digital solutions.

[0040] In this example, the DAC weight error sampling, holding and comparison module 300 is implemented as follows: Figure 3 , which includes a sampling and holding capacitor 301, a sampling switch 303, a differential amplifier 304, and a latch comparator 302. When RST is set to 1, a certain 1-bit weight bit of the main DAC will be set to 1, and the sampling and holding capacitor C1 will sample the output voltage of the DAC; when RST is set to 0, a certain 1-bit mutually exclusive weight bit of the main DAC will be set to 1. At this time, the voltage difference on the right side of capacitor C1 is the difference between the 1-bit weight of the main DAC and the mutually exclusive weight. The difference is amplified by the amplifier 304 and then sent to the comparator 302 for comparison. Then, the SAR logic will control the auxiliary DAC to search for the weight difference cycle by cycle according to the output of the comparator 302, and store the difference converted bit code value in the register. For N M bit main DAC, the difference acquisition and search will be repeated at most N times M Secondly, in order to save calibration time, only some bits of the main DAC can be calibrated for weight difference, and some low-bit weights may not be calibrated.

[0041] In this example, the DAC weight error sampling, holding and comparison module 300 is implemented as follows: Figure 3 It includes an amplifier 304, an analog-to-digital converter 305, a digital difference register 301, and a digital comparator 302. The main function of the preamplifier 304 is to amplify the difference between the DAC output of the main DAC weight position 1 and the DAC output of the mutually exclusive weight position 1 to match the range of the down-converter ADC 305 and reduce the accuracy requirements of the ADC. The difference between the weight and the mutually exclusive weight is quantized by ADC 305 and stored in a register as the positive input of the digital comparator. Then, the SAR logic controls the auxiliary DAC code value cycle by cycle based on the output of comparator 302 and sends the voltage change of the DAC output to the negative input of the digital comparator. The SAR logic controls the auxiliary DAC based on the comparator output to search for and quantize the difference between the weight and the mutually exclusive weight.

[0042] Figure 3 The structure of the amplifier 304 is as follows: Figure 4 As shown in the figure, it is a switched capacitor amplifier with offset Auto-Zero function. During the high level period of CK1, the weight position of a certain bit of the main DAC is 1, the left plate of the sampling capacitor Cp1 samples the DAC output voltage V1, and the right plate samples the offset voltage of OTA1; during the low level period of CK1, the mutually exclusive weight position of a certain bit of the main DAC is 1, and the left plate of the sampling capacitor Cp1 samples the DAC output voltage V2. The amplifier output is the amplified difference, that is, G*(V2-V1).

[0043] In this example, the algorithm flow chart for the SAR logic control auxiliary DAC to search for the difference between a certain 1-bit weight of the main DAC and the mutually exclusive weight is shown in the figure. Figure 5 As shown, the search process is described with reference to the descriptions of 407A to 407I in the figure.

[0044] In this example, the complete flow chart for searching the difference between all bit weights of the main DAC is as follows: Figure 6 As shown, the entire weight calibration process of the main DAC refers to the description of 401 to 412 in the figure, and the weight error of each bit of the main DAC refers to formula (1). The calculation process is completed by the calculation unit solidified by AISC.

[0045] Since the resistance of the amplifier, comparator, and DAC in the calibration path will generate noise interference, which will seriously affect the accuracy of weight error calibration, in order to minimize the impact of noise, when calibrating the weight error of a certain 1-bit of the main DAC, Figure 6 Repeat steps 403 to 408 multiple times, and calculate the error code value ΔV obtained each time. m Perform arithmetic averaging and store the average value in a register.

[0046] According to the above implementation plan, a 16-bit DAC model was built to verify the effect of the calibration scheme, and the INL and DNL performance of the main DAC before and after calibration were verified using Matlab modeling. The verification results are as follows: Figure 7 . In the constructed model, the 16-bit is a Segmented R-2R structure, of which the lower 12 bits adopt the R-2R structure and the upper 4 bits adopt the thermometer code structure. In the constructed model, the auxiliary DAC adopts a 9-bit Segmented R-2R structure, of which the lower 6 bits adopt the R-2R structure and the upper 3 bits adopt the thermometer code structure. Referring to engineering experience, the random mismatch of the minimum resistance unit of the DAC during verification is 1sigma=0.4%, and the scale reduction resistor takes 40 minimum resistance units. Use matlab to model and perform a 100-point Monte Carlo simulation, and the results are as follows Figure 7 As shown in the figure, (a) shows the DAC performance before weight error calibration, with a maximum INL of 45LSB and a maximum DNL of 26LSB; (b) shows the DAC performance after weight error calibration, with a maximum INL of 1.1LSB and a maximum DNL of 0.7LSB. It can be seen that the calibration algorithm significantly improves DAC performance.

[0047] The above demonstrates the universality of this high-precision DAC solution and calibration algorithm, applying it to any resistive or current mirror DAC structure. However, the auxiliary DAC's bit width and scaling factor must be designed based on a compromise between the primary DAC's initial accuracy. Modeling verification demonstrates that DAC linearity is significantly improved after calibration.

Claims

1. A high-precision digital-to-analog converter, characterized in that: It includes a DAC body, a DAC weight error sampling, holding and comparison module, a calibration logic controller, an error successive approximation logic controller, a weight error calculator, a weight error register, a first mode switch and a second mode switch, and a weight error accumulator; the first mode switch and the second mode switch are two-to-one selectors, and the enable signals are both error correction instructions, wherein the 0 input terminal of the first mode switch is connected to the external input data, the 1 input terminal of the first mode switch is connected to the output of the calibration logic controller, the output of the first mode switch is connected to an input terminal of the DAC body, and the input of the calibration logic controller is connected to the error correction instruction; the other input terminal of the DAC body is connected to the output of the second mode switch, the 0 input terminal of the second mode switch is connected to the output of the weight error accumulator, and the 1 input of the second mode switch is connected to the output of the error successive approximation logic controller; The input of the weight error accumulator is the output of the weight error register and external input data, the input of the weight error register is the output of the calibration logic controller and the output of the weight error calculator, the input of the weight error calculator is the output of the calibration logic controller and the output of the error successive approximation logic controller, the input of the error successive approximation logic controller is the output of the calibration logic controller and the output of the DAC weight error sampling, holding and comparison module, the input of the DAC weight error sampling, holding and comparison module is the output of the DAC body, and the DAC body outputs the digital-to-analog conversion result; The DAC body includes a main DAC, an auxiliary DAC, and an attenuator, wherein the input of the main DAC is connected to the output of the first mode switch, the input of the auxiliary DAC is connected to the output of the second mode switch, and the output of the auxiliary DAC is superimposed with the output of the main DAC after passing through the attenuator to obtain a digital-to-analog conversion result; when the error correction instruction is pulled high, the code value selection of the main DAC is provided by the calibration logic controller, and the code value of the auxiliary DAC is provided by the error successive approximation logic controller; when the error correction instruction is pulled low, the code value of the main DAC is provided by external input data, and the code value of the auxiliary DAC is provided by the weighted error accumulator; wherein the auxiliary DAC is used to compensate for the nonlinear error of the main DAC; The DAC weight error sampling, holding and comparison module includes a two-to-one multiplexing switch, a weight difference holder and a weight error comparator, wherein the enable signal of the two-to-one multiplexing switch is the output of the calibration logic controller, the fixed end of the two-to-one multiplexing switch is connected to the output of the DAC body, the first active end of the two-to-one multiplexing switch is connected to the positive input end of the weight error comparator through the weight difference holder, the second active end of the two-to-one multiplexing switch is connected to the negative input end of the weight error comparator, and the output end of the weight error comparator is the output end of the DAC weight error sampling, holding and comparison module.

2. A high-precision digital-to-analog converter according to claim 1, characterized in that: The calibration logic controller has a built-in timing logic for controlling DAC weight error calibration. When the input error correction instruction is high, it controls the DAC main body, DAC weight error sampling and holding and comparison module, error successive approximation logic controller, weight error calculator, and weight error register to work together according to the set process to obtain the weight and mutual exclusion weight difference of each bit of the main DAC, and calculates the weight error of the main DAC through the weight error calculator, and then stores the weight error in the weight error register. The definition of the weight and mutual exclusion weight is that for the i-th bit of the main DAC, its weight refers to the output Vm(i) of the DAC when the i-th bit is set to 1, and the mutual exclusion weight refers to the output Vmr(i) of the DAC when all low-order bits less than i are set to 1.

3. A high-precision digital-to-analog converter according to claim 2, characterized in that: The timing logic of the DAC weight error calibration is used to store the difference between the weight and the mutually exclusive weight of the main DAC, and cooperate with the error successive approximation logic controller and the auxiliary DAC to complete the search and storage of the difference. The specific implementation method is: for the i-th bit of the main DAC, first sample and hold the weight error of the i-th bit, the calibration logic controller connects the two-to-one multiplexing switch to the first active end, and controls the i-th bit of the main DAC to be set to 1, the weight difference holder stores the weight output voltage value Vm(i) of the main DAC, and then the calibration logic controller sets the 0th to i-1th bits of the main DAC to 1, the weight difference holder then stores the mutually exclusive weight output voltage value Vmr(i) output by the main DAC, and the weight difference holder stores the difference Vm(i)-Vmr(i) of the two samples to a storage medium or register; the weight error search process is that the calibration logic controller connects the two-to-one multiplexing switch to the second active end, the error successive approximation logic controller, the auxiliary DAC, and the weight error comparator constitute a SAR ADC, and converts Vm(i)-Vmr(i) into digital code value ∆Vm(i) through binary search algorithm and stores it in register.

4. A high-precision digital-to-analog converter according to claim 3, characterized in that: The weight error calculator calculates the weight error in the following way: the weight error Weight_err(i) of the i-th bit is: ， Among them, N M is the bit width of the main DAC.

5. The high-precision digital-to-analog converter according to claim 3, wherein: The weight error register is a bit-width N A bits, depth N M The stack of bits stores the calculated main DAC weight error Weight_err sequence in sequence.

6. The high-precision digital-to-analog converter according to claim 1, characterized in that: The first mode switch has a bit width of N M Bits two-to-one digital multiplexer.

7. The high-precision digital-to-analog converter according to claim 1, characterized in that: The second mode switch has a bit width of N A A binary multiplexer for bits.

8. The high-precision digital-to-analog converter according to claim 4, characterized in that: The function of the weighted error accumulator is to define the given main DAC code value as DATA_IN <N M :1>, calculate the total error code value C that needs to be compensated for the main DAC A and sends the code value to the data bit DA of the auxiliary DAC <N A :1>, the auxiliary DAC converts the digital error compensation code value into analog value and adds it to the DAC output; when the main DAC input code value is DATA_IN <N M :1>, the total error code value C that needs to be compensated A The calculation formula of reference formula (2) is to convert DATA_IN <N M :1> The code value of 1 in the sequence is superimposed with the value of the corresponding weight error register. The compensation code value CA is a binary code with the same bit width as the auxiliary DAC, that is, N A bit; ， Under the given code value of the main DAC, the total DAC output expression after weight error compensation is referred to formula (3): ， Where k is the scale attenuation factor of the main DAC.

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