A method of manufacturing a semiconductor structure

By etching bit lines and isolation barrier structures, memory node contact plugs are formed and gaps are sealed, solving the problems of poor contact structure morphology and difficulty in reducing parasitic capacitance, thereby improving the performance of semiconductor structures and simplifying the process.

CN116801618BActive Publication Date: 2026-07-24CHANGXIN MEMORY TECH INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
CHANGXIN MEMORY TECH INC
Filing Date
2023-06-25
Publication Date
2026-07-24

AI Technical Summary

Technical Problem

In semiconductor structures, as the manufacturing process shrinks, the size of the contact structure also shrinks. When forming the contact structure, it is easy to cause poor morphology, which affects product performance. At the same time, the existing air gap structure has a complex manufacturing process and it is difficult to effectively reduce parasitic capacitance.

Method used

By etching the bit line structure and isolation barrier, the upper surface of the bit line is lowered by a predetermined distance to form a storage node contact plug. A second dielectric layer is formed in the opening to seal the gap, simplifying the process steps, reducing the difficulty of filling the hole, avoiding holes and voids, and improving conductivity.

Benefits of technology

This effectively reduces the difficulty of forming storage node contact plugs, improves the quality and conductivity of contact plugs, simplifies the process steps, and reduces parasitic capacitance.

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Abstract

Disclosed is a method for manufacturing a semiconductor structure, comprising: providing an initial structure, the initial structure comprising a substrate, a plurality of bit line structures on the substrate, and a plurality of isolation fences, the bit line structures and the isolation fences crossing each other to define a plurality of openings, and a filling layer formed in the openings; etching the filling layer to lower an upper surface of the filling layer by a first preset distance, and remaining filling layer still filling a lower part of the openings; etching the bit line structures to lower at least part of an upper surface of the bit line structures by a second preset distance; removing the remaining filling layer; and forming a storage node contact plug in the openings.
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