A system for eliminating clock skew in synchronous control for redundant controller coordinated control

Abstract

This invention discloses a system for eliminating clock skew in the coordinated control of redundant controllers, belonging to the field of clock synchronization technology. It includes a master controller, a synchronization source module, and multiple slave controllers. The master controller communicates with the multiple slave controllers via a bidirectional transmission channel for signal exchange, enabling the master controller to control the multiple slave controllers through the bidirectional transmission channel. The synchronization source module communicates with the master controller and the multiple slave controllers, sending interrupt trigger signals or time acquisition signals. The synchronization source module periodically sends interrupt trigger signals or time acquisition signals to the master controller and slave controllers, allowing them to periodically calibrate their clocks at equal intervals. This resets the clock skew value, preventing its accumulation and keeping it within a reasonable range.

Description

Technical Field

[0001] This invention belongs to the field of clock synchronization technology, specifically relating to a system for eliminating clock deviations in the coordinated control of redundant controllers. Background Technology

[0002] With the development of network and control technologies, traditional factories are transforming into intelligent factories, and manufacturing workshops are gradually evolving into digital workshops. Similarly, industrial control systems are developing from instrument control, analog control, centralized computer control, distributed computer control, and fieldbus control to a new stage of networked control. Among various networked control technologies, the most rapidly developing and widely applied is the industrial Ethernet control system, based on Ethernet technology in the field of computer network communication. While industrial Ethernet control systems offer advantages such as high transmission rate, high reliability, real-time performance, scalability, and maintainability, they also face new challenges in the face of increasingly large data volumes, more diverse data sources, and more complex control tasks. These challenges include multi-controller task scheduling, real-time information interaction, and collaborative control operation. The first and most crucial step in solving these problems is achieving high-precision clock synchronization among multiple controllers within the network control system, ensuring that all controllers in the network operate on the same clock reference.

[0003] During controller development, to meet higher safety requirements, situations necessitate redundant controllers or require different controllers to operate synchronously, necessitating high-precision synchronous control. However, due to clock skew and hardware errors, slight deviations in the controller clocks can occur, leading to discrepancies during coordinated synchronous operation. These discrepancies accumulate over time and gradually increase. Summary of the Invention

[0004] To address the issue of discrepancies arising during the coordinated synchronous operation of multiple controllers, which accumulate over time and gradually increase, this invention aims to provide a system for eliminating synchronization control clock deviations in the coordinated control of redundant controllers, thereby resolving the aforementioned problems.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a system for eliminating synchronization control clock deviation in redundant controller coordinated control, comprising: a master controller, a synchronization source module, and multiple slave controllers;

[0006] The main controller communicates with multiple slave controllers through a bidirectional transmission channel for signal exchange between the main controller and the multiple slave controllers, enabling the main controller to control the multiple slave controllers through the bidirectional transmission channel.

[0007] The synchronization source module is connected and communicates with the main controller and multiple slave controllers to send interrupt trigger signals or time acquisition signals.

[0008] The main controller includes:

[0009] The host clock signal communicates with the main controller and is used to keep time for the main controller;

[0010] The master transceiver unit communicates with the master controller and is used by the master controller to send master clock AC signals to the slave controller and by the master controller to receive slave clock AC signals sent by the slave controller.

[0011] The slave controller includes:

[0012] The slave clock signal communicates with the slave controller and is used to keep time for the slave controller;

[0013] The slave transceiver unit communicates with the slave controller and is used to send slave clock AC signals to the master controller and to receive master clock AC signals sent by the master controller.

[0014] The main controller also includes:

[0015] The host clock calibration unit communicates with the host clock signal and the host transceiver unit to obtain the timing duration of the host clock signal and the timing duration of the slave clock signal recorded by the slave clock AC signal received by the host transceiver unit. It is used to compare and calibrate the timing duration of the host clock signal with the timing duration of the slave clock signal.

[0016] The clock deviation analysis unit communicates with the host clock calibration unit and is used to calculate the deviation value between the timing duration of the host clock signal and the timing duration of the slave clock signal. The clock deviation analysis unit also communicates with the host transceiver unit and is used to transmit the deviation value to the host transceiver unit, enabling the host transceiver unit to transmit the deviation value to the slave transceiver unit.

[0017] The slave controller also includes:

[0018] The slave clock calibration unit communicates with the slave transceiver unit to obtain the deviation value received by the slave transceiver unit. The slave clock calibration unit also communicates with the slave clock signal to calibrate the slave clock signal based on the deviation value.

[0019] The synchronization source module includes:

[0020] The clock acquisition unit communicates with the host transceiver unit and the slave transceiver unit to synchronize the source module to send interrupt trigger signals or time acquisition signals to the master controller and multiple slave controllers.

[0021] In a preferred embodiment, the slave controller further includes a slave on / off unit, which controls the on / off state of the slave controller. The slave controller communicates with the slave transceiver unit and controls the slave transceiver unit to receive the master clock AC signal and to send the slave clock received signal.

[0022] In a preferred embodiment, the synchronization source module further includes a period control unit that communicates with the clock acquisition unit and is able to periodically send pulse signals to the clock acquisition unit, enabling the clock acquisition unit to periodically send interrupt trigger signals and time acquisition signals to the host transceiver unit and the slave transceiver unit.

[0023] In a preferred embodiment, the synchronization source module further includes a period adjustment unit, which communicates with the period control unit and is used to adjust and control the frequency of the pulse signal sent by the period control unit to the clock acquisition unit.

[0024] As a preferred embodiment, the bidirectional transmission channel includes the following types: CAN bus, SPI bus, and I2C bus.

[0025] As a preferred embodiment, the method of using the system for eliminating synchronization control clock deviation in redundant controller coordinated control includes the following steps:

[0026] S1: The host clock signal keeps the main controller in time;

[0027] S2: The slave clock signal is used to keep time for the slave controller;

[0028] S3: Set the frequency of pulse signals sent by the period control unit to the missing acquisition unit through the period adjustment unit;

[0029] S4: The signal acquisition unit sends an interrupt trigger signal and a time acquisition signal to the host transceiver unit and the slave transceiver unit;

[0030] S5: After receiving the interrupt trigger signal and the time acquisition signal, the slave transceiver unit can obtain the timing duration of the slave through the slave clock signal and send it back to the master transceiver unit.

[0031] S6: The host clock calibration unit obtains the timing duration of the host through the host clock signal, and can obtain the timing duration of the slave through the host transceiver unit, and can compare and calibrate the timing duration of the host with the timing duration of the slave.

[0032] S7: The clock-side analysis unit analyzes and calculates the timing duration of the slave device and the timing duration of the master device, calculates the deviation value that the slave controller needs to calibrate, and sends the calculated deviation value to the slave transceiver module through the master transceiver module;

[0033] S8: The slave clock calibration unit can obtain the deviation value through the slave transceiver module and calibrate the slave clock signal according to the deviation value.

[0034] In a preferred embodiment, in the method of using the system for eliminating synchronous control clock deviation in the coordinated control of redundant controllers, before the signal acquisition unit sends the interrupt trigger signal and time acquisition signal to the master transceiver unit and the slave transceiver unit, the slave transceiver unit in the slave controller in the redundant state can be turned on or off by the slave on / off unit.

[0035] Compared with the prior art, the beneficial effects of the present invention are:

[0036] This is a system for eliminating clock deviation in the coordinated control of redundant controllers. The synchronization source module can periodically send interrupt trigger signals or time acquisition signals to the master controller and the slave controller, so that the master controller and the slave controller can periodically calibrate the clock at the same interval, reset the clock deviation value, avoid the accumulation of clock deviation value, and thus control the clock deviation value within a reasonable range.

[0037] This is a system for eliminating synchronous control clock deviation in the coordinated control of redundant controllers. It can control the on / off state of the slave controller through the slave on / off unit, and thus control the on / off state of the slave transceiver unit. It can selectively calibrate the clock deviation between the redundant slave controller and the master controller, avoid calibrating the slave controller when it is in an idle state, and reduce the operating pressure of the system.

[0038] This is a system for eliminating synchronous control clock deviation in the coordinated control of redundant controllers. It can set the time interval for the period control unit to send pulse signals through the period adjustment unit, thereby adjusting the time interval for the clock acquisition unit to send time acquisition signals, that is, adjusting the frequency of sending time acquisition signals per unit time, and thus setting the clock calibration period. Attached Figure Description

[0039] Figure 1 This is a hardware block diagram of a system for eliminating synchronous control clock deviation in the coordinated control of redundant controllers, as proposed in this invention.

[0040] Figure 2 This is a block diagram of the overall principle of a system software for eliminating synchronous control clock deviation in the coordinated control of redundant controllers proposed in this invention.

[0041] Figure 3 This is a flowchart illustrating a method for eliminating synchronization control clock deviation in redundant controller coordinated control, as proposed in this invention. Detailed Implementation

[0042] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0043] For examples, please refer to Figure 1-2 The present invention provides a system for eliminating synchronization control clock deviation in redundant controller coordinated control, comprising: a master controller, a synchronization source module and multiple slave controllers, wherein the synchronization source module is independent of the master controller and the multiple slave controllers;

[0044] The master controller communicates with multiple slave controllers through a bidirectional transmission channel for signal exchange between the master controller and the multiple slave controllers, enabling the master controller to control multiple slave controllers through the bidirectional transmission channel.

[0045] The types of bidirectional transmission channels include: CAN bus, SPI bus, and I2C bus. CAN bus has low cost, high utilization, reliable error handling and detection mechanisms, and can automatically retransmit corrupted information. Nodes can automatically exit the bus in case of severe errors. SPI bus can simultaneously send and receive serial data. The main advantages of I2C bus are its simplicity and efficiency. Because the interface is directly on the component, I2C bus occupies very little space, reducing board space and the number of chip pins, thus lowering interconnection costs. In practical applications, different bidirectional transmission channel types can be selected according to different usage requirements.

[0046] The synchronization source module connects and communicates with the master controller and multiple slave controllers to send interrupt trigger signals or time acquisition signals;

[0047] The main controller includes:

[0048] The host clock signal communicates with the main controller and is used to keep time for the main controller;

[0049] The master transceiver unit communicates with the master controller and is used by the master controller to send master clock AC signals to the slave controller and by the master controller to receive slave clock AC signals sent by the slave controller.

[0050] From the controller, including:

[0051] The slave clock signal communicates with the slave controller and is used to keep time for the slave controller;

[0052] The slave transceiver unit communicates with the slave controller and is used to send slave clock AC signals to the master controller and to receive master clock AC signals sent by the master controller. The master clock AC signal includes the timing duration of the master clock signal, and the slave clock AC signal includes the timing duration of the slave clock signal.

[0053] The main controller also includes:

[0054] The host clock calibration unit communicates with the host clock signal and the host transceiver unit. It is used to acquire the timing duration of the host clock signal and the timing duration of the slave clock signal recorded by the slave clock AC signal received by the host transceiver unit. It is used to compare and calibrate the timing duration of the host clock signal with the timing duration of the slave clock signal. The operations of acquiring the timing duration of the host clock signal and acquiring the timing duration of the slave clock signal are synchronized. By collecting the timing duration of the same time period, it is possible to accurately compare and analyze the clock deviation.

[0055] The clock deviation analysis unit communicates with the host clock calibration unit to calculate the deviation between the timing duration of the host clock signal and the timing duration of the slave clock signal. The clock deviation analysis unit also communicates with the host transceiver unit to transmit the deviation value to the host transceiver unit, enabling the host transceiver unit to transmit the deviation value to the slave transceiver unit.

[0056] The controller also includes:

[0057] The slave clock calibration unit communicates with the slave transceiver unit to obtain the deviation value received by the slave transceiver unit. The slave clock calibration unit also communicates with the slave clock signal to calibrate the slave clock signal according to the deviation value, so that the deviation between the calibrated slave clock signal and the master clock signal can be reset.

[0058] The synchronization source module includes:

[0059] The clock acquisition unit communicates with the host transceiver unit and the slave transceiver unit. It is used to synchronize the source module to send interrupt trigger signals or time acquisition signals to the master controller and multiple slave controllers. This ensures that the operation of the synchronization source module to send interrupt trigger signals or time acquisition signals to the master controller and multiple slave controllers is simultaneous and synchronized. It can guarantee that the master controller and multiple slave controllers can receive the time acquisition signal at the same time, which facilitates the accurate acquisition of timing duration and improves the accuracy of calibration.

[0060] In this embodiment, the slave controller also includes a slave on / off unit, which is used to control the on / off state of the slave controller. The slave controller communicates with the slave transceiver unit and is used to control the slave transceiver unit to receive the master clock AC signal and to control the slave transceiver unit to send the slave clock received signal. The on / off unit can selectively shut down redundant slave controllers. There may be slave controllers that are not used for a long time. Shutting them down will prevent the slave controllers from receiving the time acquisition signal, thus avoiding the need to calibrate slave controllers that have been idle for a long time and reducing the workload of the system. If it is necessary to calibrate idle slave controllers, the slave controllers can be turned on by the slave on / off unit before the clock acquisition unit sends the time acquisition signal, so that the slave transceiver unit can receive the time acquisition signal, thereby facilitating the calibration of redundant slave controllers.

[0061] In this embodiment, the synchronization source module also includes a period control unit, which communicates with the clock acquisition unit and can periodically send pulse signals to the clock acquisition unit, so that the clock acquisition unit can periodically send interrupt trigger signals and time acquisition signals to the host transceiver unit and the slave transceiver unit, thereby enabling periodic calibration.

[0062] The synchronization source module also includes a period adjustment unit, which communicates with the period control unit and is used to adjust and control the frequency of the pulse signal sent by the period control unit to the clock acquisition unit. It can adjust the frequency of the pulse signal sent by the period control unit within a unit time according to the required interval, thereby controlling the time interval between two adjacent time acquisition signals.

[0063] In this embodiment, please refer to Figure 3 A method for using a system to eliminate synchronization control clock skew in redundant controller coordinated control includes the following steps:

[0064] S1: The host clock signal keeps the main controller in time;

[0065] S2: The slave clock signal is used to keep time for the slave controller;

[0066] S3: Set the frequency of pulse signals sent by the period control unit to the missing acquisition unit through the period adjustment unit;

[0067] S4: The signal acquisition unit sends an interrupt trigger signal and a time acquisition signal to the host transceiver unit and the slave transceiver unit;

[0068] S5: After receiving the interrupt trigger signal and the time acquisition signal, the slave transceiver unit can obtain the timing duration of the slave through the slave clock signal and send it back to the master transceiver unit.

[0069] S6: The host clock calibration unit obtains the timing duration of the host through the host clock signal, and can obtain the timing duration of the slave through the host transceiver unit, and can compare and calibrate the timing duration of the host with the timing duration of the slave.

[0070] S7: The clock-side analysis unit analyzes and calculates the timing duration of the slave device and the timing duration of the master device, calculates the deviation value that the slave controller needs to calibrate, and sends the calculated deviation value to the slave transceiver module through the master transceiver module;

[0071] S8: The slave clock calibration unit can obtain the deviation value through the slave transceiver module and calibrate the slave clock signal according to the deviation value;

[0072] In one method of using a system for eliminating synchronous control clock deviation in the coordinated control of redundant controllers, before the signal acquisition unit sends the interrupt trigger signal and time acquisition signal to the host transceiver unit and the slave transceiver unit, the slave transceiver unit in the redundant state can be turned on or off by the slave on / off unit, and it is possible to select whether to perform clock calibration on some slave controllers.

[0073] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A system for eliminating synchronization control clock bias in redundant controller coordinated control, characterized by, The application relates to a synchronization system, which comprises a master controller, a synchronization source module and a plurality of slave controllers. The master controller communicates with the plurality of slave controllers through a bidirectional transmission channel, and signals are exchanged between the master controller and the plurality of slave controllers, so that the master controller can control the plurality of slave controllers through the bidirectional transmission channel. The synchronization source module communicates with the master controller and the plurality of slave controllers, and is used for sending an interrupt trigger signal or a time acquisition signal. The master controller comprises a master clock signal, which communicates with the master controller and is used for timing the master controller. The master controller further comprises a master clock calibration unit, which communicates with the master clock signal and the master transceiver unit, is used for acquiring the timing duration of the master clock signal, and is used for acquiring the timing duration of the slave clock signal recorded by the slave clock exchange signal received by the master transceiver unit, and is used for comparing and calibrating the timing duration of the master clock signal and the timing duration of the slave clock signal. The master controller further comprises a clock deviation analysis unit, which communicates with the master clock calibration unit, is used for calculating the deviation value between the timing duration of the master clock signal and the timing duration of the slave clock signal, and communicates with the master transceiver unit, so that the master transceiver unit can transmit the deviation value to the slave transceiver unit. The slave controller further comprises a slave clock calibration unit, which communicates with the slave transceiver unit, is used for acquiring the deviation value received by the slave transceiver unit, and communicates with the slave clock signal, so as to calibrate the slave clock signal according to the deviation value. The synchronization source module comprises a clock acquisition unit, which communicates with the master transceiver unit and the slave transceiver unit, and is used for synchronously sending the interrupt trigger signal or the time acquisition signal to the master controller and the plurality of slave controllers. The slave controller further comprises a slave start-stop unit, which is used for controlling the start-stop state of the slave controller, and communicates with the slave transceiver unit, so as to control the slave transceiver unit to receive the master clock exchange signal and to send the slave clock receiving signal. The synchronization source module further comprises a period control unit, which communicates with the clock acquisition unit, can periodically send a pulse signal to the clock acquisition unit, and enables the clock acquisition unit to periodically send the interrupt trigger signal and the time acquisition signal to the master transceiver unit and the slave transceiver unit. The synchronization source module further comprises a period adjustment unit, which communicates with the period control unit, and is used for adjusting and controlling the frequency of the pulse signal sent by the period control unit to the clock acquisition unit. ​ ​ ​ ​ ​ ​ 2. The system for eliminating clock bias in synchronization control in redundant controller coordinated control according to claim 1, wherein, ​ 3. The system for eliminating clock bias in synchronization control for redundant controller coordinated control according to claim 1, wherein, ​ 4. The system for eliminating clock bias in synchronization control for redundant controller coordinated control according to claim 3, wherein, ​ 5. The system for eliminating clock bias in synchronization control for redundant controller coordinated control according to claim 1, wherein, The type of the bidirectional transmission channel includes: a can bus, an spi bus and an i2c bus.

6. The system for eliminating clock deviation in synchronization control in the coordinated control of redundant controllers according to any one of claims 1-5, characterized in that, The use method of the synchronization control clock deviation elimination system for the redundant controller coordinated control includes the following steps: S1: the host clock signal is used to time the main controller; S2: the slave clock signal is used to time the slave controller; S3: the cycle adjustment unit is used to set the frequency of the pulse signal sent by the cycle control unit to the missing acquisition unit; S4: the signal acquisition unit is used to send the interrupt trigger signal and the time acquisition signal to the host transceiver unit and the slave transceiver unit; S5: after the slave transceiver unit receives the interrupt trigger signal and the time acquisition signal, the timing duration of the slave controller can be obtained through the slave clock signal, and the feedback is sent to the host transceiver unit; S6: the host clock calibration unit obtains the timing duration of the host through the host clock signal, and can obtain the timing duration of the slave controller received through the host transceiver unit, and can compare and calibrate the timing duration of the host and the timing duration of the slave controller; S7: the clock edge side analysis unit analyzes and calculates the timing duration of the slave controller and the timing duration of the host, calculates the deviation value of the slave controller to be calibrated, and sends the calculated deviation value to the slave transceiver module through the host transceiver module; S8: the slave clock calibration unit can obtain the deviation value through the slave transceiver module, and calibrate the slave clock signal according to the deviation value.

7. The system for eliminating clock bias in synchronization control for redundant controller coordinated control according to claim 6, wherein, In the use method of the synchronization control clock deviation elimination system for the redundant controller coordinated control, before the signal acquisition unit sends the interrupt trigger signal and the time acquisition signal to the host transceiver unit and the slave transceiver unit, the slave transceiver unit in the slave controller in the redundant state can be started or stopped through the slave start-stop unit.

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