Inter-board heart beat monitoring method and system

Abstract

The application relates to an inter-board heartbeat monitoring method and system, which comprises the following steps: determining the access state of a sub-board on a main board; based on the determined access state, performing heartbeat count verification on each sub-board once per heartbeat monitoring period for all accessed sub-boards; wherein the heartbeat count verification comprises: sending main board information for requesting sub-board feedback of sub-board information to the accessed sub-board, wherein the sub-board information comprises sub-board heartbeat count; in the case of receiving the sub-board information, judging whether the sub-board heartbeat count falls between a minimum critical heartbeat count and a maximum critical heartbeat count; in the case of not falling therebetween, increasing the verification error count and judging whether the verification error count is greater than a fault tolerance threshold; and in the case of the verification error count being greater than the fault tolerance threshold, determining that the sub-board is abnormally running. The heartbeat monitoring of the main board on the sub-board is realized through inter-board communication, which is convenient to implement and low in cost, and has universality.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more specifically, to a method and system for monitoring inter-board heartbeats. Background Technology

[0002] With the rapid development of the four modernizations of automobiles (electrification, connectivity, intelligence, and sharing), and the increasing complexity of vehicle electronics, traditional distributed architectures can no longer meet the growing computing demands. Their lengthy wiring harnesses are also a major drawback. Therefore, the concept of centralization is gradually gaining traction in the automotive field. The development of vehicle electronic and electrical architectures is generally divided into three categories: modular and integrated architecture solutions (distributed), centralized domain fusion architecture solutions, and onboard computer cloud computing architecture solutions. Furthermore, with the rapid development of autonomous driving, the computing power requirements of vehicle electronic and electrical architectures for controllers are gradually increasing. Simultaneously, to support functions such as lane departure warning and traffic recognition, forward collision warning, electronic control units (ECUs) for parking assistance, and human-machine interaction, vehicle electronic and electrical architectures require more powerful processing cores to run more complex operating systems. In contrast, single-type microprocessors, whether central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), or application-specific integrated circuits (ASICs), cannot meet the higher-level autonomous driving requirements. Therefore, the main control chip in the domain controller is moving towards a heterogeneous architecture integrating "CPU + xPU," thereby better supporting the hardware acceleration needs of various scenarios. Summary of the Invention

[0003] The embodiments of this application provide a method and system for monitoring heartbeat between boards, which can realize the heartbeat monitoring of the motherboard to the daughterboard through inter-board communication. It is easy to implement, low in cost, and universally applicable.

[0004] According to one aspect of this application, an inter-board heartbeat monitoring method is provided, the method comprising: determining the access status of a daughterboard on a motherboard; based on the determined access status, performing a heartbeat count verification once per heartbeat monitoring cycle for all daughterboards connected to the motherboard; wherein the heartbeat count verification comprises: sending motherboard information to the daughterboard connected to the motherboard, wherein the motherboard information includes a request command for requesting feedback of daughterboard information, the daughterboard information including a daughterboard heartbeat count; upon receiving the daughterboard information fed back by the daughterboard, determining whether the daughterboard heartbeat count of the daughterboard information falls between a minimum critical heartbeat count and a maximum critical heartbeat count; if the daughterboard heartbeat count does not fall between the minimum critical heartbeat count and the maximum critical heartbeat count, incrementing the verification error count and determining whether the verification error count is greater than a fault tolerance threshold; and if the verification error count is greater than the fault tolerance threshold, determining that the daughterboard is malfunctioning.

[0005] In some embodiments of this application, optionally, the minimum critical heartbeat count and the maximum critical heartbeat count are determined based on heartbeat count check values.

[0006] In some embodiments of this application, optionally, if the subboard heartbeat count falls between the minimum critical heartbeat count and the maximum critical heartbeat count, the heartbeat count check value is updated using the subboard heartbeat count.

[0007] Optionally, in some embodiments of this application, if the number of verification errors is not greater than the fault tolerance threshold, it is determined whether the sub-board heartbeat count is less than the minimum critical heartbeat count or greater than the maximum critical heartbeat count; if the sub-board heartbeat count is less than the minimum critical heartbeat count, the heartbeat count verification value is updated with the minimum critical heartbeat count; and if the sub-board heartbeat count is greater than the maximum critical heartbeat count, the heartbeat count verification value is updated with the maximum critical heartbeat count.

[0008] In some embodiments of this application, optionally, the motherboard includes a daughterboard slot for connecting a daughterboard; determining the connection status of the daughterboard on the motherboard includes: performing a daughterboard connection determination once for each daughterboard slot in each status confirmation cycle for all daughterboard slots of the motherboard.

[0009] In some embodiments of this application, optionally, the daughterboard access determination includes: determining whether the voltage output of the daughterboard slot is normal; if the voltage output is normal, reading a voltage feedback signal for the daughterboard slot and determining whether the voltage feedback signal is normal; and if the voltage feedback signal is normal, determining that the daughterboard slot is connected to the daughterboard.

[0010] Optionally, in some embodiments of this application, the sub-board access determination further includes: when the voltage feedback signal is abnormal, incrementing the number of cycles for the sub-board slot and determining whether the number of cycles reaches a cycle threshold; when the number of cycles does not reach the cycle threshold, further reading the voltage feedback signal and determining whether the voltage feedback signal is normal; and when the number of cycles reaches the cycle threshold, determining that the sub-board slot is not connected to the sub-board.

[0011] According to another aspect of this application, an inter-board heartbeat monitoring system is provided, the inter-board heartbeat monitoring system comprising: a memory configured to store instructions; and a processor configured to execute the instructions such that the inter-board heartbeat monitoring system performs any of the inter-board heartbeat monitoring methods described above.

[0012] According to another aspect of this application, a vehicle is provided, the vehicle including any of the inter-panel heart rate monitoring systems described above.

[0013] According to yet another aspect of this application, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed by a processor, cause the processor to perform any of the inter-board heartbeat monitoring methods described above.

[0014] The inter-board heartbeat monitoring method and system of this application can be dynamically managed according to the actual access status of the sub-boards, realizing the plug-and-play function of each sub-board. In some embodiments, the inter-board heartbeat monitoring method and system of this application adopt a self-learning mechanism, which can automatically obtain the access status of the sub-boards without manual calibration, reducing manual work. Attached Figure Description

[0015] The above and other objects and advantages of this application will become more fully clear from the following detailed description taken in conjunction with the accompanying drawings, wherein the same or similar elements are denoted by the same reference numerals.

[0016] Figure 1 An inter-board communication architecture according to an embodiment of this application is shown;

[0017] Figures 2 to 3 An embodiment of the inter-plate heartbeat monitoring method according to this application is shown;

[0018] Figure 4 An inter-board heartbeat monitoring system according to an embodiment of this application is shown. Detailed Implementation

[0019] For purposes of brevity and illustrative purposes, the principles of this application are described herein primarily with reference to exemplary embodiments thereof. However, those skilled in the art will readily recognize that the same principles are equivalently applicable to all types of inter-plate heartbeat monitoring methods and systems, and that these same or similar principles can be implemented therein, without departing from the true spirit and scope of this application.

[0020] The following will combine Figure 1 The following describes the configuration of the motherboard 110 and daughterboard 120 in one embodiment of this application.

[0021] In some embodiments, the motherboard 110 and daughterboards 120 can be used in a vehicle's central computing platform (CCP). The motherboard 110 may include multiple daughterboard slots, allowing multiple daughterboards 120 to be deployed on the motherboard 110 by connecting to corresponding daughterboard slots. Connecting daughterboards 120 to the motherboard 110 increases its computing power. Based on functional division, the multiple daughterboards 120 connected to the motherboard 110 can respectively provide computing power to the motherboard 110 in multiple functions such as intelligent driving, intelligent vehicle control, and intelligent cockpit, as a supplement to the motherboard 110's computing power. By supplementing the motherboard 110's computing power through daughterboards 120, for example, the high computing power requirements of the CCP in autonomous driving scenarios for rapid processing of real-time information such as road conditions and weather (e.g., unified real-time analysis, massive data processing, and complex logical operations) can be met. In some embodiments, to facilitate the implementation of their respective functions by each daughterboard 120, sensors such as cameras and radars can be directly connected to their respective daughterboards 120.

[0022] In some embodiments, high-speed network data transmission can be achieved between the various sub-boards 120 and between the main board 110 and the various sub-boards 120 through a ring network formed by a distributed gateway. Based on the real-time data analysis and processing capabilities of the individual sub-board chips, and through communication between the various sub-boards 120 and between the main board 110 and the sub-boards 120, the CCP can achieve the sharing of vehicle perception, computing power, and power supply. However, if one of the multiple sub-boards 120 fails without the main board system's knowledge, it may cause related functional abnormalities in the main board system.

[0023] This application provides a method for monitoring heart rate between plates 200 (see [link]). Figure 2 and Figure 3 ) and System 400 (see Figure 4 This system enables rapid location and response to the failure of the daughterboard 120, and can provide failure information to upper-layer services for optimizing computing power allocation. In some embodiments, the inter-board heartbeat monitoring method 200 can be executed by the motherboard 110 to dynamically manage the entire motherboard system, including the daughterboard 120, and to meet functional safety requirements. For example, the motherboard 110 can monitor the power supply and status of the daughterboard 120. Furthermore, the motherboard 110 can force the daughterboard 120 to perform a hardware reset to manage the power supply status of each daughterboard 120; for example, the daughterboard 120 can be restarted by power-off to reset its status.

[0024] To achieve the control and functional safety requirements of the entire motherboard system by the motherboard 110, the motherboard 110 can employ a microcontroller unit (MCU) with an Automotive Safety Integrity Level (ASIL) of D. In some embodiments, a TC397 chip (Aurix chip) can be used as the main program execution chip of the motherboard 110. For example, the TC397 chip can run instructions for executing the inter-board heartbeat monitoring method 200. While selecting the TC397 chip, the motherboard 110 can also select a TLE35584 chip to manage its own power supply status. In some embodiments, the daughterboard chip of the daughterboard 120 can be a system-on-a-chip (SoC) or an MCU. Figure 1 In the illustrated embodiment, the motherboard 110 can simultaneously connect to six daughterboards 120. As an example, three of the six daughterboards 120 can use S32G chips, and the other three daughterboards 120 can use TDA4 chips.

[0025] The motherboard 110 is the core and hub for power control in the entire CCP. In some embodiments, the motherboard 110 may include a built-in motherboard power management chip to control the voltage output to each daughterboard 120 and initiate monitoring functions for each daughterboard 120. Through the monitoring function of the motherboard power management chip, the motherboard 110 can monitor in real time whether each daughterboard 120 has experienced faults such as over-temperature, over-voltage, or over-current. If a fault is detected in a daughterboard 120, the motherboard 110 can generate an interrupt through the INTB pin and trigger a motherboard response, thereby quickly shutting down the relevant power output to prevent damage to related components and protect the system module. In addition, the motherboard 110 can be configured to monitor the temperature or voltage of the motherboard power management chip itself to ensure the normal operation of the motherboard system.

[0026] The motherboard power management chip can achieve ASIL D rating to improve system safety and stability. For example, in the case of motherboard 110 using the TC397 chip, motherboard 110 can use VR5510 and PF7100 chips as its power management chips. In this example, the TC397 chip can communicate with these two motherboard power management chips via the integrated circuit bus (I2C) to periodically read their operating status and perform heartbeat monitoring on all associated daughterboards 120.

[0027] Additionally, the motherboard 110 may include an internal watchdog timer. Using a watchdog strategy, a watchdog feed operation can be performed via SPI commands to monitor in real time whether the tasks on the motherboard 110 are executing correctly. In some embodiments, when the watchdog feed function is enabled on the motherboard 110, the watchdog feed action can be performed at fixed intervals to ensure that the heartbeat monitoring task executed by the motherboard system software operates normally. As an example, the fixed interval for performing the watchdog feed action could be 500ms.

[0028] Each of the multiple daughterboards 120 may include its own daughterboard power management chip. The motherboard 110 can monitor the voltage output status of the daughterboard power management chip within each daughterboard 120 in real time to confirm the operating status of the daughterboard power management chip in each daughterboard 120. As an example, each daughterboard 120 uses a VR5510 chip as its daughterboard power management chip. In some embodiments, the motherboard power management chip can perform a series of monitoring functions on each daughterboard power management chip (such as overvoltage, overcurrent, overtemperature, etc.). If the monitored parameters exceed the threshold as determined by software logic, a protection mechanism can be triggered to shut down the relevant power output.

[0029] In addition, each daughterboard 120 can include an internal watchdog timer. By enabling watchdog monitoring and power monitoring functions, the normal execution of tasks on each daughterboard 120 can be monitored, thereby ensuring the stability of the daughterboard system and further improving the security of the daughterboard 120. In some embodiments, when the watchdog feeding function is enabled on the daughterboard 120, the watchdog feeding action can be performed at fixed intervals to ensure that the daughterboard system executes the daughterboard heartbeat counting feedback task normally when it receives a heartbeat counting request from the motherboard 110. That is to say, the chip systems of the motherboard 110 and the daughterboard 120 can constitute the entire heartbeat monitoring system.

[0030] In the example where daughterboard 120 is connected to motherboard 110 via daughterboard slots, the voltage output provided by motherboard 110 to daughterboard 120 can be referred to as "daughterboard slot voltage output". During the initialization phase, motherboard 110 can configure the corresponding daughterboard power management chips in each daughterboard 120, enabling voltage output control and related voltage signal sampling and monitoring for each daughterboard slot. It should be noted that for stable systems, since their daughterboard power management chips are functioning normally, even if daughterboard 120 malfunctions, the normal voltage output of the daughterboard power chips will generally not be affected. Based on this, embodiments of this application can obtain the daughterboard connection status at each location by real-time monitoring of the voltage output status at the corresponding daughterboard slot location for all daughterboard slots in motherboard 110. If the power management system of each daughterboard 120 is supplying power normally, it indicates that the pin signal of the daughterboard power management chip is normal, and it can be determined that the current daughterboard slot is connected to a daughterboard 120. If no pin signal of the daughterboard power management chip of daughterboard 120 is detected, it can be determined that the current daughterboard slot is not connected to a daughterboard 120. The pin signal of the daughterboard power management chip is used to provide feedback on the voltage output status of daughterboard 120. This paper refers to the pin signal of the daughterboard power management chip as the "voltage feedback signal". As an example, the voltage feedback signal can be the PGOOD signal.

[0031] This application embodiment does not require a manual calibration process. The daughterboard connection status can be determined by reading back the corresponding voltage output signal, thereby improving the adaptability of the system heartbeat monitoring and confirming the benchmark of the motherboard 110 monitoring the daughterboard 120 through self-learning.

[0032] In order to enable the motherboard 110 to control the entire motherboard system in real time, real-time communication between boards is very important. Figure 1 An inter-board communication architecture according to one embodiment of this application is illustrated. Figure 1 In the illustrated inter-board communication architecture, the motherboard 110 can determine the access status of the daughterboard 120 in real time and obtain the heartbeat status of each daughterboard 120 based on the daughterboard access status, thereby confirming whether the corresponding daughterboard 120 is working properly. For example... Figure 1 As shown, due to the requirements for collaborative work and configuration between a motherboard 110 and multiple functional daughterboards 120, data exchange is necessary between the device boards. Therefore, a communication mechanism needs to be established between the motherboard 110 and different daughterboards 120 to form a maintainable and manageable channel. In the example of connecting the motherboard 110 via a daughterboard slot, multiple daughterboards 120 connected to the daughterboard slot can achieve inter-board communication connections with the motherboard 110 through connecting lines.

[0033] like Figure 1 As shown, the connection lines may include a chip select signal channel 130, a voltage signal channel 140, and a data channel 150. The voltage signal channel 140 may be a signal channel through which the daughterboard 120 provides a voltage feedback signal (e.g., a PGOOD level signal) to the motherboard 110. In... Figure 1 In the example shown, the motherboard 110 is provided with a general purpose input / output port (GPIO) 111. The voltage feedback signal transmitted from the daughterboard 120 via the voltage signal channel 140 can be provided to the motherboard 110 through GPIO 111. The chip select signal channel 130 can be a signal channel for the motherboard 110 to send a chip select signal to the daughterboard 120. The data channel 150 can be used for inter-board data transmission between the motherboard 110 and the daughterboard 120, as well as between the various daughterboards 120.

[0034] Inter-board communication in the embodiments of the application can be implemented through hardwired communication. For example, embodiments of this application can obtain the status of each daughter board 120 through hardwired signals, thereby confirming the number of daughter boards 120 inserted on the motherboard 110, which can not only meet the requirements of personalized functions, but also confirm the initial status of inter-board communication.

[0035] In some embodiments, a Serial Peripheral Interface (SPI) master-slave communication protocol can be used to construct the inter-board communication for the heartbeat monitoring protocol. The motherboard 110 can act as the SPI master, sending the corresponding daughterboard status and heartbeat request commands to each daughterboard 120; the daughterboard 120 can act as the SPI slave, replying to the motherboard 110 with its own heartbeat count and other information as response data. Using a custom encapsulation of an upper-layer protocol based on SPI for inter-board communication enables both signal transmission and monitoring, as well as command control. This approach is convenient to implement, low-cost, and universally applicable.

[0036] As an example, a heartbeat monitoring protocol can be shown in Table 1.

[0037] Table 1 Heartbeat Monitoring Protocol

[0038]

[0039] As shown in Table 1, the heartbeat monitoring protocol may include bytes 1 (BYTE1) through byte 5 (BYTE5). Each BYTE in BYTE1 through BYTE5 includes a corresponding master request and slave response byte pair.

[0040] Master_Request and Slaver_Response each consist of 8 bits (Bit0 to Bit7). Master_Request is transmitted from motherboard 110 to slave board 120, and Slaver_Response is transmitted from slave board 120 to motherboard 110. BYTE1 is used to transmit the request command, BYTE2 to BYTE3 are used to transmit the slave board status, BYTE4 is a reserved byte, and BYTE5 is a check bit used to verify whether BYTE1 to BYTE4 have been interfered with. In some embodiments, Master_Request can be transmitted from motherboard 110 to slave board 120 every heartbeat monitoring cycle T2 (e.g., 100ms), and Slaver_Response can be transmitted from slave board 120 to motherboard 110 simultaneously.

[0041] Next, we will combine Figure 2 and Figure 3 This application describes an embodiment of an inter-board heartbeat monitoring method 200.

[0042] Figures 2 to 3 An inter-board heartbeat monitoring method 200 according to an embodiment of this application is shown, wherein the inter-board heartbeat monitoring method 200 includes an access status determination step 210 for determining the access status of the daughter board 120 on the motherboard 110 (see [link]). Figure 2) and heartbeat count verification step 310 for performing heartbeat count verification on daughterboard 120 (see Figure 3 ).

[0043] Figure 2 A flowchart illustrating the execution of access status determination step 210 is shown. For an embodiment where the motherboard 110 is connected via a daughterboard slot, each execution of access status determination step 210 involves performing a daughterboard access determination for each daughterboard slot on the motherboard 110 to determine the access status of the daughterboard 120 on the motherboard 110. In some embodiments, access status determination step 210 can be executed once per status confirmation period T1. As an example, the status confirmation period T1 can be 5 seconds; in other embodiments, the status confirmation period T1 can also be other time values. Figure 2 As shown, the access status determination step 210 may include steps S220 to S242.

[0044] In step S220, the heartbeat monitoring configuration of the motherboard 110 to the daughterboard 120 is initialized. In some embodiments, step S220 may include ADC / I2C initialization and I / O expansion chip startup configuration. After step S220, step S222 may be further executed. It should be noted that step S220 can be executed as needed; if configuration initialization is not required, step S220 may be omitted, and step S222 may be executed directly.

[0045] In step S222, the current daughterboard slot to be determined is identified (also referred to herein as the "current daughterboard slot" or "current daughterboard slot"). The current daughterboard slot to be determined may be a daughterboard slot that has not been determined in the current access status determination step 210. In some embodiments, for all daughterboard slots on the motherboard 110, the access status determination step 210 may determine whether each daughterboard slot is connected to the daughterboard 120 in a predetermined order. Accordingly, the current daughterboard slot to be determined in step S222 may be determined in a predetermined order. After step S222, step S224 may be further executed.

[0046] In step S224, the voltage output of the daughterboard slot to be judged, as determined in step S222, is read. For example, the output voltage of the motherboard power management chip on the motherboard 110 can be read via the analog-to-digital converter (ADC) channel in the motherboard 110. After step S224, step S226 can be further executed.

[0047] In step S226, it is determined whether the voltage output read in step S224 is normal. If the voltage output is determined to be normal, step S230 can be further executed. If the voltage output is determined to be abnormal, step S228 can be further executed.

[0048] In step S228, it is determined that the current power supply status of the daughterboard slot is abnormal and an error is reported for the abnormal status.

[0049] In step S230, a voltage feedback signal (e.g., a PGOOD level signal) is read for the current daughterboard slot. As an example, daughterboard 120 can transmit a voltage feedback signal to motherboard 110 via voltage signal channel 140, so that motherboard 110 can read the voltage feedback signal via voltage signal channel 140. As described above, when daughterboard 120 is connected to motherboard 110 via daughterboard slot, the voltage feedback signal can originate from the corresponding daughterboard 120. After step S230, step S232 can be further executed.

[0050] In step S232, it is determined whether the voltage feedback signal read in step S230 is normal. If the voltage feedback signal is determined to be normal, step S234 can be further executed. If the voltage feedback signal is determined to be abnormal, step S236 can be further executed.

[0051] In step S234, it is determined that the current daughterboard slot is connected to daughterboard 120. After step S234, step S242 can be further executed.

[0052] In step S236, the loop count is incremented. In some embodiments, the initial value of the loop count can be 0. Optionally, step S236 may include incrementing the loop count by 1. That is, the loop count can be incremented by 1 each time step S236 is executed. After step S236, step S238 can be further executed.

[0053] In step S238, it is determined whether the number of cycles determined in step S236 has reached the cycle threshold. As an example, the cycle threshold can be 5; in other embodiments, the cycle threshold can also be other values. If the number of cycles reaches the cycle threshold, step S240 can be further executed. If the number of cycles does not reach the cycle threshold, the process can return to step S230 to reread the voltage feedback signal.

[0054] In step S240, it is determined that the current daughterboard slot is not connected to daughterboard 120. That is, for the example with a loop threshold of 5, it can be determined that the current daughterboard slot is not connected to daughterboard 120 if the voltage feedback signal is abnormal for 5 loops. After step S240, step S242 can be further executed.

[0055] In step S242, it is determined whether there are any unchecked daughterboard slots. In the example where each daughterboard slot is checked sequentially according to a preset order to determine whether it is connected to daughterboard 120, it can be determined whether there are any unchecked daughterboard slots by confirming whether the currently checked daughterboard slot is the last daughterboard slot in the current check sequence: if it is the last daughterboard slot, it is determined that there are no unchecked daughterboard slots; if it is not the last daughterboard slot, it is determined that there are unchecked daughterboard slots. If it is determined that there are unchecked daughterboard slots via step S242, step S222 can be further executed to determine the next daughterboard slot to be checked. If it is determined that there are no unchecked daughterboard slots via step S242, step S244 can be further executed to end the current round of connection status determination step 210.

[0056] As described above, after the current access status determination step 210 is completed, the next stage of access status determination step 210 can be executed when the next status confirmation cycle T1 arrives. In some embodiments, the motherboard 110 can periodically and proactively trigger self-learning behavior to execute the access status determination step 210 to dynamically manage the access status of the daughterboard, thereby checking the access status of the daughterboard 120 throughout its entire lifecycle. That is, based on the periodic execution of the access status determination step 210, the motherboard 110 can dynamically monitor the dynamic plugging and unplugging of each daughterboard 120 and update the access status of the daughterboard 120, thereby enabling plug-and-play functionality for the daughterboard 120. In other embodiments, an inspection process (i.e., access status determination step 210) can also be triggered by an external service. Optionally, the triggering behavior of the external service can be a Unified Diagnostic Service (UDS) or a pulse width modulation (PWM) signal with a fixed period input from the outside.

[0057] based on Figure 2The access status determination step 210 shown can confirm the access status of the daughter board 120 on the motherboard 110 for all daughter board slots on the motherboard 110. Based on the access status of the daughter board 120 on the motherboard 110, the inter-board heartbeat monitoring method 200 further includes performing a heartbeat count check once for each daughter board 120 connected to the motherboard 110 in each heartbeat monitoring cycle T2, so as to periodically confirm whether each daughter board 120 connected to the motherboard 110 is operating normally. In some embodiments, the heartbeat monitoring cycle T2 can be 100ms; in other embodiments, the heartbeat monitoring cycle T2 can also be other time values.

[0058] Figure 3 A flowchart illustrating the heartbeat count verification step 310 is shown. Figure 3 As shown, the heartbeat count verification step 310 may include steps S320 to S356.

[0059] In step S320, a subboard (also referred to herein as the "current subboard") 120 for which motherboard information is to be sent is determined. The motherboard information may include a request command to request feedback from the subboard 120, and the subboard information may include a subboard heartbeat count. By sending motherboard information to the subboard 120, feedback from the current subboard 120 can be requested, thereby enabling further heartbeat count verification for that subboard 120. In other words, the subboard 120 for which motherboard information is to be sent as determined in step S320 can also be considered the subboard 120 for which heartbeat count verification is to be performed.

[0060] In some embodiments, since a heartbeat count verification is performed on each daughterboard 120 connected to the motherboard 110 each time the heartbeat count verification step 310 is executed, the daughterboard 120 for which motherboard information is currently to be sent in step S320 may be a daughterboard that has not been verified in this round of heartbeat count verification step 310. In some embodiments, the heartbeat count verification step 310 may verify the heartbeat count of each daughterboard 120 connected to the motherboard 110 in a pre-set order. Accordingly, the daughterboard 120 to be verified in step S320 may be determined in a pre-set order. After step S320, step S322 may be further executed.

[0061] In step S322, motherboard information is sent to the current daughter board 120 determined in step S320. In some embodiments, the motherboard information can be sent from the motherboard 110 to the daughter board 120 via the chip select signal channel 130. Since the motherboard information may include a request command requesting the daughter board to provide feedback on its own information, and the daughter board information may include a daughter board heartbeat count, step S322 can request feedback on the daughter board heartbeat count from the current daughter board 120. In some embodiments, the motherboard 110 can sequentially select daughter boards 120 for communication via the SPI chip select signal to query the specific heartbeat information of the corresponding daughter board 120. After step S322, step S324 can be further executed.

[0062] In step S324, it is determined whether sub-board information has been received from sub-board 120. If sub-board information has been received from sub-board 120, step S332 can be further executed. If sub-board information has not been received from sub-board 120, step S326 can be further executed.

[0063] In step S326, the number of no-feedback counts is incremented. In some embodiments, the initial value of the no-feedback count can be 0. Optionally, step S326 may include incrementing the no-feedback count by 1. That is, whenever step S324 determines that no feedback information has been received from the sub-board 120, the no-feedback count can be incremented by 1. After step S326, step S328 can be further executed.

[0064] In step S328, it is determined whether the number of no-feedback attempts updated in step S326 has reached the no-feedback threshold. If the number of no-feedback attempts reaches the no-feedback threshold, it can be determined that the sub-board 120 is malfunctioning and has lost contact, and step S340 can be further executed. If the number of no-feedback attempts has not reached the no-feedback threshold, step S330 can be further executed.

[0065] In step S330, it is determined whether the trigger period T3 is met. If the trigger period T3 is met, step S322 can be further executed to resend the motherboard information to the current daughterboard 120. If the trigger period T3 is not met, step S330 can be returned to continuously determine whether the trigger period T3 is met. The trigger period T3 can be a time value shorter than the heartbeat monitoring period T2. For example, for an example where the heartbeat monitoring period T2 is 100ms, the trigger period T3 can be 10ms. Correspondingly, if no daughterboard information is received from the daughterboard 120 and the number of no-feedback instances has not reached the no-feedback threshold, motherboard information can be sent to the current daughterboard 120 every 10ms trigger period T3 to request the current daughterboard 120 to provide feedback again.

[0066] In step S332, a heartbeat count verification value is obtained. In some embodiments, the heartbeat count verification value may be stored on the motherboard 110. During the execution of heartbeat count verification step 310, the heartbeat count verification value can be updated as needed. For example, as... Figure 3 As shown, the heartbeat count check value can be updated during any of steps S338, S350, and S352. Step S334 can be further executed after step S332.

[0067] In step S334, the minimum critical heartbeat count and the maximum critical heartbeat count are determined based on the heartbeat count verification value obtained in step S332. As an example, the minimum critical heartbeat count and the maximum critical heartbeat count can be determined by subtracting and adding a critical deviation value, respectively, from the heartbeat count verification value. For instance, if the critical deviation value is predetermined to be 5, and the heartbeat count verification value obtained in step S332 is 10, the minimum critical heartbeat count can be 5 (i.e., 10 - 5), and the maximum critical heartbeat count can be 15 (i.e., 10 + 5). After step S334, step S336 can be further executed.

[0068] In step S336, it is determined whether the subboard heartbeat count in the subboard information obtained in step S324 falls between the minimum critical heartbeat count and the maximum critical heartbeat count. If the subboard heartbeat count falls between the minimum critical heartbeat count and the maximum critical heartbeat count, it means that the subboard heartbeat count in the subboard information fed back by the current subboard 120 is in sync with the heartbeat count verification value stored in the motherboard 110 or the deviation is within a reasonable range. In this case, step S338 can be further executed. If the subboard heartbeat count does not fall between the minimum critical heartbeat count and the maximum critical heartbeat count, it means that the subboard heartbeat count of the current subboard 120 is not in sync with the heartbeat count verification value and the deviation exceeds a reasonable range. In this case, step S340 can be further executed.

[0069] In step S338, it is determined that the current sub-board 120 is operating normally, and the sub-board heartbeat check value is updated using the current sub-board heartbeat count. That is, after requesting the sub-board heartbeat count from the current sub-board 120, if the main board 110 receives feedback from the sub-board 120, and the feedback sub-board heartbeat count is within a reasonable range (i.e., the deviation from the heartbeat count check value is less than the critical deviation value (e.g., 5), falling between the minimum and maximum critical heartbeat counts), then the current sub-board 120 is considered to be working normally. At this time, resetting the sub-board heartbeat check value using the current sub-board heartbeat count is to reduce the startup time deviation between the main board 110 and the sub-board 120, as well as occasional system cycle offsets. By synchronizing the sub-board heartbeat check value with the sub-board heartbeat count (obtained via step S324) to reset the sub-board heartbeat check value stored in the main board 110, synchronous operation between the sub-board heartbeat check value and the sub-board heartbeat count can be achieved. In other words, this behavior avoids the problem of system time asynchrony between the motherboard 110 and the daughterboard 120 as running time increases, thereby enhancing the robustness of the system. After step S338, step S346 can be further executed.

[0070] In step S340, the number of verification errors is incremented. In some embodiments, the initial value of the number of verification errors can be 0. Optionally, step S340 may include incrementing the number of verification errors by 1.

[0071] Based on the above description, there are two possible scenarios for incrementing the number of verification errors: one is when a request for feedback on the daughterboard heartbeat count is made to daughterboard 120 but no response is received, and the request for a response from daughterboard 120 is repeated every trigger period T3 (e.g., 10ms) until the number of no-feedback events reaches the no-feedback threshold (e.g., 5 times); the other is when the received daughterboard heartbeat count does not fall between the minimum critical heartbeat count and the maximum critical heartbeat count. In other words, in some embodiments, whenever either of these scenarios occurs, the number of verification errors can be incremented by 1 via step S340. After step S340, step S342 can be further executed.

[0072] In step S342, it is determined whether the number of verification errors updated in step S340 is greater than the fault tolerance threshold. If the number of verification errors is greater than the fault tolerance threshold, step S344 can be further executed. If the number of verification errors is not greater than the fault tolerance threshold, step S348 can be further executed.

[0073] In step S344, it is determined that the current sub-board 120 is malfunctioning. After step S344, step S346 can be further executed.

[0074] In step S346, the currently determined sub-board status is updated, and the currently determined sub-board status is transmitted to other sub-boards 120 connected to the mainboard 110. After step S346, step S354 can be further executed.

[0075] In step S348, it is determined whether the sub-board heartbeat count is less than the minimum critical heartbeat count or greater than the maximum critical heartbeat count. If step S348 determines that the sub-board heartbeat count is less than the minimum critical heartbeat count, step S352 can be further executed. If step S348 determines that the sub-board heartbeat count is greater than the maximum critical heartbeat count, step S350 can be further executed.

[0076] In step S350, the heartbeat count verification value is updated using the maximum critical heartbeat count. In step S352, the heartbeat count verification value is updated using the minimum critical heartbeat count. Combining steps S348 and S350, it can be seen that step S354 can be further executed after step S352 and after step S350.

[0077] Based on the above steps, it can be seen that if the heartbeat count in the current sub-board information fed back by sub-board 120 is not as frequent as the heartbeat count verification value stored in the motherboard 110 and exceeds a reasonable range (i.e., not falling between the minimum critical heartbeat count and the maximum critical heartbeat count), then it can be determined that the current verification is faulty and it can be further determined whether the number of verification errors has reached the fault tolerance threshold. If the fault tolerance threshold has not been reached, it is considered that the current sub-board program has a potential abnormality but has not reached the standard for confirming an abnormality. At this time, the motherboard 110 can use the critical heartbeat count (i.e., the minimum critical heartbeat count or the maximum critical heartbeat count) that is closer to the sub-board heartbeat count to reset the heartbeat count verification value, and wait for the next heartbeat monitoring cycle T2 to make the judgment again. Until the number of heartbeat verifications that the current sub-board 120 is potentially abnormal reaches the fault tolerance threshold, the motherboard 110 confirms that the current sub-board 120 is malfunctioning and informs each sub-board 120 of this situation.

[0078] In step S354, it is determined whether there is a sub-board 120 that has not undergone heartbeat count verification. In the example where heartbeat count verification is performed on each sub-board 120 connected to the motherboard 110 in a pre-set order, it can be determined whether there is a sub-board 120 that has not undergone heartbeat count verification in the following way: confirm whether the sub-board 120 currently undergoing heartbeat count verification is the last sub-board 120 in the heartbeat count verification sequence. If it is the last sub-board 120, it is determined that there is no sub-board 120 that has not undergone heartbeat count verification; if it is not the last sub-board 120, it is determined that there is a sub-board 120 that has not undergone heartbeat count verification. If it is determined through step S354 that there is a sub-board 120 that has not undergone heartbeat count verification, step S320 can be further executed to determine the next sub-board 120 to be subjected to heartbeat count verification. If it is determined through step S354 that there is no sub-board 120 that has not undergone heartbeat count verification, step S356 can be further executed to end the current round of heartbeat count verification step 310.

[0079] As described above, in some embodiments, after the current heartbeat counting verification step 310 is completed, the next stage of heartbeat counting verification step 310 can be executed when the next heartbeat monitoring cycle T2 (e.g., 100ms) arrives. Specifically, for each heartbeat monitoring cycle T2, the motherboard 110 can sequentially select each daughterboard 120 via the SPI chip select signal for one-to-one communication to query the specific heartbeat information of each daughterboard 120.

[0080] The inter-board heartbeat monitoring method 200 of this application optimizes the monitoring process of the motherboard 110 to the daughter board 120, and independently designs an inter-board communication protocol, which can realize the heartbeat monitoring of the motherboard 110 to the daughter board 120, thereby quickly and easily diagnosing the status of the daughter board 120, simplifying the monitoring link, improving the response capability and the dependence on the protocol stack.

[0081] Figure 4 An inter-board heartbeat monitoring system 400 according to one embodiment of this application is shown. Figure 4As shown, the inter-board heartbeat monitoring system 400 includes a memory 410 (e.g., non-volatile memory such as flash memory, ROM, hard disk drive, disk, optical disk, etc.) and a processor 420. The memory 410 stores instructions executable by the processor 420, which is configured to execute the instructions to implement the inter-board heartbeat monitoring method 200 according to one or more embodiments of the present invention. In some embodiments, the motherboard 110 may include the inter-board heartbeat monitoring system 400. When the processor 330 on the motherboard 110 executes the instructions, the motherboard 110 can perform heartbeat monitoring on each of the connected daughter boards 120, thereby enabling real-time monitoring of the status of each daughter board 120, ensuring that each daughter board 120 is operating normally after the computing power allocation, and ensuring rapid response after a daughter board 120 failure. As an example, the processor 330 may be a TC397 chip on the motherboard 110.

[0082] This application also provides a vehicle comprising the inter-board heartbeat monitoring system 400 as described in any of the embodiments of this application above. The term "vehicle" as used in this application is intended to refer to any suitable vehicle having a drive system consisting of at least a battery, a power conversion device, and a drive motor, such as a hybrid electric vehicle, an electric vehicle, a plug-in hybrid electric vehicle, etc. A hybrid electric vehicle is a vehicle having two or more power sources, such as a gasoline-powered and an electric vehicle.

[0083] According to another aspect of this application, a computer-readable storage medium is provided, wherein instructions are stored that, when executed by a processor, cause the processor to perform any of the inter-board heartbeat monitoring methods 200 described above. The computer-readable medium referred to in this application includes various types of computer storage media, and can be any available medium accessible by a general-purpose or special-purpose computer. For example, the computer-readable medium may include RAM, ROM, EPROM, E... 2 PROM, registers, hard disks, removable disks, CD-ROMs or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other temporary or non-temporary medium capable of carrying or storing desired units of program code in the form of instructions or data structures and accessible by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. As used herein, disks typically magnetically copy data, while discs optically copy data using lasers. Combinations of the above should also be included within the scope of computer-readable media. An exemplary storage medium is coupled to a processor so that the processor can read and write information from / to the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and storage medium may reside as discrete components in the user terminal.

[0084] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Those skilled in the art can conceive of other feasible variations or substitutions based on the technical scope disclosed in this application, and such variations or substitutions are all covered within the scope of protection of this application. Where there is no conflict, the embodiments and features described in the embodiments of this application can also be combined with each other. The scope of protection of this application is determined by the claims.

Claims

1. A method for monitoring heart rate between plates, characterized in that, The inter-plate heart rate monitoring method includes: Determine the connection status of the daughterboard on the motherboard; Based on the determined access status, for all sub-boards connected to the motherboard, a heartbeat count verification is performed on each sub-board once in each heartbeat monitoring cycle; The heartbeat count verification includes: Send motherboard information to a daughterboard connected to the motherboard, wherein the motherboard information includes a request command for requesting the daughterboard to provide feedback on its information, and the daughterboard information includes a daughterboard heartbeat count. Upon receiving the subboard information fed back by the subboard, determine whether the subboard heartbeat count in the subboard information falls between the minimum critical heartbeat count and the maximum critical heartbeat count; If the subboard heartbeat count does not fall between the minimum critical heartbeat count and the maximum critical heartbeat count, increment the check error count and determine whether the check error count is greater than the fault tolerance threshold; and If the number of verification errors exceeds the fault tolerance threshold, the sub-board is determined to be malfunctioning.

2. The interplate heart rate monitoring method according to claim 1, characterized in that, The minimum critical heartbeat count and the maximum critical heartbeat count are determined based on the heartbeat count check value.

3. The interplate heart rate monitoring method according to claim 2, characterized in that, If the subboard heartbeat count falls between the minimum critical heartbeat count and the maximum critical heartbeat count, the heartbeat count check value is updated using the subboard heartbeat count.

4. The interplate heart rate monitoring method according to claim 2, characterized in that, If the number of verification errors is not greater than the fault tolerance threshold, determine whether the sub-board heartbeat count is less than the minimum critical heartbeat count or greater than the maximum critical heartbeat count; If the heartbeat count of the subboard is less than the minimum critical heartbeat count, the heartbeat count check value is updated with the minimum critical heartbeat count. and If the heartbeat count of the subboard is greater than the maximum critical heartbeat count, the heartbeat count verification value is updated with the maximum critical heartbeat count.

5. The interplate heart rate monitoring method according to claim 1, characterized in that, The motherboard includes a daughterboard slot for connecting a daughterboard; The determination of the access status of the daughterboard on the motherboard includes: for all daughterboard slots on the motherboard, performing a daughterboard access judgment once for each daughterboard slot in each status confirmation cycle.

6. The interplate heart rate monitoring method according to claim 5, characterized in that, The sub-board access determination includes: Determine whether the voltage output of the daughterboard slot is normal; When the voltage output is normal, read the voltage feedback signal for the daughterboard slot and determine whether the voltage feedback signal is normal; and If the voltage feedback signal is normal, it is determined that the sub-board slot is connected to the sub-board.

7. The interplate heart rate monitoring method according to claim 6, characterized in that, The sub-board access determination also includes: If the voltage feedback signal is abnormal, the number of cycles is incremented for the sub-board slot and it is determined whether the number of cycles has reached the cycle threshold. If the number of cycles does not reach the cycle threshold, the voltage feedback signal is further read and it is determined whether the voltage feedback signal is normal; and If the number of cycles reaches the cycle threshold, it is determined that the sub-board slot is not connected to the sub-board.

8. A board-to-board heartbeat monitoring system, characterized in that, The inter-board heartbeat monitoring system includes: Memory configured to store instructions; and A processor configured to execute the instructions to cause the inter-board heartbeat monitoring system to perform the inter-board heartbeat monitoring method as described in any one of claims 1-7.

9. A vehicle, characterized in that, The vehicle includes the inter-panel heart rate monitoring system as described in claim 8.

10. A computer-readable storage medium storing instructions, characterized in that, When the instruction is executed by the processor, the processor performs the inter-board heartbeat monitoring method as described in any one of claims 1-7.

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