Semiconductor device and method of manufacturing the same, electronic device

Abstract

The application provides a semiconductor device and a preparation method thereof and an electronic device, relates to the technical field of semiconductors, and is used for solving the problem of uneven surface of a semiconductor device after a planarization process, so as to improve the yield of the semiconductor device. The preparation method of the semiconductor device comprises the following steps: forming a plurality of fins on a substrate; forming a plurality of first sacrificial gates located in a first region and a plurality of second sacrificial gates located in a second region; and forming an interlayer dielectric layer. The interlayer dielectric layer is planarized to expose the surfaces of the plurality of first sacrificial gates and the plurality of second sacrificial gates away from the substrate. An isolation structure is formed, the isolation structure divides the fins into first fins located below the plurality of first sacrificial gates and second fins located below the plurality of second sacrificial gates, and the isolation structure surrounds the plurality of first fins and the plurality of first sacrificial gates. The above semiconductor device is applied to an electronic device to improve the yield of the electronic device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor device and a preparation method thereof, and an electronic device. BACKGROUND

[0002] In view of the influence of the high-temperature processing step in the source-drain epitaxy process on the performance and reliability of the gate stack in the Complementary Metal Oxide Semiconductor (CMOS), the semiconductor preparation process is mostly changed from preparing the gate first and then preparing the source and the drain to preparing the source and the drain after preparing the sacrificial gate, and then replacing the sacrificial gate with a metal gate, that is, to the Replacement Metal Gate (RMG) process.

[0003] Although the RMG process can avoid the influence of the source-drain epitaxy process on the gate, it also makes the structure of the semiconductor device more complex, thereby making the topography of the device surface more complex and making the planarization process of the device more challenging. After the planarization process, if the surface is uneven, it will have an adverse effect on the subsequent process, which may eventually lead to device failure and reduce the yield. SUMMARY

[0004] Embodiments of the present application provide a semiconductor device and a preparation method thereof, and an electronic device, which are used to improve the problem of uneven surface after the planarization process of the semiconductor device, so as to improve the yield of the semiconductor device.

[0005] To achieve the above object, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a preparation method of a semiconductor device is provided. The preparation method includes: forming a plurality of fins on a substrate, the fins extending along a first direction parallel to the substrate; forming a plurality of first sacrificial gates located in a first region and a plurality of second sacrificial gates located in a second region, the first sacrificial gates and the second sacrificial gates extending along a second direction parallel to the substrate, the first direction and the second direction intersecting; the plurality of first sacrificial gates and the plurality of second sacrificial gates are arranged on the plurality of fins, and the second region is around the first region; forming an interlayer dielectric layer covering the plurality of first sacrificial gates and the plurality of second sacrificial gates; planarizing the interlayer dielectric layer to expose the surfaces of the plurality of first sacrificial gates and the plurality of second sacrificial gates away from the substrate; forming an isolation structure, the isolation structure separates the fins into first fins located below the plurality of first sacrificial gates and second fins located below the plurality of second sacrificial gates, and the isolation structure surrounds the plurality of first fins and the plurality of first sacrificial gates.

[0007] In the method for manufacturing the semiconductor device provided by some embodiments of the present application, the fins are first arranged on the substrate, and the first sacrificial gates are arranged on the first regions and the second sacrificial gates are arranged on the second regions, then the interlayer dielectric layer is formed, the planarization processing is performed on the interlayer dielectric layer, and finally the isolation structure is formed to divide the fins into the first fins and the second fins. In this way, before the planarization processing is performed, the fins, the first sacrificial gates and the second sacrificial gates are uniformly distributed on the substrate in the semiconductor device, so that in the planarization process of the interlayer dielectric layer, the problem of large surface height difference and uneven surface height of the semiconductor device caused by the uneven distribution of the circuit structures on the substrate and the different grinding speeds of different regions is less likely to occur, thereby effectively improving the yield of the semiconductor device and improving the performance of the semiconductor device.

[0008] Meanwhile, compared with the case that in the related art, the circuit structures are first manufactured, and then the dummy structures are arranged in the gaps between the adjacent two circuit structures, the size of the isolation structure spacing between the first fins and the second fins, the first sacrificial gates and the second sacrificial gates can be smaller in the method for manufacturing the semiconductor device provided by some embodiments of the present application, so that the subsequent other planarization processes are less likely to be affected, thereby further improving the yield of the semiconductor device and improving the performance of the semiconductor device.

[0009] In some embodiments, the forming of the isolation structure comprises: etching the second sacrificial gates and the fins in a first preset region to form a first isolation groove; the first preset region is located on one side of the plurality of first sacrificial gates along the second direction, and the first isolation groove extends along the first direction. A first isolation part is formed in the first isolation groove. Etching the interlayer dielectric layer and the fins in a second preset region to form a second isolation groove; the second preset region is located on one side of the plurality of first sacrificial gates along the first direction, and the second isolation groove extends along the second direction. A second isolation part is formed in the second isolation groove. The isolation structure comprises the first isolation part and the second isolation part. In this way, the first sacrificial gates and the second sacrificial gates can be better spaced apart by the first isolation part and the second isolation part, so that after the first sacrificial gates are replaced by the first gates and the second sacrificial gates are replaced by the second gates, the first gates and the second gates can be better spaced apart, and the use performance of the first gates is ensured.

[0010] In some embodiments, a size of the first isolation portion in the second direction is less than or equal to twice a distance between center lines of two adjacent fins; and / or, the substrate is provided with at least one first sacrificial gate group including a plurality of the first sacrificial gates; a size of the second isolation portion in the first direction is less than or equal to twice a distance between center lines of two adjacent first sacrificial gates in a first sacrificial gate group adjacent to the second isolation portion. In this way, the size of the first isolation portion in the second direction is small, and the size of the second isolation portion in the first direction is also small, so that in subsequent other planarization processes, the semiconductor device surface is less likely to have a significant height difference due to the first isolation portion and / or the second isolation portion, thereby further improving the yield of the semiconductor device.

[0011] In some embodiments, the etching the second sacrificial gates and the fins in the first pre-set region to form the first isolation groove includes: forming a first mask layer on the interlayer dielectric layer, the first mask layer including a first opening extending along the first direction and exposing end portions of a plurality of the second sacrificial gates adjacent to the plurality of first sacrificial gates. Via the first opening, etching the exposed end portions of the plurality of the second sacrificial gates and the fins below the end portions to form the first isolation groove.

[0012] In some embodiments, before the forming the plurality of first sacrificial gates and the plurality of second sacrificial gates, the preparation method further includes: forming an insulating layer on the substrate, portions of the fins being embedded in the insulating layer and the remaining portions protruding above a top surface of the insulating layer. The etching the exposed end portions of the plurality of the second sacrificial gates and the fins below the end portions to form the first isolation groove via the first opening includes: etching the end portions of the plurality of the second sacrificial gates exposed by the first opening to expose the fins below the end portions. Etching the fins to form a first recess in the insulating layer and a second recess on the insulating layer. The first isolation groove includes the first recess and the second recess.

[0013] In some embodiments, the etching the ILD layer and the fin in the second preset region to form the second isolation groove comprises: forming a second mask layer on the ILD layer, the second mask layer comprising a second opening, the second opening extending along the second direction and exposing the ILD layer between the first target sacrificial gate and the second target sacrificial gate; the first target sacrificial gate and the second target sacrificial gate being the closest first sacrificial gate and the closest second sacrificial gate in the plurality of first sacrificial gates and the plurality of second sacrificial gates along the first direction. Etching the exposed ILD layer and the fin under the ILD layer via the second opening to form the second isolation groove. In this way, the material to be etched is less during the formation of the second isolation groove, the etching process is simple, and the preparation efficiency of the semiconductor device is improved.

[0014] In some embodiments, before the forming the ILD layer, the preparation method further comprises: forming a dielectric layer covering two opposite sides of the plurality of first sacrificial gates and the plurality of second sacrificial gates along the first direction. Forming a source and a drain on the fin; along the first direction, the source and the drain are respectively located on two sides of the first sacrificial gate and two sides of the second sacrificial gate. Forming an etching stop layer covering the dielectric layer and the source and the drain.

[0015] In some embodiments, the etching the ILD layer and the fin in the second preset region to form the second isolation groove comprises: etching the exposed ILD layer to expose the etching stop layer under the ILD layer. Etching the exposed etching stop layer to expose the source or the drain under the etching stop layer. Etching the exposed source or drain and the fin under the source or the drain to form the second isolation groove.

[0016] In some embodiments, the second opening also exposes a part of the surface of the first target sacrificial gate close to the second target sacrificial gate and a part of the surface of the second target sacrificial gate close to the first target sacrificial gate. In the process of etching the ILD layer and the fin under the ILD layer via the second opening to form the second isolation groove, the first target sacrificial gate and the second target sacrificial gate are also etched. In this way, the size of the second opening in the first direction is larger, and the process of patterning the second mask layer is simpler. At the same time, the size of the second isolation groove in the first direction is also larger, and the size of the second isolation part is also larger, so that the first sacrificial gate and the second sacrificial gate can be better separated, and the first gate and the second gate formed subsequently can also be separated.

[0017] In some embodiments, the medium layer covering the side of the first target sacrificial gate close to the second target sacrificial gate is a first target medium layer, the etching stop layer covering the first target medium layer is a first target etching stop layer, the medium layer covering the side of the second target sacrificial gate close to the first target sacrificial gate is a second target medium layer, and the etching stop layer covering the second target medium layer is a second target etching stop layer. The second opening also exposes the first target medium layer, the first target etching stop layer, the second target medium layer, and the second target etching stop layer away from the end surface of the substrate.

[0018] The method for etching the interlayer dielectric layer and the fin in the second preset area to form the second isolation groove comprises: synchronously etching the first target sacrificial gate, the first target medium layer, the first target etching stop layer, the second target sacrificial gate, the second target medium layer, the second target etching stop layer, and the interlayer dielectric layer between the first target sacrificial gate and the second target sacrificial gate via the second opening to form a third recess; the bottom surface of the third recess has a spacing between the upper surface of the source or the drain located between the first target sacrificial gate and the second target sacrificial gate in the direction perpendicular to the substrate. The remaining first target medium layer, first target etching stop layer, second target medium layer, and second target etching stop layer are etched. The remaining interlayer dielectric layer between the first target sacrificial gate and the second target sacrificial gate is etched to expose the etching stop layer below the interlayer dielectric layer. The remaining first target sacrificial gate and second target sacrificial gate, the exposed etching stop layer, the source or the drain below the etching stop layer, and the fin below the source or the drain are etched to form the second isolation groove.

[0019] In some embodiments, before the isolation structure is formed, there is a gap between the plurality of first sacrificial gates and the plurality of second sacrificial gates in the second direction. The gap is less than or equal to the distance between the center lines of two adjacent fins. In this way, each fin can be provided with a first sacrificial gate or a second sacrificial gate, so that the first sacrificial gates and the second sacrificial gates are uniformly distributed on the substrate, thereby facilitating the improvement of the problem of uneven surface of the semiconductor device after the planarization process caused by uneven distribution of the sacrificial gate structure on the substrate, improving the yield of the semiconductor device, and improving the performance of the semiconductor device.

[0020] In some embodiments, the preparation method further comprises: replacing the first sacrificial gate with a first gate and replacing the second sacrificial gate with a second gate.

[0021] In a second aspect, a semiconductor device is provided, which includes a substrate, a plurality of first fins and a plurality of second fins, a plurality of first gates and a plurality of second gates, an interlayer dielectric layer, and an isolation structure. The plurality of first fins and the plurality of second fins are disposed on the substrate and extend along a first direction parallel to the substrate. The plurality of first gates and the plurality of second gates extend along a second direction parallel to the substrate, the first direction intersects the second direction; the plurality of first gates are disposed across the plurality of first fins, and the plurality of second gates are disposed across the plurality of second fins. The interlayer dielectric layer covers regions between the plurality of first gates and regions between the plurality of second gates, exposing surfaces of the plurality of first gates and the plurality of second gates away from the substrate. The isolation structure separates the plurality of first fins and the plurality of second fins, and separates the plurality of first gates and the plurality of second gates, and surrounds the plurality of first fins and the plurality of first gates. In some embodiments, the plurality of first fins and the plurality of second fins are made of the same material and disposed in the same layer, and the plurality of first gates and the plurality of second gates are made of the same material and disposed in the same layer.

[0022] In some embodiments of the semiconductor device, the first fins and the second fins are made of the same material and disposed in the same layer, and the first gates and the second gates are made of the same material and disposed in the same layer, i.e., the first fins and the second fins are obtained by fin cutting, and the first gates and the second gates are prepared at the same time. Therefore, in the preparation process of the semiconductor device, the fins are uniformly laid on the substrate first, the first sacrificial gates corresponding to the first gates and the second sacrificial gates corresponding to the second gates are formed, then the interlayer dielectric layer is formed, the interlayer dielectric layer is planarized, and finally the isolation structure is formed to separate the fins into the first fins and the second fins, and separate the first sacrificial gates and the second sacrificial gates. In this way, before the planarization process, the fins, the first sacrificial gates, and the second sacrificial gates are uniformly distributed on the substrate, so that in the planarization process of the interlayer dielectric layer, the surface height difference of the semiconductor device is not likely to be large due to the uneven distribution of the circuit structures on the substrate, and the surface height is not likely to be uneven, thereby effectively improving the yield of the semiconductor device and improving the performance of the semiconductor device.

[0023] Meanwhile, compared with the case that in the related art, the circuit structures are prepared first, and then the dummy structures are disposed in the gaps between adjacent two circuit structures, the size of the isolation structure separating the first fins and the second fins, and the first sacrificial gates and the second sacrificial gates can be smaller in some embodiments of the semiconductor device, so that the subsequent other planarization processes are not likely to be affected, further improving the yield of the semiconductor device and improving the performance of the semiconductor device.

[0024] In some embodiments, the isolation structure includes a first isolation portion and a second isolation portion. The first isolation portion extends along the first direction and is located on one side of the plurality of first gates along the second direction. The second isolation portion extends along the second direction and is located on one side of the plurality of first gates along the first direction. In this way, the first gates and the second gates can be better separated in both the first direction and the second direction.

[0025] In some embodiments, the first isolation portion includes a plurality of sub-isolation portions arranged in the first direction. The sub-isolation portions are located on the extension lines of the second gates, and the width of the sub-isolation portions in the first direction is equal to the width of the second gates in the first direction.

[0026] In some embodiments, the semiconductor device further includes an insulating layer. Part of the plurality of first fins and the plurality of second fins are embedded in the insulating layer, and the rest protrude above the upper surface of the insulating layer. The sub-isolation portion includes a first part embedded in the insulating layer and a second part located on the insulating layer; the size of the first part in the second direction is equal to the size of the second fin in the second direction.

[0027] In some embodiments, along the first direction, the closest first gate and second gate in the plurality of first gates and the plurality of second gates are the first target gate and the second target gate, respectively. The semiconductor device further includes: a first target dielectric layer covering the side of the first target gate close to the second target gate; a first target etching stop layer covering the first target dielectric layer; a second target dielectric layer covering the side of the second target gate close to the first target gate; and a second target etching stop layer covering the second target dielectric layer. Wherein, along the first direction, the second isolation portion is located between the first target etching stop layer and the second target etching stop layer.

[0028] In some embodiments, the semiconductor device further includes: a first dielectric layer and a second dielectric layer covering the two opposite sides of the second isolation portion in the first direction, respectively. A first etching stop layer and a second etching stop layer, the first etching stop layer covering the first dielectric layer, and the second etching stop layer covering the second dielectric layer.

[0029] In some embodiments, the isolation structure includes two first isolation portions and two second isolation portions. Along the second direction, the two first isolation portions are located on opposite sides of the plurality of first gates, respectively. Along the first direction, the two second isolation portions are located on opposite sides of the plurality of first gates, respectively. The two first isolation portions and the two second isolation portions are connected to form a frame shape.

[0030] In some embodiments, the semiconductor device further comprises a third dielectric layer, a source and a drain, and a third etching stop layer. The third dielectric layer covers opposite two sides of the plurality of first gates and the plurality of second gates in the first direction; the source and the drain are located on the plurality of first fins and the plurality of second fins; in the first direction, the source and the drain are located on two sides of the first gate and two sides of the second gate, respectively; the third etching stop layer covers the third dielectric layer, the source and the drain.

[0031] In some embodiments, a size of the first isolation portion in the second direction is less than or equal to twice a distance between center lines of two adjacent first fins; and / or, the substrate is provided with at least one first gate group comprising a plurality of the first gates; a size of the second isolation portion in the first direction is less than or equal to twice a distance between center lines of two adjacent first gates in a first gate group adjacent to the second isolation portion. In this way, the size of the first isolation portion and / or the second isolation portion is small, and when other planarization processes are subsequently performed, the problem of unevenness of the surface of the semiconductor device after the planarization process is unlikely to occur due to the difference in material between the first isolation portion and / or the second isolation portion and the first gate and the second gate, thereby effectively improving the yield of the semiconductor device.

[0032] In some embodiments, the plurality of first fins and the plurality of second fins have equal widths; and / or, the distance between any two adjacent fins in the plurality of first fins and the plurality of second fins is equal; and / or, the plurality of second gates have equal widths; and / or, the distance between any two adjacent second gates is equal. In this way, the first fins, the second fins and the second gates are relatively uniform, and when the semiconductor device is prepared, the fins and the second sacrificial gates are uniformly distributed, thereby effectively improving the problem of different polishing rates and different surface heights of the semiconductor device caused by uneven distribution of structures, and improving the yield of the semiconductor device.

[0033] In a third aspect, an electronic device is provided, which comprises a printed circuit board and the semiconductor device of any one of the embodiments of the second aspect; the semiconductor device and the printed circuit board are electrically connected. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A flowchart of a method for preparing a semiconductor device according to an embodiment of the present application is shown in the figure;

[0035] Figures 2A-7 For Figure 1 The structure diagram of the semiconductor device corresponding to each step in the flowchart is shown in the figure;

[0036] Figure 8 A top view of a semiconductor device according to an embodiment of the present application is shown in the figure;

[0037] Figure 9 A flowchart of another method of fabricating a semiconductor device according to embodiments of the present application;

[0038] Figure 10 A top view of a semiconductor device according to embodiments of the present application;

[0039] Figure 11 A top view of a semiconductor device according to embodiments of the present application; Figure 10 A cross-sectional view at D-D';

[0040] Figure 12 A perspective view of a semiconductor device according to embodiments of the present application;

[0041] Figure 13 A flowchart of another method of fabricating a semiconductor device according to embodiments of the present application;

[0042] Figure 14 A perspective view of a substrate according to embodiments of the present application;

[0043] Figure 15 A top view of another semiconductor device according to embodiments of the present application;

[0044] Figure 16 A perspective view of another semiconductor device according to embodiments of the present application;

[0045] Figure 17 A top view of a semiconductor device according to embodiments of the present application; Figure 15 A cross-sectional view at F-F';

[0046] Figure 18 A perspective view of another semiconductor device according to embodiments of the present application;

[0047] Figure 19 A structure of a semiconductor device according to embodiments of the present application;

[0048] Figure 20 A top view of another semiconductor device according to embodiments of the present application;

[0049] Figure 21 A top view of a semiconductor device according to embodiments of the present application; Figure 20 A cross-sectional view at G-G';

[0050] Figure 22 A perspective view of another semiconductor device according to embodiments of the present application;

[0051] Figure 23 A top view of another semiconductor device according to embodiments of the present application;

[0052] Figure 24 A top view of a semiconductor device according to embodiments of the present application; Figure 23 A cross-sectional view at H-H';

[0053] Figure 25 for Figure 23 a sectional view at I-I';

[0054] Figure 26 a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present application;

[0055] Figure 27 a top view of another semiconductor device according to an embodiment of the present application;

[0056] Figure 28 a top view of another semiconductor device according to an embodiment of the present application;

[0057] Figure 29 a top view of another semiconductor device according to an embodiment of the present application;

[0058] Figure 30 a top view of another semiconductor device according to an embodiment of the present application;

[0059] Figure 31 a top view of another semiconductor device according to an embodiment of the present application;

[0060] Figure 32 a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present application;

[0061] Figures 33-34 for Figure 32 a structure diagram of a semiconductor device corresponding to each step in the flow chart shown;

[0062] Figure 35 a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present application;

[0063] Figure 36 a perspective view of another semiconductor device according to an embodiment of the present application;

[0064] Figure 37 a structure diagram of another semiconductor device according to an embodiment of the present application;

[0065] Figure 38 a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present application;

[0066] Figure 39 a state diagram of a semiconductor device according to an embodiment of the present application;

[0067] Figure 40 a top view of another semiconductor device according to an embodiment of the present application;

[0068] Figure 41A flowchart illustrating another method for fabricating a semiconductor device provided in this application embodiment;

[0069] Figure 42 and Figure 43 for Figure 41 The flowchart shown contains structural diagrams of the semiconductor devices corresponding to each step.

[0070] Figure 44 A flowchart illustrating another method for fabricating a semiconductor device provided in this application embodiment;

[0071] Figure 45 A flowchart illustrating another method for fabricating a semiconductor device provided in this application embodiment;

[0072] Figures 46-48 for Figure 45 The flowchart shown contains structural diagrams of the semiconductor devices corresponding to each step.

[0073] Figure 49 A flowchart illustrating another method for fabricating a semiconductor device provided in this application embodiment;

[0074] Figures 50-53 for Figure 49 The flowchart shown illustrates the state diagrams of the semiconductor devices corresponding to each step.

[0075] Figure 54 A flowchart illustrating another method for fabricating a semiconductor device provided in this application embodiment;

[0076] Figure 55 A top view of yet another semiconductor device provided in an embodiment of this application;

[0077] Figure 56 A top view of yet another semiconductor device provided in an embodiment of this application;

[0078] Figure 57 for Figure 56 Cross-sectional view at J-J';

[0079] Figure 58 for Figure 56 Cross-sectional view at K-K';

[0080] Figure 59 This is a structural diagram of another semiconductor device provided in an embodiment of this application;

[0081] Figure 60 This is a structural diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0082] With reference to the drawings, the technical solutions in the embodiments of the present application will be described below. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application.

[0083] Hereinafter, in the embodiments of the present application, the terms "first", "second", and the like are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0084] In the embodiments of the present application, "up", "down", "left" and "right" are not limited to the relative positions of the components shown in the drawings, and it should be understood that these directional terms can be relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the position of the components shown in the drawings.

[0085] In the embodiments of the present application, unless the context requires otherwise, the term "comprising" is interpreted as open, inclusive meaning, i.e. "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplarily" or "some examples" and the like are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The exemplary representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0086] As used herein, "about", "approximately" or "nearly" includes the stated value and the average value within an acceptable deviation range of the specific value, wherein the acceptable deviation range is determined by the ordinary skill in the art considering the measurement being discussed and the error related to the measurement of the specific quantity (i.e. the limitation of the measurement system).

[0087] As used herein, "parallel," "perpendicular," "equal" include the recited condition and conditions that are approximately the recited condition, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the acceptable deviation range for approximately parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and approximately perpendicular, where the acceptable deviation range for approximately perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximately equal can be, for example, a difference between the two that is less than or equal to 5% of either.

[0088] It should be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0089] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations and / or equivalent circuit diagrams that are depicted as idealized examples which are employed to more effectively convey the principles of the exemplary embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0090] In some embodiments, as shown in Figure 1 A method of fabricating a semiconductor device is provided. The method of fabricating a semiconductor device includes:

[0091] S1', as shown in Figure 2A and Figure 2B A plurality of first fins 20' extending along a first direction X are formed on a substrate 10'. The substrate 10' includes a plurality of active areas AA and blank areas BB surrounding the active areas AA, the plurality of first fins 20' are formed on each active area AA, and no first fin 20' is formed on the blank areas BB. The first direction X is parallel to the substrate 10'.

[0092] S2', as shown in Figure 3A and Figure 3BAs shown in S3', a plurality of first sacrificial gates 30' extending along a second direction Y are formed. The first sacrificial gates 30' are disposed across the plurality of first fins 20'. Here, the second direction Y intersects the first direction X, and the second direction Y is parallel to the substrate 10'.

[0093] S3', as shown in Figure 4A and Figure 4B As shown in S4', an interlayer dielectric layer 60' is formed, covering the first sacrificial gates 30'.

[0094] S4', as shown in Figure 5 As shown in S5', the interlayer dielectric layer 60' is planarized to expose surfaces of the plurality of first sacrificial gates 30' away from the substrate 10'.

[0095] S5', as shown in Figure 6 As shown in S6', the first sacrificial gates 30' are replaced with first gates 70'.

[0096] As an example, a chemical mechanical polishing (CMP) process can be used to planarize the interlayer dielectric layer 60'.

[0097] S6', as shown in Figure 7 As shown in S6', the first sacrificial gates 30' are replaced with first gates 70'.

[0098] It can be understood that, since the etching rate of the chemical mechanical polishing process is affected by the material and the structure distribution density, and before the interlayer dielectric layer is formed, the structures such as the first fins 20', the first sacrificial gates 30', the source electrodes 40', and the drain electrodes 50' are disposed on the active areas AA, and the structures such as the first fins 20', the first sacrificial gates 30', the source electrodes 40', and the drain electrodes 50' are not disposed on the blank areas BB, and the structure distributions of the first fins 20', the first sacrificial gates 30', the source electrodes 40', and the drain electrodes 50' on different active areas AA are also not completely the same. Therefore, after the interlayer dielectric layer 60' is planarized, the height of the surface of the interlayer dielectric layer 60' on the active areas AA of the substrate 10' is different from the height of the surface of the interlayer dielectric layer 60' on the blank areas BB of the substrate 10', the height of the surface of the interlayer dielectric layer 60' on different active areas AA is also likely to be different, and the height of the surface of the interlayer dielectric layer 60' at different positions of the same active area AA is also likely to be different.

[0099] For example, after planarizing the interlayer dielectric layer 60', the surface height of the interlayer dielectric layer 60' on the blank area BB can be lower than the surface height of the interlayer dielectric layer 60' on the active area AA. For the active area AA, the surface height of the interlayer dielectric layer 60' in the region with less first sacrificial gates 30' is lower than the surface height of the interlayer dielectric layer 60' in the region with more first sacrificial gates 30'.

[0100] However, after planarizing the interlayer dielectric layer 60', the uneven surface height of the interlayer dielectric layer 60' can cause adverse effects on subsequent steps. For example, after replacing the first sacrificial gates 30' with the first gates 70', chemical mechanical polishing is needed to remove the gate material on the surface of the interlayer dielectric layer 60'. The uneven surface height of the interlayer dielectric layer 60' can affect the removal of the gate material. For example, when the surface of the first gate 70' on the active area AA is polished, the gate material on the surface of the blank area BB is not completely removed (resulting in the formation of an electrical connection of the first gate 70' that should not be electrically connected), which can easily cause the semiconductor device to fail after the semiconductor device is completely prepared. Or, when the gate material on the blank area BB is directly polished, the first gate 70' on the active area AA is partially or completely removed, which can also cause the semiconductor device to fail.

[0101] Based on this, in some other embodiments, as shown in FIG. 1C, another method for preparing a semiconductor device is also provided. The method includes forming a circuit structure 101 and a dummy structure 102 on a substrate 10", wherein the substrate 10" includes a plurality of active areas AA and a blank area BB surrounding the active areas AA. One circuit structure is formed on each active area AA, and a plurality of dummy structures 102 are formed on the blank area BB. Figure 8

[0102] The circuit structure 101 includes a transistor, and the transistor includes a first fin 20", a first sacrificial gate 30", a source and a drain (not shown). For example, the transistor can be a fin field-effect-transistor (FinFET).

[0103] The dummy structure 102 is similar to the circuit structure 101 and also includes a transistor, and the transistor includes a second fin, a second sacrificial gate, a source and a drain. The second fin can be made of the same material as the first fin and is spaced apart from the first fin. The second sacrificial gate can be made of the same material as the first sacrificial gate and is spaced apart from the second sacrificial gate. However, the dummy structure 102 does not have an actual electrical function.

[0104] For example, the surface of the circuit structure away from the substrate can be flush with the surface of the dummy structure away from the substrate. ​

[0105] Since the dummy structure 102 is made of the same material as the circuit structure 101, and has a similar structure, the problem of uneven surface of the interlayer dielectric layer caused by different materials or uneven distribution of structures can be effectively alleviated when the interlayer dielectric layer is subsequently planarized.

[0106] However, since the size of the dummy structure 102 is fixed, the position where the dummy structure 102 is arranged is limited. When the size of the gap region between the active areas AA is smaller than the size of the smallest dummy structure 102, the gap region cannot correspond to the arrangement of the dummy structure 102. In this way, the gap region still has the above-mentioned problem. That is, the region where the dummy structure 102 is not arranged will still cause the difference in the polishing rate of the chemical mechanical polishing process.

[0107] Although it is possible to arrange the dummy structure 102 in more gap regions by designing a smaller size of the dummy structure 102. On the one hand, the process is difficult and the cost is high. On the other hand, since the dummy structure 102 is prepared after the preparation of the circuit structure 101, a certain gap (at least in the order of microns) needs to be reserved between the dummy structure 102 and the circuit structure 101 for isolation during the preparation of the dummy structure 102. Therefore, there are still many regions (for example, the above-mentioned gap) that still have the problem of difference in the polishing rate of the chemical mechanical polishing process.

[0108] To solve the above-mentioned problems, some embodiments of the present application provide a preparation method of a semiconductor device, as shown in Figure 9 , comprising:

[0109] S1, as shown in Figures 10-12 , a plurality of fins 20 are formed on a substrate 10, and the fins 20 extend along a first direction X parallel to the substrate 10.

[0110] For example, the substrate 10 can be one of bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), and SiGe-on-insulator (SGOI).

[0111] For example, the substrate 10 can be a wafer, for example, a silicon wafer.

[0112] For example, as shown in Figure 10 , the fins 20 can uniformly cover the substrate 10.

[0113] In some examples, as shown in Figure 10 , the fins 20 are arranged in a plurality of rows along the first direction X.As shown, along the first direction X, the lengths d1 of the multiple fins 20 are equal. Along the second direction Y, the widths d2 of the multiple fins 20 are equal, and the distance L1 between the centerlines O of adjacent fins 20 is equal. Wherein, as... Figure 10 As shown, the centerline O extends along the first direction X. Figure 11 As shown, the distance h1 from the top surface 21 of the multiple fins 20 to the upper surface of the substrate 10 is equal.

[0114] This configuration facilitates the fabrication of fin 20, simplifies the semiconductor device fabrication process, and also helps improve the uniformity of the structural distribution on the substrate 10 before the formation of the interlayer dielectric layer 50.

[0115] This application does not impose any restrictions on the length d1, width d2, distance L1 between the center lines O of two adjacent fins 20, or distance h1 from the top surface 21 of the fin to the upper surface of the substrate 10. These can be set according to the specific requirements of the semiconductor device and the process conditions. The number of fins 20 is also not limited in this application. Figure 10 The example uses 16 fins.

[0116] In some examples, such as Figure 13 As shown, S1, forming multiple fins 20 on the substrate 10 may include:

[0117] S11, such as Figure 14 As shown, a substrate 10a is provided.

[0118] S12, see reference Figure 12 The substrate 10a is etched to form a substrate 10 and multiple fins 20 located on the substrate 10.

[0119] For example, a mask layer can be formed on the substrate 10a, and the substrate can be etched based on the mask layer to form the substrate 10 and multiple fins 20 located on the substrate 10.

[0120] It is understood that the method of forming multiple fins 20 on the substrate 10 in this application is not limited to this.

[0121] S2, such as Figures 15-17 As shown, multiple first sacrificial gates 30 are formed in a first region S1 and multiple second sacrificial gates 40 are formed in a second region S2. The first sacrificial gates 30 and the second sacrificial gates 40 extend along a second direction Y parallel to the substrate 10, and the first direction X and the second direction Y intersect. The multiple first sacrificial gates 30 and the multiple second sacrificial gates 40 are disposed across multiple fins 20, and the second region S2 is located around the first region S1.

[0122] Exemplarily, the first and second sacrificial gates 30 and 40 are made of the same material. When the first and second sacrificial gates 30 and 40 are made of the same material, the material of the first and second sacrificial gates 30 and 40 may, for example, include at least one of polysilicon, amorphous silicon, amorphous carbon. Since the material such as polysilicon, amorphous silicon, amorphous carbon is easy to be etched, has good shape retention, and is easy to be removed, when the first and second sacrificial gates 30 and 40 are formed by at least one of polysilicon, amorphous silicon, amorphous carbon, the first and second sacrificial gates 30 and 40 can have good shape and stable structure, and are easy to be removed.

[0123] The first and second sacrificial gates 30 and 40 are made of the same material, so that the grinding rates of the first and second sacrificial gates 30 and 40 are the same during chemical mechanical grinding, thereby facilitating the improvement of the problem of uneven surface height of the interlayer dielectric layer after planarization of the interlayer dielectric layer due to different grinding rates.

[0124] In some examples, the first and second sacrificial gates 30 and 40 can be formed simultaneously based on the same mask plate.

[0125] The first direction X and the second direction Y intersect, for example, can be perpendicular to each other.

[0126] It can be understood that, referring to Figure 16 , the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 are arranged across the plurality of fins 20. That is, the plurality of first sacrificial gates 30 cover the top surface 21 of the fin 20 and the two opposite side surfaces 22 of the fin 20 in the second direction Y. The plurality of second sacrificial gates 40 also cover the top surface 21 of the fin 20 and the two opposite side surfaces 22 of the fin 20 in the second direction Y.

[0127] Exemplarily, as shown in Figure 15 , the substrate 10 includes a first region S1 and a second region S2. The first region S1 corresponds to the active area AA in the above embodiments, and the second region S2 corresponds to the blank area BB in the above embodiments.

[0128] The "second region S2 is located around the first region S1" may, for example, as shown in Figure 15 , the second region S2 surrounds the two opposite sides of the first region S1 in the first direction X, and the two opposite sides of the first region S1 in the second direction Y. Alternatively, when the first region S1 is located at the edge of the substrate 10, the second region S2 may also surround the circumferential side of the first region S1 away from the edge.

[0129] It can be understood that the first region S1 and the second region S2 do not overlap.

[0130] In some examples, referring to Figure 17 The top surface 31 of the first sacrificial gate 30 is flush or approximately flush with the top surface 41 of the second sacrificial gate 40. That is, in the third direction Z perpendicular to the substrate 10, the distance from the top surface 31 of the first sacrificial gate 30 to the upper surface of the substrate 10 and the distance from the top surface 41 of the second sacrificial gate 40 to the upper surface of the substrate 10 are both approximately h2.

[0131] In this way, the plurality of second sacrificial gates 40 are arranged around the plurality of first sacrificial gates 30, and the top surface 41 of the second sacrificial gate 40 is flush or approximately flush with the top surface 31 of the first sacrificial gate 30. When subsequently planarizing the interlayer dielectric layer, the first sacrificial gate 30 and the second sacrificial gate 40 in different regions can be ground at the same time, and it is less likely that the structure distribution is uneven in different regions of the substrate 10, resulting in different grinding rates in different regions and uneven surface height of the semiconductor device after grinding, thereby improving the yield of the semiconductor device.

[0132] In some examples, the width d3 of the first sacrificial gate 30 and the width d4 of the second sacrificial gate 40 can be equal. In other examples, the width d3 of the first sacrificial gate 30 is greater than the width d4 of the second sacrificial gate 40. In yet other examples, the width d3 of the first sacrificial gate 30 is less than the width d4 of the second sacrificial gate 40.

[0133] It can be understood that the width d3 of part of the plurality of first sacrificial gates 30 and the width d4 of the second sacrificial gate 40 can be equal, and the width d3 of another part of the plurality of first sacrificial gates 30 and the width d4 of the second sacrificial gate 40 can not be equal.

[0134] In some embodiments of the present application, the width of the first sacrificial gate 30 and the second sacrificial gate 40 is not limited and can be designed according to actual needs.

[0135] For example, along the first direction X, the width d3 of the plurality of first sacrificial gates 30 can also be equal, and the width d4 of the plurality of second sacrificial gates 40 can also be equal. In this way, it is beneficial for the preparation of the first sacrificial gate 30 and the second sacrificial gate 40, and simplifies the preparation process of the semiconductor device.

[0136] S3, as shown in Figure 18 and Figure 19 The interlayer dielectric layer 50 is formed, covering the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40.

[0137] For example, the material of the interlayer dielectric layer 50 can include one or more of silicon carbide, silicon oxycarbide, silicon nitride, silicon oxide, and silicon oxynitride.

[0138] The interlayer dielectric layer 50 is used to isolate the lower layer circuit structure (e.g., source and drain) and the upper layer circuit trace.

[0139] S4, as shown in Figures 20-22 The interlayer dielectric layer 50 is planarized to expose the surfaces of the plurality of first and second sacrificial gates 30 and 40 away from the substrate 10.

[0140] For example, the interlayer dielectric layer 50 can be planarized by a chemical mechanical polishing process.

[0141] It can be understood that the planarization of the interlayer dielectric layer 50 exposes the surfaces of the plurality of first and second sacrificial gates 30 and 40 away from the substrate 10, thereby facilitating the subsequent removal of the first and second sacrificial gates 30 and 40 to form the first and second gates.

[0142] S5, as shown in Figure 23 , Figure 24 and Figure 25 The isolation structure 60 is formed to divide the fins 20 into the first fins 201 under the plurality of first sacrificial gates 30 and the second fins 202 under the plurality of second sacrificial gates 40, and the isolation structure 60 surrounds the plurality of first fins 201 and the plurality of first sacrificial gates 30.

[0143] In the method for manufacturing the semiconductor device provided by some embodiments of the present application, the fins 20 are first arranged on the first region S1 and the second region S2 of the substrate 10 (i.e., the fins 20 uniformly cover the substrate 10), the first sacrificial gates 30 are arranged on the first region S1, and the second sacrificial gates 40 are arranged on the second region S2, then the interlayer dielectric layer 50 is formed, the interlayer dielectric layer 50 is planarized, and finally the isolation structure 60 is formed to divide the fins 20 into the first fins 201 and the second fins 202. In this way, before the planarization process, the fins 20, the first sacrificial gates 30 and the second sacrificial gates 40 are uniformly distributed on the substrate 10, so that during the planarization of the interlayer dielectric layer 50, the circuit structure on the substrate is not easily unevenly distributed, and the materials in different regions are not easily different, which can prevent the grinding speed from being different in different regions, and can prevent the surface height of the semiconductor device from being greatly different and the surface height from being uneven, thereby effectively improving the yield of the semiconductor device and improving the performance of the semiconductor device.

[0144] Meanwhile, compared with the case that the circuit structure 101 is prepared first and then the dummy structure 102 is arranged in the gap between the two adjacent circuit structures 101 in the related art, in the preparation method of the semiconductor device provided by some embodiments of the present application, the fin 20, the first sacrificial gate 30 and the second sacrificial gate are cut after the planarization of the interlayer dielectric layer, so that the isolation structure 60 is obtained, which is spaced between the first fin and the second fin, the first sacrificial gate 30 and the second sacrificial gate 40, and the size of the isolation structure 60 can be smaller, so that the subsequent other planarization process is not easily affected, and the yield of the semiconductor device is further improved, and the performance of the semiconductor device is improved.

[0145] In some embodiments, as shown in Figure 26 Step S5 of forming the isolation structure 60 includes:

[0146] S51, as shown in Figure 27 and Figure 28 , etching the second sacrificial gate 40 and the fin 20 in the first preset area S3 to form a first isolation groove 601. Along the second direction Y, the first preset area S3 is located on one side of the plurality of first sacrificial gates 30, and the first isolation groove 601 extends along the first direction X.

[0147] For example, the wet etching or dry etching process can be used to etch the second sacrificial gate 40 and the fin 20 in the first preset area S3 to form the first isolation groove 601.

[0148] S52, as shown in Figure 24 and Figure 29 , a first isolation part 61 is formed in the first isolation groove 601.

[0149] For example, the material of the first isolation part 61 can be oxide or nitride.

[0150] For example, after the first isolation part 61 is formed, the semiconductor device can be subjected to a planarization process to remove the material of the first isolation part 61 located outside the first isolation groove 601.

[0151] S53, as shown in Figure 30 , etching the interlayer dielectric layer 50 and the fin 20 in the second preset area S4 to form a second isolation groove 602. Along the first direction X, the second preset area S4 is located on one side of the plurality of first sacrificial gates 30, and the second isolation groove 602 extends along the second direction Y.

[0152] For example, the wet etching or dry etching process can be used to etch the interlayer dielectric layer 50 and the fin 20 in the second preset area S4 to form the second isolation groove 602.

[0153] S54, as shown in Figure 23 andFigure 25 The second isolation part 62 is formed in the second isolation groove 602.

[0154] The isolation structure 60 includes the first isolation part 61 and the second isolation part 62.

[0155] For example, the material of the second isolation part 62 can be oxide or nitride.

[0156] In some examples, the material of the first isolation part 61 can be the same as the material of the second isolation part 62.

[0157] For example, after the second isolation part 62 is formed, a planarization process can be performed on the semiconductor device to remove the material of the second isolation part 62 outside the second isolation groove 602.

[0158] It can be understood that the application does not limit the order of forming the first isolation part 61 and the second isolation part 62. For example, the first isolation groove 601 can be formed, the first isolation part 61 is formed in the first isolation groove 601, and then the second isolation groove 602 is formed, and the second isolation part 62 is formed in the second isolation groove 602. Alternatively, for example, the second isolation groove 602 can be formed first, the second isolation part 62 is formed in the second isolation groove 602, and then the first isolation groove 601 is formed, and the first isolation part 61 is formed in the first isolation groove 601.

[0159] In some embodiments of the application, by forming the first isolation groove 601 on one side of the plurality of first sacrificial gates 30 in the second direction Y, and forming the first isolation part 61 in the first isolation groove 601, the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 adjacent in the second direction Y can be better spaced apart, and then after replacing the first sacrificial gate 30 with the first gate and replacing the second sacrificial gate 40 with the second gate, the first gate and the second gate adjacent in the second direction Y can be better spaced apart.

[0160] Similarly, by forming the second isolation groove 602 on one side of the plurality of first sacrificial gates 30 in the first direction X, and forming the second isolation part 62 in the second isolation groove 602, the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 adjacent in the first direction X can be better spaced apart, and then after replacing the first sacrificial gate 30 with the first gate and replacing the second sacrificial gate 40 with the second gate, the first gate and the second gate adjacent in the first direction X can be better spaced apart, and the use performance of the first gate can be ensured.

[0161] In some embodiments of the present application, the first isolation groove 601 and the second isolation groove 602 are prepared separately, so that the accuracy of the size of the first isolation groove 601 and the second isolation groove 602 can be ensured in the development process of the continuous reduction of the semiconductor process node, and the problem of large difference between the required size (size in the first direction X and / or size in the second direction Y) of the first isolation groove 601 and the second isolation groove 602 and the actual prepared size due to the reduction of the semiconductor size can be avoided.

[0162] In some embodiments, as shown in FIG. 6A, the size d5 of the first isolation part 61 in the second direction Y is less than or equal to twice the distance L1 between the center lines O of the adjacent two fins 20. Figure 23

[0163] As shown in FIG. 6B, the center line O of the fin 20 extends in the first direction X. Figure 23

[0164] By such arrangement, the size d5 of the first isolation part 61 in the second direction Y is small, and even if the grinding rate of the area where the first isolation part 61 is located is different from the grinding rate of the area where the first gate and the second gate are located due to the difference between the first isolation part 61 and the first gate and the second gate material during subsequent other grinding process, the problem of different height after grinding of the area where the first isolation part 61 is located and the area where the first gate and the second gate are located, and the area of the recessed or protruding part in the semiconductor device is also small, and the semiconductor device is not easy to fail or have defects.

[0165] In some embodiments, as shown in FIG. 6A, the size d5 of the first isolation part 61 in the second direction Y is less than or equal to twice the distance L1 between the center lines O of the adjacent two fins 20. Figure 31 As shown in FIG. 6B, the center line O of the fin 20 extends in the first direction X.

[0166] As shown in FIG. 6A, the substrate 10 is provided with at least one first sacrificial gate group 301, and the first sacrificial gate group 301 includes a plurality of first sacrificial gates 30. The size d6 of the second isolation part 62 in the first direction X is less than or equal to twice the distance L2 between the center lines P of the adjacent two first sacrificial gates 30 in the first sacrificial gate group 301 adjacent to the second isolation part 62.

[0167] As shown in FIG. 6B, the center line P of the first sacrificial gate 30 extends in the second direction Y. Figure 23 Figure 31 As shown in FIG. 6A, the substrate 10 is provided with at least one first sacrificial gate group 301, and the first sacrificial gate group 301 includes a plurality of first sacrificial gates 30. The size d6 of the second isolation part 62 in the first direction X is less than or equal to twice the distance L2 between the center lines P of the adjacent two first sacrificial gates 30 in the first sacrificial gate group 301 adjacent to the second isolation part 62. Figure 21 For example, the substrate is provided with four first sacrificial gate groups 301. In the clockwise direction, the four first sacrificial gate groups 301 are respectively the first group 3011, the second group 3012, the third group 3013 and the fourth group 3014.

[0168] ​​​When a plurality of first sacrificial gate groups 301 are provided on the substrate 10, each first sacrificial gate group 301 can correspond to a first region S1.

[0169] When a plurality of first sacrificial gate groups 301 are provided on the substrate 10, the widths d3 of the first sacrificial gates 30 in the same first sacrificial gate group 301 can be the same. The widths d3 of the first sacrificial gates 30 in different first sacrificial gate groups 301 can be the same or different. Figure 31 An example is given in the case where the widths of the first sacrificial gates 30 in different first sacrificial gate groups 301 are different.

[0170] Different first sacrificial gate groups 301 can be used to construct different circuit structures, which can have different performance and be used to implement different functions. For example, the circuit structures can be driving circuit structures, pixel circuits, amplification circuit structures, power management circuit structures, charge protection circuit structures, control circuit structures, and image sensor circuit structures. The present application is not limited in this regard.

[0171] The number of first sacrificial gates 30 in different first sacrificial gate groups 301 is not limited in the present application. For example, as shown in FIG. 6, four first sacrificial gate groups 301 can respectively include 5 first sacrificial gates 30, 7 first sacrificial gates 30, 8 first sacrificial gates 30, and 11 first sacrificial gates 30. Figure 21

[0172] In some embodiments of the present application, the size d6 of the second isolation portion 62 in the first direction X is small, and the area of the upper surface of the second isolation portion 62 is also small. Therefore, even if the grinding rate of the area where the second isolation portion 62 is located is different from the grinding rate of the area where the first gate and the second gate are located due to the difference in material between the second isolation portion 62 and the first gate and the second gate during subsequent other grinding processes, the problem of different heights after grinding of the area where the second isolation portion 62 is located and the area where the first gate and the second gate are located does not occur, and the area of the recessed or protruding part in the semiconductor device is also small, and the semiconductor device is not prone to failure or defects.

[0173] In some examples, when a plurality of first sacrificial gate groups 301 are provided on the substrate 10, the distance L2 between the center lines P of two adjacent first sacrificial gates 30 in different first sacrificial gate groups 301 can not be equal.

[0174] In some embodiments, referring to FIG. 6, when a plurality of first sacrificial gate groups 301 are provided on the substrate 10, the size d6 of the second isolation portion 62 in the first direction X is less than or equal to twice the minimum value of the distance L2 between the center lines P of two adjacent first sacrificial gates 30 in the plurality of first sacrificial gate groups 301. Figure 31

[0175] ​​With this configuration, the second isolation portion 62 is smaller in size in the first direction X, and the area of ​​the upper surface of the second isolation portion 62 is also smaller. After subsequent polishing processes, the area of ​​the depressions or protrusions that may appear in the semiconductor device is also smaller, and the semiconductor device is less likely to fail or malfunction.

[0176] In some embodiments, such as Figure 32 As shown, step S51, etching the second sacrificial gate 40 and fin 20 within the first preset region S3 to form the first isolation trench 601, includes:

[0177] S511, such as Figure 33 As shown, a first mask layer 51 is formed on the interlayer dielectric layer 50. The first mask layer 51 includes a first opening 511, which extends along a first direction X and exposes a plurality of second sacrificial gates 40 near the ends 42 of a plurality of first sacrificial gates 30.

[0178] For example, the first mask layer 51 can be a hard mask.

[0179] It is understandable that the first opening 511 corresponds to the first preset area S3.

[0180] For example, the first opening 511 in the first mask layer 51 can be obtained by forming a photoresist layer on the first mask layer 51, patterning the photoresist layer, and then etching the first mask layer 51 based on the patterned photoresist layer.

[0181] S512, such as Figure 34 As shown, the exposed ends 42 of multiple second sacrificial gates 40 and the fins 20 below the ends 42 are etched through the first opening 511 to form a first isolation groove 601.

[0182] In some embodiments, such as Figure 35 As shown, before step S2, which involves forming multiple first sacrificial gates 30 and multiple second sacrificial gates 40, the fabrication method further includes:

[0183] S21, such as Figure 36 and Figure 37 As shown, an insulating layer 70 is formed on the substrate 10, with a portion of the fin 20 embedded in the insulating layer 70 and the remainder protruding from the upper surface 71 of the insulating layer 70.

[0184] For example, the material of the insulating layer 70 may include a binary or multi-component compound composed of elements such as silicon (Si), carbon (C), nitrogen (N), and oxygen (O), for example, it may include silicon carbon oxynitride (SiC). x O y N z ), silicon dioxide (SiC) x O ySilicon nitride (SiN) x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y At least one of the following. Alternatively, the material of the insulating layer 70 may also contain one or more of the following elements: hydrogen (H), fluorine (F), chlorine (Cl).

[0185] For example, an insulating material can be deposited first, and then the insulating material can be planarized so that the surface of the insulating material away from the substrate is flush or nearly flush with the top surface of the fin. Then, an etch-back process can be used to control the thickness of the insulating layer 70 by controlling the etch-back time, so that the upper surface 71 of the insulating layer 70 is lower than the top surface 21 of the fin 20.

[0186] It is understandable that since the fins 20 are uniformly laid on the substrate 10, the grinding rate of different areas is roughly the same when the insulating material is planarized, resulting in unevenness on the surface of the semiconductor device after the insulating material is planarized.

[0187] In some examples, after the insulating layer 70 is formed and before the formation of multiple first sacrificial gates 30 and multiple second sacrificial gates 40, a gate oxide layer may also be formed, the gate oxide layer being located between the fin 20 and the first sacrificial gate 30, and between the fin 20 and the second sacrificial gate 40.

[0188] In some embodiments, such as Figure 38 As shown, step S512 involves etching the exposed ends 42 of multiple second sacrificial gates 40 and the fins 20 below the ends 42 through the first opening 511 to form a first isolation groove 601, including:

[0189] S5121, such as Figure 39 As shown, the ends 42 of the multiple second sacrificial gates 40 exposed by the first opening 511 are etched, exposing the fins 20 below the ends 42.

[0190] S5122, such as Figure 34 As shown, fin 20 is etched to form a first recess 603 in the insulating layer 70 and a second recess 604 on the insulating layer.

[0191] The first isolation groove 601 includes a first recess 603 and a second recess 604.

[0192] In some embodiments, such as Figure 40 As shown, the first isolation groove 601 includes a plurality of isolation sub-grooves 605 arranged at intervals along the first direction X. Each isolation sub-groove 605 includes a first groove 603 and a second groove 604.

[0193] In some embodiments, such as Figure 41As shown, step S53, etching the interlayer dielectric layer 50 and the fin 20 in the second preset region S4 to form a second isolation groove 602, including:

[0194] S531, as Figure 42 shown, a second mask layer 52 is formed on the interlayer dielectric layer 50, the second mask layer 52 includes a second opening 521, the second opening 521 extends along the second direction Y, and exposes the interlayer dielectric layer 50 between the first target sacrificial gate 32 and the second target sacrificial gate 42. The first target sacrificial gate 32 and the second target sacrificial gate 42 are the closest first sacrificial gate 30 and second sacrificial gate 40 in the plurality of first sacrificial gate 30 and the plurality of second sacrificial gate 40 along the first direction X.

[0195] Exemplarily, the second mask layer 52 can be a hard mask.

[0196] It can be understood that the second opening 521 corresponds to the second preset region S4.

[0197] Exemplarily, the second opening 521 in the second mask layer 52 can be obtained by forming a photoresist layer on the second mask layer 52, patterning the photoresist layer, and then etching the second mask layer 52 based on the patterned photoresist layer.

[0198] S532, as Figure 43 shown, the exposed interlayer dielectric layer 50 and the fin 20 below the interlayer dielectric layer 50 are etched via the second opening 521 to form a second isolation groove 602.

[0199] In this way, during the formation of the second isolation groove 602, the material etched is less, and the etching process is simple, which is conducive to improving the preparation efficiency of the semiconductor device.

[0200] In some embodiments, as Figure 44 shown, before step S3, forming the interlayer dielectric layer 50, the preparation method further includes:

[0201] S31, referring to Figure 21 , a dielectric layer 11 is formed, the dielectric layer 11 covers two opposite sides of the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 in the first direction X.

[0202] Exemplarily, the dielectric layer 11 can be formed after the first sacrificial gate 30 and the second sacrificial gate 40 are formed.

[0203] Exemplarily, the material of the dielectric layer 11 can include silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride, etc.

[0204] In some examples, the dielectric layer 11 can be a single-layer structure, and in other examples, the dielectric layer 11 can be a multi-layer structure.

[0205] The medium layer 11 can be used to protect the first and second sacrificial gates 30 and 40. After the first and second sacrificial gates 30 and 40 are replaced by the first and second gates respectively, the medium layer 11 can also be used to protect the first and second gates.

[0206] In some examples, the medium layer 11 can be a material with low dielectric constant. In this way, after the first and second gates are formed, the medium layer 11 can also be used to reduce the coupling capacitance between two adjacent first gates in the first direction X, and improve the stability of the circuit structure in the semiconductor device.

[0207] S32, referring to Figure 21 The source 12 and the drain 13 are formed on the fin 20. In the first direction X, the source 12 and the drain 13 are respectively located on the two sides of the first and second sacrificial gates 30 and 40.

[0208] In an example, the source 12 and the drain 13 can be formed on the fin 20 after the medium layer 11 is formed after the first and second sacrificial gates 30 and 40 are formed.

[0209] In an example, the source 12 and the drain 13 can be formed on the fin 20 by epitaxial growth.

[0210] S33, an etching stop layer 14 is formed, covering the medium layer 11, the source 12 and the drain 13.

[0211] In an example, the etching stop layer 14 can be formed after the source 12 and the drain 13 are formed on the fin 20 and before the interlayer dielectric layer 50 is formed.

[0212] Based on this, in some embodiments, as shown in Figure 45 S532, via the second opening 521, the exposed interlayer dielectric layer 50 and the fin 20 under the interlayer dielectric layer 50 are etched to form a second isolation groove 602, including:

[0213] S5321, as shown in Figure 46 The exposed interlayer dielectric layer 50 is etched to expose the etching stop layer 14 under the interlayer dielectric layer 50.

[0214] S5322, as shown in Figure 47 The exposed etching stop layer 14 is etched to expose the source 12 or the drain 13 under the etching stop layer 14.

[0215] In some examples, as shown in Figure 47As shown, after etching the exposed etching stop layer 14, the exposed can be the source 12. Alternatively, in other examples, after etching the exposed etching stop layer 14, the exposed can be the drain 13.

[0216] S5323、refer to Figure 43 , etching the exposed source 12 or drain 13, and the fin 20 under the source 12 or drain 13, to form the second isolation groove 602.

[0217] In some embodiments, as Figure 48 shown, the second opening 521 also exposes part of the surface of the first target sacrificial gate 32 close to the second target sacrificial gate 42, and part of the surface of the second target sacrificial gate 42 close to the first target sacrificial gate 32.

[0218] In this way, in the process of step S532, etching the exposed interlayer dielectric layer 50 and the fin 20 under the interlayer dielectric layer 50 via the second opening 521 to form the second isolation groove 602, the first target sacrificial gate 32 and the second target sacrificial gate 42 are also etched.

[0219] By setting in this way, the size of the second opening 521 in the first direction X is larger, and the process of patterning the second mask layer 52 is simpler. At the same time, the size of the second isolation groove 602 in the first direction X is also larger, and the size of the second isolation part 62 formed in the first direction X is larger, so that it can better isolate the first sacrificial gate 30 and the second sacrificial gate 40 adjacent in the first direction X, thereby better isolating the first gate and the second gate adjacent in the first direction X.

[0220] In some embodiments, as Figure 48 shown, the medium layer 11 covering the side surface of the first target sacrificial gate 32 close to the second target sacrificial gate 42 is the first target medium layer 111, the etching stop layer 14 covering the first target medium layer 111 is the first target etching stop layer 141, the medium layer 11 covering the side surface of the second target sacrificial gate 42 close to the first target sacrificial gate 32 is the second target medium layer 112, and the etching stop layer 14 covering the second target medium layer 112 is the second target etching stop layer 142.

[0221] The second opening 521 also exposes the end surface of the first target medium layer 111, the first target etching stop layer 141, the second target medium layer 112, and the second target etching stop layer 142 away from the substrate 10.

[0222] Based on this, in some embodiments, as Figure 49 shown, step S53, etching the interlayer dielectric layer 50 and the fin 20 in the second predetermined area S4 to form the second isolation groove 602, includes:

[0223] S533, asFigure 50 As shown, via the second opening 521, the first target sacrificial gate 32, the first target dielectric layer 111, the first target etching stop layer 141, the second target sacrificial gate 42, the second target dielectric layer 112, the second target etching stop layer 142, and the interlayer dielectric layer 50 between the first target sacrificial gate 32 and the second target sacrificial gate 42 are synchronously etched to form a third recess 606. In a direction perpendicular to the substrate 10, a bottom surface of the third recess 606 has a spacing L3 from an upper surface of the source 12 or the drain 13 between the first target sacrificial gate 32 and the second target sacrificial gate 42.

[0224] S534, as shown in Figure 51 The remaining first target dielectric layer 111, the first target etching stop layer 141, the second target dielectric layer 112, and the second target etching stop layer 142 are etched.

[0225] S535, as shown in Figure 52 The remaining interlayer dielectric layer 50 between the first target sacrificial gate 32 and the second target sacrificial gate 42 is etched to expose the etching stop layer 14 below the interlayer dielectric layer 50.

[0226] S536, as shown in Figure 53 The remaining first target sacrificial gate 32 and the second target sacrificial gate 42, the exposed etching stop layer 14, the source 12 or the drain 13 below the etching stop layer 14, and the fin 20 below the source 12 or the drain 13 are etched to form a second isolation groove 602.

[0227] It can be understood that the method for forming the second isolation groove 602 is not limited to this in the embodiments of the present application.

[0228] In some embodiments, referring to Figure 15 Before the isolation structure 60 is formed, there is a gap d7 between the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 in the second direction Y. The gap d7 is less than or equal to the distance L1 between the center lines O of the adjacent two fins 20.

[0229] In this way, the gap d7 between the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 is less than or equal to the distance L1 between the center lines O of the adjacent two fins 20, so that the sacrificial gate structure (the first sacrificial gate or the second sacrificial gate) is arranged on each fin 20, and the sacrificial gate structure is more uniformly distributed on the substrate, thereby facilitating improvement of the problems such as unevenness of the surface of the semiconductor device, failure or poor performance of the semiconductor device, and the like after the planarization of the interlayer dielectric layer due to uneven distribution of the sacrificial gate structure on the substrate.

[0230] In some embodiments, as shown in Figure 54 The preparation method further includes:

[0231] S6, such as Figure 55 As shown, the first sacrificial gate 30 is replaced with the first gate 30a, and the second sacrificial gate 40 is replaced with the second gate 40a.

[0232] In some embodiments, the first gate 30a may be a single-layer structure, and in this case, for example, the material of the first gate 30a may include a metallic material.

[0233] In other embodiments, the first gate 30a may be a multilayer structure, in which case, for example, the first gate 30a may include a metal layer and a high dielectric constant insulating layer.

[0234] Similarly, in some embodiments, the second gate 40a can be a single-layer structure. In this case, for example, the material of the second gate 40a may include a metallic material.

[0235] In other embodiments, the second gate 40a may be a multilayer structure, in which case, for example, the second gate 40a may include a metal layer and a high dielectric constant insulating layer.

[0236] like Figure 55 As shown, in some embodiments of this application, a semiconductor device 100 is provided. The semiconductor device 100 includes a substrate 10, a plurality of first fins 201, a plurality of second fins 202, a plurality of first gates 30a, a plurality of second gates 40a, an interlayer dielectric layer 50, and an isolation structure 60. The plurality of first fins 201 and the plurality of second fins 202 are disposed on the substrate 10 and extend along a first direction X parallel to the substrate 10.

[0237] For example, a first fin 201 is disposed on a first region S1 of the substrate 10. A second fin 202 is disposed on a second region S2 of the substrate 10.

[0238] In some examples, the width of each of the multiple first fins 201 can be equal.

[0239] In some examples, the width of each of the multiple second fins 202 can be equal.

[0240] It is understood that the width of the first fin 201 is the same as the width of the aforementioned fin 20. The width of the second fin 202 is the same as the width of the aforementioned fin 20. Therefore, in some examples, the width of the first fin 201 and the width of the second fin 202 can be equal.

[0241] In some examples, the spacing between any two adjacent first fins 201 in a plurality of first fins 201 can be equal.

[0242] In some examples, the spacing between any two adjacent second fins 202 in a plurality of second fins 202 can be equal.

[0243] In this way, the fabrication of the first fins 201 and the second fins 202 can be facilitated, and the preparation process of the semiconductor device can be simplified.

[0244] The plurality of first gates 30a and the plurality of second gates 40a extend along a second direction Y parallel to the substrate 10, and the first direction X intersects the second direction Y. The plurality of first gates 30a are disposed across the plurality of first fins 201, and the plurality of second gates 40a are disposed across the plurality of second fins 202.

[0245] For example, the first gates 30a are disposed on the first region S1 of the substrate 10. The second gates 40a are disposed on the second region S2 of the substrate 10.

[0246] In some examples, the widths of the plurality of second gates 40a can be equal.

[0247] In some examples, the spacing between any two adjacent second gates 40a can be equal.

[0248] In this way, the preparation of the second gates 40a can be facilitated, and the preparation process of the semiconductor device can be simplified.

[0249] The interlayer dielectric layer 50 covers the regions between the plurality of first gates 30a and the regions between the plurality of second gates 40a, and exposes the surfaces of the plurality of first gates 30a and the plurality of second gates 40a away from the substrate 10.

[0250] The isolation structure 60 separates the plurality of first fins 201 and the plurality of second fins 202, and separates the plurality of first gates 30a and the plurality of second gates 40a, and surrounds the plurality of first fins 201 and the plurality of first gates 30a.

[0251] In some examples, the plurality of first fins 201 and the plurality of second fins 202 are made of the same material and are disposed in the same layer, and the plurality of first gates 30a and the plurality of second gates 40a are made of the same material and are disposed in the same layer.

[0252] It should be noted that, the plurality of first fins 201 and the plurality of second fins 202 are made of the same material and are disposed in the same layer, and the plurality of first gates 30a and the plurality of second gates 40a are made of the same material and are disposed in the same layer, that is, the first fins 201 and the second fins 202 are simultaneously prepared and formed, and are both obtained by dividing the fins 20. The first gates 30a and the second gates 40a are simultaneously prepared and formed.

[0253] It can be understood that the semiconductor device provided by some embodiments of the present application is prepared by the preparation method described in any of the above embodiments. Therefore, the semiconductor device provided by some embodiments of the present application can achieve the same beneficial effects as the preparation method described in any of the above embodiments.

[0254] In some embodiments, as Figure 55As shown, the isolation structure 60 includes a first isolation part 61 and a second isolation part 62.

[0255] The first isolation part 61 extends along the first direction X and is located on one side of the plurality of first gates 30a along the second direction Y. The second isolation part 62 extends along the second direction Y and is located on one side of the plurality of first gates 30a along the first direction X.

[0256] By such arrangement, the isolation structure 60 is arranged around the first gate 30a, so that the first gate 30a can be better separated from the second gate 40a, and the normal operation of the first gate 30a is ensured.

[0257] In some embodiments as shown in Figure 56 The first isolation part 61 includes a plurality of sub-isolation parts 63 arranged along the first direction X, the sub-isolation parts 63 are located on the extension line of the second gate 40a, and the width of the sub-isolation part 63 in the first direction X is equal to the width of the second gate 40a in the first direction X.

[0258] In some embodiments as shown in Figure 57 The semiconductor device 100 further includes an insulating layer 70. Part of the plurality of first fins 201 and the plurality of second fins 202 are embedded in the insulating layer 70, and the rest protrude from the upper surface 71 of the insulating layer 70. The sub-isolation part 63 includes a first part 631 embedded in the insulating layer 70 and a second part 632 located on the insulating layer 70. The size of the first part 631 in the second direction Y is equal to the size of the second fin 202 in the second direction Y.

[0259] In some embodiments as shown in Figure 58 Along the first direction X, the closest first gate 30a and the closest second gate 40a in the plurality of first gates 30a and the plurality of second gates 40a are respectively the first target gate 31a and the second target gate 41a. The semiconductor device 100 further includes a first target dielectric layer 111, a first target etching stop layer 141, a second target dielectric layer 112, and a second target etching stop layer 142.

[0260] The first target dielectric layer 111 covers the side of the first target gate 31a close to the second target gate 41a. The first target etching stop layer 141 covers the first target dielectric layer 111. The second target dielectric layer 112 covers the side of the second target gate 41a close to the first target gate 31a. The second target etching stop layer 142 covers the second target dielectric layer 112. Among them, along the first direction X, the second isolation part 62 is located between the first target etching stop layer 141 and the second target etching stop layer 142.

[0261] It can be understood that in the process of etching the interlayer dielectric layer 50, the etching stop layer 14, the source electrode 12 or the drain electrode 13, and the fin 20 under the source electrode 12 or the drain electrode 13 in steps S5321-S5323, partial erosion of the etching stop layer 14 covering the first target sacrificial gate 32 and the second target sacrificial gate 42 is inevitable, so that the first target etching stop layer 141 and the second target etching stop layer 142 in the obtained semiconductor device 100 are thinner than the etching stop layer covering the other first gate 30a or second gate 40a.

[0262] In some embodiments, as shown in FIG. 1, the semiconductor device 100 further includes a first dielectric layer 113, a second dielectric layer 114, a first etching stop layer 143, and a second etching stop layer 144. Figure 59

[0263] The first dielectric layer 113 and the second dielectric layer 114 cover two opposite sides of the second isolation portion 62 in the first direction X, respectively. The first etching stop layer 143 covers the first dielectric layer 113, and the second etching stop layer 144 covers the second dielectric layer 114.

[0264] In some embodiments, as shown in FIG. 1, the semiconductor device 100 further includes a first dielectric layer 113, a second dielectric layer 114, a first etching stop layer 143, and a second etching stop layer 144. Figure 55 In this way, by arranging the isolation structure 60 on both sides of the plurality of first gates 30a in the first direction X and on both sides of the plurality of first gates 30a in the second direction Y, the first gate 30a and the second gate 40a are better isolated, the working performance of the first gate 30a is ensured, and the use performance of the semiconductor device 100 is improved.

[0265] In some embodiments, as shown in FIG. 1, the semiconductor device 100 further includes a first dielectric layer 113, a second dielectric layer 114, a first etching stop layer 143, and a second etching stop layer 144.

[0266] Figure 59 In some embodiments, as shown in FIG. 1, the semiconductor device 100 further includes a first dielectric layer 113, a second dielectric layer 114, a first etching stop layer 143, and a second etching stop layer 144.

[0267] In some embodiments, as shown in FIG. 1, the semiconductor device 100 further includes a first dielectric layer 113, a second dielectric layer 114, a first etching stop layer 143, and a second etching stop layer 144. Figure 56 ​​As shown, the first isolation part 61 has a dimension d8 in the second direction Y that is less than or equal to twice a distance L4 between center lines M of two adjacent first fins 20.

[0268] The center line M of the first fin 20 extends along the first direction X.

[0269] In this way, the first isolation part 61 has a small dimension d8 in the second direction Y, so that after the first isolation part 61 is formed, the first isolation part 61 has less impact on a subsequent planarization process, which is conducive to improving the yield of the semiconductor device and improving the performance of the semiconductor device.

[0270] In some embodiments, referring to Figure 56 The substrate 10 is provided with at least one first gate group 301a, and the first gate group 301a includes a plurality of first gates 30a. The second isolation part 62 has a dimension d9 in the first direction X that is less than or equal to twice a distance L5 between center lines N of two adjacent first gates 30a in a first gate group 301a adjacent to the second isolation part 62.

[0271] The center line N of the first gate 30a extends along the second direction Y.

[0272] In this way, the second isolation part 62 has a small dimension d9 in the first direction X, so that after the second isolation part 62 is formed, the second isolation part 62 has less impact on a subsequent planarization process, which is conducive to improving the yield of the semiconductor device and improving the performance of the semiconductor device.

[0273] As Figure 60 shown, some embodiments of the present application also provide an electronic device 1000, such as a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product. The consumer electronic product is, for example, a mobile phone, a tablet computer, a notebook computer, an e-book reader, a personal computer (PC), a personal digital assistant (PDA), a desktop display, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, etc. The home electronic product is, for example, a smart door lock, a television, a remote controller, a refrigerator, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), etc. The vehicle-mounted electronic product is, for example, a vehicle-mounted navigation device, a vehicle-mounted DVD, etc. The financial terminal product is, for example, an ATM machine, a self-service terminal, etc. The embodiments of the present application do not specially limit the specific form of the above electronic device.

[0274] The electronic device 1000 described above can include a semiconductor device 100 and a printed circuit board (PCB) 200 and the like, and the semiconductor device 100 is electrically connected with the printed circuit board 200 to realize signal intercommunication.

[0275] The electronic device 1000 provided by some embodiments of the present application can achieve the same technical effects as the preparation method of the semiconductor device described in any of the above embodiments, and will not be repeated here.

[0276] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The preparation method comprises: forming a plurality of fins on a substrate, the fins extending along a first direction parallel to the substrate; forming a plurality of first sacrificial gates located in a first region and a plurality of second sacrificial gates located in a second region, the first sacrificial gates and the second sacrificial gates extending along a second direction parallel to the substrate, the first direction and the second direction intersecting; the plurality of first sacrificial gates and the plurality of second sacrificial gates are arranged across the plurality of fins, and the second region is around the first region; forming an interlayer dielectric layer covering the plurality of first sacrificial gates and the plurality of second sacrificial gates; planarizing the interlayer dielectric layer to expose surfaces of the plurality of first sacrificial gates and the plurality of second sacrificial gates away from the substrate; forming an isolation structure, the isolation structure separates the fins into first fins located below the plurality of first sacrificial gates and second fins located below the plurality of second sacrificial gates, the isolation structure surrounds the plurality of first fins and the plurality of first sacrificial gates.

2. The production method according to claim 1, characterized by, The forming of the isolation structure comprises: etching the second sacrificial gates and the fins in a first preset region to form a first isolation groove; along the second direction, the first preset region is located on one side of the plurality of first sacrificial gates, and the first isolation groove extends along the first direction; forming a first isolation portion in the first isolation groove; etching the interlayer dielectric layer and the fins in a second preset region to form a second isolation groove; along the first direction, the second preset region is located on one side of the plurality of first sacrificial gates, and the second isolation groove extends along the second direction; forming a second isolation portion in the second isolation groove; The isolation structure comprises the first isolation portion and the second isolation portion.

3. The preparation method according to claim 2, characterized in that, The size of the first isolation portion in the second direction is less than or equal to twice the distance between the center lines of two adjacent fins; and / or, The substrate is provided with at least one first sacrificial gate group, the first sacrificial gate group comprises the plurality of first sacrificial gates; the size of the second isolation portion in the first direction is less than or equal to twice the distance between the center lines of two adjacent first sacrificial gates in the first sacrificial gate group adjacent to the second isolation portion.

4. The production method according to claim 2, characterized by, The etching of the second sacrificial gates and the fins in the first preset region to form the first isolation groove comprises: forming a first mask layer on the interlayer dielectric layer, the first mask layer comprises a first opening, the first opening extends along the first direction, and exposes the end of the plurality of second sacrificial gates close to the plurality of first sacrificial gates; etching the end of the plurality of second sacrificial gates exposed via the first opening and the fins below the end to form the first isolation groove.

5. The preparation method according to claim 4, characterized in that, Before the forming of the plurality of first sacrificial gates and the plurality of second sacrificial gates, the preparation method further comprises: forming an insulating layer on the substrate, part of the fins is embedded in the insulating layer, and the remaining part protrudes above the surface of the insulating layer; The etching of the end of the plurality of second sacrificial gates exposed via the first opening and the fins below the end to form the first isolation groove comprises: etching end portions of the plurality of second sacrificial gates exposed by the first opening to expose fins under the end portions; etching the fins to form a first recess in the insulating layer and a second recess on the insulating layer; wherein the first isolation groove comprises the first recess and the second recess.

6. The preparation method according to claim 2, characterized in that, The etching the interlayer dielectric layer and the fins in the second preset region to form the second isolation groove comprises: forming a second mask layer on the interlayer dielectric layer, the second mask layer comprising a second opening, the second opening extending along the second direction and exposing the interlayer dielectric layer between a first target sacrificial gate and a second target sacrificial gate; the first target sacrificial gate and the second target sacrificial gate being the closest first sacrificial gate and second sacrificial gate in the plurality of first sacrificial gates and the plurality of second sacrificial gates along the first direction; etching the exposed interlayer dielectric layer and the fins under the interlayer dielectric layer via the second opening to form the second isolation groove.

7. The production method according to claim 6, wherein Before the forming the interlayer dielectric layer, the preparation method further comprises: forming a dielectric layer covering two opposite sides of the plurality of first sacrificial gates and the plurality of second sacrificial gates in the first direction; forming a source and a drain on the fins; along the first direction, the source and the drain are respectively located on two sides of the first sacrificial gate and two sides of the second sacrificial gate; forming an etching stop layer covering the dielectric layer and the source and the drain.

8. The method of claim 7, wherein, The etching the interlayer dielectric layer and the fins in the second preset region to form the second isolation groove comprises: etching the interlayer dielectric layer exposed by the second opening to expose the etching stop layer under the interlayer dielectric layer; etching the exposed etching stop layer to expose the source or the drain under the etching stop layer; etching the exposed source or drain and the fins under the source or the drain to form the second isolation groove.

9. The preparation method according to claim 7, characterized in that, The second opening also exposes a part of the surface of the first target sacrificial gate close to the second target sacrificial gate and a part of the surface of the second target sacrificial gate close to the first target sacrificial gate; In the process of etching the exposed interlayer dielectric layer and the fins under the interlayer dielectric layer via the second opening to form the second isolation groove, the first target sacrificial gate and the second target sacrificial gate are also etched.

10. The method of claim 9, wherein, The dielectric layer covering the side of the first target sacrificial gate close to the second target sacrificial gate is a first target dielectric layer, the etching stop layer covering the first target dielectric layer is a first target etching stop layer, the dielectric layer covering the side of the second target sacrificial gate close to the first target sacrificial gate is a second target dielectric layer, and the etching stop layer covering the second target dielectric layer is a second target etching stop layer; The second opening also exposes end surfaces of the first target dielectric layer, the first target etching stop layer, the second target dielectric layer and the second target etching stop layer away from the substrate; The etching the interlayer dielectric layer and the fins in the second preset region to form the second isolation groove comprises: Synchronously etching the first target sacrificial gate, the first target dielectric layer, the first target etching stop layer, the second target sacrificial gate, the second target dielectric layer, the second target etching stop layer, and the interlayer dielectric layer between the first target sacrificial gate and the second target sacrificial gate via the second opening to form a third recess, the bottom surface of the third recess and the upper surface of the source or drain between the first target sacrificial gate and the second target sacrificial gate having a spacing in a direction perpendicular to the substrate; Etching the remaining first target dielectric layer, first target etching stop layer, second target dielectric layer, and second target etching stop layer; Etching the remaining interlayer dielectric layer between the first target sacrificial gate and the second target sacrificial gate to expose the etching stop layer below the interlayer dielectric layer; Etching the remaining first target sacrificial gate and second target sacrificial gate, the exposed etching stop layer, the source or drain below the etching stop layer, and the fin below the source or drain to form a second isolation groove.

11. The production method according to any one of claims 1 to 10, characterized by, Before forming the isolation structure, there is a gap between the plurality of first sacrificial gates and the plurality of second sacrificial gates in the second direction; The gap is less than or equal to the distance between the center lines of two adjacent fins.

12. The production method according to any one of claims 1 to 10, characterized by, The preparation method further comprises: Replacing the first sacrificial gate with a first gate and replacing the second sacrificial gate with a second gate.

13. A semiconductor device, characterized by comprising: Comprise: A substrate; A plurality of first fins and a plurality of second fins disposed on the substrate and extending in a first direction parallel to the substrate; A plurality of first gates and a plurality of second gates extending in a second direction parallel to the substrate, the first direction intersecting the second direction; the plurality of first gates being disposed across the plurality of first fins, and the plurality of second gates being disposed across the plurality of second fins; An interlayer dielectric layer covering the areas between the plurality of first gates and the areas between the plurality of second gates, exposing the surfaces of the plurality of first gates and the plurality of second gates away from the substrate; An isolation structure spacing the plurality of first fins and the plurality of second fins, and spacing the plurality of first gates and the plurality of second gates, and surrounding the plurality of first fins and the plurality of first gates; Wherein, the plurality of first fins and the plurality of second fins are of the same material and disposed in the same layer, and the plurality of first gates and the plurality of second gates are of the same material and disposed in the same layer.

14. The semiconductor device of claim 13, wherein, The isolation structure comprises: A first isolation portion extending in the first direction and located on one side of the plurality of first gates in the second direction; A second isolation portion extending in the second direction and located on one side of the plurality of first gates in the first direction.

15. The semiconductor device of claim 14, wherein, The first isolation portion comprises a plurality of isolation sub-portions arranged in the first direction, the isolation sub-portions being located on the extension lines of the second gates, and the width of the isolation sub-portions in the first direction being equal to the width of the second gates in the first direction.

16. The semiconductor device of claim 15, wherein, Further comprise: An insulating layer, part of the plurality of first fins and the plurality of second fins being embedded in the insulating layer, and the remaining part protruding above the upper surface of the insulating layer; The isolation sub includes a first part embedded in the insulating layer and a second part on the insulating layer; the size of the first part in the second direction is equal to the size of the second fin in the second direction.

17. The semiconductor device of claim 14, wherein, In the first direction, the closest first gate and second gate in the plurality of first gates and the plurality of second gates are respectively a first target gate and a second target gate; The semiconductor device further comprises: A first target dielectric layer covering the side of the first target gate close to the second target gate; A first target etching stop layer covering the first target dielectric layer; A second target dielectric layer covering the side of the second target gate close to the first target gate; A second target etching stop layer covering the second target dielectric layer; In the first direction, the second isolation sub is located between the first target etching stop layer and the second target etching stop layer.

18. The semiconductor device of claim 14, wherein, Further comprising: A first dielectric layer and a second dielectric layer covering two opposite sides of the second isolation sub in the first direction; A first etching stop layer and a second etching stop layer, the first etching stop layer covering the first dielectric layer, and the second etching stop layer covering the second dielectric layer.

19. The semiconductor device of claim 14, wherein, The isolation structure includes two first isolation subs and two second isolation subs, in the second direction, two first isolation subs are respectively located on opposite sides of the plurality of first gates; in the first direction, two second isolation subs are respectively located on opposite sides of the plurality of first gates; two first isolation subs and two second isolation subs are connected to form a frame shape.

20. The semiconductor device of any one of claims 13-19, wherein, Further comprising: A third dielectric layer covering two opposite sides of the plurality of first gates and the plurality of second gates in the first direction; A source and a drain located on the plurality of first fins and the plurality of second fins; in the first direction, the source and the drain are respectively located on two sides of the first gate and two sides of the second gate; A third etching stop layer covering the third dielectric layer, the source and the drain.

21. The semiconductor device of any one of claims 14-19, wherein, The size of the first isolation sub in the second direction is less than or equal to twice the distance between the center lines of two adjacent first fins; And / or, The substrate is provided with at least one first gate group, the first gate group includes a plurality of first gates; the size of the second isolation sub in the first direction is less than or equal to twice the distance between the center lines of two adjacent first gates in the first gate group adjacent to the second isolation sub.

22. The semiconductor device of any one of claims 13-19, wherein, The width of the plurality of first fins and the plurality of second fins is equal; and / or, The distance between any two adjacent fins in the plurality of first fins and the plurality of second fins is equal; and / or, The width of the plurality of second gates is equal; and / or, The distance between any two adjacent second gates is equal.

23. An electronic device, comprising: It comprises a printed circuit board and a semiconductor device according to any one of claims 13-22; the semiconductor device and the printed circuit board are electrically connected.

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