Semiconductor memory devices

Abstract

The embodiments provide a semiconductor memory device capable of reducing operating current. In the semiconductor memory device of the embodiments, a first readout operation includes a first readout voltage supply operation that supplies a readout through voltage to a first conductive layer, a first readout voltage supply operation that supplies a readout voltage smaller than the readout through voltage to the first conductive layer, and a second readout voltage supply operation that supplies a readout through voltage to the first conductive layer. The second readout operation includes a second readout voltage supply operation that supplies a readout voltage to a second conductive layer that is the same as or different from the first conductive layer, and a third readout voltage supply operation that supplies a readout through voltage to the second conductive layer. The first readout operation and the second readout operation are executed consecutively, and during the period from the execution of the second readout voltage supply operation to the end of the third readout voltage supply operation, the voltages of a plurality of first non-selective conductive layers that are different from the first conductive layer or the second conductive layer are maintained at the readout through voltage.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2022-47942 (filed on March 24, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] This embodiment relates to a semiconductor memory device. Background Technology

[0003] A semiconductor memory device is known, which includes a memory string and a plurality of first wirings electrically connected to the memory string. The memory string includes a plurality of memory transistors connected in series, and the gate electrodes of the plurality of memory transistors are connected to the plurality of first wirings. Summary of the Invention

[0004] The implementation provides a semiconductor memory device capable of reducing operating current.

[0005] One embodiment of a semiconductor memory device includes: a memory string having a plurality of memory transistors connected in series; and a plurality of conductive layers connected to the gate electrodes of the plurality of memory transistors. A first readout operation is performed based on input to a first command set, and a second readout operation is performed based on input to a second command set. The first readout operation includes: a first readout voltage supply operation, supplying a readout voltage to a first conductive layer, which is one of the plurality of conductive layers; a first readout voltage supply operation, after performing the first readout voltage supply operation, supplying a readout voltage smaller than the readout voltage to the first conductive layer; and a second readout voltage supply operation, after performing the first readout voltage supply operation, supplying a readout voltage to the first conductive layer. The second readout action includes: a second readout voltage supply action, which, after the first readout action is performed, supplies a readout voltage to a second conductive layer that is the same as or different from the first conductive layer, which is one of a plurality of conductive layers; and a third readout through voltage supply action, which, after the second readout voltage supply action is performed, supplies a readout through voltage to the second conductive layer. The first readout action and the second readout action are performed consecutively, and during the period from the execution of the second readout through voltage supply action to the end of the third readout through voltage supply action, the voltages of the first non-selective conductive layer that is different from the first conductive layer and the second non-selective conductive layer that is different from the second conductive layer are maintained at the readout through voltage. Attached Figure Description

[0006] Figure 1 This is a schematic block diagram illustrating the structure of the storage system 10 according to the first embodiment.

[0007] Figure 2 This is a schematic side view showing an example of the structure of the storage system 10.

[0008] Figure 3 This is a schematic top view showing an example of the structure of the storage system 10.

[0009] Figure 4 This is a schematic block diagram illustrating the structure of the memory die (MD) according to the first embodiment.

[0010] Figure 5 This is a schematic circuit diagram representing a portion of the structure of a memory die (MD).

[0011] Figure 6 This is a schematic circuit diagram representing a portion of the structure of a memory die (MD).

[0012] Figure 7 This is a schematic circuit diagram representing a portion of the structure of a memory die (MD).

[0013] Figure 8 This is a schematic circuit diagram representing a portion of the structure of a memory die (MD).

[0014] Figure 9 This is a schematic circuit diagram representing a portion of the structure of a memory die (MD).

[0015] Figure 10 This is a schematic circuit diagram representing a portion of the structure of a memory die (MD).

[0016] Figure 11 This is a schematic circuit diagram representing a portion of the structure of a memory die (MD).

[0017] Figure 12 This is a schematic exploded perspective view showing an example of the structure of the semiconductor memory device according to this embodiment.

[0018] Figure 13 This indicates that chip C M A schematic bottom view of the structure example.

[0019] Figure 14 This is a schematic cross-sectional view showing a portion of the structure of a memory die (MD).

[0020] Figure 15 This is a schematic cross-sectional view showing a portion of the structure of a memory die (MD).

[0021] Figure 16 This indicates that chip C M A schematic bottom view of part of the structure.

[0022] Figure 17 This indicates that chip C M A schematic cross-sectional view of a portion of the structure.

[0023] Figure 18 (a) and (b) are schematic diagrams used to illustrate the data recorded in the storage unit MC.

[0024] Figure 19 It is used for receiving command set CS R1 A sequence diagram illustrating the actions at a given time.

[0025] Figure 20 It is used for receiving command set CS R2 A sequence diagram illustrating the actions at a given time.

[0026] Figure 21 It is a schematic cross-sectional view used to illustrate the readout voltage supply operation.

[0027] Figure 22 It is a timing diagram used to illustrate the read operation of cache access.

[0028] Figure 23 This refers to the command data D held in the Command Register (CMR) and Address Register (ADR) during a cache read operation. CMD and address data D ADD An example diagram.

[0029] Figure 24 This is a timing diagram used to explain the readout operation of the connection reading according to the first embodiment.

[0030] Figure 25 This refers to the command data D held in the command register CMR and address register ADR during the read operation of the connection read according to the first embodiment. CMD and address data D ADD An example diagram.

[0031] Figure 26 A timing diagram used to explain the readout operation of the connection reading according to the third embodiment.

[0032] Figure 27 This refers to the command data D held in the command register CMR and address register ADR during the read operation of the connection read according to the third embodiment. CMD and address data D ADD An example diagram.

[0033] Figure 28 This is a timing diagram used to explain the readout operation of the connection reading according to the fourth embodiment.

[0034] Figure 29This is a schematic timing diagram used to explain the readout operation of the connection reading according to the fifth embodiment.

[0035] Figure 30 This is a timing diagram used to explain the readout operation of the connection reading according to the sixth embodiment.

[0036] Label Explanation

[0037] 110 conductive layer, 120 semiconductor layer, 130 gate insulating film, WL word line, WL S Select word lines (first conductive layer, second conductive layer, third conductive layer), WLU non-select word lines (first non-select conductive layer, second non-select conductive layer, third non-select conductive layer), MC memory cell, MS memory string, SU string cell, BLK memory block, MCA memory cell array. Detailed Implementation

[0038] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic, and for ease of explanation, some structures may be omitted. Also, sometimes common parts in multiple embodiments are given the same reference numerals, and descriptions are omitted.

[0039] Furthermore, when "semiconductor memory device" is mentioned in this specification, it sometimes means a memory die, and sometimes it means a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Further, it sometimes also means the structure of a mainframe computer, such as a smartphone, tablet computer, or personal computer.

[0040] In addition, when "control circuit" is mentioned in this specification, it may mean a peripheral circuit such as a sequencer set in the memory chip, or a control chip or control die connected to the memory chip, or a structure that includes both of these.

[0041] Furthermore, when this specification mentions that the first structure is "electrically connected" to the second structure, this can mean that the first structure and the second structure are directly connected, or that the first structure is connected to the second structure via wiring, semiconductor components, or transistors. For example, in the case of three transistors connected in series, even if the second transistor is in the off state, the first transistor is still "electrically connected" to the third transistor.

[0042] Additionally, when this specification mentions that the first structure is "connected" "between" the second and third structures, it sometimes means that the first, second, and third structures are connected in series, and the second structure is connected to the third structure via the first structure.

[0043] In addition, when this specification mentions that a circuit or the like makes two wires "conduct", it may mean, for example, that the circuit or the like includes a transistor or the like, which is located in the current path between the two wires, and that the transistor or the like is in the ON state.

[0044] In addition, in this specification, the predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0045] In addition, in this specification, the direction along the predetermined surface is sometimes referred to as the first direction, the direction along the predetermined surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the predetermined surface is referred to as the third direction. These first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0046] Furthermore, in this specification, the terms "upper" and "lower" are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Additionally, when referring to a certain structure as a lower surface or lower end, it signifies the surface or end of that structure on the substrate side; when referring to it as an upper surface or upper end, it signifies the surface or end of that structure on the opposite side from the substrate. Furthermore, a surface intersecting the X or Y direction is called a side surface, etc.

[0047] [First Implementation]

[0048] [Storage System 10]

[0049] Figure 1 This is a schematic block diagram illustrating the structure of the storage system 10 according to the first embodiment.

[0050] The storage system 10 performs tasks such as reading, writing, and erasing user data based on signals sent from the host computer 20. The storage system 10 may be, for example, a memory chip, memory card, SSD, or other system capable of storing user data. The storage system 10 includes multiple memory chips (MDs) and a control chip (CD).

[0051] Storage die MD stores user data. Storage die MD has multiple storage blocks BLK. Each storage block BLK has multiple page PGs. A storage block BLK can also be the unit of execution for erase operations. A page PG can also be the unit of execution for read and write operations.

[0052] like Figure 1 As shown, the control die CD is connected to multiple memory dies MD and the host computer 20. The control die CD includes, for example, a logic physical transformation table 21, a FAT (File Allocation Table) 22, an erase count holding unit 23, an ECC circuit 24, and an MPU (Micro Processor Unit) 25.

[0053] The logical-physical translation table 21 is maintained by associating the logical address received from the host computer 20 with the physical address of the page PG allocated in the memory die MD. The logical-physical translation table 21 is implemented, for example, by RAM (Random Access Memory) or the like, which is not shown.

[0054] FAT22 maintains FAT information indicating the status of each page group (PG). This FAT information includes, for example, information indicating "valid," "invalid," and "erased." For instance, a "valid" page PG stores valid data read according to commands from the host computer 20. Conversely, an "invalid" page PG stores invalid data that was not read according to commands from the host computer 20. Furthermore, in an "erased" page PG, no data was stored after the erasure process was performed. FAT22 is implemented, for example, by RAM (not shown).

[0055] The erase count holding unit 23 holds the erase count in relation to the physical address corresponding to the memory block BLK and the number of erase operations performed on the memory block BLK. The erase count holding unit 23 is implemented, for example, by RAM (not shown).

[0056] ECC circuit 24 detects errors in the data read from the memory die MD and corrects the data if possible.

[0057] MPU25 refers to the logic-physical transformation table 21, FAT22, erase count holding unit 23, and ECC circuit 24 to perform logic address to physical address transformation, bit error detection / correction, garbage collection (compaction), wear leveling, and other processes.

[0058] Figure 2 This is a schematic side view showing an example of the structure of the storage system 10 according to this embodiment. Figure 3This is a schematic top view illustrating this structural example. For ease of explanation, in... Figure 2 and Figure 3 A portion of the structure is omitted.

[0059] like Figure 2 As shown, the memory system 10 according to this embodiment includes a mounting substrate (MSB), multiple memory dies (MDs), and a control die (CD). Pad electrodes Px are provided at the Y-direction end of the upper surface of the mounting substrate (MSB). The areas of the upper surface of the mounting substrate (MSB) other than the Y-direction end are bonded to the lower surface of the memory dies (MDs) using an adhesive or the like. Multiple memory dies (MDs) are stacked on the mounting substrate (MSB). Pad electrodes Px are provided at the Y-direction end of the upper surface of the memory dies (MDs). The areas of the upper surface of the memory dies (MDs) other than the Y-direction end are bonded to the lower surface of other memory dies (MDs) or the control die (CD) using an adhesive or the like. The control die (CD) is stacked on the memory dies (MDs). Pad electrodes Px are provided at the Y-direction end of the upper surface of the control die (CD).

[0060] like Figure 3 As shown, the mounting substrate MSB, multiple memory dies MD, and control die CD each have multiple pad electrodes Px arranged in the X direction. The multiple pad electrodes Px disposed on the mounting substrate MSB, multiple memory dies MD, and control die CD are interconnected via bonding wires B.

[0061] also, Figure 2 and Figure 3 The structure shown is merely an example; the actual structure can be adjusted accordingly. For example, in Figure 2 and Figure 3 In the example shown, a control die CD is stacked on top of multiple memory dies MD. Furthermore, the memory dies MD and the control die CD are connected via a bonding wire B. Additionally, the multiple memory dies MD and the control die CD are contained within a single package. However, the control die CD may also be contained in a different package than the memory dies MD. Furthermore, the multiple memory dies MD and the control die CD may also be interconnected via through electrodes or the like, instead of via a bonding wire B.

[0062] [Circuit structure of memory die MD]

[0063] Figure 4 This is a schematic block diagram illustrating the structure of the memory die MD according to the first embodiment. Figures 5 to 11 This is a schematic circuit diagram representing a portion of the structure of a memory die (MD).

[0064] In addition, Figure 4The diagram illustrates multiple control terminals. These control terminals are sometimes represented as control terminals corresponding to a high active signal (positive logic signal). Additionally, they are sometimes represented as control terminals corresponding to a low active signal (negative logic signal). Furthermore, they are sometimes represented as control terminals corresponding to both high and low active signals. Figure 4 In this specification, the labels for control terminals corresponding to active-low signals include an overline. Furthermore, the labels for control terminals corresponding to active-low signals include a forward slash (" / "). Figure 4 Taking the above description as an example, the specific technical solution can be adjusted appropriately. For example, some or all of the high-level active signals can be made low-level active signals, and some or all of the low-level active signals can be made high-level active signals.

[0065] like Figure 4 As shown, the memory die MD includes a memory cell array MCA and peripheral circuitry PC. The peripheral circuitry PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. Additionally, the peripheral circuitry PC includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. Furthermore, the peripheral circuitry PC includes input / output control circuitry (I / O) and logic circuitry CTR.

[0066] [Circuit structure of a memory cell array (MCA)]

[0067] like Figure 5 As shown, the memory cell array MCA has multiple memory blocks BLK as described above. Each of these memory blocks BLK has multiple string cells SU. Each of these string cells SU has multiple memory strings MS. One end of each of these memory strings MS is connected to the peripheral circuit PC via a bit line BL. In addition, the other end of each of these memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0068] The memory string (MS) includes a drain-side select transistor (STD), multiple memory cells (MCs) (memory transistors), a source-side select transistor (STS), and a source-side select transistor (STSb). The STD, MCs, STS, and STSb are connected in series between the bit line BL and the source line SL. Hereinafter, the STD, STS, and STSb are sometimes simply referred to as the select transistors (STD, STS, STSb).

[0069] The memory cell MC is a field-effect transistor. The memory cell MC has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as the channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. The memory cell MC stores one or more bits of data. Furthermore, word lines WL are connected to the gate electrodes of multiple memory cells MC corresponding to a memory string MS. These word lines WL are shared and connected to all memory strings MS in a memory block BLK.

[0070] The select transistors (STD, STS, STSb) are field-effect transistors. Each select transistor (STD, STS, STSb) has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as the channel region. Select gate lines (SGD, SGS, SGSb) are connected to the gate electrodes of the select transistors (STD, STS, STSb). A drain-side select gate line SGD shares a common ground with all memory strings MS in a single string cell SU. A source-side select gate line SGS shares a common ground with all memory strings MS in a memory block BLK. A source-side select gate line SGSb shares a common ground with all memory strings MS in a memory block BLK.

[0071] [Circuit structure of voltage generation circuit VG]

[0072] For example, Figure 6 As shown, the voltage generation circuit VG( Figure 4 It has multiple voltage generation units vg1 to vg3. Voltage generation units vg1 to vg3 generate a predetermined voltage during read, write, and erase operations, and supply the voltage via voltage supply line L. VG (L VG1 ~L VG3 The voltage generation unit (vg1) outputs the programming voltage used during the write operation. Additionally, the voltage generation unit (vg2) outputs the read pass voltage (V), described later, during the read operation. READ Additionally, voltage generation unit VG2 outputs the write pass voltage used during the write operation. Furthermore, voltage generation unit VG3 outputs the read voltage (described later) during the read operation. Furthermore, voltage generation unit VG3 outputs the verification voltage (described later) during the write operation. Voltage generation units VG1 to VG3 can be, for example, boost circuits such as charge pump circuits, or buck circuits such as regulators. These buck and boost circuits are respectively connected to the voltage supply line L. P For voltage supply line L P Supply voltage V CC Or ground voltage VSS ( Figure 4 These voltage supply lines L P For example, connected to a reference Figure 2 , Figure 3 The pad electrode Px has been described. The operating voltage output from the voltage generation circuit VG is appropriately adjusted according to the control signal from the sequencer SQC.

[0073] The charge pump circuit 32 in the voltage generation circuit VG Figure 7 It includes a voltage output circuit 32a, a voltage divider circuit 32b, and a comparator 32c. The voltage output circuit 32a supplies voltage to the voltage supply line L. VG Output voltage V OUT Voltage divider circuit 32b and voltage supply line L VG Connection. Comparator 32c is based on the voltage V output from voltage divider circuit 32b. OUT ′ and reference voltage V REF The magnitude of the signal determines the magnitude of the voltage output signal, which is then used to output a feedback signal FB to the voltage output circuit 32a.

[0074] like Figure 8 As shown, the voltage output circuit 32a includes multiple transistors 32a2a and 32a2b. These transistors 32a2a and 32a2b are alternately connected to the voltage supply line L. VG With voltage supply line L P Between. For the voltage supply line L shown in the diagram. P Supply voltage V CC The gate electrodes and drain electrodes of multiple transistors 32a2a and 32a2b connected in series are connected to a capacitor 32a3. Additionally, the voltage output circuit 32a includes an AND circuit 32a4, a level shifter 32a5a, and a level shifter 32a5b. The AND circuit 32a4 outputs a logical sum of a clock signal CLK and a feedback signal FB. The level shifter 32a5a boosts the output signal of the AND circuit 32a4 for output. The output terminal of the level shifter 32a5a is connected to the gate electrode of transistor 32a2a via capacitor 32a3. The level shifter 32a5b boosts the inverted signal of the output signal of the AND circuit 32a4 for output. The output terminal of the level shifter 32a5b is connected to the gate electrode of transistor 32a2b via capacitor 32a3.

[0075] When the feedback signal FB is in the "H (high level)" state, the clock signal CLK is output from the AND circuit 32a4. Simultaneously, the clock signal CLK is output from the voltage supply line L. VG Supply line L P Electron transfer, voltage supply line L VGThe voltage increases. On the other hand, when the feedback signal FB is in the "L (low level)" state, the clock signal CLK is not output from the AND circuit 32a4. Therefore, the voltage supply line L... VG The voltage does not increase.

[0076] like Figure 7 As shown, the voltage divider circuit 32b includes a resistive element 32b2 and a variable resistive element 32b4. The resistive element 32b2 is connected to the voltage supply line L. VG Between the voltage divider terminal 32b1 and the voltage supply line L. A variable resistor element 32b4 is connected in series between the voltage divider terminal 32b1 and the voltage supply line L. P Between. Regarding the voltage supply line L P Supply ground voltage V SS The resistance value of the variable resistor element 32b4 can be controlled according to the operating voltage control signal V. CTRL To make adjustments. Therefore, the voltage V at voltage divider terminal 32b1. OUT The size of ′ can be controlled by the operating voltage control signal V. CTRL To make adjustments.

[0077] like Figure 9 As shown, the variable resistor element 32b4 has multiple current paths 32b5. These multiple current paths 32b5 are connected in parallel to the voltage divider terminal 32b1 and the voltage supply line L. P Between. Multiple current paths 32b5 each have a resistor element 32b6 and a transistor 32b7 connected in series. The resistance values ​​of the resistor elements 32b6 in each current path 32b5 can also be different. An operating voltage control signal V is input to the gate electrode of the transistor 32b7. CTRL Different bits. In addition, the variable resistor element 32b4 may also have a current path 32b8 that does not include the transistor 32b7.

[0078] like Figure 7 As shown, comparator 32c outputs a feedback signal FB. The feedback signal FB is, for example, the voltage V at voltage divider terminal 32b1. OUT ′Ratio to reference voltage V REF In large cases, it becomes the "L" state. Additionally, the feedback signal FB, for example, is in the voltage V. OUT ′Ratio to reference voltage V REF In the case of a small value, it becomes the "H" state.

[0079] [Circuit structure of the row decoder RD]

[0080] For example, Figure 6 As shown, the row decoder RD includes a block decoder BLKD, a word line decoder WLD, a driver circuit DRV, and an address decoder (not shown).

[0081] The block decoder BLKD has multiple block decoding units blkd. These multiple block decoding units blkd correspond to multiple memory blocks BLK in the memory cell array MCA. Each block decoding unit blkd has multiple transistors T. BLK Multiple transistors T BLK This corresponds to the multiple word lines WL in the memory block BLK. Transistor T BLK For example, a field-effect NMOS transistor. Transistor T BLK The drain electrode of transistor T is connected to the word line WL. BLK The source electrode is connected to the wiring CG. The wiring CG is connected to all block decoding units blkd in the block decoder BLKD. Transistor T BLK The gate electrode is connected to the signal line BLKSEL. Multiple signal lines BLKSEL are provided corresponding to all block decoding units (blkd). Furthermore, the signal lines BLKSEL are connected to all transistors T in the block decoding unit (blkd). BLK connect.

[0082] In read and write operations, for example, with the address register ADR ( Figure 4 In the block address, the voltage of one BLKSEL signal line becomes "H", and the voltages of other BLKSEL signal lines become "L". For example, a predetermined drive voltage of positive magnitude is supplied to one BLKSEL signal line, and a ground voltage V is supplied to the other BLKSEL signal lines. SS Therefore, all word lines (WL) and all routing lines (CG) in a memory block (BLK) corresponding to that block address are connected. Additionally, all word lines (WL) in other memory block (BLK) become floating.

[0083] The word line decoder (WLD) has multiple word line decoding units (wld). These multiple word line decoding units (wld) correspond to multiple memory cells (MC) in the memory string (MS). In the illustrated example, the word line decoding unit (wld) has two transistors (T). WLS T WLU Transistor T WLS T WLU For example, a field-effect NMOS transistor. Transistor T WLS T WLU The drain electrode of transistor T is connected to wiring CG. WLS Source electrode and wiring CG S Connection. Transistor T WLU Source electrode and wiring CG U Connection. Transistor T WLS gate electrode and signal line WLSEL S Connection. Transistor T WLU gate electrode and signal line WLSEL UConnection. The transistor T on one side contained in the full word line decoding unit wld. WLS Correspondingly, multiple signal lines WLSEL are provided. S The transistor T on the other side is contained in the complete word line decoding unit wld. WLU Correspondingly, multiple signal lines WLSEL are provided. U .

[0084] In read and write operations, for example, with the address register ADR ( Figure 4 The signal line WLSEL corresponding to the word line decoding unit wld of the page address in ) S The voltage becomes the "H" state, and its corresponding WLSEL U The voltage becomes "L" state. Additionally, the signal line WLSEL corresponding to the other word line decoding unit wld... S The voltage becomes the "L" state, and its corresponding WLSEL U The voltage becomes the "H" state. Additionally, for the wiring CG... S Supply and Selection Word Line WL S The corresponding voltage. Additionally, regarding the wiring CG... U Supply and non-selective word line WL U The corresponding voltage. Therefore, the word line WL corresponding to the aforementioned page address is supplied with and selected. S The corresponding voltage. Additionally, the supply to other word lines WL is the same as that to the non-selected word lines WL. U The corresponding voltage.

[0085] The drive circuit DRV, for example, has 6 transistors T DRV1 ~T DRV6 Transistor T DRV1 ~T DRV6 For example, a field-effect NMOS transistor. Transistor T DRV1 ~T DRV4 Drain electrode and wiring CG S Connection. Transistor T DRV5 T DRV6 Drain electrode and wiring CG U Connection. Transistor T DRV1 The source electrode is supplied via voltage line L VG1 It is connected to the output terminal of the voltage generation unit vg1. Transistor T DRV2 T DRV5 The source electrode is supplied via voltage line L VG2 It is connected to the output terminal of the voltage generation unit vg2. Transistor T DRV3 The source electrode is supplied via voltage line L VG3It is connected to the output terminal of the voltage generation unit VG3. Transistor T DRV4 T DRV6 The source electrode is supplied via voltage line L P And compared with the reference Figure 2 , Figure 3 The pad electrode Px connection has been described. In transistor T... DRV1 ~T DRV6 The gate electrodes are connected to signal lines VSEL1 to VSEL6 respectively.

[0086] In read-out and write-out operations, for example, with wired CG... S The voltage of one of the corresponding signal lines VSEL1 to VSEL4 is designated as "H", while the others are designated as "L". Additionally, this relates to the wiring CG. U The voltage of one of the corresponding two signal lines, VSEL5 and VSEL6, becomes the "H" state, and the voltage of the other becomes the "L" state.

[0087] Address decoders not shown, for example, according to the sequencer SQC ( Figure 4 The control signals of ) sequentially affect the address register ADR ( Figure 4 The row address RA is referenced. The row address RA includes the block address and page address mentioned above. The address decoder uses the above signal lines BLKSEL and WLSEL. S WLSEL U The voltage control is in either "H" or "L" state.

[0088] In addition, Figure 6 In the example, the row decoder RD has one block decoding unit blkd for each memory block BLK. However, this structure can be modified appropriately. For example, one block decoding unit blkd can also be set for each of two or more memory blocks BLK.

[0089] [Circuit structure of the Sensing Amplifier Module (SAM)]

[0090] For example, Figure 10 As shown, the sensing amplifier module SAM ( Figure 4 It has multiple sense amplifier units (SAUs). These multiple sense amplifier units (SAUs) correspond to multiple bit lines (BLs). Each sense amplifier unit (SAU) includes a sense amplifier (SA), wiring (LBUS), and latch circuits (SDL, DL0~DLn). L (n L (Numbers are natural numbers). The charging transistor 55 for pre-charging is connected in the LBUS wiring (...). Figure 11 The wiring LBUS is connected to the wiring DBUS via a switching transistor DSW.

[0091] like Figure 11 As shown, the sensing amplifier SA includes a sensing transistor 41. The sensing transistor 41 discharges the charge on the wiring LBUS based on the current flowing in the bit line BL. The source electrode of the sensing transistor 41 is connected to the supplied ground voltage V. SS The voltage supply line is connected. The drain electrode is connected to the wiring LBUS via the switching transistor 42. The gate electrode is connected to the bit line BL via the sensing node SEN, the discharge transistor 43, the node COM, the clamping transistor 44, and the withstand transistor 45. In addition, the sensing node SEN is connected to the internal control signal line CLKSA via the capacitor 48.

[0092] Additionally, the sensing amplifier SA includes a voltage transfer circuit. Based on data latched in the latch circuit SDL, the voltage transfer circuit selectively connects node COM and sensing node SEN to the supplied voltage V. DD The voltage supply line or the supply voltage V SRC The voltage supply line is turned on. The voltage transmission circuit includes node N1, charging transistor 46, charging transistor 49, charging transistor 47, and discharging transistor 50. Charging transistor 46 is connected between node N1 and sensing node SEN. Charging transistor 49 is connected between node N1 and node COM. Charging transistor 47 is connected between node N1 and the supply voltage V. DD The discharge transistor 50 is connected between node N1 and the supply voltage V. SRC The voltage supply lines are connected between them. Furthermore, the gate electrodes of charging transistor 47 and discharging transistor 50 are jointly connected to node INV_S of the latch circuit SDL.

[0093] Furthermore, the sensing transistor 41, switching transistor 42, discharging transistor 43, clamping transistor 44, charging transistor 46, charging transistor 49, and discharging transistor 50 are, for example, enhancement-mode NMOS transistors. The breakdown transistor 45 is, for example, a depletion-mode NMOS transistor. The charging transistor 47 is, for example, a PMOS transistor.

[0094] Additionally, the gate electrode of switching transistor 42 is connected to signal line STB. The gate electrode of discharge transistor 43 is connected to signal line XXL. The gate electrode of clamping transistor 44 is connected to signal line BLC. The gate electrode of withstand transistor 45 is connected to signal line BLS. The gate electrode of charging transistor 46 is connected to signal line HLL. The gate electrode of charging transistor 49 is connected to signal line BLX. These signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to the sequencer SQC.

[0095] The latch circuit SDL includes nodes LAT_S, INV_S, inverter 51, inverter 52, switching transistor 53, and switching transistor 54. Inverter 51 has an output terminal connected to node LAT_S and an input terminal connected to node INV_S. Inverter 52 has an input terminal connected to node LAT_S and an output terminal connected to node INV_S. Switching transistor 53 is disposed in the current path between node LAT_S and wiring LBUS. Switching transistor 54 is disposed in the current path between node INV_S and wiring LBUS. Switching transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of switching transistor 53 is connected to sequencer SQC via signal line STL. The gate electrode of switching transistor 54 is connected to sequencer SQC via signal line STI.

[0096] Latch circuits DL0~DLn L It is constructed in a similar manner to the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL is connected to the gate electrodes of the charging transistor 47 and the discharging transistor 50 in the sense amplifier SA. Latch circuits DL0 to DLn L This is different from the latch circuit SDL.

[0097] The switching transistor DSW is, for example, an NMOS transistor. The switching transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switching transistor DSW is connected to the sequencer SQC via the signal line DBS.

[0098] In addition, such as Figure 10 As illustrated, the aforementioned signal lines STB, HLL, XXL, BLX, BLC, and BLS are shared and connected among all the sense amplifier units SAU contained in the sense amplifier module SAM. Additionally, the aforementioned supply voltage V... DD The voltage supply line and the supply voltage V SRC The voltage supply lines are shared and connected among all the sense amplifier units (SAUs) included in the sense amplifier module (SAM). Similarly, the signal lines STI and STL of the latch circuit SDL are shared and connected among all the sense amplifier units (SAUs) included in the sense amplifier module (SAM). Likewise, the latch circuits DL0 to DLn... L The signal lines TI0 to TIn correspond to signal lines STI and STL. L TL0~TLn L Each of these is shared and connected among all the sense amplifier units (SAU) included in the sense amplifier module (SAM). On the other hand, multiple signal lines (DBS) are provided corresponding to each of the sense amplifier units (SAU) included in the sense amplifier module (SAM).

[0099] [Circuit structure of cache memory (CM)]

[0100] like Figure 10 As shown, the high-speed cache memory CM ( Figure 4 It has multiple latch circuits XDL. These multiple latch circuits XDL are connected to the latch circuits within the sense amplifier module (SAM) via a DBUS wiring system. The data DAT contained in these multiple latch circuits XDL are sequentially transmitted to the sense amplifier module (SAM) or the input / output control circuit (I / O).

[0101] Additionally, a decoding circuit and a switching circuit (not shown) are connected to the cache memory CM. The decoding circuit decodes the column address CA held in the address register ADR. The switching circuit, based on the output signal of the decoding circuit, activates the latch circuit corresponding to the column address CA and the bus DB. Figure 4 ) Conduction.

[0102] [Circuit structure of the sequencer SQC]

[0103] Sequencer SQC ( Figure 4 According to the command data D stored in the command register CMR CMD The sequencer outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG. Additionally, the sequencer SQC outputs appropriate state data D representing its own state to the state register STR. ST .

[0104] Additionally, the sequencer SQC generates a ready / busy signal RB and outputs it to terminal RBn. The ready / busy signal RB indicates to the control die CD whether it is in a ready state (able to accept commands from the control die CD) or a busy state (not accepting commands). During the period when the voltage at terminal RBn is in the "L" state (busy period), access to the memory die MD is essentially prohibited. Conversely, during the period when the voltage at terminal RBn is in the "H" state (ready period), access to the memory die MD is permitted. Furthermore, terminal RBn, for example, is referenced... Figure 2 , Figure 3 This is achieved using the previously described pad electrode Px.

[0105] [Circuit structure of input / output control circuit (I / O)]

[0106] The input / output control circuit (I / O) includes data signal input / output terminals DQ0-DQ7, trigger signal input / output terminals DQS and / DQS, multiple input circuits, multiple output circuits, a shift register, and a buffer circuit. The multiple input circuits, multiple output circuits, shift register, and buffer circuit are connected to the supplied power supply voltage V. CC and grounding voltage VSS Terminal connections.

[0107] Data signal input / output terminals DQ0~DQ7, trigger signal input / output terminals DQS, / DQS, and the supplied power supply voltage V CC The terminals, for example, are referenced. Figure 2 , Figure 3 The pad electrode Px, as described above, is used for implementation. Data input via data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, address register ADR, or command register CMR based on internal control signals from the logic circuit CTR. Conversely, data output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit based on internal control signals from the logic circuit CTR.

[0108] Multiple input circuits include, for example, comparators connected to any one of the data signal input / output terminals DQ0 to DQ7 or to both the trigger signal input / output terminals DQS and / DQS. Multiple output circuits include, for example, an OCD (Off-Chip Driver) circuit connected to any one of the data signal input / output terminals DQ0 to DQ7 or to both the trigger signal input / output terminals DQS and / DQS.

[0109] [Circuit structure of the CTR logic circuit]

[0110] Logic circuit CTR ( Figure 4 External control signals are received from the control die CD via external control terminals / CEn, CLE, ALE, / WE, RE, / RE, and internal control signals are output to the input / output control circuit (I / O) based on these signals. Furthermore, the external control terminals / CEn, CLE, ALE, / WE, RE, / RE are, for example, derived from a reference... Figure 2 , Figure 3 This is achieved using the previously described pad electrode Px.

[0111] [Structure of a memory die (MD)]

[0112] Figure 12 This is a schematic exploded perspective view showing an example of the structure of the semiconductor memory device according to this embodiment. For example... Figure 12 As shown, the memory die MD has a chip C on the memory cell array MCA side. M And the peripheral circuit PC side chip C P .

[0113] In chip C MThe upper surface of the chip has multiple pad electrodes Px that can be connected to bonding wires (not shown). Additionally, on chip C... M Multiple bonding electrodes P are provided on the lower surface. I1 Additionally, in chip C... P Multiple bonding electrodes P are provided on the upper surface. I2 The following is about chip C. M Multiple bonding electrodes P will be set. I1 The side where multiple pad electrodes Px are located is called the front side, and the side where these are located is called the back side. Additionally, regarding chip C... P Multiple bonding electrodes P will be set. I2 The side facing out is called the surface, and the side opposite the surface is called the back surface. In the illustrated example, chip C P The surface is set in a way that is greater than that of the chip C P On the back, near the top, is chip C. M The back is set at a higher position than chip C M The upper part of the surface.

[0114] Chip C M and chip C P Configured as chip C M Surface and chip C P The surfaces are facing each other. Multiple bonded electrodes P I1 Each with multiple bonding electrodes P I2 Correspondingly, it is configured to be able to adhere to multiple bonding electrodes P I2 The position of the electrode P. I1 and bonding electrode P I2 As for using chip C M and chip C P The bonding electrode, which is attached and electrically conductive, performs its function.

[0115] In addition, Figure 12 In the example, chip C M The corners a1, a2, a3, and a4 are respectively connected to chip C P The corners b1, b2, b3, and b4 correspond.

[0116] Figure 13 This indicates that chip C M A schematic bottom view of a structural example. Figure 13 The bonding electrode P is omitted in the text. I1 A part of the structure of etc. Figure 14 and Figure 15 This is a schematic cross-sectional view showing a portion of the structure of a memory die (MD). Figure 16 This indicates that chip C M A schematic bottom view of part of the structure. Figure 17 This indicates that chip C M A schematic cross-sectional view of a portion of the structure. Figure 17 The YZ section is shown, but when observing sections other than the YZ section along the central axis of semiconductor layer 120 (e.g., the XZ section), the same pattern can also be observed. Figure 17 Same construction.

[0117] [Chip C] M [Construction]

[0118] exist Figure 13 In the example, chip C M It has four plain storage planes (MPL0, MPL1, MPL2, and MPL3) arranged in the X direction. The four plain storage planes MPL0 to MPL3 are respectively connected to the memory cell array (MCA). Figure 5 Corresponding to this. Furthermore, each of these four storage planes, MPL0 to MPL3, has multiple storage blocks (BLKs) arranged in the Y direction. Additionally, in... Figure 13 In the example, each of the multiple storage blocks BLK has a hook-up region R located at both ends in the X direction. HU and the storage hole area R located between these joint areas MH Additionally, chip C M It has a peripheral region R located at one end of the four storage planes MPL0 to MPL3, further in the Y direction. P .

[0119] Furthermore, in the illustrated example, the joining region R HU Set in the storage cell array region R MCA The two ends in the X direction. However, this structure is merely an example, and the specific structure can be appropriately adjusted. For example, the joining region R HU It can also be set not in the storage cell array region R MCA Instead of being located at both ends in the X direction, it is positioned at one end in the X direction. Additionally, the joining region R... HU It can also be set in the storage cell array area R MCA The central position or the position near the center in the X direction.

[0120] For example, Figure 14 As shown, chip C M With matrix layer L SB Set in the substrate layer L SB The lower storage cell array layer L MCA and set in the storage cell array layer L MCA The multiple wiring layers below are CH, M0, M1, and MB.

[0121] [Chip C] M The base layer L SB [Construction]

[0122] For example, such as Figure 14 As shown, the matrix layer L SB Equipped with storage cell array layer L MCA The conductive layer 100 on the upper surface, the insulating layer 101 disposed on the upper surface of the conductive layer 100, the back wiring layer MA disposed on the upper surface of the insulating layer 101, and the insulating layer 102 disposed on the upper surface of the back wiring layer MA.

[0123] The conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), a metal such as tungsten (W), or a silicide such as tungsten silicide (WSi).

[0124] Conductive layer 100 serves as the source line SL ( Figure 5 It functions as part of the conductive layer 100 and the four storage planes MPL0 to MPL3. Figure 13 Four are correspondingly provided. Regions VZ that do not contain the conductive layer 100 are provided at the ends of the storage planes MPL0 to MPL3 in the X and Y directions.

[0125] The insulating layer 101 may contain, for example, silicon oxide (SiO2).

[0126] The back-side wiring layer MA comprises multiple wiring layers MA. These multiple wiring layers MA may also contain, for example, aluminum (Al).

[0127] A portion of the multiple wiring ma is used as the source line SL ( Figure 5 This wiring ma is part of the 4 storage planes MPL0 to MPL3 ( Figure 13 There are four corresponding wiring ma. Each of these wiring ma is electrically connected to the conductive layer 100.

[0128] Additionally, a portion of the multiple wiring ma functions as pad electrodes Px. This wiring ma is located in the surrounding area R. P The wiring ma is in the region VZ that does not contain the conductive layer 100 and is connected to the memory cell array layer L. MCA The via contact electrode CC is connected. In addition, a portion of the wiring ma is exposed on the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0129] The insulating layer 102 is, for example, a passivation layer formed of an insulating material such as polyimide.

[0130] [Chip C] MStorage cell array layer L MCA Storage hole area R MH [Construction in]

[0131] For reference Figure 13 As explained, in the memory cell array layer L MCA Multiple storage blocks (BLKs) are configured and arranged in the Y direction. For example... Figure 14 As shown, an inter-block insulating layer ST, such as silicon oxide (SiO2), is provided between two adjacent memory blocks BLK in the Y direction.

[0132] For example, Figure 14 As shown, the memory block BLK includes multiple conductive layers 110 arranged in the Z direction and multiple semiconductor layers 120 extending in the Z direction. Additionally, as... Figure 17 As shown, a gate insulating film 130 is disposed between multiple conductive layers 110 and multiple semiconductor layers 120.

[0133] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may also include a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 110 may also contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An interlayer insulating layer 111, such as silicon oxide (SiO2), is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0134] One or more of the uppermost conductive layers 110 among multiple conductive layers 110 serve as source-side select transistors (STS). Figure 5 The gate electrode and source side select gate line SGS function (see reference). Figure 14 These multiple conductive layers 110 are electrically independent according to each memory block BLK.

[0135] Additionally, multiple conductive layers 110 located further below serve as memory cells MC ( Figure 5 The gate electrode and word line WL function. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0136] Additionally, one or more conductive layers 110 located further below it function as the gate electrode and drain-side selected gate line (SGD) of the drain-side selected transistor (STD). For example, Figure 16 As shown, the width Y in the Y direction of these multiple conductive layers 110 SGD The width Y in the Y direction of the conductive layer 110, which functions as the word line WL, is greater than the width Y of the conductive layer 110. WL Small. In addition, an insulating layer SHE, such as silicon oxide (SiO2), is provided between two adjacent conductive layers 110 in the Y direction.

[0137] For example, Figure 16 As shown, the semiconductor layers 120 are arranged in a predetermined pattern in the X and Y directions. The semiconductor layers 120 serve as a memory string (MS). Figure 12 The multiple memory cells (MCs) and the channel regions of the selection transistors (STDs, STSs) contained therein function. The semiconductor layer 120 includes, for example, polysilicon (Si). The semiconductor layer 120 has a generally cylindrical shape, and an insulating layer 125, such as silicon oxide, is disposed in the central portion. The outer peripheral surfaces of the semiconductor layer 120 are surrounded by multiple conductive layers 110, and face each other.

[0138] Additionally, an impurity region (not shown) is provided at the upper end of the semiconductor layer 120. This impurity region is connected to the conductive layer 100 (see reference). Figure 14 This impurity region contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0139] Additionally, an impurity region (not shown) is provided at the lower end of the semiconductor layer 120. This impurity region is connected to the bit line BL via via contact electrode ch and via contact electrode Vy. This impurity region contains, for example, N-type impurities such as phosphorus (P).

[0140] For example, Figure 16 As shown, the gate insulating film 130 has a generally cylindrical shape that covers the outer peripheral surface of the semiconductor layer 120. For example, as Figure 17 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 stacked between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 include, for example, silicon oxide (SiO2). The charge storage film 132 includes, for example, silicon nitride (SiN) and other films capable of storing charge. The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120, excluding the contact portion between the semiconductor layer 120 and the conductive layer 110.

[0141] In addition, Figure 17 An example is shown where the gate insulating film 130 has a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0142] [Chip C] M Storage cell array layer L MCA The joint area R HU [Construction in]

[0143] like Figure 15 As shown, in the joint region R HU Multiple via contact electrodes CC are provided. These multiple via contact electrodes CC extend in the Z direction and are connected to the conductive layer 110 at their upper ends.

[0144] [Chip C] M Storage cell array layer L MCA The surrounding area R P [Construction in]

[0145] For example, Figure 14 As shown, in the surrounding area R P Multiple via contact electrodes CC are provided corresponding to the pad electrode Px. These multiple via contact electrodes CC are connected to the pad electrode Px at their upper ends.

[0146] [Chip C] M [Construction of wiring layers CH, M0, M1, MB]

[0147] The multiple wirings contained in the wiring layers CH, M0, M1, and MB, for example, are connected to the memory cell array layer L. MCA The structure and chip C in P At least one of the structures in the structure is electrically connected.

[0148] The wiring layer CH includes multiple via contact electrodes ch to serve as multiple wirings. These multiple via contact electrodes ch may also include, for example, a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrodes ch are disposed corresponding to the multiple semiconductor layers 120 and are connected to the lower end of the multiple semiconductor layers 120.

[0149] The wiring layer M0 comprises multiple wirings m0. These multiple wirings m0 may, for example, comprise a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). Furthermore, a portion of the multiple wirings m0 functions as bit lines BL. For example, ... Figure 16 As shown, the bit lines BL are arranged in the X direction and extend in the Y direction.

[0150] For example, Figure 14 As shown, the wiring layer M1 includes multiple wirings m1. These multiple wirings m1 may, for example, include a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0151] The wiring layer MB includes multiple bonding electrodes P I1 These multiple bonded electrodes P I1 For example, it may also include barrier conductive films such as titanium nitride (TiN) and laminated films of metal films such as copper (Cu).

[0152] [Chip C]P [Construction]

[0153] For example, Figure 14 As shown, chip C P It includes a semiconductor substrate 200, an electrode layer GC disposed above the semiconductor substrate 200, and wiring layers D0, D1, D2, D3, D4, and DB disposed above the electrode layer GC.

[0154] [Chip C] P [Structure of semiconductor substrate 200]

[0155] The semiconductor substrate 200 includes, for example, P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 200, there are, for example, an N-type well region 200N containing N-type impurities such as phosphorus (P), a P-type well region 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S without N-type well regions 200N and P-type well regions 200P, and an insulating region 200I. The N-type well region 200N, the P-type well region 200P, and the semiconductor substrate region 200S function as part of multiple transistors Tr and multiple capacitors, respectively, constituting a peripheral circuit PC.

[0156] [Chip C] P [Construction of the electrode layer GC]

[0157] An electrode layer GC is disposed on the upper surface of the semiconductor substrate 200, separated by an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200. Furthermore, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are respectively connected to a via contact electrode CS.

[0158] The N-type well region 200N, the P-type well region 200P, and the semiconductor substrate region 200S of the semiconductor substrate 200 function as channel regions of multiple transistors Tr constituting the peripheral circuit PC and electrodes of one side of multiple capacitors, respectively.

[0159] The multiple electrodes gc contained in the electrode layer GC function as the gate electrodes of the multiple transistors Tr that constitute the peripheral circuit PC, and as the electrodes on the other side of the multiple capacitors.

[0160] The via contact electrode CS extends in the Z direction and is connected at its lower end to the upper surface of the semiconductor substrate 200 or the electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection point between the via contact electrode CS and the semiconductor substrate 200. The via contact electrode CS may, for example, comprise a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0161] [Chip C] P [Construction of wiring layers D0, D1, D2, D3, D4, DB]

[0162] For example, Figure 14 As shown, the multiple wirings contained in D0, D1, D2, D3, D4, and DB are, for example, connected to the memory cell array layer L. MCA The structure and chip C in P At least one of the structures in the structure is electrically connected.

[0163] Wiring layers D0, D1, and D2 each include multiple wirings d0, d1, and d2. These multiple wirings d0, d1, and d2 may also include, for example, stacked films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W).

[0164] Wiring layers D3 and D4 each include multiple wirings d3 and d4. These multiple wirings d3 and d4 may also include, for example, stacked films of barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu).

[0165] The wiring layer DB includes multiple bonding electrodes P I2 These multiple bonded electrodes P I2 For example, it may also include barrier conductive films such as titanium nitride (TiN) and laminated films of metal films such as copper (Cu).

[0166] [Threshold voltage of memory cell MC]

[0167] Next, refer to Figure 18 The threshold voltage of the memory cell MC is explained. Figure 18 (a) is a schematic histogram used to illustrate the threshold voltage of the memory cell MC. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. Figure 18 (b) is an example of the threshold voltage of the storage cell MC and the data recorded in the storage cell MC.

[0168] As described above, the memory cell array (MCA) has multiple memory cells (MCs). When write operations are performed on these multiple memory cells (MCs), the threshold voltage of these MCs is controlled to various states. Figure 18 Figure (a) shows the distribution of threshold voltages for memory cells MC controlled in eight states. For example, the threshold voltage of a memory cell MC controlled in state A is higher than that of a memory cell MC controlled in state A. Figure 18 The readout voltage V of (a) CGAR Larger than the read voltage V CGBR Smaller. Additionally, the threshold voltage of all memory cells (MCs) is smaller than... Figure 18 Multiple readouts of (a) are obtained through voltage V READ VREADK V READL Small.

[0169] In addition, multiple readouts are achieved through voltage V READ V READK V READL To be applied to the non-select word line WL during the read operation U Voltage within a range of multiple voltage values ​​(refer to) Figure 21 ).exist Figure 18 In example (a), the voltage V is read. READK Compare the readings of the voltage V READ Large, read the voltage V READ Compare the readings of the voltage V READL Large. However, these reads are transmitted via voltage V. READ V READK V READL The relationship between the voltage values ​​is taken as an example, and is not limited to such voltage values.

[0170] In this embodiment, by adjusting the storage unit MC to 8 states, 3 bits of data are recorded in each storage unit MC.

[0171] For example, the Er state corresponds to the lowest threshold voltage (the threshold voltage of the memory cell MC in the erase state). For example, the memory cell MC corresponding to the Er state is allocated the data "111".

[0172] Furthermore, state A corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state Er mentioned above. For example, the memory cell MC corresponding to state A is allocated the data "110".

[0173] Furthermore, state B corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state A. For example, the memory cell MC corresponding to state B is allocated the data "100".

[0174] Similarly, in the diagram, states C through G correspond to threshold voltages that are higher than those corresponding to states B through F. For example, data “000”, “010”, “011”, “001”, and “101” are assigned to the memory cells MC corresponding to these distributions.

[0175] In addition, in such Figure 18 In the case of such an allocation as illustrated in (b), the data in the low-order bits (lower page: LP) can be read through two read voltages V. CGAR V CGER The data of the median bit (middle page: MP) can be determined by three readout voltages V. CGBR VCGDR V CGFR The data in the high-order bits (upper page) can be determined by two readout voltages V. CGCR V CGGR The data is then analyzed. This type of data allocation is sometimes referred to as a 2-3-2 code.

[0176] Furthermore, the number of bits of data recorded in the storage unit MC, the number of states, and the data allocation for each state can be appropriately changed.

[0177] [Types of Reading Action Patterns]

[0178] Next, the types of read operation modes involved in this embodiment will be described. The types of read operation modes involved in this embodiment include a normal read mode, a cache read mode, and a connection read mode.

[0179] [Typical Reading Mode]

[0180] The normal read mode is the mode that performs the normal read operation. During normal read, when the ready / busy signal RB is controlled to the "H" state (ready state), the command set indicating normal read is input from the control die CD (see below). Figure 30 Command set CS R3 When the readout action begins, the ready / busy signal RB is controlled to the "L" state (busy state).

[0181] When a normal read operation ends, the Ready / Busy signal RB is switched from the "L" state (busy state) to the "H" state (ready state), becoming capable of accepting the set of commands instructing normal reads. In normal read mode, the state of the Ready / Busy signal RB is consistent with "True Busy". "True Busy" indicates that access to the Sensing Amplifier Module (SAM) is disabled, or that a write, read, or erase operation is being performed on the Memory Cell Array (MCA).

[0182] [Cache read mode]

[0183] The cache read mode is the mode for performing a cache read operation. During a cache read, when the ready / busy signal RB is in the "H" state (ready state), and a set of commands instructing a cache read is received (see below)... Figure 19 Command set CS R1When the read operation begins, the ready / busy signal RB is temporarily switched from the "H" state (ready state) to the "L" state (busy state), and then immediately switched back from the "L" state (busy state) to the "H" state (ready state). This sequential change of the ready / busy signal RB in the order of "H" state, "L" state, and "H" state notifies the control die CD that the memory die MD is in cache read mode.

[0184] When the Ready / Busy signal RB is in the "H" state (Ready state), it can accept a set of commands instructing a cache read as the next read operation, even if a cache read operation has not yet finished. In the case of consecutive cache read operations, after the i-th (e.g., i is an integer greater than 1) cache read operation finishes, the (i+1)-th cache read operation begins. In this case, after accepting the set of commands instructing the (i+1)-th cache read, the Ready / Busy signal RB changes from the "H" state (Ready state) to the "L" state (Busy state). When the (i+1)-th cache read operation begins, the Ready / Busy signal RB returns to the "H" state (Ready state). In cache read mode, the state of the Ready / Busy signal RB is inconsistent with "True busy".

[0185] [Connection read mode]

[0186] The connection read mode is the mode in which a connection read operation is performed. The semiconductor memory device according to this embodiment is configured to perform a connection read mode in addition to the normal read and cache read modes. Connection reads are essentially performed in the same way as cache reads. However, in connection reads, not only when the ready / busy signal RB is controlled in the "H" state (ready state), but also when the ready / busy signal RB is controlled in the "L" state (busy state), sometimes a set of commands instructing connection reads (see below) are also received. Figure 20 Command set CS R2 , Figure 30 Command set CS R4 Furthermore, in the case of continuous connection read operations, the i-th (e.g., i is an integer greater than 1) and i+1-th read operations are executed consecutively without interruption (see below). Figure 24 ).

[0187] [Read the set of commands used for the action]

[0188] Next, the actions taken when receiving the command set for the read-out action will be explained. Figure 19 It is used for receiving command set CS R1 A sequence diagram illustrating the actions at a given time. Figure 20 It is used for receiving command set CS R2 A sequence diagram illustrating the actions at a given time.

[0189] Furthermore, in the following explanation, sometimes two-digit hexadecimal numbers are used to represent the 8-bit data input to the 8 data signal input / output terminals DQ0 to DQ7. For example, when "0, 0, 0, 0, 0, 0, 0, 0, 0" is input to the 8 data signal input / output terminals DQ0 to DQ7, this data is sometimes represented as data 00h, etc. Additionally, when "1, 1, 1, 1, 1, 1, 1, 1" is input, this data is sometimes represented as data FFh, etc.

[0190] [Receive command set CS] R1 [Motion at the time]

[0191] exist Figure 19 The example illustrates the command set CS that is input to the memory die MD during a read operation of a cache read. R1 Sometimes it will be used with the command set CS. R1 The corresponding action is called the "first readout action". As described later, the first readout action includes the first readout voltage supply action, the first readout voltage supply action, and the second readout voltage supply action. This command set CS R1 This is the command set that instructs the aforementioned cache reads. However, it's not just for cache reads; the command set CS also applies to read operations during join reads. R1 It is also input into the memory die MD (refer to) Figure 23 ).

[0192] Command set CS R1 This includes data 00h, A101, A102, A103, A104, A105, and 31h. Sometimes this command set CS... R1 The portion of data A101, A102, A103, A104, and A105 contained within this data is called data Add. This data Add is the data input into the address register ADR.

[0193] At timer t101, the control die CD inputs data 00h to the storage die MD as command data D. CMD ( Figure 4 That is, based on each bit of data 00h, the voltage of data signal input / output terminals DQ0 to DQ7 is set to "H" or "L", "H" is input to external control terminal CLE, and "L" is input to external control terminal ALE. In this state, the external control terminal / WE is raised from "L" to "H". Data 00h is the command input at the start of the readout operation.

[0194] At timer t102, the control die CD inputs data A101 to the memory die MD as address data D. ADD ( Figure 4 That is, based on each bit of data A101, the voltage of data signal input / output terminals DQ0 to DQ7 is set to "H" or "L", "L" is input to external control terminal CLE, and "H" is input to external control terminal ALE. In this state, the external control terminal / WE is raised from "L" to "H". Data A101 is part of column address CA.

[0195] At timer t103, the control die CD outputs data A102 to the memory die MD as address data D. ADD ( Figure 4 Data A102 is part of column address CA.

[0196] At timer t104, the control die CD inputs data A103 to the memory die MD as address data D. ADD ( Figure 4 Data A103 is a portion of row address RA. Data A103 may include, for example, a block address and a page address. The block address is the data that determines the storage block BLK. The page address is the data that determines the string cell SU and the word line WL.

[0197] At timer t105, the control die CD inputs data A104 to the memory die MD as address data D. ADD ( Figure 4 Data A104 is a portion of row address RA. Data A104 may include, for example, block address and page address.

[0198] At timer t106, the control die CD inputs data A105 to the memory die MD as address data D. ADD ( Figure 4 Data A105 includes chip address and plane address. The chip address is the data used to determine a memory dies (MDs) from multiple memory dies (MDs) controlled by the control die (CD). The plane address is the data used to determine a memory plane from multiple memory planes (MPL0 to MPL3) controlled by the control die (CD).

[0199] At timer t107, the control die CD inputs data 31h to the storage die MD as command data D. CMD ( Figure 4 Data 31h represents the command set CS related to the read operation. R1 The input has ended.

[0200] At timer t108, the voltage at terminal RBn (ready / busy signal RB) changes from the "H" state to the "L" state, disabling access to memory die MD. Additionally, a read operation is performed on memory die MD.

[0201] [Receive command set CS] R2 [Motion at the time]

[0202] exist Figure 20 The example illustrates the command set CS that is input to the memory die MD during a read operation in a connection read. R2 Sometimes it will be used with the command set CS. R2 The corresponding action is called the "second readout action". As described later, the second readout action includes the second readout voltage supply action and the third readout through voltage supply action. This command set CS R2 This is the command set used to instruct the connection read described above. The command set CS... R2 This includes data XXh, 00h, A101, A102, A103, A104, A105, and 31h. Command set CS. R2 The data outside of XXh and the command set CS R1 It is the same. That is, in the command set CS R1 The command set with the data XXh appended to the beginning is the command set CS. R2 The data XXh is a prefix command. In the diagram, the prefix command is recorded as "Pre".

[0203] Furthermore, the 8 bits constituting the data XXh can be either "0" or "1". Additionally, the first to fourth bits and the fifth to eighth bits of the 8 bits constituting the data XXh can be the same or different.

[0204] In addition, Figure 19 and Figure 20 In the example, the command set CS R1 and command set CS R2 The data Add in the code is set to data A101, A102, A103, A104, and A105. However, this data Add does not mean the same address; it can also be different addresses.

[0205] At time t200, the control die CD inputs data XXh to the storage die MD as command data D. CMD ( Figure 4That is, based on each bit of data XXh, the voltage of data signal input / output terminals DQ0 to DQ7 is set to "H" or "L", "H" is input to external control terminal CLE, and "L" is input to external control terminal ALE. In this state, the external control terminal / WE is raised from "L" to "H". Data XXh is the command for the read operation of notifying the connection to read the memory die MD.

[0206] The actions and uses of receiving data A101, A102, A103, A104, A105, and 31h during timers t201 to t207. Figure 19 The operations of timers t101 to t107, which have already been explained, are the same. Therefore, repeated explanations are omitted.

[0207] [Read voltage supply action]

[0208] Next, the read voltage supply operations (first read voltage supply operation and second read voltage supply operation) for normal read, cache read and connection read will be explained.

[0209] Figure 21 This is a schematic cross-sectional view used to illustrate the read voltage supply operation. Furthermore, the read voltage supply operation described below is common to any read operation, including normal reads, cache reads, and connection reads.

[0210] Furthermore, in the following explanation, the word line WL that will sometimes become the object of the action is referred to as the selection word line WL. S The word lines other than that are called non-selective word lines WL. U Additionally, the following example illustrates this: For the multiple storage units MC contained in the string unit SU that become the object of the action, connected to the select word line WL... S The memory cell (hereinafter sometimes referred to as "select memory cell MC") performs the read voltage supply operation. Additionally, in the following description, such a structure comprising multiple select memory cells MC is sometimes referred to as a select page PG.

[0211] In the readout voltage supply operation, for example, supplying voltage V to the bit line BL. DD For example, latch "H" to... Figure 11 The latching circuit DL0 sets the states of signal lines STB, XXL, BLC, BLS, HLL, and BLX to "L, L, H, H, H, H". This supplies voltage V to bit line BL and sensing node SEN. DD Additionally, a voltage V is supplied to the source line SL. SRC Voltage V SRC It can be compared with the ground voltage V SS Large, or can be related to ground voltage VSS Equal. Voltage V DD Specific voltage V SRC big.

[0212] Additionally, during the readout voltage supply operation, a voltage V is supplied to the drain-side gate selection line SGD. SG Voltage V SG Specific voltage V DD Large. Additionally, the voltage V SG With voltage V DD The voltage difference is greater than the threshold voltage of the drain-side selective transistor STD. Therefore, an electron channel is formed in the channel region of the drain-side selective transistor STD, and the transfer voltage V... DD .

[0213] Additionally, during the readout voltage supply operation, a voltage V is supplied to the source-side gate select lines SGS and SGSb. SG Voltage V SG Specific voltage V SRC Large. Additionally, the voltage V SG With voltage V SRC The voltage difference is greater than the threshold voltage of the source-side selective transistors STS and STSb. Therefore, an electron channel is formed in the channel region of the source-side selective transistors STS and STSb, and the transport voltage V... SRC .

[0214] Additionally, during the readout voltage supply operation, the voltage supply to the select word line WL in the Z direction is... S Two adjacent non-select word lines WL U (Hereinafter sometimes referred to as the non-select word line WL) U1 Supply readout voltage V READK Additionally, compared to the non-selected word line WL U1 The non-select word line WL on the source pole line SL side U (Hereinafter sometimes referred to as the non-select word line WL) U2 Supply readout voltage V READL Additionally, compared to the non-selected word line WL U1 The non-selection word line WL on the BL side of the positioning line U (Hereinafter sometimes referred to as the non-select word line WL) U3 Supply readout voltage V READ Read the voltage V. READ V READK V READL Average voltage V DD V SRC Large. Additionally, read the voltage V. READ V READK V READL With voltage V DD VSRC The voltage difference is greater than the threshold voltage of the memory cell MC, regardless of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, transmitting voltage V to the selected memory cell MC. DD V SRC .

[0215] Additionally, during the read voltage supply operation, the select word line WL is... S Supply readout voltage V CGR Read the voltage V CGR Compare the readings of the voltage V READ V READK V READL Small. Read the voltage V CGR It is a reference Figure 18 The readout voltage V has been explained. CGAR ~V CGGR Any one of them. Read the voltage V. CGR With voltage V SRC The voltage difference is greater than the threshold voltage of a portion of the data-recorded storage cells MC. Therefore, a portion of the data-recorded storage cells MC are in the ON (conducting) state. Consequently, current flows in the bit line BL connected to these storage cells MC. On the other hand, the read voltage V... CGR With voltage V SRC The voltage difference is smaller than the threshold voltage of a portion of the data-recorded storage cells MC. Therefore, a portion of the data-recorded storage cells MC are in the OFF (disconnected) state. Consequently, no current flows in the bit line BL connected to such storage cells MC.

[0216] Additionally, during the readout voltage supply operation, the sensing amplifier SA ( Figure 11 The system detects whether current flows in the bit line BL, thereby detecting the ON / OFF state of the memory cell MC. This action will be referred to as a "sensing action." In a sensing action, for example, when a voltage V is supplied to the bit line BL... DD In this state, the states of signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, H, H, H, L, L". This causes the sensing amplifier SA ( Figure 11 The sensing node SEN of the sensor is turned on and the bit line BL is turned on. Additionally, after a certain period, the states of signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, L, H, H, L, L". This activates the sensing amplifier SA ( Figure 11 The sensing node SEN of the signal transistor 41 is electrically separated from the bit line BL. After performing the sensing action, the state of the signal line STB is temporarily set to "H". Thus, the sensing transistor 41 and the wiring LBUS ( Figure 11When the circuit is turned on, the charge on the wiring LBUS is either discharged or maintained. Additionally, a latch circuit within the sense amplifier unit (SAU) is connected to the wiring LBUS, and this latch circuit latches the data from the wiring LBUS.

[0217] Furthermore, during the read voltage supply operation, AND and OR operations are performed on the data representing the state of the aforementioned memory cell MC as needed, thereby calculating the data recorded in the memory cell MC. This data is then transmitted via a wiring LBUS (LBUS). Figure 11 The switching transistor DSW and wiring DBUS are transmitted to the cache memory CM. Figure 4 The latching circuit within.

[0218] [Read operation of cache access]

[0219] Next, the read operation of the cache will be explained.

[0220] Figure 22 It is a timing diagram used to illustrate the read operation of cache access. Figure 23 This represents the command data D held in the Command Register (CMR) and Address Register (ADR) during a cache read operation. CMD and address data D ADD The example diagram is shown below. Furthermore, the following explanation illustrates the following example, which is: by referring to... Figure 18 Data was allocated to each memory cell (MC) in the manner described in (b), and data was read from the low-order page (LP) and the middle-order page (MP).

[0221] When initiating a cache read operation, the control die CD outputs a command set CS to the memory die MD via data signal input / output terminals DQ0-DQ7, instructing the cache read operation. R1 (1). For example Figure 22 As shown, command set CS R1 (1) Includes data 00h, Add, and 31h. Furthermore, in order to handle multiple command sets CS... R1 To differentiate, the command set CS R1 It was given a number.

[0222] At timer t401, when the input command set CS is received... R1 (1) Command set CS R1 (1) The data 00h and 31h are used as command data D CMD To be held in the command register CMR, command set CS R1 (1) The data Add is used as address data D ADD To be kept in the address register ADR ( Figure 23 ).

[0223] The sequencer SQC is based on the command set CS R1 The input (1) controls the terminal RBn (ready / busy signal RB) from the "H" state to the "L" state. Along with this, access to the memory die MD is disabled. Additionally, a read operation is performed on the memory die MD. Furthermore, at the point when the read operation begins, "True busy" changes from the "H" state to the "L" state.

[0224] During timers t402 to t404, the select word line WL contained in the selected memory block BLK is... S The voltage from the ground voltage V SS Charge to readout voltage V READ Additionally, the non-selected word lines WL contained in the selected memory block BLK will be... U1 WL U2 WL U3 The voltages are respectively from the ground voltage V SS Charge to readout voltage V READK V READL V READ Additionally, a voltage V is supplied to the bit line BL and source line SL contained in the selected memory block BLK. SRC .

[0225] Here, all word lines WL contained in the selected memory block BLK are charged to multiple read pass voltages V. READK V READL V READ At that time, for the voltage generation unit vg2 ( Figure 6 ) to perform its function, or to supply positive charges to the voltage generation unit vg2 ( Figure 6 The charge pump circuit 32 supplies voltage. Thus, as... Figure 22 As shown, when the supplied power supply voltage V CC The operating current I flowing in the pad electrode Px CC Increase.

[0226] At timer t403, the sequencer SQC controls terminal RBn from the "L" state to the "H" state. By changing terminal RBn in this sequence of "H", "L", and "H", the control die CD is notified to the storage die MD that it is in cache read mode.

[0227] Figure 22 The actions of timers t402 to t404 are equivalent to the first readout action via voltage supply.

[0228] Additionally, at timer t404, voltage V is applied to bit line BL. DD Charging. Voltage V is applied to the alignment line BL. DD During charging, a charge pump circuit 32 (not shown) that supplies voltage to the bit line BL supplies positive charge. Thus, as... Figure 22 As shown, when the supplied power supply voltage V CC The operating current I flowing in the pad electrode Px CC Increase.

[0229] Additionally, during timer t404, the selection word line WL is used. S The readout voltage V was supplied. CGER After the low voltage, the readout voltage V is supplied. CGER Therefore, with Figure 18 In (a), the memory cell MC corresponding to states Er to D becomes ON, and the memory cell MC corresponding to states E to G becomes OFF. The following refers to the selection word line WL. S Supply readout voltage V CGR This description means "for the selection word line WL". S The readout voltage V was supplied. CGR After the low voltage, the readout voltage V is supplied. CGR ".

[0230] The sensing action is performed at timer t405. Figure 22 (The "sense" in the text). Therefore, the sensing amplifier SA obtains the readout voltage V. CGER The corresponding readout data. During sensing operations, the amount of charge required to charge the sensing node (SEN) increases. Furthermore, as... Figure 22 As shown, when the supplied power supply voltage V CC The operating current I flowing in the pad electrode Px CC Increase.

[0231] Next, select the word line WL. S Supply readout voltage V CGAR Therefore, with Figure 18 In (a), the memory cell MC corresponding to the Er state becomes ON, and the memory cells MC corresponding to states A to G become OFF.

[0232] The sensing action is performed at timer t406. As a result, the sensing amplifier SA obtains the readout voltage V. CGAR The corresponding read data. At this time, it is also like... Figure 22 As shown, when the supplied power supply voltage V CC The operating current I flowing in the pad electrode Px CC Increase.

[0233] The actions of timers t404 to t407 are equivalent to references Figure 21 The described readout voltage supply operation (first readout voltage supply operation). For example... Figure 21 and Figure 22 As shown, during the readout voltage supply operation, the non-select word line WL... U1 Supply readout voltage V READK Additionally, for non-selected word lines WL U2 Supply readout voltage V READL Additionally, for non-selected word lines WL U3 Supply readout voltage V READ .

[0234] During the timer period t407 to t408, the selection word line WL is... S Supply readout voltage V READ Sometimes the period between timers t407 and t408 is referred to as the channel clean period. The channel clean period is for the select word line WL. S The voltage will drop to the readout voltage V. CGR The voltage is increased to the readout voltage V READ During this period. Additionally, the selected word line WL can also be selected during the channel clearing period. S Supply readout voltage V READK Or V READL Instead of reading through voltage V READ Additionally, during the channel clearing process, the non-select word line WL... U1 WL U2 WL U3 The readout voltage V is supplied separately. READK V READL V READ .

[0235] Additionally, at timer t407, the voltage supplied to bit line BL will be drawn from voltage V. DD Change to voltage V SRC .

[0236] In addition, such as Figure 22 As shown, an operating current I is generated during channel clearing. CC This is because: during channel clearing, the select word line WL... S Reading is performed through voltage V READ Charging.

[0237] Figure 22 The actions of timers t407 to t408 are equivalent to the second readout action via voltage supply.

[0238] At timer t408, select word line WL S Supply ground voltage V SS Additionally, for non-selected word lines WL U1 WL U2 WL U3 Supply ground voltage V SS .

[0239] The sequencer SQC operates based on the command set CS from the control die CD. R1 (2) Input (timer t409) controls terminal RBn from the "H" state to the "L" state. Additionally, as... Figure 23 As shown, the actions of timers t401 to t409 are consistent with the command set CS. R1 (1) The corresponding read action (first read action). Then, execute the command set CS. R1 (2) The corresponding reading action.

[0240] During timers t410 to t412, the select word line WL contained in the selected memory block BLK is... S The voltage from the ground voltage V SS Charge to readout voltage V READ Additionally, the non-selected word lines WL contained in the selected memory block BLK will be... U1 WL U2 WL U3 The voltages are respectively from the ground voltage V SS Charge to readout voltage V READK V READL V READ Therefore, as Figure 22 As shown, when the supplied power supply voltage V CC The operating current I flowing in the pad electrode Px CC Increase.

[0241] At timer t411, the sequencer SQC controls the terminal RBn from the "L" state to the "H" state.

[0242] Figure 22 The actions of timers t410 to t412 are equivalent to the first readout action via voltage supply.

[0243] At timer t412, voltage V is supplied to the bit line BL. DD Additionally, for the selection word line WL S Supply readout voltage V CGFR Therefore, with Figure 18 In (a), the memory cell MC corresponding to Er state to E state becomes ON state, and the memory cell MC corresponding to F state to G state becomes OFF state.

[0244] The sensing action is performed at time t413. As a result, the sensing amplifier SA obtains the readout voltage V. CGFR The corresponding readout data. As mentioned above, during the sensing action, the supplied power supply voltage V... CC The operating current I flowing in the pad electrode Px CC Increase.

[0245] Next, select the word line WL. S Supply readout voltage V CGDR Therefore, with Figure 18 In (a), the memory cell MC corresponding to Er state to C state becomes ON state, and the memory cell MC corresponding to D state to G state becomes OFF state.

[0246] Additionally, a sensing operation is performed at time t414. As a result, the sensing amplifier SA obtains the readout voltage V. CGDR The corresponding read data. At this time, the supplied power supply voltage V CC The operating current I flowing in the pad electrode Px CC It also increases.

[0247] Next, select the word line WL. S Supply readout voltage V CGBR Therefore, with Figure 18 In (a), the memory cell MC corresponding to Er state to A state becomes ON state, and the memory cell MC corresponding to B state to G state becomes OFF state.

[0248] Additionally, a sensing operation is performed at time t415. As a result, the sensing amplifier SA obtains the readout voltage V. CGBR The corresponding read data. At this time, the supplied power supply voltage V CC The operating current I flowing in the pad electrode Px CC It also increases.

[0249] The actions of timers t412 to t416 are equivalent to references Figure 21 The described readout voltage supply operation (first readout voltage supply operation). For example... Figure 21 and Figure 22 As shown, during the read voltage operation, the non-select word line WL... U1 WL U2 WL U3 Supply voltage V respectively READK V READL V READ .

[0250] During the channel clearing period from timer t416 to timer t417, the select word line WL is... SSupply readout voltage V READ Furthermore, during trench clearing, the non-select word line WL... U1 WL U2 WL U3 Supply voltage V respectively READK V READL V READ .

[0251] Additionally, at time t416, the voltage supplied to the bit line BL will be transferred from voltage V. DD Change to voltage V SRC .

[0252] Figure 22 The actions of timing t416 to timing t417 are equivalent to the second readout action via voltage supply.

[0253] At timer t417, select word line WL S Supply ground voltage V SS Additionally, for non-selected word lines WL U1 WL U2 WL U3 Supply ground voltage V SS .

[0254] The sequencer SQC operates based on the command set CS from the control die CD. R1 (3) Input (timer t418) controls terminal RBn from the "H" state to the "L" state. Additionally, as... Figure 23 As shown, the actions of timers t409 to t418 are consistent with the command set CS. R1 (2) The corresponding readout action (first readout action). Then, execute the command set CS. R1 (3) The corresponding reading action.

[0255] In addition, Figure 22 The example illustrates readout actions for the low and middle bits, but high-bit readout actions can also be performed. High-bit readout actions are essentially performed in the same way as low and middle bit readout actions. However, in high-bit readout actions, the select word line WL is first... S Supply readout voltage V CGGR Then, a sensing action is performed. Next, the selection word line WL is selected. S Supply readout voltage V CGCR To perform sensing actions.

[0256] [Read action during connection reading]

[0257] Next, the readout operation of the connection reading according to the first embodiment will be described.

[0258] Figure 24 This is a timing diagram used to explain the readout operation of the connection reading according to the first embodiment. Figure 25 This refers to the command data D stored in the command register CMR and address register ADR during the read operation of the connection read according to the first embodiment. CMD and address data D ADD The example diagram is shown below. Furthermore, the following explanation illustrates the example of using... Figure 22 Similarly, as explained, by reference Figure 18 Data is allocated to each memory cell (MC) in the manner described in (b), and data is read from the low-order page (LP), middle-order page (MP), and high-order page (UP).

[0259] When the read operation begins, the control die CD outputs a command set CS to the memory die MD via data signal input / output terminals DQ0-DQ7, instructing the read operation to read from the cache. R1 .like Figure 24 As shown, command set CS R1 This includes data 00h, Add, and 31h.

[0260] Data Add is, for example, set to determine the data of the low-order page (LP), storage plane MPLx, storage block BLKy, word line WLm, and storage string MSn of the action object.

[0261] At timer t301, when the input command set CS is received... R1 At that time, command set CS R1 The data 00h and 31h are used as command data D CMD To be held in the command register CMR, command set CS R1 (1) The data Add is used as address data D ADD To be stored in the address register ADR. For example Figure 25 As shown, the command register (CMR) and address register (ADR) contain registers for the "currently executing action" and the "next action to be executed." Command set CS R1 The data 00h, Add, and 31h are held in the "register of the currently executing action".

[0262] The sequencer SQC is based on the command set CS R1 The input controls the terminal RBn (ready / busy signal RB) from the "H" state to the "L" state. Simultaneously, access to the memory die MD is disabled. Furthermore, a read operation is performed on the memory die MD. Additionally, at the point when the read operation begins, "True busy" changes from the "H" state to the "L" state.

[0263] During timers t302 to t304, the select word line WL contained in the selected memory block BLK is... S The voltage from the ground voltage V SS Charge to readout voltage V READ Additionally, the non-selected word lines WL contained in the selected memory block BLK will be... U1 WL U2 WL U3 The voltages are respectively from the ground voltage V SS Charge to readout voltage V READK V READL V READ Additionally, a voltage V is supplied to the bit line BL and source line SL contained in the selected memory block BLK. SRC .

[0264] With Figure 22 The same situation described in the timer t402 is also true. Figure 24 The timing t302 is supplied with power voltage V. CC The operating current I flowing in the pad electrode Px CC It also increases.

[0265] At timer t303, the sequencer SQC controls the terminal RBn from the "L" state to the "H" state.

[0266] Figure 24 The actions of timers t302 to t304 are equivalent to the first readout action via voltage supply.

[0267] Additionally, at timer t304, voltage V is applied to bit line BL. DD Charging. (And in) Figure 22 As explained in the timer t404, similarly, when the power supply voltage V is supplied... CC The operating current I flowing in the pad electrode Px CC Increase.

[0268] Additionally, at timer t304, when selecting word line WL... S The readout voltage V was supplied. CGER After the low voltage, the readout voltage V is supplied. CGER Therefore, with Figure 18 In (a), the memory cell MC corresponding to states Er to D becomes ON, and the memory cell MC corresponding to states E to G becomes OFF. The following refers to the selection word line WL. S Supply readout voltage V CGR This description means "for the selection word line WL". S The readout voltage V was supplied. CGRAfter the low voltage, the readout voltage V is supplied. CGR ".

[0269] The sequencer SQC uses a command set CS to indicate the read action of the connection read. R2 (1) Input (timer t305) controls terminal RBn from the "H" state to the "L" state. Furthermore, in order to control multiple command sets CS... R2 To differentiate, the command set CS R2 It was given a number.

[0270] like Figure 24 As shown, command set CS R2 (1) Includes data XXh(Pre), 00h, Add, 31h. The sequencer SQC is based on the command set CS. R2 (1) The attached data Pre(XXh) is used to identify the state of being in the connection read mode.

[0271] When input command set CS R2 (1) Command set CS R2 (1) The data XXh(Pre), 00h, and 31h are used as command data D. CMD To be held in the command register CMR, command set CS R2 (1) The data Add is used as address data D ADD To be stored in the address register ADR. For example Figure 25 As shown, command set CS R2 (1) The data XXh(Pre), 00h, Add and 31h are held in the "register of the next action to be performed".

[0272] Command set CS R2 (1) The data Add contained is, for example, the data of the middle page (MP), storage plane MPLx, storage block BLKy, word line WLm and storage string MSn of the action object.

[0273] Command set CS R1 The included address data D ADD and command set CS R2 (1) The address data D contained therein ADD The storage plane (MPx), storage block (BLKy), word line (WLm), and storage string (MSn) are common.

[0274] The sensing action is performed at timer t306. Figure 24 (The "sense" in the text). Therefore, the sensing amplifier SA obtains the readout voltage V. CGER The corresponding read data. At this time, the supplied power supply voltage V CCThe operating current I flowing in the pad electrode Px CC Increase.

[0275] Next, select the word line WL. S Supply readout voltage V CGAR Therefore, with Figure 18 In (a), the memory cell MC corresponding to the Er state becomes ON, and the memory cells MC corresponding to states A to G become OFF.

[0276] The sensing action is performed at timer t307. As a result, the sensing amplifier SA obtains the readout voltage V. CGAR The corresponding read data. At this time, the supplied power supply voltage V CC The operating current I flowing in the pad electrode Px CC This is also increased. The sense amplifier module (SAM) transmits the read data obtained through sensing actions to the cache memory (CM). When the read data transmitted from the sense amplifier module (SAM) is stored in the latch circuit (XDL), the cache memory (CM) outputs a signal indicating this status to the sequencer (SQC).

[0277] The actions of timers t304 to t308 are equivalent to references Figure 21 The described readout voltage supply operation (first readout voltage supply operation). For example... Figure 21 and Figure 24 As shown, during the readout voltage supply operation, the non-select word line WL... U1 The readout voltage V was supplied. READK Additionally, for non-selected word lines WL U2 Supply readout voltage V READL Additionally, for non-selected word lines WL U3 Supply readout voltage V READ .

[0278] During the timer period t308 to t309, the selection word line WL is... S Supply readout voltage V READ The period between timers t308 and t309 is related to... Figure 22 The timing periods t407 to t408 are also the channel clean period. Furthermore, during the channel clean period, the non-select word line WL... U1 WL U2 WL U3 The readout voltage V is supplied separately. READK V READL V READ .

[0279] Additionally, during channel clearing, a voltage V is supplied to the source line SL.DD Therefore, the bit line BL and the source line SL become the same potential. During channel clearing, multiple read-through voltages V are supplied to all word lines WL of block BLKy. READK V READL V READ Therefore, all memory cells MC connected to these word lines WL become ON. Thus, when there is a potential difference between the bit line BL and the source line SL, a through current flows between the bit line BL and the source line SL. Therefore, by making the bit line BL and the source line SL the same voltage V... DD To prevent the flow of through current.

[0280] During connect read, during channel clearing for word line WL (select word line WL) S and non-selective word line WL U1 WL U2 WL U3 The reading is obtained through voltage V. READK V READL V READ The supply also serves as the subsequent readout action for word lines WL (especially non-selective word lines WL). U The reading is obtained through voltage V. READ Charging. That is, during connected reading, the read voltage V supplied to the word line WL is not allowed to be interrupted during channel clearing. READK V READL V READ Discharge is performed as the readout of word line WL in the subsequent readout operation via voltage V. READK V READL V READ The charging voltage is reused. Therefore, no readout is generated through the voltage V. READK V READL V READ The operating current I during the charging of the word line WL CC .

[0281] In addition, such as Figure 24 As shown, an operating current I is generated during channel clearing. CC This is because: during channel clearing, the select word line WL... S Reading is performed through voltage V READ The charging process. However, the operating current I during channel clearing... CC Compare multiple readouts through voltage V READK V READL V READ The operating current I during charging of all word lines WL CC (The operating current I during the period from timer t302 to timer t304)CC This is because: during the period from timer t302 to timer t304, all word lines WL within the selected memory block BLK are transferred from the ground voltage V. SS Charge to readout voltage V READK V READL V READ In contrast, during the channel clearing period (between timer t308 and timer t309), only the select word line WL is selected. S From the read voltage V CGAR Charge to readout voltage V READ .

[0282] Furthermore, in a linked read, the selection word line WL in the read action performed in the linked read can be omitted if the storage plane MPL and the storage block BLK are the same as the previously executed read action (e.g., the first read action of timers t301 to t309). S The reading is obtained through voltage V READ Charging. When the first read operation (e.g., timer t301 to timer t309) and the second read operation (e.g., timer t309 to timer t316) are executed consecutively, if the storage plane MPL and the storage block BLK are the same, then the read pass voltage V is supplied to all word lines WL within the storage block BLK, which is the target of the first read operation. READK V READL V READ In this case, even if one of the multiple word lines WL within the storage block BLK is selected as the selected word line WL... S The voltage supply action of the first readout can also be omitted in the second readout action.

[0283] In addition, after inputting the command set CS R2 (1) When the command set CS is used R2 (1) If the storage plane MPL or storage block BLK determined by the data Add is different from the storage plane MPL or storage block BLK in the previous read operation, perform a cache read operation (first read operation) (refer to) Figure 22 ).

[0284] Figure 24 The actions of timers t308 to t310 are equivalent to the second readout through voltage supply.

[0285] In timer t309, select word line WL S Supply readout voltage V CGFR Therefore, with Figure 18In (a), the memory cells MC corresponding to Er state to E state become ON state, and the memory cells MC corresponding to F state to G state become OFF state. Thus, in the read operation of the connection read (second read operation), the operation equivalent to the first read voltage supply operation in the read operation of the cache read (first read operation) is omitted. Furthermore, a voltage V is supplied to the source line SL. SRC At this time, the voltage of bit line BL is maintained at voltage V. DD .

[0286] At time t310, the sequencer SQC, based on the signal input from the cache memory CM (indicating that the read data has been stored in the latch circuit XDL), controls the terminal RBn from the "L" state to the "H" state. Additionally, at time t311, the sequencer SQC, based on the command set CS... R2 (2) Input (timer t311) controls terminal RBn from the "H" state to the "L" state. Additionally, as... Figure 25 As shown, the actions of timers t301 to t310 are related to the command set CS. R1 The corresponding read action (first read action). Then, execute the command set CS. R2 (1) The corresponding reading action.

[0287] The sequencer SQC is based on the command set CS R2 (2) The attached data Pre(XXh) is used to identify the state of being in the connection reading mode.

[0288] When input command set CS R2 (2) Command set CS R2 (2) The data XXh(Pre), 00h, and 31h are used as command data D. CMD To be held in the command register CMR, command set CS R2 (2) The data Add is used as address data D ADD To be stored in the address register ADR. For example Figure 25 As shown, command set CS R2 (2) The data XXh(Pre), 00h, Add and 31h are held in the "register of the next action to be performed".

[0289] Command set CS R2 (2) The data Add included is, for example, the data of the high page (UP), storage plane MPLx, storage block BLKy, word line WLm and storage string MSn of the action object.

[0290] Command set CS R2 (1) The address data D contained thereinADD and command set CS R2 (2) The address data D contained therein ADD The storage plane (MPx), storage block (BLKy), word line (WLm), and storage string (MSn) are common.

[0291] The sensing action is performed at time t312. As a result, the sensing amplifier SA obtains the readout voltage V. CGFR The corresponding readout data. As mentioned above, during the sensing action, the supplied power supply voltage V... CC The operating current I flowing in the pad electrode Px CC Increase.

[0292] Next, select the word line WL. S Supply readout voltage V CGDR Therefore, with Figure 18 In (a), the memory cell MC corresponding to Er state to C state becomes ON state, and the memory cell MC corresponding to D state to G state becomes OFF state.

[0293] Additionally, a sensing operation is performed at time t313. As a result, the sensing amplifier SA obtains the readout voltage V. CGDR The corresponding read data. At this time, the supplied power supply voltage V CC The operating current I flowing in the pad electrode Px CC Increase.

[0294] Next, select the word line WL. S Supply readout voltage V CGBR Therefore, with Figure 18 In (a), the memory cell MC corresponding to Er state to A state becomes ON state, and the memory cell MC corresponding to B state to G state becomes OFF state.

[0295] Additionally, a sensing operation is performed at time t314. As a result, the sensing amplifier SA obtains the readout voltage V. CGBR The corresponding read data. At this time, the supplied power supply voltage V CC The operating current I flowing in the pad electrode Px CC This is also increased. The sense amplifier module (SAM) transmits the read data obtained through sensing actions to the cache memory (CM). When the read data transmitted from the sense amplifier module (SAM) is stored in the latch circuit (XDL), the cache memory (CM) outputs a signal indicating this status to the sequencer (SQC).

[0296] Actions and references of timers t309 to t315 Figure 21 The described readout voltage supply action (second readout voltage supply action) is equivalent. For example... Figure 21 and Figure 24 As shown, during the read voltage operation, the non-select word line WL... U1 WL U2 WL U3 Supply voltage V respectively READK V READL V READ .

[0297] The same actions are performed during the channel clearing period of timers t315 to t316 as during the channel clearing period of timers t308 to t309. That is, during the channel clearing period, the select word line WL is... S Supply readout voltage V READ Furthermore, during trench clearing, the non-select word line WL... U1 WL U2 WL U3 Supply voltage V respectively READK V READL V READ .

[0298] Additionally, during channel clearing, a voltage V is supplied to the source line SL. DD Therefore, the bit line BL and the source line SL are at the same potential, preventing through current flow. Additionally, during channel clearing, the multiple read pass voltages V supplied to all word lines WL are prevented from being applied. READK V READL V READ Discharge is performed, and the readout voltage V is used in the subsequent readout operation. READ Select word line WL S The charging voltage can be reused.

[0299] Furthermore, in subsequent join read operations (e.g., the second read operation from time t316 to time t322), the selection word line WL can be omitted if the storage plane MPL and storage block BLK are the same as those in the previous join read operation (e.g., the second read operation from time t309 to time t316). S The reading is obtained through voltage V READ Charging. In the case of two consecutive second read operations, if the memory plane MPL and memory block BLK are the same, then a read pass voltage V is supplied to all word lines WL within the memory block BLK, which was the target of the previous second read operation. READK V READL V READ In this case, even if one of the multiple word lines WL within the storage block BLK is selected as the selected word line WL... SThe voltage supply action of the first readout can also be omitted in the second readout action.

[0300] Figure 24 The actions of timers t315 to t316 are equivalent to the third readout through voltage supply.

[0301] At timer t316, select word line WL S Supply readout voltage V CGGR Therefore, with Figure 18 In (a), the memory cells MC corresponding to the Er to F states become ON, and the memory cells MC corresponding to the G state become OFF. Additionally, a voltage V is supplied to the source line SL. SRC At this time, the voltage of bit line BL is maintained at voltage V. DD .

[0302] At time t317, the sequencer SQC, based on the signal input from the cache memory CM (indicating that the read data has been stored in the latch circuit XDL), controls the RBn terminal from the "L" state to the "H" state. Additionally, the sequencer SQC, based on the command set CS... R2 (3) Input (timer t318) controls terminal RBn from the "H" state to the "L" state. Additionally, as... Figure 25 As shown, the actions of timers t310 to t317 are consistent with the command set CS. R2 (1) The corresponding readout action (second readout action). Then, execute the command set CS. R2 (2) The corresponding readout actions (actions of timer t317 to timer t323).

[0303] The sequencer SQC is based on the command set CS R2 (3) The attached data Pre(XXh) is used to identify the state of being in the connection reading mode.

[0304] When input command set CS R2 (3) Command set CS R2 (3) The data XXh(Pre), 00h, and 31h are used as command data D. CMD To be held in the command register CMR, command set CS R2 (3) The data Add is used as address data D ADD To be stored in the address register ADR. For example Figure 25 As shown, command set CS R2 (3) The data XXh(Pre), 00h, Add and 31h are held in the "register of the next action to be performed".

[0305] Although Figure 24 Not shown in the diagram, but set as command set CS R2 (3) The included data Add is, for example, the data for the high page (UP), storage plane MPLx, storage block BLKy, word line WLm, and storage string MSn that determine the action object.

[0306] The sensing action is performed at time t319. As a result, the sensing amplifier SA obtains the readout voltage V. CGGR The corresponding readout data. As mentioned above, during the sensing action, the supplied power supply voltage V... CC The operating current I flowing in the pad electrode Px CC Increase.

[0307] Next, select the word line WL. S Supply readout voltage V CGCR Therefore, with Figure 18 In (a), the memory cell MC corresponding to Er state to B state becomes ON state, and the memory cell MC corresponding to C state to G state becomes OFF state.

[0308] Additionally, a sensing operation is performed at time t320. As a result, the sensing amplifier SA obtains the readout voltage V. CGCR The corresponding read data. At this time, the supplied power supply voltage V CC The operating current I flowing in the pad electrode Px CC This is also increased. The sense amplifier module (SAM) transmits the read data obtained through sensing actions to the cache memory (CM). When the read data transmitted from the sense amplifier module (SAM) is stored in the latch circuit (XDL), the cache memory (CM) outputs a signal to the sequencer (SQC) indicating this status.

[0309] Actions and references of timers t316 to t321 Figure 21 The described readout voltage supply action (second readout voltage supply action) is equivalent. For example... Figure 21 and Figure 24 As shown, during the read voltage operation, the non-select word line WL... U1 WL U2 WL U3 Supply voltage V respectively READK V READL V READ .

[0310] The same actions are performed during the channel clearing periods of time t321 to time t322 as during the channel clearing periods of time t308 to time t309 and time t315 to time t316.

[0311] Figure 24The actions of timers t321 to t322 are equivalent to the third readout action via voltage supply.

[0312] At timer t323, the sequencer SQC, based on the signal input from the cache memory CM (indicating that the read data has been stored in the latch circuit XDL), controls the terminal RBn from the "L" state to the "H" state. This enables it to accept command sets.

[0313] [Effect]

[0314] With the increasing integration of semiconductor memory devices, the conductive layer 110 stacked in the Z direction ( Figure 14 , Figure 15 The number of word lines (WL) is constantly increasing. Along with this, the amount of charge required to charge the word lines (WL), especially the non-selective word lines (WL), is constantly increasing, even with the supplied power supply voltage V. CC The operating current I flowing in the pad electrode Px CC The current continuously increases. Accompanying this, power consumption and heat generation sometimes increase. To reduce such operating current I... CC For example, it can also extend Figure 22 The timing from t410 to t412 reduces the amount of charge moved per unit time. However, in such cases, the time required for reading multiple pages can sometimes become longer.

[0315] In this embodiment, the read pass voltage V supplied to the word line WL during channel clearing is not allowed. READK V READL V READ Discharge is performed, and the readout voltage V is used in the subsequent readout operation. READK V READL V READ The charging voltage of the word line WL is reused. Therefore, the readout voltage V can be reduced. READK V READL V READ Word lines WL (especially non-selective word lines WL) U The operating current I during charging CC .

[0316] Furthermore, in this embodiment, the read-through voltage V in the read operation can be omitted if the storage plane MPL and the storage block BLK are the same. READ For selecting the word line WL S This allows for faster charging of multiple pages. Therefore, it reduces the time required to read multiple pages.

[0317] In addition, sometimes in Figure 25The "register for next action" shown contains not only the command set CS indicating the connection read. R2 The data also maintains the CS command set that instructs cache reads. R1 The data. For example, sometimes the plane address or block address of the currently executing first or second read action is different from the plane address or block address of the next read action. In this case, as described above, the join read action (second read action) cannot be executed, therefore, the command set CS input indicating cache read is not executed. R1 Furthermore, this command set CS R1 It is held in the "register for the next action to be executed". However, the "register for the next action to be executed" can also only hold the command set CS. R2 . dedicated register.

[0318] Furthermore, in serving as Figure 23 If the address register (ADR) and command register (CMR), which are the registers for the currently executing action, are not free, the memory die (MD) cannot accept any command set, nor will it execute any action based on that command set. Furthermore, when used as... Figure 25 If the two sets of address registers, ADR and CMR, namely "Register of the currently executing action" and "Register of the next action to be executed", are not free, the memory die MD cannot accept any command set, nor will it execute any action based on that command set.

[0319] [Second Implementation]

[0320] In the connection read according to the second embodiment, the information is provided to the select word line WL just before the channel clearing period. S Readout voltage V CGR The level of the channel is adjusted to change the length during channel clearing.

[0321] As mentioned above Figure 24 As shown, just before the channel clearing period (timer t308 to timer t309), the signal is supplied to the select word line WL. S Readout voltage V CGR The readout voltage V corresponding to state A CGAR In this case, the length of the channel clearing period (timing t308 to timing t309) is time T1. Additionally, just before the channel clearing period (timing t315 to timing t316), the selected word line WL is supplied... S Readout voltage V CGR The readout voltage V corresponding to state B CGBRIn this case, the length of the channel clearing period (timing t315 to timing t316) is time T2. Additionally, just before the channel clearing period (timing t321 to timing t322), the signal is supplied to the select word line WL. S Readout voltage V CGR The readout voltage V corresponding to state C CGCR In this case, the length of the ditch clearing period (time t321 to time t322) is time T3.

[0322] In order to supply to the select word line WL S The voltage from the read voltage V CGAR Rise to readout voltage V READ The time required to read the voltage V CGBR Rise to readout voltage V READ The time required to read the voltage V CGCR Rise to readout voltage V READ The required time varies. Therefore, in the second embodiment, the time required is based on the time supplied to the select word line WL before the channel clearing period. S Readout voltage V CGR The level of the channel is adjusted to change the length during channel clearing.

[0323] exist Figure 24 In the example, the voltage V is read. CGAR Comparison of readout voltage V CGBR Small. Therefore, it is made to read the voltage V. CGAR Rise to readout voltage V READ The time ratio makes it read from the voltage V CGBR Rise to readout voltage V READ The time required is longer. Therefore, the time T1 during ditch clearing is longer than the time T2.

[0324] Additionally, the read voltage V CGBR Comparison of readout voltage V CGCR Small. Therefore, it is made to read the voltage V. CGBR Rise to readout voltage V READ The time ratio makes it read from the voltage V CGCR Rise to readout voltage V READ The time required is longer. Therefore, the time T2 during ditch clearing is longer than the time T3.

[0325] According to the configuration of the second embodiment, it is possible to determine the readout voltage V. CGR The level is adjusted appropriately to control the length of the channel clearing process.

[0326] [Third Implementation]

[0327] In the connection reading according to the third embodiment, the command set CS is input. R2 Then other command sets CS were entered. R2 In the case of ', the command set CS R2 Replace with other command sets CS R2 ′.

[0328] Figure 26 This is a timing diagram used to explain the readout operation of the connection reading according to the third embodiment. Figure 27 This refers to the command data D held in the command register CMR and address register ADR during the read operation of the connection read according to the third embodiment. CMD and address data D ADD An example diagram. Furthermore... Figure 26 The operation and reference of timers 301 to 323 (except for timer 30X) Figure 24 The actions described are the same, therefore, repeated descriptions are omitted.

[0329] Similar to the first embodiment described above, the input instruction set CS for connection reading is used. R2 (1). In the third embodiment, after inputting the command set CS R2 (1) After that, Figure 26 The timer t30X has a new command set CS input. R2 In case (1), the already entered command set CS R2 (1) The command set CS that was replaced with the newly entered command set R2 (1)′. For example, as shown in the following example. Figure 27 As shown, the command set CS is held in the "register of the action to be executed next". R2 (1) The data is controlled by the command set CS R2 (1)' data overwriting. In this case, such as Figure 27 As shown, for the actions of timers t310 to t311 and t311 to t317, the command set CS is executed. R2 (1)′ refers to the action specified by the data.

[0330] The state of terminal RBn (ready / busy signal RB) indicates whether a command set can be accepted. As mentioned above, normally, when terminal RBn is in the "H" state (ready period), it indicates that a command set can be accepted, and when terminal RBn is in the "L" state (busy period), it indicates that a command set cannot be accepted. However, the data Pre(XXh) signifies a special command that the memory die MD can accept even during a busy period. The memory die MD, based on the command set CS... R2Commands with a prefix (data XXh(Pre)) are identified as special command sets, and such command sets are exceptionally entered and processed even during busy periods.

[0331] However, when the memory die MD is in the "L" state (busy state) of terminal RBn (ready / busy signal RB), it will not execute the action based on the command set even if the input does not have a command set with a prefix command (data XXh(Pre)).

[0332] Able to input the command set CS to be replaced R2 (1)′ is the period up to the timing of the end of the first read voltage supply operation (timing of the start of the channel clearing period: t308). This is because: after the start of the channel clearing period, even if the input command set CS is entered... R2 (1)′, also unable to perform the read operation of connection reading.

[0333] In addition, Figure 27 The "register for next action" shown sometimes contains more than just the command set CS for performing a connection read. R2 The data also maintains the CS command set that instructs cache reads. R1 The data. However, the "register for the next action" can also only hold the command set CS. R2 . dedicated register.

[0334] According to the configuration of the third embodiment, the command set CS is output from the control die CD. R2 (1) After that, for example, even if the first read is generated and the command set CS is generated. R2 (1) In cases where data is required at addresses different from those specified, the command set CS held in the register can also be output by outputting other command sets CSR2(1)′. R2 (1) data is replaced with data from other command sets CSR2(1)′.

[0335] [Fourth Implementation]

[0336] In the connection reading involved in the first embodiment described above, the selection word line WL will be sent... S The supplied readout voltage V CGR The read voltage has switched from a high level to a low level. In contrast, in the connection read according to the fourth embodiment, the select word line WL is switched... S The supplied readout voltage V CGR Switching from a low-level readout voltage to a high-level readout voltage.

[0337] Figure 28This is a timing diagram used to explain the readout operation of the connection reading according to the fourth embodiment.

[0338] In the readout voltage supply operation of the connection reading according to the first embodiment described above, such as Figure 24 As shown, according to the read voltage V CGER V CGAR The order of the select word lines WL S Supply was made, according to the read voltage V CGFR V CGDR V CGBR The order of the select word lines WL S Supply was made, according to the read voltage V CGGR V CGCR The order of the select word lines WL S Supply was made. In contrast, in the readout voltage supply operation for connection reading according to the fourth embodiment, such as... Figure 28 As shown, according to the read voltage V CGAR V CGER The order of the select word lines WL S Supply is made according to the read voltage V. CGBR V CGDR V CGFR The order of the select word lines WL S Supply is made according to the read voltage V. CGCR V CGGR The order of the select word lines WL S To provide supply. Regarding the other components, see reference. Figure 24 The content has been explained repeatedly, therefore, the repeated explanations are omitted.

[0339] In this configuration, the readout voltage V can also be reduced. READK V READL V READ Word lines WL (especially non-selective word lines WL) U The operating current I during charging CC Furthermore, it can shorten the time required to read multiple pages.

[0340] [Fifth Implementation]

[0341] Next, refer to Figure 29 The connection reading in the multiple storage planes (MPLs) according to the fifth embodiment will be described. Figure 29 This is a schematic timing diagram used to explain the readout operation of the connection reading according to the fifth embodiment.

[0342] For reference Figure 13 As explained, the memory die MD (chip C) MThe device has four storage planes, MPL0 to MPL3. The semiconductor memory device according to the fifth embodiment can simultaneously perform linked read operations on multiple select pages PG contained in different storage planes MPL0 to MPL3, or perform linked read operations in parallel at independent timings. This function is sometimes referred to as AIPR (Asynchronous Independent Plane Read).

[0343] In addition, Figure 29 In the text, "Read Operation" is used for example with... Figure 24 The actions of timers t304–t308, t309–t315, and t316–t321 correspond to these timers. Additionally, “Ch-Clean” is, for example, associated with… Figure 24 The corresponding time intervals t308 to t309, t315 to t316, and t3321 to t322 correspond to the channel clearing period.

[0344] During the read operation, each of the four memory planes MPL0 to MPL3 is in the "L" state of "True Busy". Additionally, each of the four memory planes MPL0 to MPL3 outputs a ready / busy signal RB from terminal RBn. Furthermore, each of the four memory planes MPL0 to MPL3 receives a command set CS. R1 CS R2 Execution and command set CS R1 CS R2 The corresponding actions generate operating currents I corresponding to the actions of the four storage planes MPL0 to MPL3, respectively. CC .

[0345] The ready / busy signal RB of the memory die MD is output as the OR condition for the ready / busy signals RB of each memory plane MPL0 to MPL3. Additionally, the control die CD cannot simultaneously output multiple command sets CS. R1 CS R2 Therefore, the control die CD uses the command set CS for each memory plane MPL0 to MPL3. R1 CS R2 The output timing is non-overlapping, and the command set CS is output to each storage plane MPL0~MPL3 in a manner that avoids overlap. R1 CS R2 Additionally, the operating current I in the memory die MD... CC It is the operating current I of each storage plane MPL0 to MPL3 CC The result is obtained by adding them together.

[0346] According to the configuration of the fifth embodiment, the readout voltage V can be reduced in each storage plane MPL0 to MPL3. READK V READL V READ For word lines WL (especially non-selective word lines WL) U The operating current I during charging CC As a result, the operating current I in the memory die MD can be further reduced. CC .

[0347] [Sixth Implementation]

[0348] Next, refer to Figure 30 The connection reading after normal reading according to the sixth embodiment will be described. Figure 30 This is a timing diagram used to explain the readout operation of the connection reading according to the sixth embodiment.

[0349] In the first embodiment ( Figure 24 In the sixth embodiment, at time t303, terminal RBn is controlled from the "L" state to the "H" state, and at time t305, terminal RBn is controlled from the "H" state to the "L" state. In contrast, in the sixth embodiment... Figure 30 During timing t303 to t305, terminal RBn is maintained in the "L" state.

[0350] In addition, in the first embodiment ( Figure 24 In this process, the memory die MD first inputs the command set CS, which instructs the cache to be read, from the control die CD. R1 Then, the command set CS indicating the connection read was input from the control die CD. R2 In contrast, in the sixth embodiment ( Figure 30 In the first step, the command set CS, which is usually read, is indicated from the control die CD input. R3 Then, the command set CS is read from the control die CD input. R4 .

[0351] Sometimes it will be with the command set CS R3 The corresponding read action is called the first read action, and it will be associated with the command set CS. R4 The corresponding reading action is called the second reading action. For example... Figure 30 As shown, command set CS R3 This includes data such as 00h, Add, and 30h. For example... Figure 30 As shown, command set CS R4 This includes data Pre(XXh), 00h, Add, and 30h.

[0352] As mentioned above, the data Pre(XXh) signifies a special command that the memory chip MD can process even during busy periods. The memory chip MD, based on the command set CS... R4 Commands with a prefix (data XXh(Pre)) are identified as special command sets, and such command sets are exceptionally entered and processed even during busy periods.

[0353] However, when the memory die MD is in the "L" state (busy state) of terminal RBn (ready / busy signal RB), it will not execute the action based on the command set even if a command set without the prefix command (data XXh(Pre)) is input.

[0354] Able to input command set CS R4 (1) is the period up to the time when the first read voltage supply operation ends (time when the channel clearing period begins: t308). This is because: after the channel clearing period begins, even if the input command set CS is entered... R4 (1) It is also unable to perform the read operation for connection reading. Figure 30 In the example, the input command set CS is at timer t30Y. R4 (1).

[0355] also, Figure 30 Command set CS R4 (2) CS R4 (3) During the ready period and Figure 24 Command set CS, etc. R2 (2) CS R2 (3) Input is performed at the same time. However, Figure 30 Command set CS R4 (2) CS R4 (3) Input can also be made during busy periods. In this case, the command set CS can be input. R4 (2) CS R4 (3) is also the period until the timing of the end of the first read voltage supply operation (the timing of the start of the channel clearing period).

[0356] In this configuration, the readout voltage V can also be reduced. READK V READL V READ For word lines WL (especially non-selective word lines WL) U The operating current I during charging CC Furthermore, it can shorten the time required to read multiple pages.

[0357] [Other Implementation Methods]

[0358] The semiconductor memory devices according to the first to sixth embodiments have been described above. However, the semiconductor memory devices described above are merely examples, and their operation, structure, etc., can be appropriately adjusted.

[0359] For example, in the semiconductor memory devices according to embodiments 1 to 6, as shown in reference... Figure 16 As explained, each memory cell (MC) records 3 bits of data. However, the data recorded in the memory cell (MC) can be 1 bit, 2 bits, or more than 4 bits.

[0360] Additionally, for example in Figure 24 During the channel clearing process (timers t308 to t309, etc.), a voltage V is supplied to the source line SL. DD However, a voltage V can also be supplied to the bit line BL during channel clearing (timers t308 to t309, etc.). SRC Even with this configuration, it is possible to keep the bit line BL and the source line SL at the same potential during channel clearing.

[0361] Additionally, the control die CD can also output a command set CS indicating connection reading during periods when it is not possible to output. R2 In this case, the output indicates the command set CS for cache reads. R1 .

[0362] Additionally, the command set CS that indicates the connection to be read. R2 It allows for an unlimited number of inputs. Additionally, it is compatible with the command set CS. R2 The corresponding second readout action can be executed any number of times consecutively.

[0363] [other]

[0364] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: A memory string having multiple memory transistors connected in series; and Multiple conductive layers are connected to the gate electrodes of the multiple storage transistors. Execute the first read action based on the input of the first command set. The second read action is performed based on the input of the second command set. The first readout action includes: The first readout voltage supply operation supplies a readout voltage to the first conductive layer, which is one of the plurality of conductive layers; The first readout voltage supply operation involves supplying a readout voltage smaller than the readout through voltage to the first conductive layer after the first readout through voltage supply operation is performed; and The second readout voltage supply action involves supplying the readout voltage to the first conductive layer after the first readout voltage supply action is performed. The second readout action includes: The second readout voltage supply operation involves supplying the readout voltage to a second conductive layer, which is either the same as or different from the first conductive layer, after the first readout operation is performed; and The third readout voltage supply action involves supplying the readout voltage to the second conductive layer after the second readout voltage supply action is performed. The first readout action and the second readout action are executed consecutively. During the period from the execution of the second readout through voltage supply action to the end of the third readout through voltage supply action, the voltage of the first non-selective conductive layer, which is different from the first conductive layer, and the second non-selective conductive layer, which is different from the second conductive layer, among the plurality of conductive layers are maintained at the readout through voltage.

2. The semiconductor memory device according to claim 1, Based on the input of the second command set for the second time, after executing the second read action, the second read action is executed continuously for the second time. In the second readout voltage supply operation, After performing the second readout operation, the readout voltage is supplied to the third conductive layer, which is one of the plurality of conductive layers and is either the same as or different from the second conductive layer. The second third readout is achieved through the voltage supply operation. After performing the second readout voltage supply operation, the readout voltage is supplied to the third conductive layer. During the period from the execution of the second readout voltage supply operation to the end of the second third readout voltage supply operation, the voltage of the second non-selective conductive layer and the third non-selective conductive layer, which is different from the third conductive layer, among the plurality of conductive layers are maintained at the readout voltage.

3. The semiconductor memory device according to claim 1, When the read voltage supplied during the first read voltage supply operation before the second read voltage supply operation is about to be executed is set as the first read voltage, and the read voltage supplied during the second read voltage supply operation before the third read voltage supply operation is about to be executed is set as the second read voltage, The first readout voltage is lower than the second readout voltage. The execution time of the second readout via voltage supply action is longer than the execution time of the third readout via voltage supply action.

4. The semiconductor memory device according to claim 1, The input of the second command set is completed before the second readout is initiated via voltage supply.

5. The semiconductor memory device according to claim 1, The second input of the second command set ends before the start of the third read-through voltage supply operation. During the period from the execution of the first second read-through voltage supply operation to the end of the second third read-through voltage supply operation, the voltage of the plurality of second non-selective conductive layers is maintained at the read-through voltage.

6. The semiconductor memory device according to claim 1, The second command set can be input any number of times.

7. The semiconductor memory device according to claim 1, The second input of the second command set ends after the third readout of the first operation via voltage supply. Based on the input of the second command set for the second time, after executing the third readout via voltage supply action for the first time, the first readout action is executed.

8. The semiconductor memory device according to any one of claims 1 to 7, The readout voltage is a voltage within a range of multiple voltage values ​​applied to the non-selective conductive layer when performing the first readout action or the second readout action.

9. A semiconductor memory device comprising: Multiple storage blocks; and Power supply terminals, Execute the first read action based on the input of the first command set. The second read action is performed based on the input of the second command set. The first readout action and the second readout action are executed consecutively. The input to the second command set ends within a predetermined period, which is the period during which the first read-out action is performed. When the maximum value of the current flowing in the power supply terminal during the execution of the first readout operation is set as the first current value, and the maximum value of the current flowing in the power supply terminal during the execution of the second readout operation is set as the second current value, The second current value is smaller than the first current value.

10. The semiconductor memory device according to claim 9, Based on the input of the second command set for the second time, after executing the second read action, the second read action is executed continuously for the second time. The input of the second set of commands for the second time ends within a predetermined period during the execution of the second readout action. When the maximum value of the current flowing in the power supply terminal during the second readout operation is set as the third current value, The third current value is smaller than the first current value.

11. The semiconductor memory device according to claim 9, The first command set includes the first address data. The second command set includes the second address data. The first address data and the second address data include data that specifies the same storage block among the plurality of storage blocks.

12. The semiconductor memory device according to claim 9, It is configured to output a ready / busy signal indicating whether a set of commands can be accepted. The second command set is configured to be able to be accepted when the ready / busy signal is in a busy state where the command set cannot be accepted.

13. The semiconductor memory device according to claim 9, It is configured to output a ready / busy signal indicating whether a set of commands can be accepted. The second command set is input when the ready / busy signal is in a ready state that can accept the command set.

14. The semiconductor memory device according to claim 12 or 13, The ready / busy signal becomes busy based on the input of the command set, and returns to the ready state upon completion of the readout action in the busy state.

15. The semiconductor memory device according to any one of claims 9 to 13, When the time from the start of the first read action to the end of the first read action is defined as the first time, and the time from the start of the second read action to the end of the second read action is defined as the second time, The second time is shorter than the first time.

16. The semiconductor memory device according to any one of claims 9 to 13, The first command set and the second command set include: First command data; Address data input after the first command data; as well as The second command data is entered after the address data. The second command set includes prefix data that was entered before the first command data. The first command set does not include the prefix data.

17. The semiconductor memory device according to any one of claims 9 to 13, It has multiple planes. Each of the plurality of planes has the plurality of storage blocks. Each of the plurality of planes executes the first readout action based on the input of the first command set, and executes the second readout action based on the input of the second command set. A portion of the second readout action performed in the plurality of planes overlaps during the action.

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