A method of forming an interconnect structure
By forming a second dielectric layer and a mask layer on the substrate in the COAG process, and using two etching steps to protect the metal layer, the problems of metal layer damage and excessive mask usage are solved, and low-cost interconnect structure formation is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2022-03-25
- Publication Date
- 2026-05-29
Smart Images
Figure CN116845028B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a method for forming an interconnect structure. Background Technology
[0002] Currently, in 7 / 5nm FinFETs, the Contact On Active Gate (COAG) process has begun to be used. Compared with the traditional gate contact hole plug located above the gate structure in the isolation region, the COAG process can place the gate contact hole above the gate structure in the active area (AA), further saving chip area.
[0003] In the COAG process, combining the patterning processes for the gate contact via (VOG) and the source / drain contact via (VDR) can save on mask usage. However, this approach can cause damage to the metal layers on the source and drain. Summary of the Invention
[0004] The technical problem this application aims to solve is how to address metal layer damage in the COAG process using fewer masks.
[0005] To address the aforementioned technical problems, this application provides a method for forming an interconnect structure, comprising: providing a substrate, wherein discrete metal gates are formed on the substrate, and active drains are formed in the substrate on both sides of the metal gates; the surfaces of the substrate and the metal gates further include a first dielectric layer, the first metal layer penetrating the first dielectric layer and electrically connected to the top surface of the active drains; sequentially forming a second dielectric layer and a mask layer on the first metal layer and the first dielectric layer; performing a first etching and a second etching, wherein the first etching forms a pattern of a first gate contact hole and a first source / drain contact hole adjacent to each other in the mask layer perpendicular to the extension direction of the metal gate, and the second etching forms a pattern of a second gate contact hole and a second source / drain contact hole adjacent to each other in the mask layer perpendicular to the extension direction of the metal gate, wherein the first source / drain contact hole and the second source / drain contact hole are adjacent in the extension direction of the metal gate, and the first gate contact hole and the second gate contact hole are located on the metal gate in the active region; using the patterned mask layer as a mask, etching the second dielectric layer and the first dielectric layer to form the first gate contact hole, the second gate contact hole, the first source / drain contact hole, and the second source / drain contact hole.
[0006] In some embodiments of this application, the distance between the first source / drain contact hole and the second source / drain contact hole is 30nm to 150nm.
[0007] In some embodiments of this application, the first etching and the second etching form in the mask layer a first opening for defining the first gate contact hole, a second opening for defining the first source / drain contact hole, a third opening for defining the first gate contact hole, and a fourth opening for defining the second source / drain contact hole.
[0008] In some embodiments of this application, after the first etching and the second etching, the forming method further includes: forming a padding layer on the surface of the mask layer and the sidewall and bottom surfaces of the first opening, the second opening, the third opening and the fourth opening, for adjusting the key dimensions of the first opening, the second opening, the third opening and the fourth opening.
[0009] In some embodiments of this application, the pad layer, the second dielectric layer, and the first dielectric layer are etched in the same process.
[0010] In some embodiments of this application, the material of the liner layer includes silicon nitride and / or silicon oxide.
[0011] In some embodiments of this application, the mask layer includes a first mask layer and a second mask layer stacked sequentially on the surface of the second dielectric layer, wherein the thickness of the second dielectric layer is 3nm to 30nm, the thickness of the first mask layer is 10nm to 50nm, and the thickness of the second mask layer is 5nm to 50nm.
[0012] In some embodiments of this application, the material of the second dielectric layer includes silicon nitride, the material of the first mask layer includes silicon oxide, and the material of the second mask layer includes at least one of silicon nitride, titanium nitride, and silicon carbide.
[0013] In some embodiments of this application, the forming method further includes: removing the remaining second mask layer; forming a second metal material layer in the first gate contact hole, the second gate contact hole, the first source / drain contact hole, and the second source / drain contact hole, as well as on the surface of the remaining first mask layer; grinding the second metal material layer to form a second metal layer in the first gate contact hole, the second gate contact hole, the first source / drain contact hole, and the second source / drain contact hole with a top surface flush with the surface of the first mask layer.
[0014] In some embodiments of this application, a third dielectric layer is further included between the metal gate and the first dielectric layer, between the metal gate and the first metal layer, and between the metal gate and the source / drain; when etching the second dielectric layer and the first dielectric layer, the third dielectric layer on the gate surface of the active region is also etched.
[0015] In some embodiments of this application, the material of the first dielectric layer includes silicon oxide, and the material of the third dielectric layer includes silicon nitride and / or silicon oxide.
[0016] Compared with the prior art, the interconnect structure formation method of the present application forms a second dielectric layer and a mask layer sequentially on a first metal layer and a first dielectric layer, and forms the pattern of a first gate contact hole, a first source / drain contact hole, a second gate contact hole, and a second source / drain contact hole only in the mask layer through the first etching and the second etching. Therefore, the first metal layer on the source / drain surface is protected by the second dielectric layer and will not be exposed during the two etching processes, which can effectively reduce the damage to the first metal layer.
[0017] The first and second etching processes simultaneously form the gate contact hole and source / drain contact hole patterns in a single etching process, reducing the use of masks and significantly lowering costs. Attached Figure Description
[0018] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:
[0019] Figures 1 to 4 This is a schematic diagram of a COAG process.
[0020] Figure 5 This is a flowchart illustrating a method for forming an interconnect structure according to an embodiment of this application.
[0021] Figures 6 to 12 This is a schematic diagram of the steps in the method for forming the interconnect structure according to an embodiment of this application. Detailed Implementation
[0022] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0023] In the current COAG process, there is still a problem of damaging the metal material in the contact holes. Figure 1A top view of the initial structure for forming gate contact vias (VOG) and source / drain contact vias (VDR) using the COAG process is provided. Only key film layers are shown, such as substrate 10, fins 20 on substrate 10, metal gate 30, and source / drain 40. Both the VOG and VDR formed using the COAG process are located on the active region. The current COAG process is illustrated using the formation of VOG1, VDR1, VOG2, and VDR2 as examples. Figure 1 The sectional views at points AA and BB can be found in [reference]. Figure 2 As shown, a metal layer 50 is formed on the source / drain 40, and a dielectric layer 60 is formed on the metal gate 30. (Reference) Figure 3 A first mask layer 70 and a second mask layer 80 are sequentially formed on the surfaces of the metal layer 50 and the dielectric layer 60. (Reference) Figure 4 The first etching process is performed to obtain VDR1 and V0G1, at which point the metal layer 50 is exposed at VDR1. When a second etching process is performed to obtain VDR2 and V0G2, the exposed metal layer 50 will be damaged.
[0024] In view of this, the technical solution of this application first forms the mask pattern of VDR1, V0G1, VDR2 and V0G2 by first etching and second etching, and stops on the dielectric layer on the metal layer. Therefore, the two etching processes will not expose the metal layer on the source and drain. Finally, VDR1, V0G1, VDR2 and V0G2 are formed by one etching, which can effectively alleviate the problem of metal layer damage.
[0025] refer to Figure 5 This application provides a method for forming an interconnect structure, including:
[0026] Step S1: Provide a substrate on which discrete metal gates are formed, and source drains are formed in the substrate on both sides of the metal gates. The surfaces of the substrate and the metal gates also include a first dielectric layer, and the first metal layer penetrates the first dielectric layer and is electrically connected to the top surface of the source drains.
[0027] Step S2: A second dielectric layer and a mask layer are sequentially formed on the first metal layer and the first dielectric layer;
[0028] Step S3: Perform a first etching and a second etching, wherein the first etching forms a pattern of a first gate contact hole and a first source / drain contact hole adjacent to each other in the mask layer perpendicular to the extension direction of the metal gate, and the second etching forms a pattern of a second gate contact hole and a second source / drain contact hole adjacent to each other in the mask layer perpendicular to the extension direction of the metal gate, wherein the first source / drain contact hole and the second source / drain contact hole are adjacent in the extension direction of the metal gate, and the first gate contact hole and the second gate contact hole are located on the metal gate in the active region;
[0029] Step S4: Forming a pattern of a first gate contact hole and a first source / drain contact hole adjacent to each other in the direction perpendicular to the metal gate extension; the second etching forms a pattern of a second gate contact hole and a second source / drain contact hole adjacent to each other in the mask layer in the direction perpendicular to the metal gate extension, wherein the first source / drain contact hole and the second source / drain contact hole are adjacent in the direction of metal gate extension, and the first gate contact hole and the second gate contact hole are located on the metal gate in the active region;
[0030] Using a patterned mask layer as a mask, the second dielectric layer and the first dielectric layer are etched to form the first gate contact hole, the second gate contact hole, the first source / drain contact hole, and the second source / drain contact hole.
[0031] refer to Figure 6 This diagram illustrates a top view of the initial structure at a starting process node, showing a method for forming the interconnect structure according to an embodiment of this application. This top view only shows the main film layer structures, such as substrate 100, fins 200 on substrate 100, metal gate 300, source / drain 400, and the first gate contact via (VOG1), second gate contact via (VOG2), first source / drain contact via (VDR1), and second source / drain contact via (VDR2) to be formed subsequently. VOG1 and VDR1 are adjacent in the direction perpendicular to the metal gate 300, VOG2 and VDR2 are adjacent in the direction perpendicular to the metal gate 300, and VDR1 and VDR2 are adjacent in the direction of the metal gate 300, and VOG1 and VDR2 are located on the metal gate 300 in the active region. Due to the requirements of advanced process nodes, the spacing between VDR1 and VDR2 is small, generally between 30nm and 150nm, and should not exceed 90nm. Therefore, the patterning of VDR1 and VDR2 must be performed in two steps.
[0032] Figure 7 for Figure 6A cross-sectional view at points AA and BB. Discrete metal gates 300 are formed on the substrate 100, and the metal gates 300 span the fin 200. Source drains 400 are formed in the substrate on both sides of the metal gates 300. Since points AA and BB are located directly above the fin 200, the cross-sectional view shows the metal gates 300 on the fin 200; similarly, the source drains 400 are also located on the fin 200. The surfaces of the substrate 100 and the metal gates 300 also include a first dielectric layer 600. A first metal layer 500 penetrates the first dielectric layer 600 and is electrically connected to the top surface of the source drains 400. A third dielectric layer 310, serving an insulating function, may also be included between the metal gates 300 and the source drains 400, between the metal gates 300 and the first metal layer 500, and between the metal gates 300 and the first dielectric layer 600. The material of the third dielectric layer 310 may include silicon nitride and / or silicon oxide.
[0033] The materials of the substrate 100 and the fins 200 may include at least one of the following: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, and may also include multilayer structures formed by the materials, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), etc. In this embodiment, the materials of the substrate 100 and the fins 200 are single-crystal silicon. The material of the metal gate 300 may include metal nitrides, metal silicides, metal oxides, single-element metals and their alloys, etc. The material of the source / drain 400 may, for example, include SiGe. The material of the first metal layer 500 may, for example, include Co to reduce internal resistance. The material of the first dielectric layer 600 may include silicon oxide.
[0034] refer to Figure 8 A second dielectric layer 700 and a mask layer are sequentially formed on the first metal layer 500 and the first dielectric layer 600, wherein the second dielectric layer 700 serves as an etching stop in subsequent etching processes. The mask layer may include a first mask layer 810 and a second mask layer 820 sequentially stacked on the surface of the second dielectric layer 700. The material of the second dielectric layer 700 may include silicon nitride, the material of the first mask layer 810 may include silicon oxide, and the material of the second mask layer 820 may include at least one of silicon nitride, titanium nitride, and silicon carbide. The thickness of the second dielectric layer 700 may be 3 nm to 30 nm, the thickness of the first mask layer 810 may be 10 nm to 50 nm, and the thickness of the second mask layer 820 may be 5 nm to 50 nm.
[0035] refer to Figure 9The mask layer is etched a first time, stopping at the second dielectric layer 700, forming patterns of VOG1 and VDR1 in the mask layer. In this embodiment, the first etching forms a first opening 910 for defining VOG1 and a second opening 920 for defining VDR1 in the mask layer. Then, the mask layer is etched a second time, also stopping at the second dielectric layer 700, forming patterns of VOG2 and VDR2. Using this embodiment, the second etching forms a third opening 911 for defining VOG2 and a fourth opening 940 for defining VDR2 in the mask layer. It should be noted that the order of the first and second etching can be reversed. Both the first and second etching processes simultaneously form the gate contact hole and source / drain contact hole patterns in a single etching process, which reduces the use of masks and lowers costs. Furthermore, both etching processes stop on the second dielectric layer 700, thus avoiding unnecessary exposure of the first metal layer 500, which reduces the exposure time of the first metal layer 500 and effectively reduces the degree of damage to the first metal layer 500.
[0036] refer to Figure 10 After the first and second etching processes, the formation method of this application embodiment may further include: forming a pad layer 950 on the surface of the mask layer and the sidewall and bottom surfaces of the first opening 910, the second opening 920, the third opening 930, and the fourth opening 940, for adjusting the critical dimensions of the first opening 910, the second opening 920, the third opening 930, and the fourth opening 940 so that the contact holes formed by subsequent etching processes meet the dimensional requirements. The material of the pad layer 950 may include silicon nitride and / or silicon oxide. The thickness of the pad layer 950 may be 1 nm to 10 nm.
[0037] refer to Figure 11 Using a patterned mask layer as a mask, the second dielectric layer 700 and the first dielectric layer 600 are etched to form VOG1, VDR1, VOG2, and VDR2. When the liner layer 950 is used to adjust the opening size, the liner layer 950 is also etched away in this step.
[0038] refer to Figure 12The forming method further includes: removing the remaining second mask layer 820; forming a second metal material layer in VOG1, VDR1, VOG2 and VDR2 and on the surface of the remaining first mask layer 810; grinding the second metal material layer to form a second metal layer 960 in VOG1, VDR1, VOG2 and VDR2 with its top surface flush with the surface of the first mask layer 810.
[0039] The interconnect structure formation method of the present application embodiment significantly reduces the exposure time of the first metal layer on the source and drain, thus greatly alleviating the problem of damage to the first metal layer in the COAG process. In addition, a smaller number of masks are used in the formation process, which can significantly reduce costs.
[0040] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0041] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0042] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0043] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0044] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For example, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming an interconnect structure, characterized in that, include: A substrate is provided, on which discrete metal gates are formed, and source drains are formed in the substrates on both sides of the metal gates. The surfaces of the substrate and the metal gates further include a first dielectric layer, the first metal layer penetrating the first dielectric layer and electrically connected to the top surface of the source drains. A second dielectric layer and a mask layer are sequentially formed on the first metal layer and the first dielectric layer; A first etching and a second etching are performed, wherein the first etching forms a pattern of a first gate contact hole and a first source / drain contact hole adjacent to each other in the mask layer perpendicular to the extension direction of the metal gate, and the second etching forms a pattern of a second gate contact hole and a second source / drain contact hole adjacent to each other in the mask layer perpendicular to the extension direction of the metal gate, wherein the first source / drain contact hole and the second source / drain contact hole are adjacent in the extension direction of the metal gate, and the first gate contact hole and the second gate contact hole are located on the metal gate in the active region; Using a patterned mask layer as a mask, the second dielectric layer and the first dielectric layer are etched to form the first gate contact hole, the second gate contact hole, the first source / drain contact hole, and the second source / drain contact hole.
2. The method for forming the interconnect structure according to claim 1, characterized in that, The distance between the first source / drain contact hole and the second source / drain contact hole is 30nm to 150nm.
3. The method for forming the interconnect structure according to claim 1, characterized in that, The first etching and the second etching form in the mask layer a first opening for defining the first gate contact hole, a second opening for defining the first source / drain contact hole, a third opening for defining the first gate contact hole, and a fourth opening for defining the second source / drain contact hole.
4. The method for forming the interconnect structure according to claim 3, characterized in that, After the first etching and the second etching, the forming method further includes forming a padding layer on the surface of the mask layer and the sidewall and bottom surfaces of the first opening, the second opening, the third opening and the fourth opening, for adjusting the critical dimensions of the first opening, the second opening, the third opening and the fourth opening.
5. The method for forming the interconnect structure according to claim 4, characterized in that, The liner layer, the second dielectric layer, and the first dielectric layer are etched in the same process.
6. The method for forming an interconnect structure according to claim 4, characterized in that, The material of the liner layer includes silicon nitride and / or silicon oxide.
7. The method for forming the interconnect structure according to claim 1, characterized in that, The mask layer includes a first mask layer and a second mask layer stacked sequentially on the surface of the second dielectric layer, wherein the thickness of the second dielectric layer is 3nm to 30nm, the thickness of the first mask layer is 10nm to 50nm, and the thickness of the second mask layer is 5nm to 50nm.
8. The method for forming an interconnect structure according to claim 7, characterized in that, The material of the second dielectric layer includes silicon nitride, the material of the first mask layer includes silicon oxide, and the material of the second mask layer includes at least one of silicon nitride, titanium nitride, and silicon carbide.
9. The method for forming an interconnect structure according to claim 7, characterized in that, The forming method further includes: Remove the remaining second mask layer; A second metal material layer is formed in the first gate contact hole, the second gate contact hole, the first source / drain contact hole, and the second source / drain contact hole, as well as on the surface of the remaining first mask layer; The second metal material layer is ground to form a second metal layer whose top surface is flush with the surface of the first mask layer in the first gate contact hole, the second gate contact hole, the first source / drain contact hole and the second source / drain contact hole.
10. The method for forming an interconnect structure according to claim 1, characterized in that, A third dielectric layer is further included between the metal gate and the first dielectric layer, between the metal gate and the first metal layer, and between the metal gate and the source / drain; when etching the second dielectric layer and the first dielectric layer, the third dielectric layer on the gate surface of the active region is also etched.
11. The method for forming an interconnect structure according to claim 10, characterized in that, The material of the first dielectric layer includes silicon oxide, and the material of the third dielectric layer includes silicon nitride and / or silicon oxide.