An integrated circuit sub-kernel and integrated circuit assembly

Abstract

The application provides an integrated circuit sub-core and an integrated circuit assembly. The integrated circuit sub-core comprises a front surface inner connection interface on a front surface of the integrated circuit sub-core, a sub-core control circuit connected with the front surface inner connection interface, a back surface inner connection interface connected with the sub-core control circuit, and a back surface connection layer connected with the back surface inner connection interface. The integrated circuit sub-core and the integrated circuit assembly can realize a stacked chip structure by using chip units with different processes, reduce cost, improve stability, and reduce the time required for chip development.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to an integrated circuit chip and an integrated circuit assembly. Background Technology

[0002] Most chips in the current technology are basically system-on-chips (SOCs) with complete functions. Figure 1 An example of a System-on-a-Chip (SoC) is shown, comprising an LTE analog RF unit (currently, the main mature processes are 55nm and 40nm), a CPU digital unit (advanced processes are 7nm and 5nm), and functional units such as a DSP (mainly mature processes are 28nm and 16nm). Since only one process can be used per wafer, all units except the CPU are forced to migrate from mature processes to higher processes (such as 7nm or 5nm). Some of these units may have better stability under mature processes, thus this migration can lead to chip instability and high costs. Furthermore, chips need to continue migrating to higher processes every 18 months (according to the industry's typical upgrade pattern), resulting in the inability to reuse past chips and causing significant waste. Summary of the Invention

[0003] At least one embodiment of the present invention provides an integrated circuit sub-chip and an integrated circuit assembly, which can realize a stacked chip structure using chip cells of different processes, thereby reducing costs, improving stability, and reducing the time required for chip development.

[0004] To solve the above-mentioned technical problems, the present invention is implemented as follows: In a first aspect, embodiments of the present invention provide an integrated circuit sub-chip, comprising: a sub-chip front inline interface located on the front side of the integrated circuit sub-chip, a sub-chip control circuit connected to the sub-chip front inline interface, a sub-chip back inline interface connected to the sub-chip control circuit, and a sub-chip back connection layer connected to the sub-chip back inline interface. Neither the front inline interface nor the back inline interface of the sub-core is equipped with an anti-static protection circuit or a physical conversion unit for digital signals to analog signals. The front inline interface of the sub-core is used to connect to the back inline interface of another integrated circuit sub-core, or to connect to the back inline interface of the integrated circuit mother core through the back inline connection layer of the mother core. The sub-core back-side connection layer is a perforated connection layer that connects to the sub-core back-side inline interface, and is used to connect the sub-core back-side inline interface to the sub-core front-side inline interface of another integrated circuit sub-core through the formed perforations.

[0005] Optionally, the inline interface on the back of the sub-core and the inline interface on the front of the sub-core include a digital interface and / or a power interface.

[0006] Optionally, the back-side interconnect interface of the mother core is connected to the front-side interconnect interface of the integrated circuit daughter core through a through-silicon via (TSV) formed on the back-side interconnect layer of the mother core or through metal bonding.

[0007] Optionally, the back-side interconnect interface of the sub-chip can be connected to the front-side interconnect interface of another integrated circuit sub-chip through a through-silicon via (TSV) or metal bonding process formed on the back-side interconnect layer of the sub-chip.

[0008] In a second aspect, embodiments of the present invention provide an integrated circuit assembly including a plurality of integrated circuit sub-chips as described in the first aspect; wherein the positional relationship between the different integrated circuit sub-chips includes: vertical stacking and / or horizontal laying; when the second integrated circuit sub-chip is vertically stacked on top of the first integrated circuit sub-chip, the sub-chip back inline interface of the first integrated circuit sub-chip is connected to the sub-chip front inline interface of the second integrated circuit sub-chip.

[0009] Optionally, it also includes at least one integrated circuit mother chip, wherein, The integrated circuit mother core includes: a mother core front external connection interface located on the front of the integrated circuit mother core, a mother core control circuit connected to the mother core front external connection interface, a back interface connected to the mother core control circuit, and a mother core back connection layer connected to the back interface. The rear interface includes a bus connection and bus expansion circuit connected to the core control circuit, a core rear external connection interface connected to the bus connection and bus expansion circuit, and a core rear internal connection interface connected to the core control circuit. The core front external connection interface and the core rear external connection interface are both equipped with an anti-static protection circuit and a physical conversion unit from digital signal to analog signal. The core rear internal connection interface is not equipped with the anti-static protection circuit and the physical conversion unit. The back-side connection layer of the mother core is a perforated connection layer that connects to the back-side inline interface and the back-side outline interface of the mother core. It is used to connect the back-side outline interface of the mother core to the physical interface of an external chip through the formed perforations, and / or to connect the back-side inline interface of the mother core to the front-side inline interface of the integrated circuit sub-core. In the integrated circuit assembly: The positional relationships between different integrated circuit mother chips include: vertical stacking and / or horizontal laying; The positional relationship between the integrated circuit daughter chip and the integrated circuit mother chip includes: vertical stacking; When the first integrated circuit sub-chip is vertically stacked on the integrated circuit mother chip, the mother chip back inline interface of the integrated circuit mother chip is connected to the sub-chip front inline interface of the first integrated circuit sub-chip. When the second integrated circuit sub-chip is vertically stacked on top of the first integrated circuit sub-chip, the inline interface on the back of the first integrated circuit sub-chip is connected to the inline interface on the front of the second integrated circuit sub-chip.

[0010] Optionally, the internal interface on the back of the female core includes a digital interface and / or a power interface.

[0011] Optionally, the external interface on the front side and / or the external interface on the back side of the mother core are connected to an external chip via a metal ball-mounting process or a metal wire connection.

[0012] Optionally, the back-side interconnect interface of the mother core is connected to the front-side interconnect interface of the integrated circuit daughter core through a through-silicon via (TSV) or metal bonding process formed on the back-side interconnect layer of the mother core.

[0013] Optionally, the core control circuit includes: Security kernel and cache circuitry; An interface multiplexing and interface safety control circuit for controlling the connection to the external interface on the front side and / or the external interface on the back side of the core.

[0014] Optionally, the security kernel employs a specific instruction set for encryption operations and security control, wherein the specific instruction set is an instruction system with automatic loading random noise; the security kernel includes a low-frequency automatic suppression structure, an anti-abrasion sensor and a self-destruct device, and uses a scrambled encryption bus to protect loading instructions and data.

[0015] Optionally, the external interface on the back of the female core is connected to the interface multiplexing and switching and interface safety control circuit via a bus connection and bus expansion circuit. The back-side interface of the mother core is connected to the security core and cache circuit in the mother core control circuit.

[0016] Optionally, the core control circuit further includes: Power management circuits are used to manage the power supply to integrated circuit chips and external chips.

[0017] Optionally, the planar area of ​​the integrated circuit mother chip is greater than, equal to or smaller than the planar area of ​​the integrated circuit daughter chips stacked thereon; The planar area of ​​the first integrated circuit sub-chip is greater than, equal to or less than the planar area of ​​the integrated circuit sub-chips stacked on it.

[0018] Compared with the prior art, the integrated circuit sub-chip and integrated circuit assembly provided in the embodiments of the present invention connect the mother chip and the sub-chip through the inter-chip interface, thereby enabling the use of chip units with different processes to realize a stacked chip structure, reducing costs, improving stability, and reducing the time required for chip development. Attached Figure Description

[0019] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 An example diagram of a prior art SOC; Figure 2 This is a schematic diagram of an integrated circuit mother chip according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of an external interface according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a core control circuit according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a structure of the back connection layer of the mother core according to an embodiment of the present invention; Figure 6 This is a schematic diagram of an integrated circuit sub-chip according to an embodiment of the present invention; Figure 7 This is a schematic diagram of an integrated circuit component according to an embodiment of the present invention; Figure 8 This is a schematic diagram of another structure of an integrated circuit component according to an embodiment of the present invention; Figure 9 This is another structural schematic diagram of an integrated circuit component according to an embodiment of the present invention; Figure 10 This is an example diagram illustrating the connection between the intelligent mother chip and multiple daughter chips, as well as existing chips, according to an embodiment of the present invention. Figure 11 This is another example diagram illustrating the connection between the intelligent mother chip and multiple daughter chips, as well as existing chips, according to an embodiment of the present invention. Figure 12 This is another example diagram illustrating the connection between the intelligent mother core and multiple daughter cores and existing chips in an embodiment of the present invention. Detailed Implementation

[0020] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0021] The terms “first,” “second,” etc., used in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. The terms “and / or” in the specification and claims indicate at least one of the connected objects.

[0022] The following description provides examples and is not intended to limit the scope, applicability, or configuration set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the spirit and scope of this disclosure. Various procedures or components may be appropriately omitted, substituted, or added to the examples. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with reference to certain examples may be combined in other examples.

[0023] Please refer to Figure 2 The present invention provides an integrated circuit mother chip, which may also be called a smart mother chip or simply a mother chip, such as... Figure 2 As shown, it includes: a front external interface of the mother chip located on the front side of the integrated circuit mother chip, a mother chip control circuit connected to the front external interface of the mother chip, a back interface connected to the mother chip control circuit, and a back connection layer of the mother chip connected to the back interface.

[0024] The rear interface includes a bus connection and bus expansion circuit connected to the core control circuit, a core rear external interface connected to the bus connection and bus expansion circuit, and a core rear internal interface connected to the core control circuit. The core front external interface and the core rear external interface are both equipped with an anti-static protection circuit and a physical conversion unit from digital signal to analog signal. The core rear internal interface is not equipped with the anti-static protection circuit and the physical conversion unit.

[0025] The back-side connection layer of the mother core is a perforated connection layer that connects to the back-side inline interface and the back-side outline interface of the mother core. It is used to connect the back-side outline interface of the mother core to the physical interface of an external chip through the formed perforations, and / or to connect the back-side inline interface of the mother core to the front-side inline interface of the integrated circuit sub-core.

[0026] It should be noted that the "back side" and "front side" mentioned in this article refer to two opposing surfaces of the chip. For example, the front side of the integrated circuit mother chip can be the surface connected to the base, and the back side of the integrated circuit mother chip can be the surface connected to the integrated circuit daughter chip. The external chip can be any existing chip with complete interfaces and functional circuits.

[0027] Specifically, the internal interface on the back of the female core includes a digital interface and / or a power interface.

[0028] The external interface on the front side and / or the external interface on the back side of the mother core can be connected to an external chip via a metal ball-mounting process or a metal wire connection.

[0029] The back-side interconnect interface of the mother core can be connected to the front-side interconnect interface of the integrated circuit daughter core through a through-silicon via (TSV) formed on the back-side interconnect layer of the mother core or through metal bonding.

[0030] Figure 3 A schematic diagram of an external interface (such as a front external interface and a back external interface of the female core) is provided. Specifically, the external interface includes an anti-static protection interface, which is equipped with an anti-static protection circuit. In addition, to achieve interface signal conversion, the external interface also includes a physical conversion unit connected to the anti-static protection interface.

[0031] Figure 4 A schematic diagram of a core control circuit is provided, wherein the core control circuit includes: Security kernel and cache circuitry; An interface multiplexing and interface safety control circuit for controlling the connection to the external interface on the front side and / or the external interface on the back side of the core.

[0032] In addition, the core control circuit may also include the following circuits (not shown in the figure): Power management circuits are used to manage the power supply to integrated circuit chips and external chips.

[0033] Figure 4 A schematic diagram illustrating the connection relationship of the back-end interface of the mother core is provided. Specifically, the external interface on the back of the mother core is connected to the interface multiplexing switching and interface security control circuit via a bus connection and bus expansion circuit. The internal interface on the back of the mother core is connected to the security core and buffer circuit in the mother core control circuit.

[0034] Figure 5 A schematic diagram of a back-end connection layer for a motherboard is provided, wherein the external back-end interface and the internal back-end interface of the motherboard are respectively connected to the back-end connection layer. The back-end connection layer can form multiple through-silicon vias (TSVs) as needed. Thus, the external back-end interface can be coupled to the physical interface of an external chip through the TSVs, and the internal back-end interface can be coupled to the front-end internal interface of the integrated circuit's sub-chip through the TSVs. Please refer to Figure 6 The present invention provides an integrated circuit sub-chip, which may also be called a smart sub-chip or simply a sub-chip, specifically including: a sub-chip front inline interface located on the front of the integrated circuit sub-chip, a sub-chip control circuit connected to the sub-chip front inline interface, a sub-chip back inline interface connected to the sub-chip control circuit, and a sub-chip back connection layer connected to the sub-chip back inline interface. Neither the front inline interface nor the back inline interface of the sub-core is equipped with an anti-static protection circuit or a physical conversion unit for digital signals to analog signals. The front inline interface of the sub-core is used to connect to the back inline interface of another integrated circuit sub-core, or to connect to the back inline interface of the integrated circuit mother core through the back inline connection layer of the mother core. The sub-core back-side connection layer is a perforated connection layer that connects to the sub-core back-side inline interface, and is used to connect the sub-core back-side inline interface to the sub-core front-side inline interface of another integrated circuit sub-core through the formed perforations.

[0035] Here, the other integrated circuit sub-chip and the yet another integrated circuit sub-chip are different integrated circuit sub-chips, and these integrated circuit sub-chips can all have the same structure.

[0036] Specifically, the back-side inline interface and the front-side inline interface of the sub-core may each include a digital interface and / or a power interface.

[0037] The back-side interconnect interface of the mother core can be connected to the front-side interconnect interface of the integrated circuit daughter core through a through-silicon via (TSV) formed on the back-side interconnect layer of the mother core or through metal bonding.

[0038] The back-side interconnect interface of the sub-chip is connected to the front-side interconnect interface of another integrated circuit sub-chip through a through-silicon via (TSV) or metal bonding process formed on the back-side interconnect layer of the sub-chip. Based on the integrated circuit mother chip and integrated circuit daughter chip described above, embodiments of the present invention also provide an integrated circuit assembly, including a plurality of first integrated circuit daughter chips, wherein the positional relationship between different integrated circuit daughter chips includes: vertical stacking and / or horizontal laying; when a second integrated circuit daughter chip is vertically stacked on top of a first integrated circuit daughter chip, the back-side inline interface of the first integrated circuit daughter chip is connected to the front-side inline interface of the second integrated circuit daughter chip.

[0039] Optionally, the integrated circuit assembly in this embodiment of the invention may further include at least one integrated circuit mother die. The positional relationship between different integrated circuit mother dies includes: vertical stacking and / or horizontal placement. The positional relationship between integrated circuit daughter dies and integrated circuit mother dies includes: vertical stacking; When the first integrated circuit sub-chip is directly stacked on top of the first integrated circuit mother chip, the mother chip back inline interface of the first integrated circuit mother chip is connected to the sub-chip front inline interface of the first integrated circuit sub-chip. When the second integrated circuit sub-chip is directly stacked on top of the first integrated circuit sub-chip, the inline interface on the back of the first integrated circuit sub-chip is connected to the inline interface on the front of the second integrated circuit sub-chip.

[0040] In this embodiment of the invention, vertical stacking of two chips means that the projections of the two chips on a first plane at least partially overlap, and they are stacked and coupled together in a direction perpendicular to the first plane. The first plane may be parallel to the planar view of the chips. When at least two chips are stacked vertically in sequence, a stacked structure can be formed, where each layer of the stacked structure corresponds to one chip in the vertical stack. Horizontal stacking of two chips means that the projections of the two chips on the first plane do not overlap, and the two chips are located in the same layer of the stacked structure. The chips here include integrated circuit sub-chips and / or integrated circuit mother chips.

[0041] Furthermore, the embodiments of the present invention do not impose specific limitations on the planar area relationship between the two chips in the stacked relationship. For example, the planar area of ​​the first integrated circuit mother chip can be greater than, equal to, or smaller than the planar area of ​​the integrated circuit mother chip or integrated circuit daughter chip stacked on it. As another example, the planar area of ​​the first integrated circuit daughter chip can be greater than, equal to, or smaller than the planar area of ​​the integrated circuit daughter chip stacked on it.

[0042] During design and manufacturing, the female core is positioned with its front side facing up. After encapsulation, the female core is positioned with its front side facing down to connect with the external base.

[0043] Depending on actual needs, one or more of each type of chip, including the mother chip, daughter chip, and existing chips, can be used, and their connections can be arbitrarily stacked. After completing a full packaging module, the packaging modules can be stacked again using the POP process.

[0044] Based on the above-described master chip structure, embodiments of the present invention can implement specific functional units on the smart master chip using mature processes at low cost. Furthermore, it can reuse chip units from different processes, resulting in a reduction in overall chip cost, improved reliability, and a shortened development cycle. This is because, except for digital units such as the CPU, other smart sub-chips can continue to utilize existing mature processes and be directly stacked on the smart master chip, thereby significantly improving development efficiency. In addition, embodiments of the present invention enable the stacking of the smart master chip and multiple smart sub-chips to achieve performance exceeding that of a single high-process SOC chip using low-process technology, even without high-process equipment.

[0045] To help better understand the structure of the integrated circuit components in the embodiments of the present invention, several exemplary structures are described below.

[0046] Figure 7 The integrated circuit assembly shown includes an integrated circuit mother chip and multiple integrated circuit daughter chips 1 to n. The mother chip is located at the lowest layer of the stacked structure, with the daughter chips 1 to n stacked on top of it. The mother chip can be connected to the front inline interface of daughter chip 1 via its back inline interface. Adjacent daughter chips are connected by connecting the back inline interface of the lower-layer daughter chip to the front inline interface of the upper-layer daughter chip. Figure 7 The chips in the middle are stacked vertically.

[0047] Figure 8 The integrated circuit assembly shown includes an integrated circuit mother chip, integrated circuit daughter chips 1-2, and other chips 1-2. Here, the other chips can be various existing SOC chips. Figure 8 In this process, the integrated circuit mother chip can be connected to other chips 1-2 through the external interface on the back of the mother chip; the integrated circuit mother chip can be connected to integrated circuit daughter chip 1 through the internal interface on the back of the mother chip; integrated circuit daughter chip 1 can be connected to the internal interface on the front of integrated circuit daughter chip 2 through the internal interface on the back of the daughter chip. Figure 8 In the diagram, the positional relationship between integrated circuit sub-chips 1-2 and integrated circuit mother chip is vertical stacking; the positional relationship between other chip 1 and integrated circuit mother chip is vertical stacking; the positional relationship between other chip 2 and integrated circuit mother chip is vertical stacking; and the positional relationship between integrated circuit sub-chip 1 and other chips 1-2 is horizontal laying.

[0048] Figure 9The integrated circuit assembly shown includes integrated circuit mother chips 1-3, integrated circuit daughter chips 1-3, and other chips 1-2. Integrated circuit mother chip 1 can be connected to the front external interfaces of integrated circuit mother chips 2 and 3 via its rear external interface. Integrated circuit mother chip 2 is connected to the front internal interface of integrated circuit daughter chip 1 via its rear internal interface, and is also connected to other chips 1 via its rear external interface. Integrated circuit daughter chip 1 can be connected to the front internal interface of integrated circuit daughter chip 2 via its rear internal interface. Integrated circuit mother chip 3 is connected to the front internal interface of integrated circuit daughter chip 3 via its rear internal interface, and is also connected to other chips 2 via its rear external interface.

[0049] Figure 10 Further examples of connections between an integrated circuit mother chip (intelligent mother chip) and multiple integrated circuit daughter chips (intelligent daughter chips), as well as multiple existing chips, are provided. The integrated circuit mother chip is connected to the chip substrate via metal balls or metal wires. The front external interface of the integrated circuit mother chip includes an anti-static protection circuit and a physical conversion unit. The integrated circuit mother chip also includes a mother chip control circuit, bus connection and expansion circuit, security core, and cache circuit. These circuits are connected to the rear external interface, the rear internal interface, and the front external interface. A rear connection layer (perforated connection layer) is provided inside the integrated circuit mother chip near the back side. Through the perforations formed in this rear connection layer, the rear external interface is connected to the chip external interface of an existing chip, and / or, the rear internal interface is connected to the front internal interface of a daughter chip.

[0050] In addition, the smart sub-chip includes a sub-chip control circuit, a sub-chip back-side interconnect interface, and a sub-chip back-side connection layer. The sub-chip back-side interconnect interface connects to the sub-chip front-side interconnect interface of another smart sub-chip through a perforation formed in the sub-chip back-side connection layer.

[0051] In this embodiment of the invention, a perforation can be formed in the back connection layer of the mother core, and copper metal can be deposited on the inner surface of the perforation. The perforation extends to the back surface of the mother core, where metal can be further plated or solder balls can be added. The front internal interface of the daughter core can be directly connected to the metal or solder balls plated on the back of the mother core.

[0052] For example, the core control circuit may specifically include an interface multiplexing switching control and an interface safety control circuit. Figure 11 Further examples are given regarding the connection between the integrated circuit master chip (intelligent master chip) and multiple integrated circuit sub-chips (intelligent sub-chips), as well as multiple existing chips. Among them, The interface multiplexing switching control and interface safety control circuits are respectively connected to the front external interface of the mother core, the security core and cache circuit, the controller (or programmable controller), the power management circuit, the bus connection and bus expansion circuit.

[0053] The interface multiplexing switching control and interface security control circuit is used to perform security control on the interface multiplexing switching and connection / disconnection of the front external interface, the back external interface, and the back internal interface of the mother core, according to the control of the security kernel.

[0054] For example, the security kernel of this embodiment of the invention can use a security kernel with a specific instruction set (typically, such as LoongArch, China's first independently developed instruction set) for encryption operations and security control. The security kernel uses an instruction set with auto-loading random noise, which is resistant to logic analysis and DPA probing. It employs a low-frequency automatic suppression structure to prevent low-frequency analysis, uses anti-grinding sensors and self-destruct devices to prevent chip grinding detection, and uses a scrambled encryption bus to protect loading instructions and data. Other modules built into the security kernel include built-in memory and an encryption coprocessor. The control circuit based on the security kernel can achieve secure startup and operation. The security kernel can also perform security verification based on random numbers and authentication requests issued by the security controller in an external service platform or terminal, using these as security control conditions to control the interface multiplexing switching and on / off states of the chip's external and internal interfaces.

[0055] In this embodiment of the invention, none of the internal interfaces of the integrated circuit sub-chip and the mother chip require electrostatic discharge (ESD) protection circuits or physical conversion units. However, existing chips typically include a PHY and ESD protection circuits at their interfaces, such as... Figure 11 As shown.

[0056] Figure 12 An example diagram is provided illustrating the connection between the intelligent mother chip and multiple daughter chips, as well as existing chips, according to an embodiment of the present invention, wherein: The external interface 100 on the front of the smart core 101 can be connected to the chip base.

[0057] The smart mother core 101 has a TSV semi-through hole 102. Through the TSV semi-through hole 102, the external interface on the back of the mother core can be connected to the physical interface of the external chip 120, and / or the internal interface on the back of the mother core can be connected to the internal interface on the front of the integrated circuit daughter core 118, such as the pin 107 connected to the internal interface on the front of the smart daughter core 118.

[0058] Figure 11 In the process, the TSV semi-perforated 102 has a TSV perforated metal bump 103 formed on the back connection layer of the mother core, and the TSV perforated metal bump 103 can be connected to the metal distribution connection layer 104 of the mother core.

[0059] The intelligent mother core 101 and the intelligent daughter core 118 are bonded together by metal pillars 105 and 106.

[0060] A TSV semi-through hole 108 is formed in the smart sub-chip 118. Through the TSV semi-through hole 108, the back-side inline interface of the sub-chip can be connected to the pin 113 of the front-side inline interface of the smart sub-chip 119. A TSV semi-through hole 108 forms a TSV through-hole metal bump 109 on the back-side connection layer of the sub-chip. Through the TSV through-hole metal bump 109, a connection can be formed with the metal distribution connection layer 110 of the sub-chip.

[0061] Smart sub-cores 118 and 119 are metal-bonded via metal pillars 111 and 112. Smart sub-core 119 also includes: a TSV semi-perforation 114, a TSV perforated metal bump 115 of the sub-core back connection layer, a metal distribution connection layer 116, and a metal pillar 117 for metal bonding.

[0062] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0063] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. An integrated circuit component, characterized in that, It includes multiple integrated circuit sub-chips and at least one integrated circuit mother chip; among which, The integrated circuit sub-chip includes: The sub-chip front inline interface located on the front of the sub-chip, the sub-chip control circuit connected to the sub-chip front inline interface, the sub-chip back inline interface connected to the sub-chip control circuit, and the sub-chip back connection layer connected to the sub-chip back inline interface. Neither the front inline interface nor the back inline interface of the sub-core is equipped with an anti-static protection circuit or a physical conversion unit for digital signals to analog signals. The front inline interface of the sub-core is used to connect to the back inline interface of another integrated circuit sub-core, or to connect to the back inline interface of the integrated circuit mother core through the back inline connection layer of the mother core. The sub-core back connection layer is a perforated connection layer that connects to the sub-core back inline interface, and is used to connect the sub-core back inline interface to the sub-core front inline interface of another integrated circuit sub-core through the formed perforations. The positional relationship between different integrated circuit sub-chips includes: vertical stacking and / or horizontal laying; when the second integrated circuit sub-chip is vertically stacked on top of the first integrated circuit sub-chip, the sub-chip back inline interface of the first integrated circuit sub-chip is connected to the sub-chip front inline interface of the second integrated circuit sub-chip. The integrated circuit mother chip includes: a mother chip front external interface located on the front of the integrated circuit mother chip, a mother chip control circuit connected to the mother chip front external interface, a back interface connected to the mother chip control circuit, and a mother chip back connection layer connected to the back interface. The rear interface includes a bus connection and bus expansion circuit connected to the core control circuit, a core rear external interface connected to the bus connection and bus expansion circuit, and a core rear internal interface connected to the core control circuit. The core front external interface and the core rear external interface are both equipped with an anti-static protection circuit and a physical conversion unit from digital signal to analog signal. The core rear internal interface is not equipped with the anti-static protection circuit and the physical conversion unit. The back-side connection layer of the mother core is a perforated connection layer that connects to the back-side inline interface and the back-side outline interface of the mother core. It is used to connect the back-side outline interface of the mother core to the physical interface of an external chip through the formed perforations, and / or to connect the back-side inline interface of the mother core to the front-side inline interface of the integrated circuit sub-core. In the integrated circuit assembly: The positional relationships between different integrated circuit mother chips include: vertical stacking and / or horizontal laying; The positional relationship between the integrated circuit daughter chip and the integrated circuit mother chip includes: vertical stacking; When the first integrated circuit sub-chip is vertically stacked on the first integrated circuit mother chip, the mother chip back inline interface of the first integrated circuit mother chip is connected to the sub-chip front inline interface of the first integrated circuit sub-chip. When the second integrated circuit sub-chip is vertically stacked on top of the first integrated circuit sub-chip, the inline interface on the back of the first integrated circuit sub-chip is connected to the inline interface on the front of the second integrated circuit sub-chip.

2. The integrated circuit component according to claim 1, characterized in that, The inline interfaces on the back and front of the sub-core include digital interfaces and / or power interfaces.

3. The integrated circuit component according to claim 1, characterized in that, The back-side interconnect interface of the sub-chip is connected to the front-side interconnect interface of another integrated circuit sub-chip through a through-silicon via (TSV) or metal bonding process formed on the back-side interconnect layer of the sub-chip.

4. The integrated circuit component according to claim 1, characterized in that, The internal interface on the back of the female core includes a digital interface and / or a power interface.

5. The integrated circuit component according to claim 1, characterized in that, The external interface on the front side and / or the external interface on the back side of the mother core are connected to external chips via metal ball bonding or metal wire connection.

6. The integrated circuit component according to claim 1, characterized in that, The back-side interconnect interface of the mother core is connected to the front-side interconnect interface of the integrated circuit daughter core through a through-silicon via (TSV) or metal bonding process formed on the back-side interconnect layer of the mother core.

7. The integrated circuit component according to claim 6, characterized in that, The core control circuit includes: Security kernel and cache circuitry; An interface multiplexing and interface safety control circuit for controlling the connection to the external interface on the front side and / or the external interface on the back side of the core.

8. The integrated circuit component according to claim 7, characterized in that, The secure kernel employs a specific instruction set for encryption operations and security control, wherein the specific instruction set is an instruction system with automatic loading of random noise; the secure kernel includes a low-frequency automatic suppression structure, a wear-resistant sensor, and a self-destruct device, and uses a scrambled encryption bus to protect loading instructions and data.

9. The integrated circuit component according to claim 7, characterized in that, The external interface on the back of the mother core is connected to the interface multiplexing and switching and interface safety control circuit via a bus connection and bus expansion circuit. The back-side interface of the mother core is connected to the security core and cache circuit in the mother core control circuit.

10. The integrated circuit assembly according to claim 7, characterized in that, The core control circuit also includes: Power management circuits are used to manage the power supply to integrated circuit chips and external chips.

11. The integrated circuit component according to claim 1, characterized in that, The planar area of ​​the integrated circuit mother chip is greater than, equal to or smaller than the planar area of ​​the integrated circuit daughter chips stacked on it. The planar area of ​​the first integrated circuit sub-chip is greater than, equal to or less than the planar area of ​​the integrated circuit sub-chips stacked on it.

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