Comparator circuit, mismatch correction method, and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly to a comparator circuit, a mismatch correction method, and a memory, including: a first transistor, one terminal of which is coupled to a first node, the other terminal of which is coupled to a first control node, and the gate of which is configured to receive a first control signal; a second transistor, one terminal of which is coupled to the first node, the other terminal of which is coupled to a second control node, and the gate of which is configured to receive a second control signal; a load unit, one end of which is coupled to a second node, and the other end of which is coupled to the first control node and the second control node; a first adjustment circuit is configured to adjust, according to a first adjustment signal, the node potential of the first control node after the first transistor is turned on based on the first control signal; a second adjustment circuit is configured to adjust, according to a second adjustment signal, the node potential of the second control node after the second transistor is turned on based on the second control signal, so as to eliminate the mismatch between two input transistors of the differential structure, thereby improving the memory performance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and particularly to a comparator circuit, a mismatch correction method, and a memory. Background Art

[0002] The input circuit of a memory generally adopts a differential input structure. Although the two input transistors of the differential input structure are of the same size (including parameters such as width-to-length ratio and threshold voltage) in design, during the process of forming the input transistors on an actual silicon wafer, due to various factors (such as the dose of doped ion implantation in the process, the exposure angle, the position of the transistor, etc.), a mismatch occurs between the two input transistors.

[0003] Generally speaking, the mismatch caused by the above reasons is very small. However, the operating frequency of the memory is very high under normal operating conditions. When the signal frequency of the memory is very high (for example, the operating frequency of LPDDR4 can be 4266 MHz, and even the operating frequency of LPDDR5X can be 8533 MHz), at this time, even a small mismatch between the input transistors will have a significant impact on the performance of the product, and the impact of the above mismatch cannot be eliminated by traditional methods (such as increasing the size of the differential input transistors). Summary of the Invention

[0004] Embodiments of the present disclosure provide a comparator circuit, a mismatch correction method, and a memory to eliminate the mismatch between the two input transistors of the differential structure, thereby improving the performance of the memory.

[0005] An embodiment of the present disclosure provides a comparator circuit, including: a first transistor, one terminal of which is coupled to a first node, the other terminal of which is coupled to a first control node, and the gate of which is configured to receive a first control signal; a second transistor, one terminal of which is coupled to the first node, the other terminal of which is coupled to a second control node, and the gate of which is configured to receive a second control signal; the first transistor and the second transistor have the same transistor doping type; a load unit, one end of which is coupled to a second node, and the other end of which is coupled to the first control node and the second control node, and is configured to adjust the level of the second control node based on the level of the first control node, or adjust the level of the first control node based on the level of the second control node, and among the first control node and the second control node, the adjusted node is used to output an output signal; among the first node and the second node, one is configured to receive a high level and the other is configured to receive a low level; a first adjustment circuit, one end of which is coupled to the first node, and the other end of which is coupled to the first control node, and is configured to adjust the node potential of the first control node after the first transistor is turned on based on the first control signal according to a first adjustment signal; a second adjustment circuit, one end of which is coupled to the first node, and the other end of which is coupled to the second control node, and is configured to adjust the node potential of the second control node after the second transistor is turned on based on the second control signal according to a second adjustment signal; the first adjustment signal and the second adjustment signal are used to adjust the mismatch between the first transistor and the second transistor.

[0006] By connecting a first adjustment circuit in parallel with the first transistor, the first adjustment circuit is turned on based on the first adjustment signal. After the first adjustment circuit is turned on, the first node is connected to the first control node through the first adjustment circuit, thereby adjusting the potential of the first control node; by connecting a second adjustment circuit in parallel with the second transistor, the second adjustment circuit is turned on based on the second adjustment signal. After the second adjustment circuit is turned on, the first node is connected to the second control node through the second adjustment circuit, thereby adjusting the potential of the second control node; by adjusting the first adjustment signal and the second adjustment signal, when the first control signal and the second control signal are equal, the node potentials of the first control node and the second control node are equal, that is, through the first adjustment circuit and the second adjustment circuit, the mismatch between the first transistor and the second transistor is corrected.

[0007] In addition, the first adjustment circuit includes: a first adjustment transistor, one terminal of which is coupled to the first node, the other terminal is coupled to the first control node, and the gate is used to receive a first adjustment signal; the first adjustment transistor is configured to adjust the magnitude of the source-drain current based on the first adjustment signal; the second adjustment circuit includes: a second adjustment transistor, one terminal of which is coupled to the first node, the other terminal is coupled to the second control node, and the gate is used to receive a second adjustment signal; the second adjustment transistor is configured to adjust the magnitude of the source-drain current based on the first adjustment signal. By adjusting the magnitude of the first adjustment signal, the conduction ability of the first adjustment transistor is changed, thereby adjusting the influence of the first adjustment circuit on the potential of the first control node; by adjusting the magnitude of the second adjustment signal, the conduction ability of the second adjustment transistor is changed, thereby adjusting the influence of the second adjustment circuit on the potential of the second control node.

[0008] In addition, the first adjustment circuit includes: a first adjustment transistor group, and the first adjustment transistor group includes: x first adjustment transistors; wherein, one terminal of the x first adjustment transistors is coupled to the first node, the other terminal is coupled to the first control node, the gate is used to receive a first adjustment signal, and the first adjustment signal is used to selectively turn on the first adjustment transistor; the second adjustment circuit includes: a second adjustment transistor group, and the second adjustment transistor group includes: x second adjustment transistors; wherein, one terminal of the x second adjustment transistors is coupled to the first node, the other terminal is coupled to the second control node, the gate is used to receive a second adjustment signal, and the second adjustment signal is used to selectively turn on the second adjustment transistor; x is an integer greater than or equal to 2. By adjusting the first adjustment signal to control the number of first adjustment transistors in the first transistor group, the conduction ability of the first adjustment transistor group is changed, thereby adjusting the influence of the first adjustment circuit on the potential of the first control node; by adjusting the second adjustment signal to control the number of second adjustment transistors in the second transistor group, the conduction ability of the second adjustment transistor group is changed, thereby adjusting the influence of the second adjustment circuit on the potential of the second control node.

[0009] In addition, the source-drain conduction abilities of the x first adjustment transistors are the same after being turned on based on the same gate voltage, and the source-drain conduction abilities of the x second adjustment transistors are the same after being turned on based on the same gate voltage.

[0010] In addition, among the x first adjustment transistors, after being turned on based on the same gate voltage, the source-drain conduction ability of the nth first adjustment transistor is twice that of the (n - 1)th first adjustment transistor; among the x second adjustment transistors, after being turned on based on the same gate voltage, the source-drain conduction ability of the nth second adjustment transistor is twice that of the (n - 1)th second adjustment transistor, where n is any integer less than or equal to x and greater than or equal to 2.

[0011] In addition, the comparator circuit further includes: a switching MOS transistor, one terminal of which is used to couple to a power supply node or a ground node, the other terminal is coupled to the first node, and the gate is used to receive a switching enable signal; wherein, if the first node is used to receive a high level, the switching MOS transistor is coupled to the power supply node, and if the first node is used to receive a low level, the switching MOS transistor is coupled to the ground node; the switching MOS transistor has the same doping type as the first transistor; for the switching MOS transistor, it is turned on based on the switching enable signal to provide current to the comparator circuit, thereby turning on the comparator circuit, so that the comparator circuit is turned on during use and turned off when not in use, in order to save energy consumption; in addition, the switching MOS transistor is used to prevent the level from being directly loaded on the comparator circuit, so as to prevent the transistors in the corresponding comparator circuit from being broken down.

[0012] In addition, the comparator circuit further includes: a first protection transistor, which has the same type as the first transistor, one terminal of which is coupled to the first node, the other terminal is coupled to the first adjustment circuit, and the gate is used to receive a first control signal; a second protection transistor, which has the same type as the second transistor, one terminal of which is coupled to the first node, the other terminal is coupled to the second adjustment circuit, and the gate is used to receive a second control signal. The first protection transistor is connected in series with the first adjustment circuit and is turned on based on the first control signal, so that when the first transistor is operating, the branch where the first adjustment circuit is located is turned on simultaneously; in addition, the first protection transistor has the same type as the first transistor, and those skilled in the art understand that for the first adjustment transistor of the same size, when there is a protection transistor connected in series, under the action of the same adjustment signal, the adjustment ability of the transistor becomes weaker, and the adjustment effect on the current is more refined, thereby preventing the first adjustment circuit from over-adjusting the first control node; the second protection transistor is connected in series with the second adjustment circuit and is turned on based on the second control signal, so that when the second transistor is operating, the branch where the second adjustment circuit is located is turned on simultaneously; in addition, the second protection transistor has the same type as the second transistor, thereby preventing the second adjustment circuit from over-adjusting the second control node.

[0013] In addition, the load unit includes: a third transistor, one terminal of which is coupled to the second node, the other terminal is coupled to the first control node; a fourth transistor, one terminal of which is coupled to the second node, the other terminal is coupled to the second control node; the gates of the third transistor and the fourth transistor are coupled and coupled to the first control node; wherein, the third transistor and the fourth transistor have the same transistor doping type, and the first transistor and the third transistor have different transistor doping types.

[0014] In addition, the first node is used to couple to the power supply node, the second node is used to couple to the ground node, the first transistor and the second transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors.

[0015] In addition, the comparison circuit further includes: a calibration control circuit 300 for providing a first adjustment signal and a second adjustment signal to adjust the mismatch between the first transistor <01> and the second transistor <02>.

[0016] In addition, the calibration control circuit includes: a clock module for receiving a calibration enable signal and generating a calibration clock based on the calibration enable signal, the calibration enable signal being provided during the calibration phase; a first calibration module coupled to the clock module, initially setting the first adjustment signal to a maximum value and the second adjustment signal to a minimum value, providing the first adjustment signal and the second adjustment signal, and gradually decreasing the first adjustment signal and increasing the second adjustment signal based on the calibration clock; a judgment module for receiving output signals corresponding to different first adjustment signals and second adjustment signals and obtaining the first adjustment signal and the second adjustment signal corresponding to the first time node when the output signal undergoes a potential inversion; a storage module coupled to the judgment module for obtaining the first adjustment signal and the second adjustment signal corresponding to the first time node and providing the first adjustment signal and the second adjustment signal corresponding to the first time node during the working phase.

[0017] In addition, the calibration control circuit further includes: a second calibration module coupled to the clock module, initially setting the first adjustment signal to a minimum value and the second adjustment signal to a maximum value, providing the first adjustment signal and the second adjustment signal, and gradually increasing the first adjustment signal and decreasing the second adjustment signal based on the calibration clock; the judgment module is further configured to obtain the first adjustment signal and the second adjustment signal corresponding to the second time node when the output signal undergoes a potential inversion; the storage module is further configured to obtain the first adjustment signal and the second adjustment signal corresponding to the second time node, and use the average value of the first adjustment signals corresponding to the first time node and the second time node as the first adjustment signal to be provided during the working phase, and use the average value of the second adjustment signals corresponding to the first time node and the second time node as the second adjustment signal to be provided during the working phase.

[0018] In addition, the comparator circuit further includes: a first selection circuit for receiving an input selection signal, an input signal or a reference signal and providing a first control signal; a second selection circuit for receiving an input selection signal, an input signal or a reference signal and providing a second control signal; the first selection circuit is configured to select to provide the first control signal with the input signal or the reference signal based on the input selection signal; the second selection circuit is configured to select to provide the second control signal with the input signal or the reference signal based on the input selection signal.

[0019] An embodiment of the present disclosure provides a mismatch correction method, which is applied to the comparator circuit described above and includes: in the calibration stage, controlling the inputs of the first control signal and the second control signal to be the same; initially setting the first adjustment signal to the maximum value and the second adjustment signal to the minimum value; sequentially decreasing the first adjustment signal and increasing the second adjustment signal, and obtaining output signals corresponding to different first adjustment signals and second adjustment signals; obtaining the first adjustment signal and the second adjustment signal corresponding to the first time node when the output signal undergoes a potential inversion; using the first adjustment signal and the second adjustment signal corresponding to the first time node as the first adjustment signal and the second adjustment signal to be provided in the working stage, so as to eliminate the mismatch between the two input transistors of the differential structure, thereby improving the performance of the memory.

[0020] In addition, after obtaining the first adjustment signal and the second adjustment signal corresponding to the first time node when the output signal undergoes a potential inversion, it further includes: initially setting the first adjustment signal to the minimum value and the second adjustment signal to the maximum value; sequentially increasing the first adjustment signal and decreasing the second adjustment signal, and obtaining output signals corresponding to different first adjustment signals and second adjustment signals; obtaining the first adjustment signal and the second adjustment signal corresponding to the second time node when the output signal undergoes a potential inversion; using the first adjustment signal and the second adjustment signal corresponding to the first time node as the first adjustment signal and the second adjustment signal to be provided in the working stage includes: using the average value of the first adjustment signals corresponding to the first time node and the second time node as the first adjustment signal to be provided in the working stage; using the average value of the second adjustment signals corresponding to the first time node and the second time node as the second adjustment signal to be provided in the working stage.

[0021] An embodiment of the present disclosure provides a memory, which uses the comparator circuit provided in the above embodiment for data input to eliminate the mismatch between the two input transistors of the differential structure, thereby improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments unless otherwise stated. The figures in the drawings do not constitute a scale limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1 and Figure 2 are schematic diagrams of two structures of a comparator circuit provided in an embodiment of the present disclosure;

[0024] Figure 3 and Figure 4 are two structural schematic diagrams of a comparator circuit under a specific load provided by an embodiment of the present disclosure;

[0025] Figure 5 are structural schematic diagrams of a first adjustment circuit, a second adjustment circuit, and a switching MOS transistor provided by an embodiment of the present disclosure;

[0026] Figure 6 are specific structural schematic diagrams of a first adjustment circuit and a second adjustment circuit with protection transistors provided by an embodiment of the present disclosure;

[0027] Figure 7 are specific structural schematic diagrams of another first adjustment circuit and a second adjustment circuit with protection transistors provided by an embodiment of the present disclosure;

[0028] Figure 8 is a reception schematic diagram of a calibration control circuit provided by an embodiment of the present disclosure;

[0029] Figure 9 is a flowchart schematic diagram of a mismatch correction method provided by another embodiment of the present disclosure. Detailed implementation manners

[0030] Although the two input transistors of the differential structure are of the same size in design, during the process of forming the input transistors on the actual silicon wafer, due to various factors, mismatch will occur between the two input transistors.

[0031] The mismatch caused by the above reasons is very small, but the operating frequency of the memory is very high under normal working conditions. In the case where the signal frequency of the memory is very high, at this time, even if there is a small mismatch between the input transistors, it will have a significant impact on the performance of the product.

[0032] An embodiment of the present disclosure provides a comparator circuit to eliminate the mismatch between the two input transistors of the differential structure, thereby improving the performance of the memory.

[0033] Those of ordinary skill in the art can understand that in various embodiments of the present disclosure, many technical details are proposed for the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present disclosure can still be implemented. The following division of each embodiment is for convenience of description and should not constitute any limitation to the specific implementation manner of the present disclosure. Each embodiment can be combined with each other and cross-referenced on the premise of not contradicting each other.

[0034] Figure 1 and Figure 2 are two structural schematic diagrams of the comparator circuit provided by this embodiment,Figure 3 and Figure 4 are two schematic structural diagrams of the comparator circuit under the specific load provided in this embodiment, Figure 5 is a schematic structural diagram of the first adjustment circuit, the second adjustment circuit and the switching MOS transistor provided in this embodiment, Figure 6 is a specific schematic structural diagram of a first adjustment circuit and a second adjustment circuit with protection transistors provided in this embodiment, Figure 7 is a specific schematic structural diagram of another first adjustment circuit and a second adjustment circuit with protection transistors provided in this embodiment, Figure 8 is a receiving schematic diagram of the calibration control circuit provided in this embodiment. The comparator circuit provided in this embodiment will be further described in detail below with reference to the accompanying drawings, specifically as follows:

[0035] Referring to Figures 1 to 7 , the comparator circuit includes:

[0036] A first transistor <01>, one terminal is coupled to a first node J1, the other terminal is coupled to a first control node K1, and the gate is used to receive a first control signal R1.

[0037] A second transistor <02>, one terminal is coupled to the first node J1, the other terminal is coupled to a second control node K2, and the gate is used to receive a second control signal R2.

[0038] Wherein, the first transistor <01> and the second transistor <02> have the same transistor doping type, that is, the first transistor <01> and the second transistor <02> are used as two input transistors of a differential structure, and the first control signal R1 and the second control signal R2 are used as differential input data of the differential structure.

[0039] A load unit 101, one end is coupled to a second node J2, the other end is coupled to the first control node K1 and the second control node K2, and the load unit 101 is configured to adjust the level of the second control node K2 based on the level of the first control node K1, or adjust the level of the first control node K1 based on the level of the second control node K2. Among the first control node K1 and the second control node K2, the adjusted node is used to output an output signal S.

[0040] Wherein, the output signal S is the output signal of the differential structure.

[0041] Wherein, among the first node J1 and the second node J2, one is used to receive a high level and the other is used to receive a low level.

[0042] Specifically, when the first node J1 receives a high level and the second node J2 receives a low level, the schematic structural diagram of the comparator circuit refers to Figure 1; When the first node J1 receives a low level and the second node J2 receives a high level, the schematic structural diagram of the comparator circuit is referred to Figure 2 .

[0043] It should be noted that in this embodiment, the case where the load unit 101 controls the level of the second control node K2 based on the level of the first control node K1 is taken as an example for specific description, which does not constitute a limitation to this embodiment; in other embodiments, those skilled in the art can replace the positions of the first control node and the second control node, so as to implement the scheme that the load unit controls the level of the first control node based on the level of the second control node.

[0044] It should be noted that the above-mentioned "high level" is the level provided by the internal power supply V CC of the memory to which the comparator circuit belongs, and the above-mentioned "low level" is the level provided by the ground node GND of the comparator circuit.

[0045] Refer to Figure 3 and Figure 4 , for Figure 1 and Figure 2 The load unit 101 shown in, the load unit 101 includes:

[0046] The third transistor <03>, one terminal is coupled to the second node J2, and the other terminal is coupled to the first control node K1.

[0047] The fourth transistor <04>, one terminal is coupled to the second node J2, and the other terminal is coupled to the second control node K2.

[0048] Wherein, the gates of the third transistor <03> and the fourth transistor <04> are coupled and coupled to the first control node K1; and the transistor doping types of the third transistor <03> and the fourth transistor <04> are the same, and the transistor doping types of the first transistor <01> and the third transistor <03> are different.

[0049] It should be noted that Figure 3 Corresponding to Figure 1 is the comparator circuit structure when the first node J1 receives a high level and the second node J2 receives a low level. At this time, the first transistor <01> and the second transistor <02> are PMOS transistors, and the third transistor <03> and the fourth transistor <04> are NMOS transistors; Figure 4 Corresponding to Figure 2 is the comparator circuit structure when the first node J1 receives a low level and the second node J2 receives a high level. At this time, the first transistor <01> and the second transistor <02> are NMOS transistors, and the third transistor <03> and the fourth transistor <04> are PMOS transistors;

[0050] Furthermore, refer toFigure 5 , Figure 5 In the circuit shown, the first node J1 is used to couple to the power supply node V CC , and the second node J2 is used to couple to the ground node GND, so that the first node J1 receives a high level and the second node J2 receives a low level; correspondingly, in some embodiments, the first node J1 is used to couple to the ground node GND, and the second node J2 is used to couple to the power supply node V CC , so that the first node J1 receives a low level and the second node J2 receives a high level.

[0051] In addition, the above example only gives a specific structure of the load unit 101. In other embodiments, the load unit can also be composed of other load forms.

[0052] It should be noted that in the subsequent embodiments of the present disclosure, the first node J1 is used to couple to the power supply node V CC , and the second node J2 is used to couple to the ground node GND for specific circuit description, which does not constitute a limitation to this embodiment.

[0053] Continuing to refer to Figure 5 , the comparator circuit further includes:

[0054] The first adjustment circuit 100, one end is coupled to the first node J1 and the other end is coupled to the first control node K1, and is used to adjust the node potential of the first control node K1 after the first transistor <01> is turned on based on the first control signal R1 according to the first adjustment signal T1.

[0055] The second adjustment circuit 200, one end is coupled to the first node J1 and the other end is coupled to the second control node K2, and is used to adjust the node potential of the second control node K2 after the second transistor <02> is turned on based on the second control signal R2 according to the second adjustment signal T2.

[0056] Wherein, the first adjustment signal T1 and the second adjustment signal T2 are used to adjust the mismatch between the first transistor <01> and the second transistor <02>.

[0057] It should be noted that the "mismatch" mentioned above means that during the formation of the input transistors, due to various factors (such as the dose of doped ions implanted in the process, the exposure angle, the position of the transistors, etc.), parameter mismatches occur between the two input transistors.

[0058] Specifically, the first transistor <01> and the second transistor <02> serve as two input transistors of a differential structure. When there is no mismatch between the first transistor <01> and the second transistor <02>, after the first transistor <01> and the second transistor <02> are turned on, the first control node K1 and the first node J1 are indirectly connected. Current flows from the first node J1 to the first control node K1 through the first transistor <01>. The second control node K2 and the first node J1 are indirectly connected. Current flows from the first node J1 to the second control node K2 through the second transistor <02>. At this time, when the first control signal R1 and the second control signal R2 are equal, the potentials of the first control node K1 and the second control node K2 are the same; when there is a mismatch between the first transistor <01> and the second transistor <02>, the degrees of turn-on of the first transistor <01> and the second transistor <02> are different based on the same gate turn-on voltage, resulting in a difference in the potentials of the first control node K1 and the second control node K2, thereby affecting the output of the differential structure.

[0059] In the embodiment of the present disclosure, a first adjustment circuit 100 is connected in parallel with the first transistor <01>. The first adjustment circuit 100 is turned on based on a first adjustment signal T1. After the first adjustment circuit 100 is turned on, the first node J1 is connected to the first control node K1 through the first adjustment circuit 100, thereby adjusting the potential of the first control node K1; a second adjustment circuit 200 is connected in parallel with the second transistor <02>. The second adjustment circuit 200 is turned on based on a second adjustment signal T2. After the second adjustment circuit 200 is turned on, the first node J1 is connected to the second control node K2 through the second adjustment circuit 200, thereby adjusting the potential of the second control node K2; by adjusting the first adjustment signal T1 and the second adjustment signal T2, when the first control signal R1 and the second control signal R2 are equal, the node potentials of the first control node K1 and the second control node K2 are equal, that is, through the first adjustment circuit 100 and the second adjustment circuit 200, the mismatch between the first transistor <01> and the second transistor <02> is corrected.

[0060] More specifically, when the first control signal R1 and the second control signal R2 are equal, the first adjustment signal T1 and the second adjustment signal T2 corresponding to the occurrence potential flip time point of the output signal S are used as the correction signals for the first adjustment circuit 100 and the second adjustment circuit 200.

[0061] Reference Figures 5 to 7 , the comparator circuit further includes:

[0062] A switching MOS transistor <31> has one terminal coupled to a power supply node Vcc or a ground node GND, and the other terminal coupled to the first node J1. The gate is used to receive a switching enable signal.

[0063] Among them, if the first node J1 is used to receive a high level, the switching MOS transistor <31> is coupled to the power supply node Vcc; if the first node J1 is used to receive a low level, the switching MOS transistor <31> is coupled to the ground wire node GND.

[0064] In addition, the switching MOS transistor <31> has the same doping type as the first transistor <01>.

[0065] Among them, the switch enable signal is used to turn on the switching MOS transistor <31>. For the switching MOS transistor <31>, it is turned on based on the switch enable signal to provide current to the comparator circuit, thereby turning on the comparator circuit, so that the comparator circuit is turned on during use and turned off when not in use to save energy consumption; in addition, the switching MOS transistor <31> is used to prevent the level from being directly loaded on the comparator circuit to breakdown the transistors in the corresponding comparator circuit.

[0066] It should be noted that in this embodiment, the switching MOS transistor is used as the connecting component between the first node J1 and the power supply node Vcc or the ground wire node GND. In some embodiments, a current source can also be set to replace the switching MOS transistor as the connecting component between the first node J1 and the power supply node Vcc.

[0067] Figures 5 to 7 Taking the circuit shown as an example where the first node J1 receives a high level, at this time, the switching MOS transistor <31> and the first transistor <01> are PMOS transistors, and one end of the switching MOS transistor <31> is used to be coupled to the power supply node Vcc; if the comparator circuit receives a low level at the first node J1, refer to Figure 2 and Figure 4 , at this time, the switching MOS transistor and the first transistor <01> are NMOS transistors, and one end of the switching MOS transistor <31> is used to be coupled to the ground wire node GND.

[0068] It should be noted that the "coupling" mentioned in the above embodiments includes direct connection and indirect connection. Among them, direct connection means direct connection of the circuit, and indirect connection means indirect electrical connection through other semiconductor devices. This embodiment does not limit the semiconductor devices in the indirect connection. As long as it conforms to the connection relationship reflected in the above embodiments, it should fall within the protection scope of the present disclosure.

[0069] In some embodiments, refer to Figure 6 and Figure 7 , the comparator circuit further includes:

[0070] The first protection transistor <b1>, having the same type as the first transistor <01>, one terminal is coupled to the first node J1, the other terminal is coupled to the first adjustment circuit 100, and the gate is used to receive the first control signal R1.

[0071] The second protection transistor <b2>, of the same type as the second transistor <02>, one terminal is coupled to the first node J1, the other terminal is coupled to the second adjustment circuit 200, and the gate is for receiving the second control signal R2.

[0072] The first protection transistor <b1>Connected in series with the first adjustment circuit 100 and turned on based on the first control signal R1, when the first transistor <01> operates, the branch where the first adjustment circuit 100 is located is turned on simultaneously; in addition, the first protection transistor <b1>is of the same type as the first transistor <01>. Those skilled in the art understand that for a first adjustment transistor of the same size, when a protection transistor is connected in series, under the action of the same adjustment signal, the adjustment ability of the transistor becomes weaker, and the adjustment effect on the current is more delicate, thereby preventing the first adjustment circuit 100 from over-adjusting the first control node K1; the second protection transistor <b2>Connected in series with the second adjustment circuit 200 and turned on based on the second control signal R2, so that when the second transistor <02> operates, the branch where the second adjustment circuit 200 is located is turned on simultaneously; in addition, the second protection transistor <b2>is of the same type as the second transistor <01>, thereby preventing the second adjustment circuit 200 from over-adjusting the second control node K2.

[0073] For the first adjustment circuit 100 and the second adjustment circuit 100, this embodiment provides two implementation strategies, which are as follows:

[0074] In one implementation strategy:

[0075] The first adjustment circuit 100 includes: a first adjustment transistor <11>, one terminal of which is coupled to the first node J1, the other terminal is coupled to the first control node K1, and the gate is for receiving the first adjustment signal T1.

[0076] The first adjustment transistor <11> is configured to adjust the magnitude of the source-drain current based on the first adjustment signal T1.

[0077] The second adjustment circuit 200 includes: a second adjustment transistor <12>, one terminal of which is coupled to the first node J1, the other terminal is coupled to the second control node K2, and the gate is for receiving the second adjustment signal T2.

[0078] The second adjustment transistor <12> is configured to adjust the magnitude of the source-drain current based on the second adjustment signal T2.

[0079] In this implementation strategy, the on-conduction ability of the first adjustment transistor <11> can be changed by adjusting the magnitude of the first adjustment signal T1, thereby adjusting the influence of the first adjustment circuit 100 on the potential of the first control node K1; the on-conduction ability of the second adjustment transistor <12> can be changed by adjusting the magnitude of the second adjustment signal T2, thereby adjusting the influence of the second adjustment circuit 200 on the potential of the second control node K2.

[0080] In some embodiments, the source-drain on-conduction abilities of the first adjustment transistor <11> and the second adjustment transistor <12> are the same after being turned on based on the same gate voltage. Specifically, the source-drain on-conduction abilities of the first adjustment transistor and the second adjustment transistor can be made the same after being turned on based on the same gate voltage by setting the same transistor size.

[0081] Specific reference Figure 6 , by adjusting the magnitude of the first adjustment signal T1 input to the first adjustment transistor <11>, the conduction degree of the first adjustment transistor <11> is controlled, thereby adjusting the magnitude of the current transmitted from the first node J1 to the first control node K1 through the first adjustment circuit 100, and thus changing the influence of the first adjustment circuit 100 on the potential of the first control node K1; by adjusting the magnitude of the second adjustment signal T2 input to the second adjustment transistor <12>, the conduction degree of the second adjustment transistor <12> is controlled, thereby adjusting the magnitude of the current transmitted from the first node J1 to the second control node K2 through the second adjustment circuit 200, and thus changing the influence of the second adjustment circuit 200 on the potential of the second control node K2.

[0082] In another implementation strategy:

[0083] The first adjustment circuit 100 includes a first adjustment transistor group, and the first adjustment transistor group includes: x first adjustment transistors; one terminal of the x first adjustment transistors is coupled to the first node J1, the other terminal is coupled to the first control node K1, and the gate is used to receive the first adjustment signal T1, and the first adjustment signal T1 is used to selectively turn on the first adjustment transistors.

[0084] The second adjustment circuit 200 includes a second adjustment transistor group, and the second adjustment transistor group includes: x second adjustment transistors; one terminal of the x second adjustment transistors is coupled to the first node J1, the other terminal is coupled to the second control node K2, and the gate is used to receive the second adjustment signal T2, and the second adjustment signal T2 is used to selectively turn on the second adjustment transistors.

[0085] Wherein, x is an integer greater than or equal to 2.

[0086] In this implementation strategy, the conduction ability of the first adjustment transistor group can be changed by adjusting the number of first adjustment transistors in the first transistor group through the first adjustment signal T1, so as to adjust the influence of the first adjustment circuit 100 on the potential of the first control node K1; by adjusting the second adjustment signal T2 to control the number of second adjustment transistors in the second transistor group to change the conduction ability of the second adjustment transistor group, so as to adjust the influence of the second adjustment circuit 200 on the potential of the second control node K2.

[0087] In some embodiments, the source-drain conduction abilities of the x first adjustment transistors are the same after being turned on based on the same gate voltage, and the source-drain conduction abilities of the x second adjustment transistors are the same after being turned on based on the same gate voltage. Specifically, the same source-drain conduction abilities of different first adjustment transistors or second adjustment transistors after being turned on based on the same gate voltage can be achieved by setting the same transistor size.

[0088] In some embodiments, among the x first regulating transistors, after being turned on based on the same gate voltage, the source-drain conduction ability of the nth first regulating transistor is twice that of the (n - 1)th first regulating transistor; among the x second regulating transistors, after being turned on based on the same gate voltage, the source-drain conduction ability of the nth second regulating transistor is twice that of the (n - 1)th second regulating transistor; where n is any integer less than or equal to x and greater than or equal to 2. Specifically, different first regulating transistors or second regulating transistors can be made to have their source-drain conduction abilities vary multiplicatively after being turned on based on the same gate voltage by setting transistors with multiplicatively varying sizes.

[0089] Specifically referring to Figure 7 , for the first transistor group, the source-drain conduction ability of the second first regulating transistor <22> is twice that of the first first regulating transistor <21>, the source-drain conduction ability of the third first regulating transistor <23> (not shown) is twice that of the second first regulating transistor <22>... the source-drain conduction ability of the xth first regulating transistor <2x> is twice that of the (x - 1)th first regulating transistor <2x - 1> (not shown); for the second transistor group, the source-drain conduction ability of the second second regulating transistor <32> is twice that of the first second regulating transistor <31>, the source-drain conduction ability of the third second regulating transistor <33> (not shown) is twice that of the second second regulating transistor <32>... the source-drain conduction ability of the xth second regulating transistor <3x> is twice that of the (x - 1)th second regulating transistor <3x - 1> (not shown).

[0090] By adjusting the first regulating signal T1, different first regulating transistors in the first transistor group are controlled to conduct, thereby changing the overall source-drain conduction ability of the first transistor group, and thus adjusting the influence of the first regulating circuit 100 on the potential of the first control node K1; by adjusting the second regulating signal T2, different second regulating transistors in the second transistor group are controlled to conduct, thereby changing the overall source-drain conduction ability of the second transistor group, and thus adjusting the influence of the second regulating circuit 200 on the potential of the first control node K2; it should be noted that in Figure 7 the example shown, the first regulating signal T1 and the second regulating signal T2 are not a single signal. The first regulating signal T1 and the second regulating signal T2 each represent a signal group, and each signal in the signal group is used to independently control the corresponding transistors in the first transistor group and the second transistor group to conduct.

[0091] Referring to Figure 8 , in some embodiments, the comparator circuit further includes: a calibration control circuit 300, which is configured to provide a first adjustment signal T1 and a second adjustment signal T2 to adjust the mismatch between the first transistor <01> and the second transistor <02>.

[0092] Specifically, the calibration control circuit 300 includes:

[0093] A clock module 303, configured to receive a calibration enable signal MR and generate a calibration clock CLK based on the calibration enable signal MR. The calibration enable signal MR is provided during the calibration phase.

[0094] A first calibration module 301, coupled to the clock module 303, initially sets the first adjustment signal T1 to a maximum value and the second adjustment signal T2 to a minimum value, provides the first adjustment signal T1 and the second adjustment signal T2, and gradually decreases the first adjustment signal T1 and increases the second adjustment signal T2 based on the calibration clock CLK.

[0095] A judgment module 304, configured to receive an output signal S corresponding to different first adjustment signals T1 and second adjustment signals T2, and obtain the first adjustment signal T1 and the second adjustment signal T2 corresponding to the first time node t1 at which the potential of the output signal S flips.

[0096] A storage module 305, coupled to the judgment module 304, configured to obtain the first adjustment signal T1 and the second adjustment signal T2 corresponding to the first time node t1, and provide the first adjustment signal T1 and the second adjustment signal T2 corresponding to the first time node t1 during the working phase.

[0097] Referring to Table 1 below, Table 1 is a specific adjustment example 1:

[0098]

[0099]

[0100] Correspondingly, in some embodiments, the first calibration module 301, coupled to the clock module 303, initially sets the first adjustment signal T1 to a minimum value and the second adjustment signal T2 to a maximum value, provides the first adjustment signal T1 and the second adjustment signal T2, and gradually increases the first adjustment signal T1 and decreases the second adjustment signal T2 based on the calibration clock CLK.

[0101] At this time, its adjustment strategy refers to Table 2 below. Table 2 is a specific adjustment example 2:

[0102]

[0103] In some embodiments, the calibration control circuit 300 further includes:

[0104] The second calibration module 302, coupled to the clock module 303, initially sets the first adjustment signal T1 to the minimum value and the second adjustment signal T2 to the maximum value, provides the first adjustment signal T1 and the second adjustment signal T2, and gradually increases the first adjustment signal T1 and decreases the second adjustment signal T2 based on the calibration clock CLK.

[0105] The determination module 304 is further configured to obtain the first adjustment signal T1 and the second adjustment signal T2 corresponding to the second time node t2 at which the output signal S undergoes a potential inversion.

[0106] The storage module 305 is further configured to obtain the first adjustment signal T1 and the second adjustment signal T2 corresponding to the second time node t2, and use the average value of the first adjustment signals T1 corresponding to the first time node t1 and the second time node t2 as the first adjustment signal T1 to be provided during the working phase, and use the average value of the second adjustment signals T2 corresponding to the first time node t1 and the second time node t2 as the second adjustment signal T2 to be provided during the working phase.

[0107] Refer to Table 3 below. Table 3 is a specific adjustment example 3:

[0108]

[0109]

[0110] In some embodiments, the comparator circuit further includes:

[0111] The first selection circuit 310, which receives the input selection signal C, the input signal Din, or the reference signal Vref, and is configured to provide the first control signal R1.

[0112] The second selection circuit 320, which receives the input selection signal C, the input signal Din, or the reference signal Vref, and is configured to provide the second control signal R2.

[0113] Wherein, the first selection circuit is configured to select to provide the first control signal with the input signal or the reference signal based on the input selection signal;

[0114] The second selection circuit is configured to select to provide the second control signal with the input signal or the reference signal based on the input selection signal.

[0115] Wherein, the input signal Din is the actual input signal input to the shown comparator circuit, and the reference signal Vref is the reference signal used to determine whether the input is a high level or a low level.

[0116] Specifically, in the calibration stage, the input selection signal C is used to control the first selection circuit 310 and the second selection circuit 320 to simultaneously provide the first control signal R1 and the second control signal R2 with the input signal Din, or to simultaneously provide the first control signal R1 and the second control signal R2 with the reference signal Vref; that is, to control the first control signal R1 and the second control signal R2 to be the same signal, so as to obtain the mismatch between the first transistor <01> and the second transistor <02>, and then complete the compensation for the mismatch between the first transistor <01> and the second transistor <02> subsequently.

[0117] In the working stage, the input selection signal C is used to control the first selection circuit 310 to provide the first control signal R1 with the input signal Din, and the second selection circuit 320 to provide the second control signal R2 with the reference signal Vref; or, in the working stage, the input selection signal C is used to control the first selection circuit 310 to provide the first control signal R1 with the reference signal Vref, and the second selection circuit 320 to provide the second control signal R2 with the input signal Din.

[0118] In the embodiment of the present disclosure, a first adjustment circuit 100 is connected in parallel with the first transistor <01>. The first adjustment circuit 100 is turned on based on the first adjustment signal T1. After the first adjustment circuit 100 is turned on, the first node J1 is connected to the first control node K1 through the first adjustment circuit 100, thereby adjusting the potential of the first control node K1; a second adjustment circuit 200 is connected in parallel with the second transistor <02>. The second adjustment circuit 200 is turned on based on the second adjustment signal T2. After the second adjustment circuit 200 is turned on, the first node J1 is connected to the second control node K2 through the second adjustment circuit 200, thereby adjusting the potential of the second control node K2; by adjusting the first adjustment signal T1 and the second adjustment signal T2, when the first control signal and the second control signal are equal, the node potentials of the first control node K1 and the second control node K2 are equal, that is, through the first adjustment circuit 100 and the second adjustment circuit 200, the mismatch between the first transistor <01> and the second transistor <02> is corrected.

[0119] Each unit involved in this embodiment is a logic unit. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present disclosure, units not closely related to solving the technical problems proposed by the present disclosure are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

[0120] It should be noted that the features disclosed in the comparator circuit provided in the above embodiment can be arbitrarily combined without conflict to obtain a new comparator circuit embodiment.

[0121] Another embodiment of the present disclosure provides a mismatch correction method, which applies the comparator circuit provided in the above embodiment to eliminate the mismatch between two input transistors of a differential structure, thereby improving the memory performance.

[0122] Figure 9 The following is a schematic flowchart of the mismatch correction method provided in this embodiment. The mismatch correction method provided in this embodiment will be further described in detail below with reference to the accompanying drawings, specifically as follows:

[0123] Refer to Figure 9 , the mismatch correction method includes:

[0124] Step 401: Initially set the first adjustment signal to the maximum value and the second adjustment signal to the minimum value. Decrease the first adjustment signal and increase the second adjustment signal in sequence, and obtain the output signals corresponding to different first adjustment signals and second adjustment signals.

[0125] Step 402: Obtain the first adjustment signal and the second adjustment signal corresponding to the first time node when the output signal undergoes a potential flip.

[0126] Specifically, in the calibration stage, control the inputs of the first control signal and the second control signal to be the same; initially set the first adjustment signal to the maximum value and the second adjustment signal to the minimum value. Decrease the first adjustment signal and increase the second adjustment signal in sequence, and obtain the output signals corresponding to different first adjustment signals and second adjustment signals. Obtain the first adjustment signal and the second adjustment signal corresponding to the first time node when the output signal undergoes a potential flip; use the first adjustment signal and the second adjustment signal corresponding to the first time node as the first adjustment signal and the second adjustment signal to be provided in the working stage.

[0127] Refer to Table 1 below. Table 1 is a specific adjustment example 1:

[0128]

[0129] At this time, use the first adjustment signal A3 or A2 and the second adjustment signal A2 or A3 corresponding to the first time node t1 as the first adjustment signal and the second adjustment signal to be provided in the working stage.

[0130] In some embodiments, for step 401, it can also be set as: initially set the first adjustment signal to the minimum value and the second adjustment signal to the maximum value. Increase the first adjustment signal and decrease the second adjustment signal in sequence, and obtain the input signals corresponding to different first adjustment signals and second adjustment signals.

[0131] At this time, its adjustment strategy refers to Table 2 below. Table 2 is a specific adjustment example 2:

[0132]

[0133] At this time, use the first adjustment signal A3 or A2 corresponding to the first time node t1 and the second adjustment signal A2 or A3 as the first adjustment signal and the second adjustment signal required in the working stage.

[0134] In some embodiments, the mismatch correction method further includes:

[0135] Step 403: Initially set the first adjustment signal to the minimum value and the second adjustment signal to the maximum value. Gradually increase the first adjustment signal and decrease the second adjustment signal, and obtain the output signals corresponding to different first adjustment signals and second adjustment signals.

[0136] Step 404: Obtain the first adjustment signal and the second adjustment signal corresponding to the second time node when the output signal undergoes a potential flip.

[0137] Step 405: Use the average value of the first adjustment signals corresponding to the first time node and the second time node as the first adjustment signal required in the working stage; use the average value of the second adjustment signals corresponding to the first time node and the second time node as the second adjustment signal required in the working stage.

[0138] Specifically, after obtaining the first adjustment signal and the second adjustment signal corresponding to the first time node when the output signal undergoes a potential flip, it further includes: initially setting the first adjustment signal to the minimum value and the second adjustment signal to the maximum value; gradually increasing the first adjustment signal and decreasing the second adjustment signal, and obtaining the output signals corresponding to different first adjustment signals and second adjustment signals; obtaining the first adjustment signal and the second adjustment signal corresponding to the second time node when the output signal undergoes a potential flip.

[0139] Using the first adjustment signal and the second adjustment signal corresponding to the first time node as the first adjustment signal and the second adjustment signal required in the working stage includes: using the average value of the first adjustment signals corresponding to the first time node and the second time node as the first adjustment signal required in the working stage; using the average value of the second adjustment signals corresponding to the first time node and the second time node as the second adjustment signal required in the working stage.

[0140] Refer to Table 3 below. Table 3 is a specific adjustment example 3:

[0141]

[0142]

[0143] At this time, the first adjustment signal T1 is the average value of A1 and A3; the second adjustment signal T2 is the average value of A2 and A4.

[0144] It should be noted that the features disclosed in the mismatch correction method provided in the above embodiments can be arbitrarily combined without conflict to obtain new embodiments of the mismatch correction method.

[0145] Another embodiment of the present disclosure provides a memory, which uses the comparator circuit provided in the above embodiment for data input to eliminate the mismatch between two input transistors of a differential structure, thereby improving the performance of the memory.

[0146] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip complies with the DDR2 memory specification.

[0147] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip complies with the DDR3 memory specification.

[0148] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip complies with the DDR4 memory specification.

[0149] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip complies with the DDR5 memory specification.

[0150] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. A comparator circuit, characterized in that, it includes: A first transistor, one terminal is coupled to a first node, the other terminal is coupled to a first control node, and the gate is used to receive a first control signal; A second transistor, one terminal is coupled to the first node, the other terminal is coupled to a second control node, and the gate is used to receive a second control signal; The first transistor and the second transistor have the same transistor doping type; A load unit, one end is coupled to a second node, the other end is coupled to the first control node and the second control node, and is configured to adjust the level of the second control node based on the level of the first control node, or adjust the level of the first control node based on the level of the second control node. Among the first control node and the second control node, the regulated node is used to output an output signal; Among the first node and the second node, one is used to receive a high level and the other is used to receive a low level; A first adjustment circuit, one end is coupled to the first node, the other end is coupled to the first control node, and is used to adjust the node potential of the first control node after the first transistor is turned on based on the first control signal according to a first adjustment signal; A second adjustment circuit, one end is coupled to the first node, the other end is coupled to the second control node, and is used to adjust the node potential of the second control node after the second transistor is turned on based on the second control signal according to a second adjustment signal; The first adjustment signal and the second adjustment signal are used to adjust the mismatch between the first transistor and the second transistor; A calibration control circuit, used to provide the first adjustment signal and the second adjustment signal; The calibration control circuit includes: A clock module, used to receive a calibration enable signal and generate a calibration clock based on the calibration enable signal, and the calibration enable signal is provided in the calibration stage; A first calibration module, coupled to the clock module, initially sets the first adjustment signal to a maximum value, the second adjustment signal to a minimum value, provides the first adjustment signal and the second adjustment signal, and gradually reduces the first adjustment signal and increases the second adjustment signal based on the calibration clock; A judgment module, used to receive the output signals corresponding to different first adjustment signals and second adjustment signals, and obtain the first adjustment signal and the second adjustment signal corresponding to the first time node when the potential of the output signal flips; A storage module, coupled to the judgment module, used to obtain the first adjustment signal and the second adjustment signal corresponding to the first time node, and provide the first adjustment signal and the second adjustment signal corresponding to the first time node in the working stage.

2. The comparator circuit according to claim 1, characterized in that, it includes: The first adjustment circuit includes: a first adjustment transistor, one terminal is coupled to the first node, the other terminal is coupled to the first control node, and the gate is used to receive the first adjustment signal; The first adjustment transistor is configured to adjust the magnitude of the source-drain current based on the first adjustment signal; The second adjustment circuit includes: a second adjustment transistor, one terminal of which is coupled to the first node, the other terminal of which is coupled to the second control node, and the gate of which is configured to receive the second adjustment signal; The second adjustment transistor is configured to adjust the magnitude of the source-drain current based on the first adjustment signal.

3. The comparator circuit according to claim 1, wherein, it includes: The first adjustment circuit includes: a first adjustment transistor group, and the first adjustment transistor group includes: x first adjustment transistors; Wherein, one terminal of the x first adjustment transistors is coupled to the first node, the other terminal of which is coupled to the first control node, and the gate of which is configured to receive the first adjustment signal, and the first adjustment signal is used to selectively turn on the first adjustment transistor; The second adjustment circuit includes: a second adjustment transistor group, and the second adjustment transistor group includes: x second adjustment transistors; Wherein, one terminal of the x second adjustment transistors is coupled to the first node, the other terminal of which is coupled to the second control node, and the gate of which is configured to receive the second adjustment signal, and the second adjustment signal is used to selectively turn on the second adjustment transistor; The x is an integer greater than or equal to 2.

4. The comparator circuit according to claim 3, wherein, The source-drain conduction capabilities of the x first adjustment transistors after being turned on based on the same gate voltage are the same, and the source-drain conduction capabilities of the x second adjustment transistors after being turned on based on the same gate voltage are the same.

5. The comparator circuit according to claim 3, wherein, Among the x first adjustment transistors, after being turned on based on the same gate voltage, the source-drain conduction capability of the nth first adjustment transistor is twice that of the (n - 1)th first adjustment transistor; among the x second adjustment transistors, after being turned on based on the same gate voltage, the source-drain conduction capability of the nth second adjustment transistor is twice that of the (n - 1)th second adjustment transistor, where n is any integer less than or equal to x and greater than or equal to 2.

6. The comparator circuit according to claim 1, wherein, it further includes: A switching MOS transistor, one terminal of which is configured to be coupled to a power supply node or a ground node, the other terminal of which is coupled to the first node, and the gate of which is configured to receive a switching enable signal; Wherein, if the first node is configured to receive the high level, the switching MOS transistor is coupled to the power supply node, and if the first node is configured to receive the low level, the switching MOS transistor is coupled to the ground node; The switching MOS transistor has the same doping type as the first transistor.

7. The comparator circuit according to claim 1, wherein, it further includes: A first protection transistor, having the same type as the first transistor, one terminal of which is coupled to the first node, the other terminal of which is coupled to the first adjustment circuit, and the gate of which is configured to receive the first control signal; A second protection transistor, having the same type as the second transistor, one terminal of which is coupled to the first node, the other terminal of which is coupled to the second adjustment circuit, and the gate of which is configured to receive the second control signal.

8. The comparator circuit according to claim 1, wherein, the load unit includes: a third transistor, one terminal coupled to the second node and the other terminal coupled to the first control node; a fourth transistor, one terminal coupled to the second node and the other terminal coupled to the second control node; the gates of the third transistor and the fourth transistor are coupled and coupled to the first control node; wherein, the doping types of the third transistor and the fourth transistor are the same, and the doping types of the first transistor and the third transistor are different.

9. The comparator circuit according to claim 8, wherein, the first node is used to couple to a power supply node, the second node is used to couple to a ground node, the first transistor and the second transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors.

10. The comparator circuit according to claim 1, wherein, the calibration control circuit further includes: a second calibration module, coupled to the clock module, initially setting the first adjustment signal to a minimum value and the second adjustment signal to a maximum value, providing the first adjustment signal and the second adjustment signal, and gradually increasing the first adjustment signal and decreasing the second adjustment signal based on the calibration clock; the determination module is further configured to obtain the first adjustment signal and the second adjustment signal corresponding to the second time node when the output signal has a potential inversion; the storage module is further configured to obtain the first adjustment signal and the second adjustment signal corresponding to the second time node, and use the average value of the first adjustment signals corresponding to the first time node and the second time node as the first adjustment signal to be provided during the working stage, and use the average value of the second adjustment signals corresponding to the first time node and the second time node as the second adjustment signal to be provided during the working stage.

11. The comparator circuit according to claim 1, wherein, further includes: a first selection circuit, receiving an input selection signal, an input signal or a reference signal, for providing the first control signal; a second selection circuit, receiving the input selection signal, the input signal or the reference signal, for providing the second control signal; the first selection circuit is configured to select to provide the first control signal with the input signal or the reference signal based on the input selection signal; the second selection circuit is configured to select to provide the second control signal with the input signal or the reference signal based on the input selection signal.

12. A mismatch correction method, applied to the comparator circuit according to any one of claims 1 to 11, wherein, includes: during the calibration stage, controlling the inputs of the first control signal and the second control signal to be the same; initially setting the first adjustment signal to a maximum value and the second adjustment signal to a minimum value; successively decreasing the first adjustment signal and increasing the second adjustment signal, and obtaining output signals corresponding to different first adjustment signals and second adjustment signals; Obtain the first adjustment signal and the second adjustment signal corresponding to the first time node at which the output signal undergoes a potential flip; Use the first adjustment signal and the second adjustment signal corresponding to the first time node as the first adjustment signal and the second adjustment signal required to be provided during the working phase.

13. The mismatch correction method according to claim 12, characterized in that, after obtaining the first adjustment signal and the second adjustment signal corresponding to the first time node at which the output signal undergoes a potential flip, it further includes: Initially set the first adjustment signal to the minimum value and the second adjustment signal to the maximum value; Sequentially increase the first adjustment signal and decrease the second adjustment signal, and obtain the output signals corresponding to different first adjustment signals and second adjustment signals; Obtain the first adjustment signal and the second adjustment signal corresponding to the second time node at which the output signal undergoes a potential flip; The step of using the first adjustment signal and the second adjustment signal corresponding to the first time node as the first adjustment signal and the second adjustment signal required to be provided during the working phase includes: using the average value of the first adjustment signals corresponding to the first time node and the second time node as the first adjustment signal required to be provided during the working phase; using the average value of the second adjustment signals corresponding to the first time node and the second time node as the second adjustment signal required to be provided during the working phase.

14. A memory, characterized in that, The comparator circuit according to any one of claims 1 to 11 is applied for data input.

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