A real-time monitoring device for radiation dose in flash radiotherapy

Abstract

The application relates to a real-time monitoring device for irradiation dose of Flash radiotherapy, which comprises a host computer for initialization setting; an interactive algorithm unit in a data acquisition processing module is used for storing preset electric charge Q r transmitted by the host computer, and a trigger signal Trig-In parameter adjustment integral duration is configured and transmitted to a gain selection and control algorithm unit; the gain selection and control algorithm unit outputs a control signal according to current gain and integral duration; a super high dose detector converts detected particles into continuous current pulse signal output; a gain adjustable, dead time free dose monitoring front end processing circuit converts the current pulse signal output by the super high dose detector into a voltage signal and then outputs the voltage signal; a high speed analog-digital conversion circuit converts the voltage signal output by the front end processing circuit from an analog signal into a digital signal at high speed, and then transmits the digital signal to the data acquisition processing module to calculate current electric charge Q r After comparison, the on-off of the beam is controlled according to the comparison result.

Description

Technical Field

[0001] This invention relates to the field of medical particle radiotherapy equipment technology, and in particular to a real-time radiation dose monitoring device for Flash radiotherapy. Background Technology

[0002] Flash radiotherapy (Flash-RT) is a novel, non-invasive external beam radiation therapy technique based on the flash effect. It delivers ultra-high dose rates (approximately ≥40 Gy / s) of radiation over a short period (usually no more than 1 second) to effectively kill tumor cells while significantly reducing damage to surrounding healthy cells, thus achieving therapeutic effects. Due to the use of ultra-high doses for short-duration irradiation, the development of real-time dose monitoring and measurement systems with short-duration ultra-high dose rates is essential to ensure patient safety. Conventional irradiation dose monitoring systems suffer from low accuracy, slow response, poor reliability, limited measurement range, and lack of adjustability. These drawbacks increase the risks associated with Flash radiotherapy in clinical applications. Summary of the Invention

[0003] To address the aforementioned problems, the purpose of this invention is to provide a real-time radiation dose monitoring device for Flash radiotherapy, which can solve the problems of low accuracy, slow response speed, poor reliability, limited measurement range, and lack of adjustability in traditional radiation monitoring technologies.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: a real-time radiation dose monitoring device for Flash radiotherapy, comprising: a host computer for initialization settings, including a preset charge quantity Q. r The system also includes parameters for the Trig-In signal and displays the results; the data acquisition and processing module includes a gain selection and control algorithm unit, an integral area and correction algorithm unit, a numerical comparison algorithm unit, and an interactive algorithm unit; the interactive algorithm unit is used to store the preset charge Q transmitted from the host computer. rThe system adjusts the integration time according to the parameters of the Trig-In trigger signal configured by the host computer and transmits the data to the gain selection and control algorithm unit. The gain selection and control algorithm unit outputs a control signal based on the current gain and integration time. An ultra-high dose detector, installed in the Flash radiotherapy terminal, detects the dose and converts the detected particles into continuous current pulse signals. An adjustable-gain, dead-time-free dose monitoring front-end processing circuit converts the current pulse signal output from the ultra-high dose detector into a voltage signal and outputs it. It also adaptively selects the integration capacitor and integration time based on the current dose, and simultaneously... The selected gain level and integration time status information are uploaded to the host computer for display. A high-speed analog-to-digital converter (ADC) rapidly converts the voltage signal output from the gain-adjustable, dead-time-free dose monitoring front-end processing circuit from an analog signal to a digital signal. This digital signal is then transmitted to the data acquisition and processing module, where it is aggregated and sent to the integration area and correction algorithm unit. This unit corrects the difference between the first and second integrators in the front-end processing circuit and calculates the current charge Q, which is then transmitted to the numerical comparison algorithm unit. Simultaneously, the Q value is uploaded to the host computer for display in real time. The numerical comparison algorithm unit compares the current charge Q with the preset charge Q transmitted by the interactive algorithm unit. r After comparison, the comparison results are uploaded to the host computer for display, and the beam current is controlled to switch on and off based on the comparison results.

[0005] Furthermore, the gain-adjustable, dead-time-free dose monitoring front-end processing circuit includes a first integrator and a second integrator with an integrating switch and a bleeder switch, an optocoupler isolator, a multiplexer, an FPGA control circuit, and an attenuation circuit.

[0006] Input current signal I in After entering the front-end processing circuit, they simultaneously pass through the high-speed integrating switch S. A and integral switch S B The input is fed to the first integrator and the second integrator. The alternating operation of the first integrator and the second integrator is achieved through four control signals from the FPGA; the first integrator operation control signal S... WHA First integrator discharge control signal S WRA Second integrator operating control signal S WHB Second integrator discharge control signal S WRB All control of the integrator switches is achieved through optocoupler isolators; the outputs of the two integrators are connected to the inputs of the multiplexer, the control signal CH_AB of the multiplexer comes from the FPGA control circuit, and the output of the multiplexer is connected to the input of the attenuator to attenuate the voltage signal output by the integrator before output.

[0007] Furthermore, the FPGA controls the operation of the two integrators through four control signals, including:

[0008] After power-on and input connection, the FPGA controls the integral switch signal S. WHA Setting it low causes the first integrator to begin integrating and controls the output V. out The output V of the second integrator b The amplitude is transferred to the attenuator circuit;

[0009] The data acquisition and processing module collects the output V of the second integrator. b After the acquisition time is reached, the FPGA controls the second integrator to release the bleed switch signal S. WRB Setting it low causes the second integrator to begin discharging;

[0010] After the second integrator finishes discharging, the FPGA controls the second integrator discharge switch signal S. WRB Pull up the first integrator integral switch signal S WHA Pull up the signal, and at the same time, adjust the integration switch signal S of the second integrator. WHB Setting the integrator low causes the second integrator to begin integration, and V is controlled via the CH_AB signal. out The output is V a The amplitude is transferred to the attenuator circuit;

[0011] The data acquisition and processing module collects the output V of the first integrator. a After the acquisition time is reached, the FPGA controls the first integrator to release the bleed switch signal S. WRA Setting it low causes the second integrator to start discharging, thus operating in a ping-pong manner to monitor the input current without dead time.

[0012] Furthermore, once operation begins, the input current changes in real time. Assume the preset gain is equal to that of the discharge switch S. RA1 and S RA2 When the output amplitude of the current gain level is detected to be smaller than the expected output amplitude, the FPGA control disconnects S. RA2 When the output amplitude of the current gain setting is detected to be larger than the expected output amplitude, the FPGA controls the closing of S based on the amplitude magnitude. RA3 To S RAi One or more of them can be used to match the current gain, enabling adaptive gain switching based on the input current.

[0013] Furthermore, the attenuation circuit adopts a T-type attenuation circuit.

[0014] Furthermore, the high-speed analog-to-digital conversion circuit is constructed using high-speed ADC devices and peripheral circuitry, with the Trig-Out acquisition trigger signal and the sampling clock Sclk provided by the FPGA.

[0015] Furthermore, the charge quantity is calculated by summing the data from M sampling points:

[0016]

[0017] In the formula, V oi The output voltage is denoted by C, where C is the current value of the integrating capacitor, and Q is the charge quantity.

[0018] The present invention has the following advantages due to the adoption of the above technical solutions:

[0019] This invention solves the problems of low accuracy, slow response speed, poor reliability, limited measurement range and non-adjustability of traditional irradiation monitoring technology, and can provide a new high-precision and rapid measurement scheme for ultra-high dose monitoring of Flash radiotherapy. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall structure of the real-time radiation dose monitoring device in an embodiment of the present invention;

[0021] Figure 2 This is a detailed structural block diagram of the real-time radiation dose monitoring device in an embodiment of the present invention;

[0022] Figure 3 This is a circuit diagram of the gain-adjustable, dead-time-free dose monitoring front-end processing circuit in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of the attenuation circuit in an embodiment of the present invention. Detailed Implementation

[0024] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0026] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0027] To address the problems of low accuracy, slow response, poor reliability, limited and non-adjustable measurement range in traditional irradiation monitoring technologies, this invention provides a real-time irradiation dose monitoring device for Flash radiotherapy. The device includes an ultra-high dose detector, a gain-adjustable, dead-time-free dose monitoring front-end processing circuit, a high-speed analog-to-digital converter (ADC), and a data acquisition and processing module. The ultra-high dose detector outputs a continuous current pulse signal, which is converted into a voltage signal by the gain-adjustable, dead-time-free dose monitoring front-end processing circuit. The high-speed ADC performs high-speed digitization on this signal and sends the processed signal to the data acquisition and processing module. The FPGA in the data acquisition and processing module sends control signals to control the high-speed ADC and the front-end processing circuit. The data acquisition and processing module includes an FPGA-based front-end processing circuit gain selection algorithm, a front-end processing circuit control algorithm, an integration area and correction algorithm, a numerical comparison algorithm, and some interaction algorithms with the beam terminal and host computer software. It performs data acquisition and processing on the input signal, completes data transmission with the high-speed ADC, and finally summarizes the data in the integration area algorithm unit to calculate the charge Q, which is then compared with the system's preset charge Q. r The beam is then controlled after comparison to ensure the accuracy of the irradiation dose.

[0028] In one embodiment of the present invention, a real-time radiation dose monitoring device for Flash radiotherapy is provided. In this embodiment, as... Figure 1 , Figure 2 As shown, the device includes:

[0029] The host computer is used for initialization settings, including the preset dose (charge amount) Q. r The system displays parameters such as the frequency and pulse width of the Trig-In trigger signal, and shows the corresponding results.

[0030] The data acquisition and processing module includes a gain selection and control algorithm unit, an integral area and correction algorithm unit, a numerical comparison algorithm unit, and an interactive algorithm unit; the interactive algorithm unit is used to store the preset charge Q transmitted from the host computer. r The integration time is adjusted according to parameters such as the frequency of the Trig-In trigger signal configured by the host computer, and transmitted to the gain selection and control algorithm unit. The gain selection and control algorithm unit outputs a control signal according to the current gain and integration time. The control signal includes a signal for controlling the operation of the integrator in the front-end processing circuit and a signal for opening and closing the bleeder switch.

[0031] An ultra-high dose detector is installed in the Flash radiotherapy terminal to detect the dose and convert the detected particles into a continuous current pulse signal output, which is proportional to the intensity of the beam.

[0032] The gain-adjustable, dead-time-free dose monitoring front-end processing circuit converts the current pulse signal output by the ultra-high dose detector into a voltage signal and outputs it. It also adaptively selects the integrating capacitor and integration time according to the current dose, and uploads the status information such as the currently selected gain level and integration time to the host computer for display.

[0033] A high-speed analog-to-digital converter circuit rapidly converts the voltage signal output from the gain-adjustable, dead-time-free dose monitoring front-end processing circuit from an analog signal into a digital signal. This digital signal is then transmitted to the data acquisition and processing module, where it is aggregated and sent to the integration area and correction algorithm unit. This unit corrects the difference between the current first integrator A and the second integrator B in the front-end processing circuit and calculates the current charge Q. This result is then transmitted to the numerical comparison algorithm unit, which simultaneously uploads the Q value to the host computer for display in real time. The numerical comparison algorithm unit compares the current charge Q with the preset charge Q transmitted from the interactive algorithm unit. r After comparison, the comparison results are uploaded to the host computer for display, and the beam current is controlled according to the comparison results to achieve safe and reliable dose control.

[0034] Specifically, in this embodiment, the beam on / off state is controlled based on the comparison result as follows: if the current charge Q is greater than or equal to the preset charge Q... r When Q is reached, the data acquisition and processing module sends a control signal to stop the beam; when Q is reached... r Do not take action at this time.

[0035] In the above embodiments, the ultra-high dose detector can be a common ultra-high dose detector, such as an integrating ionization chamber.

[0036] In the above embodiments, the gain-adjustable, dead-time-free dose monitoring front-end processing circuit includes a first integrator A and a second integrator B with an integrating switch and a bleeder switch, an optocoupler isolator, a multiplexer, an FPGA control circuit, and an attenuation circuit.

[0037] Input current signal I in After entering the front-end processing circuit, they simultaneously pass through the high-speed integrating switch S. A and integral switch S B The input is fed to the first integrator A and the second integrator B. After starting operation, the front-end processing circuit matches the integrators with different sizes of integrating capacitors and integration times according to different input current signals, thereby achieving different gain adjustments. The alternating operation of the first integrator A and the second integrator B is achieved through four control signals from the FPGA; the operating control signal S for the first integrator A is... WHA First integrator A discharges control signal S WRA The second integrator B's operating control signal S WHB Second integrator B discharges control signal S WRB ​All control of the integrator switches is achieved through optocoupler isolators. The outputs of the two integrators are connected to the inputs of a multiplexer. The control signal CH_AB of the multiplexer also comes from the FPGA control circuit. The output of the multiplexer is connected to the input of an attenuator to attenuate the voltage signal output by the integrator before outputting it, facilitating data acquisition and processing by the back-end data acquisition and processing module.

[0038] In this embodiment, the gain-adjustable, dead-time-free dose monitoring front-end processing circuit can achieve gain-adjustable, dead-time-free current-to-voltage signal conversion by selecting and configuring different integrating capacitors, modifying the integration time, and using the ping-pong operation of the dual integrators, thereby improving conversion accuracy and efficiency.

[0039] In this embodiment, the preferred block diagram of the gain-adjustable, dead-time-free dose monitoring front-end processing circuit is as follows: Figure 3 As shown. The integrator with integration and discharge switch functions consists of an operational amplifier and an adjustable integrating capacitor bank C. i (Built-in or external), Integral switch S A / B and discharge switch S RA / Bi Composition. The integrating switch S of the first integrator A. A Located at the inverting input terminal of the first operational amplifier 1, with the non-inverting input terminal of the first operational amplifier 1 grounded, the adjustable integrating capacitor bank C i The bleed switch S is connected across the inverting input and output of the first operational amplifier 1. RAi With integrating capacitor C i When connected in parallel, the output terminal of the first operational amplifier 1 outputs a voltage signal V. a The integrating switch S of the second integrator B B Located at the inverting input terminal of the second operational amplifier 2, with the non-inverting input terminal of the second operational amplifier 2 grounded, the adjustable integrating capacitor bank C i The bleed switch S is connected across the inverting input and output of the second operational amplifier 2. RAi With integrating capacitor C bi When connected in parallel, the output terminal of the second operational amplifier 2 outputs a voltage signal V. b The output signal V of the first integrator A and the second integrator B a and V b Connected to a multiplexer, the multiplexer's output V out Connect to the input section of the attenuation circuit.

[0040] The attenuation circuit uses a T-type attenuation circuit, such as... Figure 4 As shown. The calculation method for each resistance value in the circuit is shown in the following formula:

[0041]

[0042] In the formula, Rc is the circuit impedance matching resistance value, and N is the attenuation factor.

[0043] The FPGA controls the operation of two integrators through four control signals, as follows:

[0044] 1) After power-on and input connection, the FPGA controls the integral switch signal S. WHA Setting the signal low (assuming the signal is active low) causes the first integrator A to begin integrating, and controls V... out The output is V b The amplitude is transferred to the attenuator circuit.

[0045] 2) The data acquisition and processing module collects the output V of the second integrator B. b After the acquisition time is reached, the FPGA controls the second integrator B to discharge the bleed switch signal S. WRB Setting it low (assuming the signal is active low) causes the second integrator B to start discharging, and the discharging time is determined by the performance of the integrator device itself.

[0046] 3) After the second integrator B finishes discharging, the FPGA controls the second integrator B to discharge the switch signal S. WRB Pull-up (assuming the signal is active low), first integrator A integrating switch signal S WHA Pull the signal high (assuming the signal is active low), and simultaneously, switch the integration signal S of the second integrator B. WHB Setting the integrator low (assuming the signal is active low) causes the second integrator B to begin integration, and controls V via the CH_AB signal. out The output is V a The amplitude is transferred to the attenuator circuit.

[0047] 4) The data acquisition and processing module collects the output V of the first integrator A. a After the acquisition time is reached, the FPGA controls the first integrator A to discharge the switch signal S. WRA Setting it low (assuming the signal is active low) causes the second integrator B to start discharging. The discharging time is determined by the performance of the integrator itself. By operating in a ping-pong manner, the input current can be monitored without dead time.

[0048] In the above steps, the input current changes in real time after the device starts working. Assume the preset gain is the discharge switch S. RA1 and S RA2 When the output amplitude of the current gain level is detected to be smaller than the expected output amplitude, the FPGA control disconnects S. RA2 When the output amplitude of the current gain setting is detected to be larger than the expected output amplitude, the FPGA controls the closing of S based on the amplitude magnitude. RA3 or S RA4 …S RAiOne or more of them are matched to the current gain to achieve adaptive gain switching based on the input current.

[0049] In the above embodiments, the high-speed analog-to-digital conversion circuit is constructed using a high-speed ADC device and peripheral circuitry. The Trig-Out acquisition trigger signal and the sampling clock Sclk are provided by the FPGA. In this embodiment, preferably, a 16-bit ADC device with a sampling rate of 200MHz or higher is used.

[0050] In the above embodiments, the gain selection and control algorithm unit in the data acquisition and processing module mainly matches the corresponding integrating capacitor and integrating time according to the input current range, and sends control signals to control the integrating switch, bleeder switch and output circuit. During operation, the front-end processing circuit supports adaptive gain switching based on the current input current and displays the current gain level and integrating time to the host computer through an interactive algorithm. The signal processed by the high-speed analog-to-digital converter is first sent to the FPGA integrating area and correction algorithm unit for calculation. The ADC sampling data related to the integrating area calculation and correction is temporarily stored in FIFO. After the acquisition is completed, the high and low levels of the trigger signal Trig-In are used to determine whether the currently acquired data comes from the first integrator A or the second integrator B. The difference in the output amplitude range of the two integrators is compared, one channel is calibrated, and a linear relationship is obtained. Then, the channel difference is compensated and corrected. After the integrating area and correction algorithm unit processes the data, it obtains the current charge Q and uploads it (or dose data) to the host computer for display in real time. The charge is calculated by summing the data of M sampling points. The calculation formula is as follows:

[0051]

[0052] In the formula, V oi C is the output voltage during a single sampling time, and C is the current value of the integrating capacitor.

[0053] The numerical comparison algorithm unit compares the total charge Q calculated by the integral area algorithm unit with the preset charge Q. r The comparison process involves no operation within a preset safety range, and if the range is exceeded, the FPGA immediately sends a control signal to the beam terminal to stop the beam. Before Flash radiotherapy begins, the entire device needs to be initialized and configured. This mainly involves the host computer sending the relevant Trig-In parameters and preset dose values ​​to the FPGA. The FPGA controls the gain switching of the front-end circuit based on the dose values ​​and stores the preset dose values ​​for comparison by the numerical comparison algorithm unit.

[0054] In summary, during use, the host computer sets the frequency, pulse width, and other parameters of the trigger signal Trig-In according to the current preset charge amount and sends them to the data acquisition and processing module. These parameters reflect the gain level, integration time, and input current range. The data acquisition and processing module sends the trigger signal Trig-In according to the host computer configuration, and the acquisition trigger signal Trig-Out simultaneously goes high. After a delay, the acquisition clock Sclk goes high. Upon receiving the acquisition trigger signal Trig-Out and the acquisition clock Sclk, the ADC begins acquiring the output signal V from the front-end processing circuit. out The data acquisition duration can be set via FPGA. When Trig-In is high, the acquired data is from integrator B; when Trig-In is low, the acquired data is from integrator A. The data acquisition and processing module compares the acquired data from integrator A and integrator B. If there is a difference in amplitude exceeding one order of magnitude, one channel is calibrated and a linear relationship is fitted for correction. Finally, the data is processed by an integration area and correction algorithm to obtain the charge Q, which is displayed to the host computer in real time. After further processing by a numerical comparison algorithm, the result is also displayed to the host computer. When the charge Q is greater than the preset charge Q, the data acquisition is considered complete. r It sends a control signal to the beam control system to stop the beam.

[0055] The monitoring device of the present invention can monitor and process signals with an input range of seven orders of magnitude (±10fC to ±10uC), with a minimum dose resolution of 0.04fC. The device has high precision, adjustable measurement range, and high detection efficiency, providing a guarantee for ultra-high dose irradiation monitoring and greatly improving its reliability and timeliness.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A real-time radiation dose monitoring device for Flash radiotherapy, characterized in that, include: The host computer is used for initialization settings, including the preset charge amount Q. r The parameters of the Trig-In trigger signal are displayed. The data acquisition and processing module includes a gain selection and control algorithm unit, an integral area and correction algorithm unit, a numerical comparison algorithm unit, and an interactive algorithm unit; the interactive algorithm unit is used to store the preset charge Q transmitted from the host computer. r The system adjusts the integration duration according to the parameters of the Trig-In trigger signal configured by the host computer and transmits the data to the gain selection and control algorithm unit; the gain selection and control algorithm unit outputs a control signal according to the current gain and integration duration. An ultra-high dose detector is installed in the Flash radiotherapy terminal to detect the dose and convert the detected particles into a continuous current pulse signal output. The gain-adjustable, dead-time-free dose monitoring front-end processing circuit converts the current pulse signal output by the ultra-high dose detector into a voltage signal and outputs it. It also adaptively selects the integrating capacitor and integration time according to the current dose, and uploads the current selected gain level and integration time status information to the host computer for display. A high-speed analog-to-digital converter circuit rapidly converts the voltage signal output from the gain-adjustable, dead-time-free dose monitoring front-end processing circuit from an analog signal into a digital signal. This digital signal is then transmitted to the data acquisition and processing module, where it is aggregated and sent to the integration area and correction algorithm unit. This unit corrects the difference between the first and second integrators in the front-end processing circuit and calculates the current charge quantity Q. This result is then transmitted to the numerical comparison algorithm unit, which simultaneously uploads the Q value to the host computer for display in real time. The numerical comparison algorithm unit compares the current charge quantity Q with the preset charge quantity Q transmitted from the interactive algorithm unit. r After comparison, the comparison results are uploaded to the host computer for display, and the beam current is controlled according to the comparison results; The gain-adjustable, dead-time-free dose monitoring front-end processing circuit includes a first integrator and a second integrator with integrating and bleed switches, an optocoupler isolator, a multiplexer, an FPGA control circuit, and an attenuation circuit; the input current signal I... in After entering the front-end processing circuit, they simultaneously pass through the high-speed integrating switch S. A and integral switch S B The input is fed to the first integrator and the second integrator. The alternating operation of the first integrator and the second integrator is achieved through four control signals from the FPGA; the first integrator operation control signal S... WHA First integrator discharge control signal S WRA Second integrator operating control signal S WHB Second integrator discharge control signal S WRB All control of the integrator switches is achieved through optocoupler isolators; the outputs of the two integrators are connected to the input of the multiplexer, the control signal CH_AB of the multiplexer comes from the FPGA control circuit, and the output of the multiplexer is connected to the input of the attenuator to attenuate the voltage signal output by the integrator before output; The FPGA controls the operation of two integrators through four control signals, including: after power-on and input connection, the FPGA controls the integrator switch signal S. WHA Setting it low causes the first integrator to begin integrating and controls the output V. out The output V of the second integrator b The amplitude is transferred to the attenuator circuit; the data acquisition and processing module collects the output V of the second integrator. b After the acquisition time is reached, the FPGA controls the second integrator to release the bleed switch signal S. WRB Setting the signal low causes the second integrator to begin discharging; once the second integrator has finished discharging, the FPGA controls the second integrator discharging switch signal S. WRB Pull up the first integrator integral switch signal S WHA Pull up the signal, and at the same time, adjust the integration switch signal S of the second integrator. WHB Setting it low causes the second integrator to begin integration, and V is controlled via the CH_AB signal. out The output is V a The amplitude is transferred to the attenuator circuit; the data acquisition and processing module collects the output V of the first integrator. a After the acquisition time is reached, the FPGA controls the first integrator to release the bleed switch signal S. WRA Setting it low causes the first integrator to start discharging, thus operating in a ping-pong manner to monitor the input current without dead time. Once operation begins, the input current changes in real time. Assume the preset gain is equal to that of the discharge switch S. RA1 and S RA2 When the output amplitude of the current gain level is detected to be smaller than the expected output amplitude, the FPGA control disconnects S. RA2 When the output amplitude of the current gain setting is detected to be larger than the expected output amplitude, the FPGA controls the closing of S based on the amplitude magnitude. RA3 To S RAi One or more of them can be selected to match the current gain, thereby achieving adaptive gain switching based on the input current. The charge is calculated by summing the data from M sampling points: In the formula, V oi Where C is the output voltage within a single sampling time, and C is the current value of the integrating capacitor. This represents the amount of electric charge.

2. The real-time radiation dose monitoring device for Flash radiotherapy as described in claim 1, characterized in that, The attenuation circuit adopts a T-type attenuation circuit.

3. The real-time radiation dose monitoring device for Flash radiotherapy as described in claim 1, characterized in that, The high-speed analog-to-digital conversion circuit is composed of high-speed ADC devices and peripheral circuits. The acquisition trigger signal Trig-Out and sampling clock Sclk are provided by the FPGA.

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