A deep silicon etching method and apparatus

Abstract

The application discloses a deep silicon etching method and equipment, and belongs to the technical field of semiconductors. The method comprises the following steps: a, using etching gas to etch the wafer, and discharging reaction gas; b, introducing high-fluorine-content etching gas to etch, closing the back helium cooling system, and increasing the wafer temperature; isotropically etching the sidewall, and discharging reaction gas; c, introducing C4F8 gas and ionizing the same, depositing a polytetrafluoroethylene passivation layer, and discharging reaction gas; d, introducing etching gas SF6, and working the back helium cooling system at full power; anisotropically etching, and discharging reaction gas; e, selectively isotropically etching SiO2, and releasing the structure. The method directly deposits a polytetrafluoroethylene release layer in the passivation layer forming process in deep silicon etching, not only can simplify the process steps, but also effectively avoids the adsorption and adhesion failure after structure release in the traditional process flow.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a deep silicon etching method and equipment. BACKGROUND

[0002] In recent years, with the development of microelectronic technology, MEMS (Micro-Electro-Mechanical System) has been highly valued by governments and scientists in developed countries. Among them, the deep silicon etching technology is a key process for realizing MEMS. It uses a mixed gas containing C and F as the etching gas. By adjusting the atomic ratio of C / F, the etching and deposition effects in the process can be controlled. Through optimization, a silicon etching effect with a large aspect ratio can be achieved. The deep silicon structures such as through silicon vias and trench gates formed by the deep silicon etching method can significantly improve the performance of the device, reduce the power consumption and volume of the device. The comb transducer or mems switch is a typical mems device. The movable and relatively close capacitive structure is prone to attract and stick together during the release of the structure by traditional process, resulting in device failure.

[0003] Taking the comb transducer as an example, the comb transducer is an important device in MEMS devices and is widely used in devices such as accelerometers and gyroscopes. As shown in Figure 1 , the main process flow of the traditional deep silicon etching method of the comb transducer usually starts from an SOI silicon wafer (a), forms a comb-tooth structure (b) by lithography and deep silicon etching method, uses the buried oxide layer (BOX) as a stop layer, then uses a buffered hydrofluoric acid solution or gaseous hydrofluoric acid to etch the buried oxide layer, and finally completes the release of the structure (c). After the release of the structure of the comb transducer, a large capacitance is formed between the comb teeth. By applying a voltage between the comb teeth, an electrostatic attraction force (capacitive force) can be generated to drive the comb transducer to move. However, when the driving voltage is greater than the threshold value or is subjected to an external force, as shown in Figure 2 , the comb transducer may attract together and cannot be separated, resulting in failure of the comb transducer.

[0004] To solve the above problems, some existing technologies use MVD (molecular vapor deposition) technology to deposit a layer of polytetrafluoroethylene anti-sticking coating on the sidewall of the structure of the typical MEMS device such as the comb transducer after the structure is formed, to prevent the occurrence of the attraction and sticking failure as shown in Figure 2 . However, this still cannot avoid the attraction and sticking failure that occurs after the structure is released in the traditional process flow, resulting in a low yield of the device. SUMMARY

[0005] In order to overcome the deficiencies of the prior art, one of the purposes of the present application is to provide a deep silicon etching method which is simple in process, can effectively avoid device suction adhesion failure and improve device yield.

[0006] To solve the above problems, the technical scheme adopted by the present application is as follows:

[0007] A deep silicon etching method, comprising the following steps:

[0008] a. Deep silicon etching of a wafer is carried out by using an etching gas containing a fluorocarbon C x F y , so that the etching reaction and deposition reaction occur simultaneously during the reaction process, and a residual passivation layer is left on the sidewall after etching is completed, and the reaction gas is discharged;

[0009] b. High-fluorine-content etching gas is introduced to make the etching reaction reach the optimal level, and at the same time, the controller is used to close the back helium cooling system to increase the temperature of the wafer, so as to accelerate the etching of the sidewall passivation layer; isotropic etching is carried out on the sidewall to remove the passivation layer on the sidewall, and the reaction gas is discharged;

[0010] c. C4F8 gas is introduced, and the C4F8 gas is ionized by ICP to deposit a polytetrafluoroethylene anti-sticking layer on the surface of the device, and the reaction gas is discharged;

[0011] d. High-fluorine-content etching gas is introduced, the back helium cooling system is opened by the controller and works at full power to avoid the temperature of the wafer from rising, so as to reduce the erosion of the sidewall anti-sticking layer; anisotropic etching is carried out to remove the anti-sticking layer of SiO2, and the reaction gas is discharged;

[0012] e. Selective isotropic etching of SiO2 is carried out by using buffered hydrofluoric acid or gaseous hydrogen fluoride to release the device structure.

[0013] As a preferred embodiment of the present application, the fluorocarbon C x F y in step a has a fluorocarbon ratio y / x>1.

[0014] As a preferred embodiment of the present application, the etching gas in step a comprises C x F y gas and O2, and the mixing ratio of C x F y gas to O2 is 50-100%:0-50%; preferably 70%:30%.

[0015] As a preferred embodiment of the present application, the vacuum degree in step a is ≤200mTorr, and the RF power is ≥5000W.

[0016] As a preferred embodiment of the present application, the high fluorine content etching gas in steps b and d is SF6 or C x F y , and C x F y The ratio of fluorocarbon to carbon y / x in F is > 2; C x F y Preferably, CF4 or C2F6.

[0017] As a preferred embodiment of the present application, the wafer temperature in step b is > 80℃.

[0018] As a preferred embodiment of the present application, the pulling power of the isotropic etching in step b is < 100w.

[0019] As a preferred embodiment of the present application, the RF power in step c is < 2000w, and the bias power is 0.

[0020] As a preferred embodiment of the present application, the RF power in step d is > 1200W, and the bias power is > 200W.

[0021] The present application also provides a deep silicon etching device, which comprises a controller configured to perform the method as described above.

[0022] Compared with the prior art, the present application has the following beneficial effects:

[0023] The present application forms a polytetrafluoroethylene anti-sticking layer directly on the sidewall during the passivation layer formation process of deep silicon etching, which not only effectively prevents the occurrence of failure caused by suction adhesion, but also greatly simplifies the process steps: the present application completes the deposition of the anti-sticking layer in one step in the deep silicon etching method, while the traditional method needs to send the wafer into an additional MVD device for deposition after completing deep silicon etching and structure release, so the method of the present application effectively simplifies the process steps and reduces the production cost compared with the traditional method. In addition, since the method of the present application forms the anti-sticking layer first and then performs the structure release process, it effectively avoids the suction adhesion failure that occurs after the structure release in the traditional process flow, greatly improving the process yield. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a process flow chart of a comb transducer in the prior art; wherein (a) is an SOI silicon wafer provided with a buried oxide layer, (b) is a comb-shaped structure formed by deep silicon etching, and (c) is a comb transducer after etching of the buried oxide layer;

[0025] Figure 2 is a structural schematic diagram of suction adhesion failure of a comb transducer;

[0026] Figure 3Process flow chart of the deep silicon etching method of the present application; wherein (a) is SOI silicon wafer with buried oxide layer, (b) is comb-shaped structure formed by deep silicon etching, with passivation layer remaining on the sidewall, (c) is comb-shaped transducer after sidewall passivation layer is etched, (d) is comb-shaped transducer with polytetrafluoroethylene anti-sticking layer deposited on the sidewall and SiO2, (e) is comb-shaped transducer with polytetrafluoroethylene anti-sticking layer on SiO2 etched away, (e) is comb-shaped transducer with buried oxide layer etched away;

[0027] Figure 4 Wafer topography obtained after step a etching of the embodiment 1 of the present application. DETAILED DESCRIPTION

[0028] The present application will be further described in conjunction with the drawings and specific embodiments.

[0029] As shown in the drawings, Figure 3 the deep silicon etching method provided by the present application comprises the following steps:

[0030] a. Deep silicon etching of the wafer is performed using etching gas containing fluorocarbon C x F y so that etching reaction and deposition reaction occur simultaneously during the reaction process, the vacuum degree is ≤200 mTorr, and the RF power is ≥5000 W, to ensure the verticality and aspect ratio of etching; after the etching is completed, the sidewall is left with residual passivation layer (b), and the reaction gas is discharged; wherein the fluorocarbon C x F y has a fluorocarbon ratio y / x > 1, so that the etching reaction is greater than the deposition reaction. The etching gas includes C x F y gas and O2, and the mixing ratio of C x F y gas to O2 is 50-100%:0-50%; preferably 70%:30%; the C x F y gas is preferably C3F8.

[0031] b. High fluorine content etching gas is introduced to make the etching reaction reach the best level, and at the same time, the controller is used to close the back helium cooling system (slowly reduce until closed) to raise the wafer temperature and the wafer temperature > 100℃, to accelerate the etching of the sidewall passivation layer; isotropic etching of the sidewall is performed at a pulling power <100 w to remove the passivation layer of the sidewall, and the reaction gas is discharged;

[0032] c. Introducing C4F8 gas and ionizing the C4F8 gas by ICP, RF power < 2000w, bias power 0, depositing polytetrafluoroethylene anti-sticking layer on the surface of the device, and discharging the reaction gas; wherein the C4F8 gas has a very low fluorocarbon ratio, which can ensure that the deposition reaction is greater than the etching reaction.

[0033] d. Introducing high fluorine content etching gas, turning on the radio frequency coil, RF power > 1200W, bias power > 200W, turning on the back helium cooling system by the controller and making it work at full power, and trying to ensure that the wafer temperature does not rise, so as to reduce the erosion of the side wall anti-sticking layer; anisotropic etching is carried out under the above parameters to remove the anti-sticking layer on the surface of SiO2, and the anti-sticking layer on the side wall is protected as much as possible, and the reaction gas is discharged;

[0034] e. Selective isotropic etching of SiO2 using buffered hydrofluoric acid or gaseous hydrogen fluoride to release the device structure. The buffered hydrofluoric acid solution is a BHF solution diluted by 1.1:10.

[0035] In the above method, the high fluorine content etching gas in steps b and d is SF6 or C x F y , and the fluorocarbon ratio y / x in C x F y > 2; C x F y is preferably CF4 or C2F6.

[0036] In the above method, during the etching process of step a, a layer of passivation layer is left on the side wall, but due to different process parameters, the composition, thickness and uniformity of the passivation layer are different. Therefore, after the etching of step a is completed, isotropic etching is needed again to ensure that the residual passivation layer on the side wall is completely removed, providing a basis for the subsequent deposition process of step c. Only deposition gas is introduced, and no etching gas is introduced, to ensure that a polytetrafluoroethylene anti-sticking layer with uniform thickness is formed. However, due to the formation of the polytetrafluoroethylene anti-sticking layer on the bottom during the deposition process, the subsequent process cannot be carried out, so the bottom SiO2 must be exposed by etching again, and in order not to damage the passivation layer on the side wall, anisotropic etching (step d) mainly by ion bombardment is carried out. After the SiO2 is exposed, the reactants can contact the SiO2 in the subsequent wet or gaseous release process, thereby completing the release of the structure (step e).

[0037] The application also provides a deep silicon etching device, which comprises a controller configured to perform the method as described above.

[0038] Example 1:

[0039] a. Deep silicon etching is performed on the wafer using 40sccm etching gas containing C3F8, so that the etching reaction and deposition reaction occur simultaneously during the reaction, and the etching reaction is greater than the deposition reaction, the vacuum degree is 100mTorr, and the RF power is 8000W, to ensure the verticality and aspect ratio of etching; after etching, the residual passivation layer (b) is left on the sidewall, and the reaction gas is discharged through a molecular pump or a vacuum pump; wherein the etching gas comprises C3F8 gas and O2, and the mixing ratio of C3F8 gas to O2 is 70%:30%.

[0040] Figure 4 The wafer topography after etching through step a of the present embodiment is shown in Figure 2. Figure 4 As can be seen, by controlling the O2 proportion in the etching gas and controlling the etching parameters, the aspect ratio of the etched trench can reach 3.52:1, and the sidewall verticality is close to 90 degrees.

[0041] b. 350sccm etching gas SF6 is introduced to make the etching reaction reach the best level, the radio frequency coil power is 1700W, and at the same time the controller is used to close the back helium cooling system (slowly reduce until closed) to make the wafer temperature rise and the wafer temperature >100℃, so as to speed up the etching of the passivation layer on the sidewall; the sidewall is isotropically etched at a pulling power of 75w to remove the passivation layer on the sidewall, and the reaction gas is discharged through a molecular pump or a vacuum pump.

[0042] c. 350sccm of C4F8 gas is introduced, and the C4F8 gas is ionized by ICP, the radio frequency coil power is 1600W, the bias power is 0, and a polytetrafluoroethylene release layer is deposited on the device surface, and the reaction gas is discharged through a molecular pump or a vacuum pump; wherein the C4F8 gas has a very low fluorocarbon ratio, which can ensure that the deposition reaction is greater than the etching reaction.

[0043] d. 350sccm of etching gas SF6 is introduced, the radio frequency coil is turned on, the RF power is 1700W, the bias power is 245W, the controller is used to open the back helium cooling system and make it work at full power, and the wafer temperature is as low as possible to reduce the erosion of the release layer on the sidewall; anisotropic etching is performed under the above parameters to remove the release layer on the surface of SiO2, and the release layer on the sidewall is protected as much as possible, and the reaction gas is discharged through a molecular pump or a vacuum pump;

[0044] e. The SiO2 is selectively isotropically etched for 1min using BHF solution diluted according to 1.1:10 to release the device structure.

[0045] Example 2:

[0046] a, the wafer is etched by using 50sccm etching gas containing C4F8, so that the etching reaction and the deposition reaction are carried out simultaneously in the reaction process, and the etching reaction is greater than the deposition reaction, the vacuum degree is 100mTorr, and the RF power is 7000W, so as to ensure the verticality and aspect ratio of etching; after the etching is completed, the residual passivation layer (b) is left on the sidewall, and the reaction gas is discharged through a molecular pump or a vacuum pump; wherein the etching gas comprises C4F8 gas and O2, and the mixing ratio of C4F8 gas and O2 is 80%:20%.

[0047] b, 350sccm etching gas C2F6 is introduced, so that the etching reaction reaches the best level, the radio frequency coil power is 1500W, and at the same time, the controller is used to close the back helium cooling system (slowly reduce until closed), so that the wafer temperature is increased and the wafer temperature is greater than 80 DEG C, so as to accelerate the etching of the passivation layer on the sidewall; the sidewall is isotropically etched by using a pulling power of 50w, so as to remove the passivation layer on the sidewall, and the reaction gas is discharged through a molecular pump or a vacuum pump.

[0048] c, 350sccm C4F8 gas is introduced, and the C4F8 gas is ionized through ICP, the radio frequency coil power is 1600W, the bias power is 0, the polytetrafluoroethylene anti-sticking layer is deposited on the device surface, and the reaction gas is discharged through a molecular pump or a vacuum pump; wherein the C4F8 gas has a very low fluorocarbon ratio, which can ensure that the deposition reaction is greater than the etching reaction.

[0049] d, 350sccm etching gas C3F8 is introduced, the radio frequency coil is started, the RF power is 1500W, the bias power is 300W, the controller is used to open the back helium cooling system and make it work at full power, and the wafer temperature is as low as possible to reduce the erosion of the anti-sticking layer on the sidewall; anisotropic etching is carried out under the above parameters, so as to remove the anti-sticking layer on the surface of SiO2, and the anti-sticking layer on the sidewall is protected as much as possible, and the reaction gas is discharged through a molecular pump or a vacuum pump;

[0050] e, the SiO2 is selectively isotropically etched for 30s by using the BHF solution diluted by 1:10, and the device structure is released.

[0051] As described above, the polytetrafluoroethylene anti-sticking layer is directly formed on the sidewall in the passivation layer forming process of deep silicon etching, the anti-sticking layer is formed first, and then the structure releasing process is carried out, which can avoid the adhesion failure caused by the structure releasing in the traditional process flow, greatly improve the process yield, and effectively simplify the process steps and reduce the production cost.

[0052] The above embodiments are only the preferred embodiments of the present application, and cannot be used to limit the protection scope of the present application, and any non-essential changes and replacements made by those skilled in the art on the basis of the present application shall fall within the protection scope of the present application.

Claims

1. A deep silicon etching method, characterized in that: Includes the following steps: a. Using compounds containing fluorocarbons C x F y The etching gas is used to perform deep silicon etching on the wafer, so that the etching and deposition reactions occur simultaneously during the reaction process. The vacuum degree is ≤200mTorr, the RF power is ≥5000W, and a residual passivation layer is left on the sidewall after etching. The reaction gas is then discharged. The fluorocarbon C... x F y The fluorocarbon ratio y / x > 1; b. Introduce etching gas with high fluorine content to achieve the optimal etching reaction level. At the same time, shut down the back helium cooling system through the controller to raise the wafer temperature to >80°C to accelerate the etching of the sidewall passivation layer. Perform isotropic etching on the sidewalls to remove the passivation layer and exhaust the reaction gas. c. Introduce C4F8 gas and ionize it using ICP to deposit a polytetrafluoroethylene anti-stick layer on the device surface, and then discharge the reaction gas. d. Introduce etching gas with high fluorine content, turn on the RF coil, RF power > 1200W, bias power > 200W, turn on the back helium cooling system through the controller and make it work at full power to avoid the wafer temperature rising and reduce the erosion of the sidewall anti-adhesion layer; perform anisotropic etching to remove the SiO2 anti-adhesion layer and exhaust the reaction gas. e. Selective isotropic etching of SiO2 using buffered hydrofluoric acid or gaseous hydrogen fluoride to release the device structure; In steps b and d, the high-fluorine-content etching gas is SF6 or C. x F y And C x F y The fluorocarbon ratio y / x > 2.

2. The deep silicon etching method according to claim 1, characterized in that: The etching gas mentioned in step a includes C x F y Gases and O2, and C x F y The mixing ratio of gas and O2 is 50~100%: 0~50%.

3. The deep silicon etching method according to claim 1 or 2, characterized in that: The traction power of isotropic etching in step b is <100W.

4. The deep silicon etching method according to claim 1 or 2, characterized in that: In step c, the RF power is <2000W and the bias power is 0.

5. A deep silicon etching apparatus, characterized in that: The deep silicon etching apparatus includes a controller configured to perform the method as described in any one of claims 1 to 4.

Images