A method for adaptive equalization of a receiver of a high-speed serial interface chip

Abstract

The application relates to the communication technical field, and discloses a receiving end equalizer adaptive method and circuit of a high-speed serial interface chip, which comprises the following steps: a digital equalizer receives an output value of an analog-to-digital converter and coefficients of each node output by an adaptive algorithm module; the output value of the analog-to-digital converter is multiplied by the coefficients of the corresponding node and then added by the digital equalizer, and the result is output; a decision device judges the output of the digital equalizer and obtains decision data; the error between the decision data and an ideal value is calculated to obtain a preliminary error value; the adaptive algorithm module compares the preliminary error value with a dead zone threshold and determines a used error value, when the preliminary error value is within the range of the dead zone threshold, the used error value is 0, and when the preliminary error value is outside the range of the dead zone threshold, the used error value is equal to the preliminary error value. By setting the error dead zone threshold, the coefficient updating is stopped under certain conditions, and the power consumption is reduced under the premise of not excessively affecting the performance.

Description

An adaptive equalizer method for the receiver of a high-speed serial interface chip. Technical Field

[0001] This application relates to the field of communication technology, and more specifically to an adaptive equalizer method for a high-speed serial interface chip. Background Technology

[0002] This section is intended to provide background or context for the embodiments of this application as set forth in the claims. The description herein is not intended to imply that it is prior art that has been disclosed, simply because it is included in this section.

[0003] In high-speed serial interface chips, inter-symbol interference (ISI) caused by channel insertion loss can affect signal transmission quality and cause bit errors. Therefore, equalization techniques are needed to compensate for channel insertion loss and mitigate the impact of ISI. In serial deserializer (SerDes) receiver solutions based on analog-to-digital converters (ADCs) and digital signal processing (DSPs), the forward feedback equalizer (FFE) is a commonly used linear digital equalizer. However, in a typical serial deserializer receiver implementation, the FFE usually accounts for the largest proportion of power consumption, and power consumption is an important indicator for evaluating serial deserializers (SerDes). The input of the FFE consists of two parts: data and coefficients. The rate of change of either part affects the overall power consumption of the FFE. Typically, the coefficients of the FFE are generated by an adaptive algorithm, and the correctness of the coefficients and the direction of adjustment are determined based on the error between the output value and the ideal value of the FFE. Coefficient adaptation is a dynamic balancing process; the stable value of the coefficients fluctuates around the ideal value, and changes in the coefficients increase the power consumption of the FFE.

[0004] In an adaptive equalization scheme at the receiver of a serial deserializer applied to analog-to-digital converters and digital signal processing, as shown in Figure 1, the function of the Freeform Equalization (FFE) is to equalize the data output from the analog-to-digital converter to minimize the impact of inter-symbol interference (ISE). The equalization method involves multiplying the data output from the analog-to-digital converter at each computation node by the corresponding coefficient, then summing the outputs of all computation nodes before outputting them to the decision unit for judgment. The decision unit is omitted in the figure. The coefficients of each computation node in the FFE come from the adaptive algorithm module, whose inputs are the sampled data output from the analog-to-digital converter and the error between the decision unit's output value and the ideal value.

[0005] The drawback of existing technologies is that the calculation of the FFE coefficients in the Least Mean Square (LMS) adaptive algorithm is a dynamic balancing process. Furthermore, due to quantization errors in digital circuits, the coefficients, after approaching the ideal value, will not remain at that value but will fluctuate around it. In digital circuits, these fluctuations increase power consumption. Since a decision is made after FFE, the balanced output does not need to be exactly equal to the ideal value; a correct decision can be made near the ideal value. Therefore, the FFE coefficients only need to be maintained near the ideal value to complete the balancing function. The additional power consumption caused by fluctuations near the ideal value after the coefficients stabilize is meaningless. Summary of the Invention

[0006] The purpose of this application is to provide an adaptive equalizer method for the receiver of a high-speed serial interface chip. By setting an error dead zone threshold, the update of the FFE coefficient is stopped under certain conditions, thereby reducing power consumption without excessively affecting performance.

[0007] This application discloses an adaptive equalizer method for the receiver of a high-speed serial interface chip, including:

[0008] The digital equalizer receives the output value of the analog-to-digital converter and the coefficients of each node output by the adaptive algorithm module;

[0009] The digital equalizer multiplies the output value of the analog-to-digital converter with the coefficients of the corresponding nodes and then adds them together before outputting the result.

[0010] The decision-maker makes a decision on the output of the digital equalizer and obtains the decision data.

[0011] Calculate the error between the decision data and the ideal value and obtain a preliminary error value; and

[0012] The adaptive algorithm module compares the initial error value with the dead zone threshold and determines the usage error value. When the initial error value is within the dead zone threshold range, the usage error value is 0. The adaptive algorithm module keeps the coefficients of each node unchanged from the previous cycle and outputs them to the digital equalizer. When the initial error value is outside the dead zone threshold range, the usage error value is equal to the initial error value. The adaptive algorithm module updates the coefficients of each node according to the output value of the analog-to-digital converter and the usage error value and outputs them to the digital equalizer.

[0013] In a preferred embodiment, the digital equalizer is a forward feedback equalizer, comprising N+M+1 nodes, where N is the number of forward nodes and M is the number of backward nodes. The formula for calculating the output value of the digital equalizer is as follows:

[0014]

[0015] Where y′(n) is the output value of the digital equalizer at time n, h(n,j) is the coefficient of the j-th node output by the adaptive algorithm module at time n, and x(n,j) is the j-th output value of the analog-to-digital converter at time n, where -N≤j≤M.

[0016] In a preferred embodiment, the preliminary error value between the decision data and the ideal value is calculated using the following formula:

[0017] e′(n)=y(n)-d(n)

[0018] The preliminary error value is compared with the dead zone threshold using the following formula to determine the error value to be used:

[0019]

[0020] Where y(n) is the output value of the decision unit, d(n) is the ideal value, e′(n) is the initial error value, e(n) is the usage error value, and e th The dead zone threshold is set.

[0021] In a preferred embodiment, the dead zone threshold is determined by simulation testing of the relationship between the size of the dead zone threshold and the bit error rate.

[0022] In a preferred embodiment, the digital equalizer includes 9 forward nodes and 22 backward nodes, and the dead zone threshold is set to 0.09.

[0023] In a preferred embodiment, the adaptive algorithm module employs the least mean square algorithm, and updates the coefficients of each node based on the output value of the analog-to-digital converter and the usage error value using the following formula:

[0024] h(n,j)=h(n-1,j)+μ(n)·x(n,j)·e(n)

[0025] Where h(n-1,j) and h(n,j) are the coefficients of the j-th node output by the adaptive algorithm module at time n-1 and time n, respectively, μ(n) is the adjustment step size, x(n,j) is the j-th output value of the analog-to-digital converter at time n, and e(n) is the usage error value.

[0026] In a preferred embodiment, the digital equalizer is a decision feedback equalizer, or a combination of a forward feedback equalizer and a decision feedback equalizer.

[0027] In a preferred embodiment, the decision maker is a decision feedback equalizer.

[0028] In a preferred embodiment, the adaptive algorithm module employs the maximum likelihood sequence estimation algorithm.

[0029] This application also discloses a receiver equalizer adaptive circuit for a high-speed serial interface chip, comprising: a digital equalizer, a decision unit, an adder, a dead-time threshold comparator, and an adaptive algorithm module.

[0030] The digital equalizer's data input is connected to the analog-to-digital converter's output; the digital equalizer's output is connected to the decision unit's input; the decision unit's output is connected to the adder's input; the adder's output is connected to the dead-zone threshold comparator's input; the adaptive algorithm module's input is connected to the dead-zone threshold comparator's output and the analog-to-digital converter's output; and the adaptive algorithm module's output is connected to the digital equalizer's coefficient input.

[0031] The digital equalizer receives the output value of the analog-to-digital converter and the coefficients of each node output by the adaptive algorithm module. The digital equalizer multiplies the output value of the analog-to-digital converter with the coefficients of the corresponding nodes and then adds them together before outputting the result.

[0032] The decision-maker makes a decision on the output of the digital equalizer and obtains decision data.

[0033] The adder calculates the error between the decision data and the ideal value to obtain a preliminary error value.

[0034] The preliminary error value is compared with the dead zone threshold by the dead zone threshold comparator to determine the error value to be used.

[0035] The adaptive algorithm module compares the initial error value with the dead zone threshold and determines the usage error value. When the initial error value is within the dead zone threshold range, the usage error value is 0. The adaptive algorithm module keeps the coefficients of each node unchanged from the previous cycle and outputs them to the digital equalizer. When the initial error value is outside the dead zone threshold range, the usage error value is equal to the initial error value. The adaptive algorithm module updates the coefficients of each node according to the output value of the analog-to-digital converter and the usage error value and outputs them to the digital equalizer.

[0036] The main differences and effects of the implementation method of this application compared with the prior art are as follows:

[0037] This invention proposes an algorithm with a dead-time threshold. When the absolute value of the error e(n) is less than a certain value (i.e., the decision coefficient h(n) has been locked near the ideal value), the coefficient h(n) is not adjusted in that clock cycle, and the coefficient remains unchanged. This reduces unnecessary coefficient jumps and lowers power consumption without excessively affecting performance.

[0038] Furthermore, a suitable dead-time threshold e can be selected based on specific simulation analysis. th This allows for optimal power consumption optimization under different digital equalizer implementation methods.

[0039] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 is a schematic diagram of an adaptive circuit for a receiver equalizer in the prior art.

[0042] Figure 2 is a schematic diagram of an adaptive circuit for a receiver equalizer according to one embodiment of this application.

[0043] Figure 3 is a schematic diagram illustrating the relationship between dead zone threshold and bit error rate in one embodiment of this application.

[0044] Figure 4 is a flowchart illustrating a receiver equalizer adaptive method according to one embodiment of this application.

[0045] The labels in each of the attached figures are as follows:

[0046] 1-Digital equalizer;

[0047] 2-Adder;

[0048] 3-Adaptive Algorithm Module;

[0049] 4-Dead-time threshold comparator;

[0050] 5-Decision Maker. Detailed Implementation

[0051] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0052] Explanation of some concepts:

[0053] High-speed serial interface: This is a serial interface standard. This technology also involves a serial deserializer (SerDes), which converts multiple low-speed parallel signals into high-speed serial signals at the transmitting end, transmits them through a transmission medium (optical fiber or copper wire), and finally converts the high-speed serial signals back into low-speed parallel signals at the receiving end.

[0054] Forward feedback equalizer (FFE) is a linear equalization technique that corrects the amplitude of the current bit based on the weighted value of the voltage amplitude of adjacent bits. The weighting coefficient of each adjacent bit is directly related to the impulse response of the channel.

[0055] Decision Feedback Equalizer (DFE): This is a non-linear equalization technique that modifies the decision threshold of the current bit by adjusting the decision level of adjacent bits.

[0056] Least Mean Square (LMS) algorithm: This is an improved version of the steepest descent algorithm. This algorithm does not require known statistical characteristics of the input signal and the desired signal. The weighting coefficients at the "current moment" are obtained by adding a proportional term of the negative mean square error gradient to the weighting coefficients at the "previous moment".

[0057] Maximum Likelihood Sequence Estimation (MLSE): This method infers the most likely transmitted signal sequence by calculating the similarity between the received signal sequence and possible transmitted signal sequences. This inference process relies on models of the signal and the channel.

[0058] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0059] This application discloses an adaptive equalizer circuit for a high-speed serial interface chip, the structure of which is shown in Figure 2. It includes: a digital equalizer 1, a decision unit 5, an adder 2, a dead-time threshold comparator 4, and an adaptive algorithm module 3. The data input terminal of the digital equalizer 1 is connected to the output terminal of an analog-to-digital converter (not shown in the figure). The output terminal of the digital equalizer 1 is connected to the input terminal of the decision unit 5. The output terminal of the decision unit 5 is connected to the input terminal of the adder 2. The output terminal of the adder 2 is connected to the input terminal of the dead-time threshold comparator 4. The input terminal of the adaptive algorithm module 3 is connected to the output terminal of the dead-time threshold comparator 4 and the output terminal of the analog-to-digital converter. The output terminal of the adaptive algorithm module 3 is connected to the coefficient input terminal of the digital equalizer 1.

[0060] Digital equalizer 1 receives the output value of the analog-to-digital converter (ADC) and the coefficients of each node output by the adaptive algorithm module 3. Digital equalizer 1 multiplies the ADC output value with the corresponding node coefficients and then sums the results before outputting the sum. Decision unit 5 makes a decision on the output of digital equalizer 1 and obtains decision data. Adder 2 calculates the error between the decision data and the ideal value and obtains a preliminary error value. Dead-zone threshold comparator 4 compares the preliminary error value with the dead-zone threshold and determines the usable error value. When the preliminary error value is within the dead-zone threshold range, the usable error value is 0, and the adaptive algorithm module 3 keeps the node coefficients from the previous cycle unchanged and outputs them to digital equalizer 1. When the preliminary error value is outside the dead-zone threshold range, the usable error value equals the preliminary error value, and the adaptive algorithm module 3 updates the coefficients of each node based on the ADC output value and the usable error value, and outputs the updated coefficients to digital equalizer 1.

[0061] In one embodiment, digital equalizer 1 is a forward feedback equalizer (FFE) comprising N+M+1 nodes, where N is the number of forward nodes, M is the number of backward nodes, and N and M are positive integers. The formula for calculating the output value of digital equalizer 1 is as follows:

[0062]

[0063] Where y′(n) is the output value of digital equalizer 1 at time n, h(n,j) is the coefficient of the j-th node of the output of adaptive algorithm module 3 at time n, and x(n,j) is the output value of analog-to-digital converter at time n, where -N≤j≤M.

[0064] In one embodiment, the preliminary error value between the decision data y(n) and the ideal value is calculated using the following formula:

[0065] e′(n)=y(n)-d(n)

[0066] The initial error value is compared with the dead zone threshold using the following formula to determine the applicable error value:

[0067]

[0068] Where y(n) is the output value of decision 5, d(n) is the ideal value, e′(n) is the initial error between the output value of decision 5 and the ideal value, and e(n) is the usage error value. th This is the set error dead zone threshold. Dead zone threshold e th The larger the setting value, the larger the corresponding coefficient h(n) locking range, and the more obvious the power consumption optimization effect. However, if the dead zone threshold value is set too large, it will affect the normal convergence of the coefficient h(n), thus affecting the performance of digital equalizer 1.

[0069] In one embodiment, the dead zone threshold e th The dead zone threshold e was tested through simulation. th The relationship between the size of the equalizer and the bit error rate is determined. In one embodiment, the forward feedback equalizer (FFE) includes 32 nodes, including 9 forward nodes, 1 master node, and 22 backward nodes connected in sequence, i.e., N equals 9 and M equals 22 in Figure 2. The analog-to-digital converter output is 8 bits, and the node coefficients are 9 bits. Through simulation analysis, the dead time threshold e is determined. th The relationship between the error rate and the bit error rate is shown in Figure 3. The normalized error dead zone threshold e is taken. th A value of 0.09 is suitable, as it neither degrades the normal convergence of coefficient h(n) nor the performance of digital equalizer 1, while also optimizing power consumption as much as possible. The simulation test method is as follows: keeping other conditions unchanged, the dead-time threshold e is changed. th The value of is recorded at the dead zone threshold e. th Bit error rate under configuration. Dead zone threshold e th The established principle is to avoid a significant increase in the bit error rate. The aforementioned dead-time threshold e... th The given value is just an example of one implementation method. Different implementation methods require corresponding simulation analysis to obtain a suitable dead-time threshold e. th Values ​​can be selected. For example, the dead zone threshold e can be set for different numbers of forward feedback equalizers (FFE) or different combinations of forward feedback equalizers (FFE) and decision feedback equalizers (DFE). th The value can be obtained by simulation testing of the dead zone threshold e. th The relationship between the size and the bit error rate is determined.

[0070] In one embodiment, the adaptive algorithm module 3 employs the Least Mean Square (LMS) algorithm. The adaptive algorithm module 3 updates the coefficients of each node based on the output value of the analog-to-digital converter and the usage error value using the following formula:

[0071] h(n,j)=h(n-1,j)+μ(n)·x(n,j)·e(n)

[0072] Where h(n-1,j) and h(n,j) are the coefficients of the j-th node output by the adaptive algorithm module 3 at time n-1 and time n, respectively, μ(n) is the adjustment step size, x(n,j) is the j-th output value of the analog-to-digital converter at time n, and e(n) is the error value.

[0073] In another embodiment, the digital equalizer 1 can be a decision feedback equalizer (DFE).

[0074] In other embodiments, the digital equalizer 1 may also be a combination of a forward feedback equalizer (FFE) and a decision feedback equalizer (DFE).

[0075] In one embodiment, the decision controller 5 is a decision feedback equalizer (DFE).

[0076] In another embodiment, the adaptive algorithm module employs the Maximum Likelihood Sequence Estimation (MLSE) algorithm.

[0077] This application also discloses a receiver equalizer adaptive method for a high-speed serial interface chip. This method can be applied to the receiver equalizer adaptive circuit shown in Figure 2. Referring to Figures 2 and 4, the method includes the following steps:

[0078] Step 101: Digital equalizer 1 receives the output value of analog-to-digital converter and the coefficients of each node output by adaptive algorithm module 3.

[0079] Step 102: The output value of the analog-to-digital converter is multiplied by the coefficients of the corresponding nodes and then summed by the digital equalizer 1 before being output.

[0080] Step 103: The decision device 5 makes a decision on the output of the digital equalizer 1 and obtains the decision data.

[0081] Step 104: Adder 2 calculates the error between the decision data and the ideal value and obtains a preliminary error value.

[0082] Step 105: The dead-zone threshold comparator 4 compares the initial error value with the dead-zone threshold and determines the error value to be used. When the initial error value is within the dead-zone threshold range, the error value is 0, the adaptive algorithm module keeps the coefficients of each node unchanged from the previous cycle and outputs them to the digital equalizer. When the initial error value is outside the dead-zone threshold range, the error value is equal to the initial error value, the adaptive algorithm module updates the coefficients of each node according to the output value of the analog-to-digital converter and the error value to be used and outputs them to the digital equalizer.

[0083] It should be noted that in the claims and specification of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0084] All references to this application are incorporated herein by reference as if each reference were individually incorporated herein by reference. Furthermore, it should be understood that after reading the foregoing teachings of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope defined by the appended claims.

[0085] In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. An adaptive equalizer method for receivers based on a high-speed serial interface chip with ADC and DSP architecture, characterized in that, include: The digital equalizer receives the output value of the analog-to-digital converter and the coefficients of each node output by the adaptive algorithm module; the digital equalizer multiplies the output value of the analog-to-digital converter with the coefficients of the corresponding nodes and then adds them together before outputting the result; the decision unit makes a decision on the output of the digital equalizer and obtains decision data; the error between the decision data and the ideal value is calculated to obtain a preliminary error value. The dead-zone threshold comparator compares the initial error value with the dead-zone threshold and determines the usage error value. When the initial error value is within the dead-zone threshold range, the usage error value is 0. The adaptive algorithm module keeps the coefficients of each node unchanged from the previous cycle and outputs them to the digital equalizer. When the initial error value is outside the dead-zone threshold range, the usage error value is equal to the initial error value. The adaptive algorithm module updates the coefficients of each node according to the output value of the analog-to-digital converter and the usage error value and outputs them to the digital equalizer. The dead-zone threshold is determined according to the relationship between the size of the dead-zone threshold and the bit error rate.

2. The receiver equalizer adaptive method according to claim 1, characterized in that, The digital equalizer is a forward feedback equalizer, comprising N+M+1 nodes, where N is the number of forward nodes and M is the number of backward nodes. The formula for calculating the output value of the digital equalizer is as follows: Where y'(n) is the output value of the digital equalizer at time n, h(n,j) is the coefficient of the j-th node output by the adaptive algorithm module at time n, and x(n,j) is the j-th output value of the analog-to-digital converter at time n, where -N≤j≤M.

3. The receiver equalizer adaptive method according to claim 1, characterized in that, The preliminary error between the decision data and the ideal value is calculated using the following formula: The initial error value is compared with the dead zone threshold using the following formula to determine the usage error value: Where y(n) is the output value of the decision unit, d(n) is the ideal value, e'(n) is the initial error value, e(n) is the usage error value, and e th The dead zone threshold is set.

4. The receiver equalizer adaptive method according to claim 1, characterized in that, The dead zone threshold is determined by simulation testing of the relationship between the size of the dead zone threshold and the bit error rate.

5. The receiver equalizer adaptive method according to claim 1, characterized in that, The digital equalizer includes 9 forward nodes and 22 backward nodes, and the dead zone threshold is set to 0.

09.

6. The receiver equalizer adaptive method according to claim 1, characterized in that, The adaptive algorithm module employs the least mean square algorithm, and updates the coefficients of each node based on the output value of the analog-to-digital converter and the usage error value using the following formula: Where h(n-1,j) and h(n,j) are the coefficients of the j-th node output by the adaptive algorithm module at time n-1 and time n, respectively, μ(n) is the adjustment step size, x(n,j) is the j-th output value of the analog-to-digital converter at time n, and e(n) is the usage error value.

7. The receiver equalizer adaptive method according to claim 1, characterized in that, The digital equalizer is a decision feedback equalizer, or a combination of a forward feedback equalizer and a decision feedback equalizer.

8. The receiver equalizer adaptive method according to claim 1, characterized in that, The decision-maker is a decision feedback equalizer.

9. The receiver equalizer adaptive method according to claim 1, characterized in that, The adaptive algorithm module uses the maximum likelihood sequence estimation algorithm.

10. A receiver-side equalizer adaptive circuit based on a high-speed serial interface chip with ADC and DSP architecture, characterized in that, include: The system comprises a digital equalizer, a decision unit, an adder, a dead-zone threshold comparator, and an adaptive algorithm module. The data input of the digital equalizer is connected to the output of the analog-to-digital converter (ADC). The output of the digital equalizer is connected to the input of the decision unit. The output of the decision unit is connected to the input of the adder. The output of the adder is connected to the input of the dead-zone threshold comparator. The input of the adaptive algorithm module is connected to the outputs of the dead-zone threshold comparator and the ADC. The output of the adaptive algorithm module is connected to the coefficient input of the digital equalizer. The digital equalizer receives the output value of the ADC and the coefficients of each node output by the adaptive algorithm module. It then multiplies and adds the output value of the ADC with the coefficients of the corresponding nodes and outputs the sum. The decision unit makes a decision on the output of the digital equalizer and obtains decision data; the adder calculates the error between the decision data and the ideal value and obtains a preliminary error value; the dead-zone threshold comparator compares the preliminary error value with the dead-zone threshold and determines the usage error value; when the preliminary error value is within the dead-zone threshold range, the usage error value is 0, the adaptive algorithm module keeps the coefficients of each node unchanged from the previous cycle and outputs them to the digital equalizer; when the preliminary error value is outside the dead-zone threshold range, the usage error value is equal to the preliminary error value, the adaptive algorithm module updates the coefficients of each node according to the output value of the analog-to-digital converter and the usage error value and outputs them to the digital equalizer, wherein the dead-zone threshold is determined according to the relationship between the size of the dead-zone threshold and the bit error rate.

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