Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The application relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure and a preparation method of the semiconductor structure. The semiconductor structure comprises a substrate, a capacitor structure, a transistor structure, a plurality of bit lines and a plurality of word lines; the capacitor structure is arranged on the substrate, the transistor structure is arranged on a side of the capacitor structure away from the substrate, one of a source and a drain of the transistor structure is electrically connected with the capacitor structure, a gate of the transistor structure is electrically connected with the word line, and the other of the source and the drain of the transistor structure is electrically connected with the bit line; a word line isolation structure is arranged between two adjacent word lines, and a bit line isolation structure is arranged between two adjacent bit lines; and the width of the word line isolation structure is not equal to the width of the bit line isolation structure. The application can improve the stability of the semiconductor structure in the process and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices.

[0003] DRAM comprises multiple repeating memory cells, each including a capacitor and a transistor. In TOC (Transistor on Capacitor) DRAM, the transistor is positioned above the capacitor, which is in contact with the substrate. DRAM also includes multiple word lines and multiple bit lines, which are spaced apart and intersect each other in their extension directions.

[0004] However, the aforementioned TOC structure of DRAM exhibits poor stability during manufacturing processes, affecting the storage performance of semiconductor memory. Summary of the Invention

[0005] This application provides a semiconductor structure and a method for fabricating the semiconductor structure, which can effectively improve the stability of the semiconductor structure during the fabrication process and enhance the performance of the semiconductor structure.

[0006] In a first aspect, this application provides a semiconductor structure, including a substrate, a capacitor structure, a transistor structure, multiple bit lines, and multiple word lines; the capacitor structure is disposed on the substrate, the transistor structure is disposed on the side of the capacitor structure away from the substrate, one of the source and drain of the transistor structure is electrically connected to the capacitor structure, the gate of the transistor structure is electrically connected to the word line, and the other of the source and drain of the transistor structure is electrically connected to the bit line; a word line isolation structure is disposed between two adjacent word lines, and a bit line isolation structure is disposed between two adjacent bit lines; the width of the word line isolation structure is not equal to the width of the bit line isolation structure.

[0007] Secondly, this application provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a capacitor structure located on the substrate; forming a transistor structure located on the capacitor structure, wherein one of the source and drain of the transistor structure is electrically connected to the capacitor structure; forming multiple word lines and multiple bit lines, wherein the word lines are electrically connected to the gate of the transistor structure, and the bit lines are electrically connected to the other of the source and drain of the transistor structure; wherein a word line isolation structure is provided between two adjacent word lines, and a bit line isolation structure is provided between two adjacent bit lines; the width of the word line isolation structure is not equal to the width of the bit line isolation structure.

[0008] The semiconductor structure and its fabrication method provided in this application, by placing the capacitor structure on a substrate and the transistor structure on the side of the capacitor structure away from the substrate, effectively reduce the fabrication difficulty of the transistor and facilitate the connection of the transistor structure with word lines and bit lines, thus better meeting the design requirements of circuit connections. By connecting one of the transistor's source and drain to the capacitor structure, the gate to the word line, and the other of the source and drain to the bit line, the signal storage and retrieval functions of the semiconductor structure are realized. By setting word line isolation structures and bit line isolation structures, the stability of signal transmission in the word lines and bit lines can be guaranteed. By setting the widths of the word line isolation structures and bit line isolation structures to be unequal, the stability of the semiconductor structure during fabrication can be improved, thereby enhancing the performance of the semiconductor structure.

[0009] The structure of this application, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0010] Figure 1 A top view of a semiconductor structure provided in an embodiment of this application;

[0011] Figure 2 A cross-sectional view of a semiconductor structure provided in an embodiment of this application;

[0012] Figure 3 A cross-sectional view of another semiconductor structure provided in an embodiment of this application;

[0013] Figure 4 for Figure 2 A partial structural diagram of part A in the middle;

[0014] Figure 5 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment;

[0015] Figure 6 A cross-sectional view of the substrate providing the semiconductor structure for the embodiments of this application;

[0016] Figure 7 A cross-sectional view of the semiconductor structure forming the first sub-trench provided in an embodiment of this application;

[0017] Figure 8 A cross-sectional view of the first sub-trench of the semiconductor structure provided in this application embodiment, showing the filling of an insulating dielectric layer.

[0018] Figure 9 A cross-sectional view of the semiconductor structure forming the second sub-trench provided in the embodiments of this application;

[0019] Figure 10A cross-sectional view of the second sub-trench of the semiconductor structure provided in this application embodiment, showing the filling of an insulating dielectric layer.

[0020] Figure 11 A cross-sectional view of the exposed second extension of the semiconductor structure provided in an embodiment of this application;

[0021] Figure 12 A cross-sectional view of the support material supporting the second extension of the semiconductor structure provided in the embodiments of this application;

[0022] Figure 13 A cross-sectional view of the portion of the insulating dielectric layer extending along the second direction of the semiconductor structure provided in the embodiments of this application;

[0023] Figure 14 A cross-sectional view of a semiconductor structure with the insulating dielectric layer removed, provided in an embodiment of this application;

[0024] Figure 15 A cross-sectional view of the doped first extension of a semiconductor structure provided in an embodiment of this application;

[0025] Figure 16 A cross-sectional view of the formation of the first conductive layer in a semiconductor structure provided in an embodiment of this application;

[0026] Figure 17 A cross-sectional view of the semiconductor structure forming the capacitor dielectric layer provided in the embodiments of this application;

[0027] Figure 18 A cross-sectional view of the formation of the second conductive layer in a semiconductor structure provided in an embodiment of this application;

[0028] Figure 19 A cross-sectional view of the semiconductor structure provided in this application, showing the removal of the support material around the first extension segment;

[0029] Figure 20 A cross-sectional view of the semiconductor structure forming the insulating dielectric layer provided in the embodiments of this application;

[0030] Figure 21 A cross-sectional view of a semiconductor structure with a portion of the insulating dielectric layer removed, provided in an embodiment of this application;

[0031] Figure 22 A cross-sectional view of the support material supporting the second extension of the semiconductor structure provided in the embodiments of this application;

[0032] Figure 23 A cross-sectional view of the removed portion of the second extension of the semiconductor structure provided in an embodiment of this application;

[0033] Figure 24A cross-sectional view of the formation of the gate dielectric layer in the semiconductor structure provided in the embodiments of this application;

[0034] Figure 25 A cross-sectional view of the semiconductor structure forming word lines provided in the embodiments of this application;

[0035] Figure 26 A cross-sectional view of the semiconductor structure forming a word line isolation trench provided in the embodiments of this application;

[0036] Figure 27 A cross-sectional view of an insulating dielectric layer formed in a word line isolation trench of a semiconductor structure provided in this application embodiment;

[0037] Figure 28 A cross-sectional view of a semiconductor structure with the mask layer removed, provided in an embodiment of this application;

[0038] Figure 29 A cross-sectional view of the semiconductor structure forming the insulating dielectric layer provided in the embodiments of this application;

[0039] Figure 30 A cross-sectional view of the semiconductor structure forming bit line trenches provided in the embodiments of this application;

[0040] Figure 31 A cross-sectional view of the formation bit line of the semiconductor structure provided in the embodiments of this application. Detailed Implementation

[0041] The inventors of this application discovered during their research that DRAM, which comprises multiple repeating memory cells, each including a capacitor and a transistor, has a TOC (Top-of-Cell) structure. In TOC DRAM, the transistor is positioned above the capacitor, which is in contact with the substrate. During DRAM manufacturing, trenches in the word line and bit line directions need to be etched into the substrate, and material layers are deposited in these trenches to form the capacitor structure. However, during the formation of these word line and bit line trenches, the remaining substrate, due to its poor support properties, is prone to collapse, reducing the stability of the DRAM and consequently impairing its storage performance.

[0042] In view of this, the semiconductor structure and its fabrication method provided in this application, by placing the capacitor structure on the substrate and the transistor structure on the side of the capacitor structure away from the substrate, can effectively reduce the fabrication difficulty of the transistor and facilitate the connection of the transistor structure with word lines and bit lines, thus better meeting the design requirements of circuit connections. By connecting one of the source and drain of the transistor to the capacitor structure, the gate to the word line, and the other of the source and drain to the bit line, the signal storage and retrieval functions of the semiconductor structure are realized. By setting word line isolation structures and bit line isolation structures, the stability of signal transmission in word lines and bit lines can be guaranteed. By setting the widths of the word line isolation structures and bit line isolation structures to be unequal, the stability of the semiconductor structure during the fabrication process can be improved, thereby enhancing the performance of the semiconductor structure.

[0043] Reference Figures 1 to 4 As shown, this application embodiment provides a semiconductor structure including a substrate 100, a capacitor structure 200, a transistor structure 300, multiple bit lines 500, and multiple word lines 400. The capacitor structure 200 is disposed on the substrate 100, and the transistor structure 300 is disposed on the side of the capacitor structure 200 away from the substrate 100. One of the source 301 and drain 303 of the transistor structure 300 is electrically connected to the capacitor structure 200, and the gate of the transistor structure 300 is electrically connected to the word line 400. The other of the source 301 and drain 303 of the transistor structure 300 is electrically connected to the bit line 500. A word line isolation structure 401 is disposed between two adjacent word lines 400, and a bit line isolation structure 501 is disposed between two adjacent bit lines 500. The width of the word line isolation structure 401 is not equal to the width of the bit line isolation structure 501.

[0044] It should be noted that the semiconductor structure provided in this application embodiment can be a memory device or a non-memory device. Memory devices may include, for example, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). Non-memory devices may be logic devices (e.g., microprocessors, digital signal processors, or microcontrollers) or similar devices. This application embodiment uses DRAM memory devices as an example for illustration.

[0045] In the embodiments of this application, the gate of transistor structure 300 is connected to word line 400 (WL), the drain 303 is connected to bit line 500 (BL), and the source 301 is connected to capacitor structure 200. Word line 400 is connected to word line driver, which inputs a voltage signal to word line 400. Word line 400 can also be directly used as the gate of transistor structure 300. The voltage signal on word line 400 can control the opening or closing of transistor structure 300, thereby reading data information stored in capacitor structure 200 through bit line 500, or writing data information into capacitor structure 200 for storage through bit line 500, thus realizing the function of storing data information in semiconductor structure.

[0046] Reference Figure 1 As shown, this embodiment of the application provides multiple word lines 400 and multiple bit lines 500. The multiple bit lines 500 are arranged in parallel and extend along a first direction L1, and are spaced apart along a second direction L2. The multiple word lines 400 are also arranged in parallel and extend along the second direction L2, and are spaced apart along the first direction L1. The first direction L1 and the second direction L2 intersect each other. In this embodiment, the angle between the first direction L1 and the second direction L2 can be a right angle, and this embodiment does not limit the value of this angle.

[0047] The word line isolation structure 401 between adjacent word lines 400 can be made of insulating material to prevent signal interference between adjacent word lines 400 and improve the stability of signal transmission in the word lines 400. Furthermore, the word line isolation structure 401 can also provide support for the word lines 400 to improve their structural stability. Similarly, the bit line isolation structure 501 has a similar effect to the word line isolation structure 401, which will not be elaborated here. Figure 1 As shown, the width of word line isolation structure 401 can be the portion shown as h, and the width of word line 400 can be the portion shown as f; the width of bit line isolation structure 501 can be the portion shown as g, and the width of bit line 500 can be the portion shown as e.

[0048] In this embodiment, the width of the word line isolation structure 401 is not equal to the width of the bit line isolation structure 501, and can include the following two implementation methods: combining Figure 1As shown, in a first feasible implementation, the width of the word line isolation structure 401 is greater than the width of the bit line isolation structure 501. Correspondingly, the width of the word line 400 is greater than the width of the bit line 500. In the semiconductor fabrication process, the word line 400 and the bit line 500 are formed through different steps. For example, trenches extending along a first direction L1 and a second direction L2 are formed in the substrate 100 by etching, respectively. The bit line 500 can be formed in the trench extending along the first direction L1, and the word line 400 can be formed in the trench extending along the second direction L2. A support material 600 is deposited in the trenches in the two extending directions, which provides support for the substrate 100 retained during the etching process. This is because the width of the word line isolation structure 401 is greater than the width of the bit line isolation structure 501, and the width of the word line 400 is greater than the width of the bit line 500. Therefore, the support material 600 can fill the trench extending along the first direction L1 while exposing a portion of the trench extending along the second direction L2. A word line 400 is formed by depositing conductive material within the trench extending along the second direction L2. During the formation of the word line 400, the support material 600 within the trench extending along the first direction L1 can consistently support the retained substrate 100 to prevent it from collapsing or tilting, thereby improving structural stability during semiconductor fabrication.

[0049] In this process, the width of word line 400 is 1 / 3 to 3 / 2 larger than the width of bit line 500. When the difference between the widths of word line 400 and bit line 500 is too large, the signal transmission capabilities of word line 400 and bit line 500 differ significantly, affecting the signal storage and retrieval processes of the semiconductor structure. Simultaneously, during the manufacturing process, the small width of bit line 500 makes it difficult to form the support material 600, and bit line 500 may deform due to the compression from the support material 600, leading to a decrease in the stability of the semiconductor structure. When the difference between the widths of word line 400 and bit line 500 is small, during the formation of the support material 600, it cannot be guaranteed that one of the trenches extending along the first direction L1 and the trenches extending along the second direction L2 will be filled by the support material 600, while the other will remain unfilled, thus affecting the formation process of word line 400 and bit line 500. Therefore, the ratio of the difference between the width of word line 400 and the width of bit line 500 can be selected within the above range, including but not limited to 2 / 3 and 1 / 2. This embodiment does not limit the specific value.

[0050] In a second feasible implementation, the width of the bit line isolation structure 501 is greater than the width of the word line isolation structure 401, and correspondingly, the width of the bit line 500 is greater than the width of the word line 400. The technical effect here is similar to that of the first implementation, and will not be described again here.

[0051] Specifically, the substrate 100 of the semiconductor structure in this embodiment may include a semiconductor layer and a substrate isolation structure 102, with the substrate isolation structure 102 located between the capacitor structure 200 and at least a portion of the semiconductor layer. The material of the semiconductor layer may include any or more of Si, Ge, SiGe, and SiC. In this embodiment, the substrate 100 is a Si substrate. The substrate isolation structure 102, disposed between the capacitor structure 200 and at least a portion of the semiconductor layer, can effectively prevent the semiconductor layer from affecting the capacitor structure 200, thereby blocking the electrical coupling between them. This can alleviate the leakage problem at the contact point between the capacitor structure 200 and the substrate 100, improve the stability of the capacitor structure 200, and thus optimize the storage performance of the semiconductor structure.

[0052] In this application embodiment, the substrate isolation structure 102 may include the following two implementations: As a first feasible implementation, refer to Figure 2 As shown, the substrate 100 includes a first semiconductor layer 101 and a second semiconductor layer 103. The first semiconductor layer 101 is stacked on the second semiconductor layer 103, and a substrate dielectric layer 1023 is disposed between the first semiconductor layer 101 and the second semiconductor layer 103, forming an SOI (Silicon On Insulator) structure. The capacitor structure 200 is in contact with the first semiconductor layer 101. The substrate dielectric layer 1023 forms a substrate isolation structure 102. The second semiconductor layer 103 may contain signal traces for this semiconductor structure, while the first semiconductor layer 101 may not contain signal traces and only serve as the structural basis for the capacitor structure 200. Therefore, the presence of signal traces in the second semiconductor layer 103 has a greater impact on the capacitor structure 200 compared to the first semiconductor layer 101. Therefore, the substrate dielectric layer 1023 is located between the second semiconductor layer 103 and the capacitor structure 200, which can effectively block the electrical coupling between the capacitor structure 200 and the second semiconductor layer 103, prevent leakage current in the capacitor structure 200, and improve the structural stability of the capacitor structure 200. The substrate dielectric layer 1023 can be an oxide layer, such as SiO2. x GeO x and SiGeO x One or more of them. The substrate dielectric layer 1023 and the first semiconductor layer 101 can be formed on the second semiconductor layer 103 by deposition. Of course, the substrate dielectric layer 1023 can also be formed by oxidizing part of the second semiconductor layer 103. Figure 2 Including Figure 1 The cross-sectional views are shown at four positions along the middle: a-a', b-b', c-c', and d-d'. Subsequent attached diagrams are similar and will not be described again.

[0053] As a second feasible implementation method, refer to Figure 3 As shown, the substrate 100 includes a first semiconductor layer 101, and a substrate isolation structure 102 is disposed between the first semiconductor layer 101 and the capacitor structure 200, with the capacitor structure 200 in contact with the substrate isolation structure 102. The substrate isolation structure 102 includes a first doped layer 1021 and a second doped layer 1022 stacked together, with different doping types for the first doped layer 1021 and the second doped layer 1022. The first doped layer 1021 and the second doped layer 1022 can be doped structures formed in a Si substrate. The first doped layer 1021 can be a P-type doped layer, and the second doped layer 1022 can be an N-type doped layer. A PN junction can be formed between the first doped layer 1021 and the second doped layer 1022. When electrical coupling occurs between the substrate 100 and the capacitor structure 200, the coupling current is exhausted at the PN junction, thereby isolating the two and preventing leakage current in the capacitor structure 200, thus improving the structural stability of the capacitor structure 200. Of course, the first doped layer 1021 can be an N-type doped layer and the second doped layer 1022 can be a P-type doped layer, but this embodiment does not limit this.

[0054] Specifically, the capacitor structure 200 includes multiple capacitors arranged in an array. Each capacitor may include a first electrode, a dielectric layer 202, and a second electrode, with the dielectric layer 202 located between the first and second electrodes. The first or second electrode between two adjacent capacitors can be used as a shared electrode, effectively reducing the mounting space occupied by the capacitor structure 200 and improving its integration. As one feasible implementation, the materials of the first and second electrodes include one or more combinations of N-Si, P-Si, Ru, RuO2, and TiN. The material of the dielectric layer 202 includes one or more combinations of Al2O3, ZrO, HfO2, SrTiO3, and BaTiO3. The dielectric layer 202 can be made of a material with a high dielectric constant to reduce leakage current and further ensure the stability of the capacitor structure 200. Figure 2 and Figure 3 As shown, the first conductive layer 201 can form the first electrode, and the second conductive layer 203 can form the second electrode.

[0055] The transistor structure 300 includes multiple transistors arranged in an array; each transistor is correspondingly associated with a capacitor. This correspondence between transistors and capacitors can be understood as the first electrode of a capacitor being electrically connected to the source 301 of a transistor, thus establishing an electrical connection between the transistor and the capacitor. In some embodiments, the second electrode of a capacitor may also be electrically connected to the source 301 of a transistor.

[0056] Combination Figures 2 to 4As shown, the transistor includes a gate and a semiconductor pillar 104 extending vertically. From the substrate 100 upwards, the semiconductor pillar 104 sequentially includes a source 301, a channel 302, and a drain 303. The gate is a ring-shaped structure surrounding the outer periphery of the channel 302. A gate dielectric layer 304 is disposed between the gate and the channel 302. The transistor in this embodiment is a vertically oriented transistor, which can effectively reduce the mounting space occupied by the transistor structure 300 and effectively improve the integration density of the transistor structure 300. Furthermore, the gate in the transistor structure 300 is a ring-shaped structure surrounding the outer periphery of the channel 302, forming a gate-all-around (GAA) structure, which can effectively improve the gate control capability of the transistor structure 300. The gate dielectric layer 304 can surround the gate and the channel 302 to avoid gate leakage current problems and improve the structural stability of the transistor. In some embodiments, in the semiconductor pillar 104 of the transistor, the drain 303 may also be located below the source 301. The drain 303 is electrically connected to the first electrode of the capacitor structure 200, and the source 301 is electrically connected to the bit line 500. This embodiment does not limit this.

[0057] Word line 400 surrounds the outer periphery of the gate of transistor structure 300, and bit line 500 is disposed on the side of transistor structure 300 away from substrate 100. It should be noted that both word line 400 and bit line 500 can be made of metallic materials, including but not limited to W and Cu, to reduce the resistance of bit line 500 and word line 400. Word line 400 surrounding the gate of transistor structure 300 effectively reduces the difficulty of connecting word line 400 to the gate. Bit line 500 being disposed on the side of transistor structure 300 away from substrate 100 reduces the difficulty of setting up bit line 500, facilitates connection of bit line 500 to external bit line drivers, and thus leads out the signal from bit line 500, which is more in line with the circuit structure design in semiconductor structures.

[0058] It should be noted that, referring to Figure 4As shown, in this embodiment, the semiconductor pillar 104 includes a first extension 1041 and a second extension 1042 connected to each other. The first extension 1041 is located on the side of the second extension 1042 near the substrate isolation structure 102, and the second extension 1042 can be used to form a transistor. The first extension 1041 is located in the capacitor structure 200. The first extension 1041 can be a conductive material, and the first conductive layer 201 can contact and be electrically connected to the first extension 1041. The first extension 1041 is connected to the second extension 1042, such that the first extension 1041 is connected to the source 301 of the transistor. Therefore, in this embodiment, the conduction between the source 301 of the transistor and the first conductive layer 201 is achieved by both being electrically connected to the first extension 1041. In some feasible embodiments, the first conductive layer 201 may be omitted, and the conductive first extension 1041 may serve as the first electrode of the capacitor.

[0059] Based on the above embodiments, referring to Figure 5 As shown, this application provides a method for fabricating a semiconductor structure, comprising:

[0060] S100: Provides a substrate. (Refer to...) Figure 6 As shown, the substrate 100 may include: forming a first semiconductor layer 101, forming a plurality of semiconductor pillars 104 arranged in an array in the first semiconductor layer 101, each semiconductor pillar 104 having a different width in a first direction L1 and a second direction L2, and forming an insulating dielectric layer 601 between adjacent semiconductor pillars 104, the first direction L1 and the second direction L2 intersecting each other.

[0061] Specifically, the process of forming the semiconductor pillar 104 may include: forming a first semiconductor layer 101, the structure of which is as follows: Figure 6-7 As shown, a plurality of first sub-trenches 602 extending along the first direction L1 are formed in the first semiconductor layer 101. The plurality of first sub-trenches 602 are arranged in parallel and spaced apart, and their structure is as follows. Figure 7 As shown. An insulating dielectric layer 601 is formed, which is located in the first sub-trench 602. The top surface of the insulating dielectric layer 601 is flush with the top surface of the first semiconductor layer 101, and its structure is as follows. Figure 8 As shown. A mask layer 604 is formed, located on the top surface of the first semiconductor layer 101 and the insulating dielectric layer 601. The material of the mask layer 604 may include, but is not limited to, boron nitride and silicon nitride. Furthermore, a portion of the first semiconductor layer 101 and a portion of the insulating dielectric layer 601 are removed along the mask layer 604 to form a plurality of second sub-trenches 603 extending along the second direction L2. The plurality of second sub-trenches 603 are arranged in parallel and spaced apart, and their structure is as shown. Figure 9As shown. An insulating dielectric layer 601 is formed again, located within the second sub-trench 603. The top surface of the insulating dielectric layer 601 is flush with the top surface of the first semiconductor layer 101, and its structure is as follows. Figure 10 The material of the insulating dielectric layer 601 filling the first sub-trench 602 and the second sub-trench 603 can be the same, including but not limited to SiO2.

[0062] In this embodiment, the overlapping portion of the first sub-trench 602 and the second sub-trench 603 forms multiple trenches, which are arranged in an array. A first semiconductor layer 101 located between adjacent trenches forms a semiconductor pillar 104. In this embodiment, the width of the first sub-trench 602 is smaller than the width of the second sub-trench 603. The width of the semiconductor pillar 104 along the first direction L1 is smaller than the width of the semiconductor pillar 104 along the second direction L2. Figure 1 As shown, the width of the semiconductor pillar 104 along the first direction L1 can be the portion shown as e in the figure, and the width of the semiconductor pillar 104 along the second direction L2 can be the portion shown as f in the figure. In some embodiments, the width of the first sub-trench 602 can also be greater than the width of the second sub-trench 603, and the width of the semiconductor pillar 104 along the first direction L1 is greater than the width of the semiconductor pillar 104 along the second direction L2. This ensures that the semiconductor pillar 104 is stably supported during the subsequent fabrication of the capacitor structure 200, transistor structure 300, bit line 500, and word line 400, thereby preventing collapse or tilting and improving the structural stability of the semiconductor pillar 104.

[0063] Specifically, in the semiconductor structure of this embodiment, a substrate isolation structure 102 is provided between the capacitor structure 200 and at least a portion of the semiconductor layer of the substrate 100. This substrate isolation structure 102 can effectively block contact leakage between the capacitor structure 200 and the semiconductor layer of the substrate 100. In this first embodiment, combined with... Figure 6 As shown, before forming the first semiconductor layer 101, the method further includes: forming a second semiconductor layer 103, with the first semiconductor layer 101 located on the second semiconductor layer; forming a substrate dielectric layer 1023, with the substrate dielectric layer 1023 located between the first semiconductor layer 101 and the second semiconductor layer 103; and the substrate dielectric layer 1023 forming a substrate isolation structure 102.

[0064] In a second embodiment, forming the first semiconductor layer 101 includes forming a first doped layer 1021 and a second doped layer 1022 in the first semiconductor layer 101. The second doped layer 1022 is located on the first doped layer 1021. The first doped layer 1021 and the second doped layer 1022 have different doping types. The first doped layer 1021 and the second doped layer 1022 form a substrate isolation structure 102. The first doped layer 1021 can be a P-type doped layer, which can be a low-concentration P-type doped layer. The second doped layer 1022 can be an N-type doped layer, which can be a high-concentration N-type doped layer. A PN junction is formed between the first doped layer 1021 and the second doped layer 1022 to isolate leakage current between the semiconductor layers of the capacitor structure 200 and the substrate 100.

[0065] After forming the substrate 100, the process includes: S200: forming a capacitor structure located on the substrate. It should be noted that before forming the capacitor structure 200, the process includes: etching away a portion of the insulating dielectric layer 601 to expose a portion of the semiconductor pillar 104, the structure of which is as follows... Figure 11 As shown. A portion of the semiconductor pillar 104 exposed in this step is the second extension 1042, while the mask layer 604 is retained. A support material 600 is deposited to form a support layer, where the support material 600 fills the space between adjacent bit lines 500 along the first direction L1, and does not fill the space between adjacent word lines 400 along the second direction L2, as shown in the diagram. Figure 12 As shown. The support material 600 includes, but is not limited to, materials containing nitrogen or carbon. The area between adjacent bit lines 500 is the first sub-groove 602, and the area between adjacent word lines 400 is the second sub-groove 603. In this embodiment, the width of the first sub-groove 602 is smaller than the width of the second sub-groove 603. Therefore, filling the first sub-groove 602 with support material 600 of the same thickness will not fill the second sub-groove 603.

[0066] After depositing the support material 600, a portion of the support material 600 is etched back to remove it, exposing the top surface of the mask layer 604 and simultaneously exposing the top surface of the insulating dielectric layer 601 located in the second sub-trench 603, as shown in the diagram. Figure 13 As shown. Further, the insulating dielectric layer 601 is etched back to expose the first extension 1041 of the semiconductor pillar 104, whose structure is as follows. Figure 14As shown. During the formation of the insulating dielectric layer 601, some of the Si in the first extension 1041 will be oxidized. The process of removing the insulating dielectric layer 601 will also remove the oxidized part of the first extension 1041. Therefore, the width of the first extension 1041 after this step is slightly smaller than the width of the second extension 1042. This allows for more space to be reserved for the subsequent formation of the capacitor, reducing the difficulty of capacitor fabrication and ensuring the structural stability of the capacitor.

[0067] Following the exposure of the first extension 1041, the process further includes: doping the first extension 1041 to form a conductive first extension 1041, the structure of which is as follows: Figure 15 As shown. It should be noted that during the doping process, dopant ions diffuse into part of the second extension 1042 and part of the semiconductor layer in the substrate 100. This effectively improves the electrical conductivity between the first extension 1041 and the second extension 1042. The conductive first extension 1041 can form the first electrode of the capacitor structure 200. Alternatively, after forming the conductive first extension 1041, the process further includes forming a first conductive layer 201 located in the trench, covering the conductive first extension 1041, and electrically communicating with the first extension 1041, as shown in the diagram. Figure 16 As shown. The first conductive layer 201 can also form the first electrode of the capacitor structure 200, thereby forming the first electrode of the COC (Conductive on Conductive) structure.

[0068] After forming the first electrode of the capacitor structure 200, the process further includes forming a capacitor dielectric layer 202, which is located in the trench and covers the sidewalls of the first conductive layer 201, as shown in the figure. Figure 17 As shown. The capacitor dielectric layer 202 can be made of the high dielectric constant material mentioned above, which will not be elaborated here. After forming the capacitor dielectric layer 202, the process further includes: forming a second conductive layer 203, which is located in the trench and covers the sidewalls of the capacitor dielectric layer 202. The second conductive layer 203 forms the second electrode of the capacitor structure 200, and its structure is as follows. Figure 18 As shown.

[0069] Combination Figure 5 As shown, after forming the capacitor structure 200, the process further includes: S300: forming a transistor structure, the transistor structure being located on the capacitor structure, and the source of the transistor structure being electrically connected to the capacitor structure.

[0070] Specifically, the support material 600 supporting the second extension 1042 is removed, exposing the second extension 1042 and the mask layer 604, as shown in the diagram. Figure 19As shown. An insulating dielectric layer 601 is formed, located in the trench, and covers the top surface of the capacitor structure 200 and the sidewall of the second extension 1042. The top surface of the insulating dielectric layer 601 can be flush with the top surface of the mask layer 604, and its structure is as follows. Figure 20 As shown. Part of the insulating dielectric layer 601 is etched back to expose the second extension 1042, the structure of which is as follows. Figure 21 As shown. Next, support material 600 is reformed in the trench. In this step, the support material 600 also fills the first sub-trench 602 but does not fill the second sub-trench 603. The support layer formed by the support material 600 can provide support for the exposed second extension 1042, ensuring the structural stability of the semiconductor pillar 104 during the fabrication of the transistor structure 300. Its structure is as follows. Figure 22 As shown. A portion of the insulating dielectric layer 601 is etched away along the support material 600, exposing a portion of the second extension 1042 near the first extension 1041, its structure as follows. Figure 23 As shown, in this step, since a portion of the second extension 1042 is oxidized during the formation of the insulating dielectric layer 601, the oxidized second extension 1042 is removed simultaneously during the removal of the insulating dielectric layer 601. This results in the width of the portion of the second extension 1042 near the first extension 1041 being smaller than the width of the remaining portion. The narrower second extension 1042 can form the transistor channel 302. This provides space for the subsequent gate dielectric layer 304 of the transistor, reducing the difficulty of transistor fabrication. From the substrate 100 upwards, the second extension 1042 sequentially forms the transistor source 301, channel 302, and drain 303. After this step, the gate dielectric layer 304 is formed, surrounding the outer periphery of the channel 302, and its structure is as follows. Figure 24 As shown, a gate is formed, which surrounds the outer periphery of the gate dielectric layer 304.

[0071] Combination Figure 5 As shown, after forming the transistor structure 300, the process further includes: S400: forming multiple word lines and multiple bit lines, whereby the word lines are electrically connected to the gate of the transistor structure and the bit lines are electrically connected to the drain of the transistor structure. Specifically, a third conductive layer is formed, which surrounds the outer periphery of the gate and is electrically connected to the gate, as shown in the diagram. Figure 25 As shown. A portion of the third conductive layer is etched away along the insulating dielectric layer 601, retaining mutually parallel third conductive layers extending along the second direction L2. The retained third conductive layers form word lines 400, with the structure shown below. Figure 26As shown, in this step, the third conductive layer is etched using the support material 600, which allows for self-aligned etching to form the word line 400, reducing the fabrication difficulty of the word line 400. An insulating dielectric layer 601 is then formed, filling the trench. The top surface of the insulating dielectric layer 601 in this step can be flush with the top surface of the mask layer 604, and its structure is as follows. Figure 27 As shown. The insulating dielectric layer 601 located between two adjacent word lines 400 forms a word line isolation structure 401. Subsequently, the mask layer 604, part of the insulating dielectric layer 601, and part of the support layer are removed by CMP (Chemical Mechanical Polishing). The top surfaces of the remaining support layer and insulating dielectric layer 601 are flush with the top surface of the second semiconductor segment, as shown in the diagram. Figure 28 As shown. Then, an insulating dielectric layer 601 is formed again, with the structure as shown. Figure 29 As shown, multiple bit line trenches are formed in the insulating dielectric layer 601. These trenches extend along the first direction L1 and are parallel to each other. A bit line isolation structure 501 is formed between adjacent bit line trenches in the insulating dielectric layer 601, as shown in the diagram. Figure 30 As shown. A fourth conductive layer is formed, located in the bit line trench. The top surface of the fourth conductive layer is flush with the top surface of the insulating dielectric layer 601. The fourth conductive layer forms a bit line 500, and its structure is as follows. Figure 31 As shown. After forming bit line 500, an insulating dielectric layer 601 can be formed to ensure the structural stability of bit line 500. Its structure can be as follows. Figure 2 and Figure 3 As shown.

[0072] In this embodiment, the width of the word line isolation structure 401 is not equal to the width of the bit line isolation structure 501. Since the width of the first sub-trench 602 is smaller than the width of the second sub-trench 603, the width of the word line isolation structure 401 is larger than the width of the bit line isolation structure 501. This can ensure the structural stability of the semiconductor pillar 104 during fabrication and improve the stability of the semiconductor structure.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A capacitor structure is formed on the substrate; A transistor structure is formed on the capacitor structure, and one of the source and drain of the transistor structure is electrically connected to the capacitor structure. Multiple word lines and multiple bit lines are formed, wherein the word lines are electrically connected to the gate of the transistor structure, and the bit lines are electrically connected to the source or drain of the transistor structure. Among them, a word line isolation structure is provided between two adjacent word lines, and a bit line isolation structure is provided between two adjacent bit lines. The width of the word line isolation structure is not equal to the width of the bit line isolation structure. Wherein, the width of the gap region between two adjacent bit lines is not equal to the width of the gap region between two adjacent word lines. Before forming the capacitor structure, the support material fills the narrower of the gap region between two adjacent bit lines and the gap region between two adjacent word lines, and the support material does not fill the wider of the gap region between two adjacent bit lines and the gap region between two adjacent word lines.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The substrate includes: A first semiconductor layer is formed, and a plurality of semiconductor pillars arranged in an array are formed in the first semiconductor layer. Each semiconductor pillar has a different width in a first direction and a second direction. An insulating dielectric layer is formed between adjacent semiconductor pillars. The first direction and the second direction intersect each other.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The width of the semiconductor pillar along the first direction is smaller than the width of the semiconductor pillar along the second direction.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that, Forming the first semiconductor layer includes: forming a first doped layer and a second doped layer in the first semiconductor layer, the second doped layer being located on the first doped layer, the first doped layer and the second doped layer having different doping types, and the first doped layer and the second doped layer forming a substrate isolation structure.

5. The method for preparing a semiconductor structure according to claim 2, characterized in that, Before forming the first semiconductor layer, it also includes: A second semiconductor layer is formed, wherein the first semiconductor layer is located on the second semiconductor; A substrate dielectric layer is formed, wherein the substrate dielectric layer is located between the first semiconductor layer and the second semiconductor layer; The substrate dielectric layer forms a substrate isolation structure.

6. The method for preparing a semiconductor structure according to claim 2, characterized in that, Before forming the capacitor structure, the method further includes: Etching removes a portion of the insulating dielectric layer, exposing a portion of the semiconductor pillar; The support material is deposited to form a support layer, wherein the support material fills the space between adjacent bit lines along the first direction, and the support material does not fill the space between adjacent word lines along the second direction.

7. A semiconductor structure, characterized in that, Obtained by the fabrication method according to claim 1, the structure includes a substrate, a capacitor structure, a transistor structure, multiple bit lines, and multiple word lines; the capacitor structure is disposed on the substrate, the transistor structure is disposed on the side of the capacitor structure away from the substrate, one of the source and drain of the transistor structure is electrically connected to the capacitor structure, the gate of the transistor structure is electrically connected to the word lines, and the other of the source and drain of the transistor structure is electrically connected to the bit lines; A word line isolation structure is provided between two adjacent word lines, and a bit line isolation structure is provided between two adjacent bit lines; The width of the word line isolation structure is not equal to the width of the bit line isolation structure.

8. The semiconductor structure according to claim 7, characterized in that, The width of the word line isolation structure is greater than the width of the bit line isolation structure.

9. The semiconductor structure according to claim 8, characterized in that, The width of the word line is greater than the width of the bit line.

10. The semiconductor structure according to claim 9, characterized in that, The width of the word line is 1 / 3 to 3 / 2 larger than the width of the bit line.

11. The semiconductor structure according to claim 7, characterized in that, The width of the bit line isolation structure is greater than the width of the word line isolation structure.

12. The semiconductor structure according to claim 11, characterized in that, The width of the bit line is greater than the width of the word line.

13. The semiconductor structure according to any one of claims 7-12, characterized in that, The substrate includes a semiconductor layer and a substrate isolation structure, the substrate isolation structure being located between the capacitor structure and at least a portion of the semiconductor layer.

14. The semiconductor structure according to claim 13, characterized in that, The substrate includes a first semiconductor layer, and a substrate isolation structure is disposed between the first semiconductor layer and the capacitor structure, with the capacitor structure in contact with the substrate isolation structure. The substrate isolation structure includes a first doped layer and a second doped layer stacked together, wherein the first doped layer and the second doped layer have different doping types.

15. The semiconductor structure according to claim 13, characterized in that, The substrate includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is stacked on the second semiconductor layer, a substrate dielectric layer is disposed between the first semiconductor layer and the second semiconductor layer, and the capacitor structure is in contact with the first semiconductor layer. The substrate dielectric layer forms the substrate isolation structure.

16. The semiconductor structure according to any one of claims 7-12, characterized in that, The capacitor structure includes multiple capacitors, which are arranged in an array.

17. The semiconductor structure according to claim 16, characterized in that, The transistor structure includes multiple transistors arranged in an array; each of the multiple transistors is corresponding to one of the multiple capacitors.

18. The semiconductor structure according to claim 17, characterized in that, The transistor includes a gate and a semiconductor pillar extending in a vertical direction; in the direction upward from the substrate, the semiconductor pillar sequentially includes a source, a channel, and a drain; the gate has a ring structure and surrounds the outer periphery of the channel; A gate dielectric layer is disposed between the gate and the channel.

19. The semiconductor structure according to any one of claims 7-12, characterized in that, The word line surrounds the outer periphery of the gate of the transistor structure, and the bit line is disposed on the side of the transistor structure away from the substrate.

20. The semiconductor structure according to any one of claims 7-12, characterized in that, The multiple bit lines extend along a first direction, and the multiple word lines extend along a second direction, with the first direction and the second direction intersecting each other.

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