A start-up ensured bandgap reference circuit

Abstract

The application discloses a band-gap reference circuit ensuring starting, which comprises a starting and biasing circuit. In the operational amplifier current source biasing circuit, all MOS devices work in the strong reverse type region; the sixth PMOS tube is a current mirror tube and is used for forming a current mirror with a current source device in a PTAT operational amplifier; a gate of the sixth PMOS tube generates a biasing voltage and is used for biasing the current source device in the PTAT operational amplifier; and a gate of the ninth NMOS tube is biased by a reference voltage output by the band-gap reference circuit. In the low-cost starting circuit, the tenth NMOS tube and the ninth NMOS tube are connected in parallel and have the same parameters; a gate of the tenth NMOS tube is connected with a gate of the eleventh NMOS tube and a source of the twelfth NMOS tube. The application can ensure that the whole band-gap reference circuit starts normally and improves the starting reliability of the band-gap reference circuit under the condition of process deviation.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a bandgap reference voltage source. Background Technology

[0002] A bandgap voltage reference, also known as a bandgap reference circuit, is a voltage reference circuit widely used in integrated circuits. It generates a fixed voltage that is independent of power supply variations, temperature changes, and circuit load. The bandgap, also known as the energy gap, refers to the energy difference between the lowest point of the conduction band and the highest point of the valence band in a semiconductor or insulator.

[0003] Traditional bandgap reference circuits require at least two BJTs (bipolar junction transistors), each located in a separate branch. A single-BJT bandgap reference circuit, on the other hand, uses only one BJT to perform the functions of a traditional bandgap reference circuit. In standard CMOS processes, BJTs occupy a relatively large area; therefore, a single-BJT bandgap reference circuit can significantly save chip area and power consumption.

[0004] Please see Figure 1This is an existing single-BJT bandgap reference circuit, including a bandgap reference core circuit 1 and a bias circuit 2. In the bandgap reference core circuit 1, a first PMOS transistor P1, a second resistor R2, a first resistor R1, and a diode-connected transistor Q1 are cascaded sequentially between the power supply voltage VDD and ground VSS. A diode-connected transistor is one whose gate and drain are shorted. The drain of the first PMOS transistor P1 outputs a reference voltage Vref, which serves as the reference voltage generated by the entire bandgap reference circuit. A second diode-connected PMOS transistor P2 and a first NMOS transistor N1 are also cascaded sequentially between the power supply voltage VDD and ground VSS. The two input terminals VA and VB of the PTAT (proportional to absolute temperature) op-amp OTA are connected to the two ends of the first resistor R1, and the output terminal VO of the PTAT op-amp OTA is connected to the gate of the first NMOS transistor N1. In the bias circuit 2, a diode-connected third PMOS transistor P3, a fourth NMOS transistor N4, a third NMOS transistor N3, and a diode-connected second NMOS transistor N2 are cascaded sequentially between the power supply voltage VDD and ground VSS. The gate of the third PMOS transistor P3 outputs a bias voltage Vbias. The gate of the fourth NMOS transistor N4 is connected to the drain of the first PMOS transistor P1. The gate of the third NMOS transistor N3 is connected to the inverting input VB of the PTAT operational amplifier OTA. Both the second NMOS transistor N2 and the third NMOS transistor N3 are biased in the subthreshold region.

[0005] Please see Figure 2 This is a specific circuit structure of an existing PTAT op-amp. The power supply voltage VDD is connected to the current source device P0. The gate of the current source device P0 is connected to the bias voltage Vbias, providing a stable current for the entire PTAT op-amp, serving as its current source. Between the current source device P0 and ground VSS, a fourth PMOS transistor P4, a diode-connected eighth NMOS transistor N8, and a diode-connected sixth NMOS transistor N6 are cascaded in sequence. Also cascaded between the current source device P0 and ground VSS are a fifth PMOS transistor P5, a seventh NMOS transistor N7, and a fifth NMOS transistor N5. The gate of the fourth PMOS transistor P4 serves as the inverting input VB of the PTAT op-amp. The gate of the fifth PMOS transistor P5 serves as the non-inverting input VA of the PTAT op-amp. The drain of the seventh NMOS transistor N7 serves as the output VO of the PTAT op-amp. The gate of the eighth NMOS transistor N8 is connected to the gate of the seventh NMOS transistor N7. The gate of the sixth NMOS transistor N6 is connected to the gate of the fifth NMOS transistor N5.

[0006] Figure 1In the middle, the bias circuit 2 uses two MOS transistors N2 and N3 biased in the subthreshold region to provide a weak subthreshold current, and injects it into the PTAT op-amp OTA in the bandgap reference core circuit 1, which can raise the output potential of the PTAT op-amp OTA and start the entire bandgap reference circuit loop.

[0007] Figure 1 In this context, the overdrive voltage of the first NMOS transistor N1 is the gate voltage of N1 minus its threshold voltage. The overdrive voltage of N1 determines the current magnitude of the cascaded branch between the second PMOS transistor P2 and the first NMOS transistor N1. To minimize current consumption in this branch, the first NMOS transistor N1 is typically a device with a high threshold voltage.

[0008] Figure 1 The single BJT bandgap reference circuit shown has the following drawbacks.

[0009] First, the initial current injected by MOS transistors N2 and N3, biased in the subthreshold region, into the PTAT operational amplifier OTA is very weak. During integrated circuit mass production, when process deviations lead to… Figure 2 When the leakage current of the seventh NMOS transistor N7 at the output terminal of the PTAT op-amp is greater than the leakage current of the fifth PMOS transistor P5 above, the output potential of the PTAT op-amp OTA may be clamped to a potential lower than that required for subsequent startup, which will cause the entire bandgap reference circuit to fail to start up.

[0010] Second, the current of a MOSFET operating in the subthreshold region exhibits exponential characteristics. Therefore, the current in bias circuit 2 will change significantly with variations in temperature and process corner. This change is transmitted to the PTAT op-amp OTA, affecting the PTAT voltage clamped at a pair of input terminals of the PTAT op-amp OTA, and ultimately affecting the temperature drift and absolute value of the reference voltage output by the bandgap reference circuit. This is described in the article "ASingle BJT Bandgap Reference With Frequency Compensation Exploiting MirrorPole" (hereinafter referred to as Reference 1) published by Myungjun Kim and SeongHwan Cho in the October 2021 issue of IEEE Journal of Solid-State Circuits, Volume 56, Issue 10.

[0011] Third, during on-chip integration, when most devices in the circuit are normal threshold voltage devices, using a separate high threshold voltage device is detrimental to matching and design rule considerations during layout drawing. This high threshold voltage device needs to maintain a spatial distance of at least several micrometers from the normal threshold voltage devices, which increases the difficulty of layout design. More importantly, this distance becomes very sensitive in smaller-size advanced process applications, increasing the overall chip layout area and raising chip manufacturing costs. Summary of the Invention

[0012] The technical problem to be solved by this invention is: how to enhance the startup reliability of the bandgap reference circuit, optimize the temperature drift of the output reference voltage, reduce the chip area, and reduce the difficulty of layout design.

[0013] To address the aforementioned technical problems, this invention proposes a bandgap reference circuit that ensures startup. The bandgap reference circuit includes startup and bias circuits; the startup and bias circuits further include an operational amplifier current source bias circuit and a low-cost startup circuit. In the operational amplifier current source bias circuit, a diode-connected sixth PMOS transistor, a ninth NMOS transistor, and a third resistor are cascaded sequentially between the power supply voltage and ground; all MOS devices operate in the strong inversion region; the sixth PMOS transistor is a current mirror transistor, forming a current mirror with the current source device in the PTAT operational amplifier; the gate of the sixth PMOS transistor generates a bias voltage to bias the current source device in the PTAT operational amplifier; the gate of the ninth NMOS transistor is biased by the reference voltage output from the bandgap reference circuit. In the low-cost startup circuit, a diode-connected seventh PMOS transistor, a diode-connected twelfth NMOS transistor, and a diode-connected eleventh NMOS transistor are cascaded sequentially between the power supply voltage and ground, and a tenth NMOS transistor is also included; the tenth NMOS transistor and the ninth NMOS transistor are connected in parallel and have the same parameters; the gate of the tenth NMOS transistor is connected to the gate of the eleventh NMOS transistor and the source of the twelfth NMOS transistor.

[0014] Furthermore, the seventh PMOS transistor, the twelfth NMOS transistor, and the eleventh NMOS transistor form a startup branch. After the bandgap reference circuit is powered on, the current in this startup branch remains constant. When the bandgap reference circuit is first powered on, the output reference voltage is insufficient to turn on the ninth NMOS transistor to supply power to the PTAT op-amp. Since the gate potential of the other parallel tenth NMOS transistor is clamped to a conducting state by the eleventh NMOS transistor in the startup branch, the op-amp current source bias circuit remains conducting through the bypass of the tenth NMOS transistor. In this way, the op-amp current source bias circuit can output a bias voltage, which generates current and injects it into the entire bandgap reference circuit loop, thus starting the entire bandgap reference circuit.

[0015] Furthermore, after the bandgap reference circuit is started, the output reference voltage turns on the ninth NMOS transistor. Since the gate voltage of the ninth NMOS transistor is higher than that of the tenth NMOS transistor, the tenth NMOS transistor is almost in the off state, and almost all the current flows through the ninth NMOS transistor. At this time, the low-cost startup circuit no longer acts on the operational amplifier current source bias circuit.

[0016] Alternatively, the third resistor can be replaced with a diode-connected transistor.

[0017] Alternatively, the sixth PMOS transistor can be replaced with a common-source, common-gate current mirror structure.

[0018] Alternatively, the seventh PMOS transistor and the twelfth NMOS transistor can be replaced with resistors.

[0019] Furthermore, the PTAT operational amplifier is a low-voltage output PTAT operational amplifier, and its specific circuit structure is as follows: the power supply voltage is connected to a current source device; the gate of the current source device is connected to a bias voltage to provide current for the entire PTAT operational amplifier, which is equivalent to a current source; a fourth PMOS transistor, an eighth NMOS transistor, and a sixth NMOS transistor are cascaded in sequence between the current source device and ground; a fifth PMOS transistor, a seventh NMOS transistor, and a fifth NMOS transistor are also cascaded in sequence; the gates of the fourth PMOS transistor and the fifth PMOS transistor serve as a pair of input terminals of the PTAT operational amplifier; the drain of the seventh NMOS transistor serves as the output terminal of the PTAT operational amplifier; the gate of the eighth NMOS transistor is connected to the gate of the seventh NMOS transistor and is also connected to a voltage provided by an external circuit; the gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor and is also connected to the drain of the eighth NMOS transistor.

[0020] Furthermore, in the low-voltage output PTAT operational amplifier, the minimum voltage at the output terminal is the sum of the overdrive voltage of the fifth NMOS transistor and the overdrive voltage of the seventh NMOS transistor.

[0021] Furthermore, the first NMOS transistor connected to the output terminal of the PTAT operational amplifier is changed from a high threshold voltage device to a normal threshold voltage device.

[0022] Furthermore, the threshold voltage of the first NMOS transistor is reduced, the gate voltage of the first NMOS transistor is also reduced, and the overdrive voltage of the first NMOS transistor remains basically unchanged.

[0023] The technical effects achieved by this invention are as follows: (1) A new startup and bias circuit is designed to ensure the normal startup of the entire bandgap reference circuit, thereby improving the startup reliability of the bandgap reference circuit under process deviation conditions. (2) No MOS transistors operating in the subthreshold region are used in the startup and bias circuit, reducing the temperature drift of the output voltage of the bandgap reference circuit. (3) High threshold voltage devices are no longer used, which enhances the circuit startup capability, reduces the difficulty of layout design, reduces chip area, reduces chip power consumption, and reduces chip manufacturing cost. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of an existing bandgap reference circuit.

[0025] Figure 2 This is a schematic diagram of an existing PTAT op-amp.

[0026] Figure 3 This is a schematic diagram of the startup and bias circuit of the bandgap reference circuit that ensures startup proposed in this invention.

[0027] Figure 4 This is a schematic diagram of the low-voltage output PTAT operational amplifier in the bandgap reference circuit for ensuring startup proposed in this invention.

[0028] The attached diagrams are as follows: 1 is the core circuit of the bandgap reference, 2 is the bias circuit, 3 is the operational amplifier current source bias circuit, and 4 is the low-cost startup circuit. Detailed Implementation

[0029] Please see Figure 3 The start-up and bias circuit of the bandgap reference circuit proposed in this invention includes an operational amplifier current source bias circuit 3 and a low-cost start-up circuit 4. Figure 3 The startup and bias circuit shown is used to replace Figure 1 Bias circuit 2 in the middle.

[0030] In the operational amplifier current source bias circuit 3, a diode-connected sixth PMOS transistor P6, a ninth NMOS transistor N9, and a third resistor R3 are cascaded sequentially between the power supply voltage VDD and ground VSS. The third resistor R3 can be replaced by a diode-connected transistor. The source of the ninth NMOS transistor N9 is grounded to VSS through the third resistor R3. The gate of the ninth NMOS transistor N9 is biased by the reference voltage Vref output from the bandgap reference circuit. The drain of the ninth NMOS transistor N9 is connected to the drain of the sixth PMOS transistor P6. The gate and drain of the sixth PMOS transistor P6 are shorted, generating a bias voltage Vbias. The source of the sixth PMOS transistor P6 is connected to the power supply voltage VDD. In the operational amplifier current source bias circuit 3, all MOS devices operate in the strong inversion region, and their current changes follow a square law. Compared with MOS devices operating in the subthreshold region, they are less sensitive to temperature changes. Therefore, the operational amplifier current source bias circuit 3 used in this invention has less impact on the temperature characteristics of the bandgap reference circuit and can optimize the temperature drift of the reference voltage output by the bandgap reference circuit.

[0031] In the operational amplifier current source bias circuit 3, the sixth PMOS transistor P6 is a current mirror transistor, forming a current mirror with the current source device P0 in the PTAT operational amplifier. Alternatively, the sixth PMOS transistor P6 can be replaced with other current mirror structures, such as a cascode current mirror. The bias voltage Vbias generated by the operational amplifier current source bias circuit 3 is used to bias the current source device P0 in the PTAT operational amplifier. Specifically, the operational amplifier current source bias circuit 3 itself can obtain a specific current through parameter setting, and then the current flows through the uppermost current mirror transistor—that is... Figure 3 The sixth PMOS transistor P6 in the circuit replicates the current to the PTAT op-amp, thus powering the PTAT op-amp. In this way, the present invention replaces the existing MOS transistor biased in the subthreshold region with the op-amp current source bias circuit 3 to power the PTAT op-amp in the single BJT bandgap reference circuit.

[0032] In the low-cost startup circuit 4, a diode-connected seventh PMOS transistor P7, a diode-connected twelfth NMOS transistor N12, and a diode-connected eleventh NMOS transistor N11 are cascaded sequentially between the power supply voltage VDD and ground VSS. A tenth NMOS transistor N10 is also included. Both the seventh PMOS transistor P7 and the twelfth NMOS transistor N12 are diode-connected and can be replaced with resistors, but diode-connected transistors occupy less chip area. The source of the tenth NMOS transistor N10 is connected to the source of the ninth NMOS transistor N9. The drain of the tenth NMOS transistor N10 is connected to the drain of the ninth NMOS transistor N9. Therefore, the tenth NMOS transistor N10 and the ninth NMOS transistor N9 are connected in parallel. The gate of the tenth NMOS transistor N10 is connected to the drain of the eleventh NMOS transistor N11 and the source of the twelfth NMOS transistor N12. The gate and drain of the eleventh NMOS transistor N11 are shorted, and its source is grounded to VSS. The drain of the twelfth NMOS transistor N12 is connected to the drain of the seventh PMOS transistor P7. The source of the seventh PMOS transistor P7 is connected to the power supply voltage VDD.

[0033] The low-cost startup circuit 4 operates as follows: three diode-connected (resistive) MOS devices—the seventh PMOS transistor P7, the twelfth NMOS transistor N12, and the eleventh NMOS transistor N11—are cascaded between the power supply voltage VDD and ground VSS to form a startup branch. After power-on, the current in this startup branch remains constant. Because the diode-connected devices have relatively large resistances and small areas, the constant current in this startup branch can be designed to be in the nA (nanoampere) range, resulting in low power consumption. The key startup transistor is the tenth NMOS transistor N10. The parameters of the tenth NMOS transistor N10 are consistent with those of the ninth NMOS transistor N9 in the op-amp current source bias circuit 3, and the two are connected in parallel. The ninth NMOS transistor N9 and the tenth NMOS transistor N10 form a configuration similar to the input pair in an op-amp. The gate of the tenth NMOS transistor N10 is connected to the gate of the eleventh NMOS transistor N11. Even when the reference voltage Vref is very low upon power-up, insufficient to turn on the ninth NMOS transistor N9 to power the PTAT op-amp in the bandgap reference circuit, the gate potential of the other parallel tenth NMOS transistor N10 is clamped to an on state by the eleventh NMOS transistor N11 in the startup branch, allowing the op-amp current source bias circuit 3 to remain conducting through the bypass of the tenth NMOS transistor N10. This allows the op-amp current source bias circuit 3 to output a bias voltage Vbias, which generates a large stable current that is injected into the entire bandgap reference circuit loop. This stable current is much larger than... Figure 2 The leakage current of the seventh NMOS transistor N7 at the output terminal of the PTAT operational amplifier. During integrated circuit mass production, when process deviations lead to... Figure 2When the leakage current of the seventh NMOS transistor N7 at the output of the PTAT op-amp is greater than the leakage current of the fifth PMOS transistor P5 above it, this larger stable current can overcome this leakage current imbalance and allow the entire bandgap reference circuit to start up smoothly. In this way, the reference voltage Vref output by the bandgap reference circuit is at its normal value, the gate bias of the ninth NMOS transistor N9 returns to its normal value, and the ninth NMOS transistor N9 is turned on. After the ninth NMOS transistor N9 is turned on, because its gate voltage Vref is much higher than that of the tenth NMOS transistor N10, the tenth NMOS transistor N10 is almost in the off state. Figure 3 In the circuit shown, almost all the current flows through the ninth NMOS transistor N9. During startup, the total current flowing through the sixth PMOS transistor P6 (i.e., the current mirror transistor) remains constant, thus not affecting the current output to the PTAT op-amp. After the bandgap reference circuit has started and is operating normally, the low-cost startup circuit 4 no longer acts on the op-amp current source bias circuit 3.

[0034] Please see Figure 4 This is the specific circuit structure of the PTAT op-amp in the bandgap reference circuit for ensuring startup proposed in this invention, which features a low-voltage output. The power supply voltage VDD is connected to the current source device P0. The gate of the current source device P0 is connected to the bias voltage Vbias, providing current to the entire PTAT op-amp, essentially acting as a current source. A fourth PMOS transistor P4, an eighth NMOS transistor N8, and a sixth NMOS transistor N6 are cascaded sequentially between the current source device P0 and ground VSS. A fifth PMOS transistor P5, a seventh NMOS transistor N7, and a fifth NMOS transistor N5 are also cascaded sequentially between the current source device P0 and ground VSS. The gate of the fourth PMOS transistor P4 serves as the inverting input VB of the PTAT op-amp. The gate of the fifth PMOS transistor P5 serves as the non-inverting input VA of the PTAT op-amp. The drain of the seventh NMOS transistor N7 serves as the output VO of the PTAT op-amp. The gate of the eighth NMOS transistor N8 is connected to the gate of the seventh NMOS transistor N7 and also to the voltage VB2 provided by an external circuit. The external circuit has a small area and low power consumption, and has almost no impact on the temperature drift of the bandgap reference output. The gate of the sixth NMOS transistor N6 is connected to the gate of the fifth NMOS transistor N5, and also to the drain of the eighth NMOS transistor N8.

[0035] Figure 4 The low-voltage output PTAT op-amp shown is used to replace Figure 2 The existing PTAT op-amps shown are identical in composition, differing only in their interconnections—primarily the sixth NMOS transistor N6 and the eighth NMOS transistor N8. Figure 2 and Figure 4In each case, the common-source cascode current mirror is composed of the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8. Figure 2 In the PTAT op-amp, the minimum output voltage at the output terminal VO is the overdrive voltage of the fifth NMOS transistor N5 + the overdrive voltage of the seventh NMOS transistor N7 + the threshold voltage of the seventh NMOS transistor N7. Figure 4 In the PTAT op-amp, the minimum output voltage at the output terminal VO is the sum of the overdrive voltage of the fifth NMOS transistor N5 and the overdrive voltage of the seventh NMOS transistor N7. The overdrive voltage of the MOS transistors is the gate-source voltage Vgs minus the threshold voltage Vth. Figure 4 The PTAT op-amp shown is Figure 2 Compared to the PTAT op-amp shown, the minimum output voltage is reduced by the threshold voltage of the seventh NMOS transistor N7, hence the name. Figure 4 The image shows a PTAT op-amp with low-voltage output. Figure 4 and Figure 2 In comparison, only the common-source cascode current mirror formed by the four NMOS transistors N5-N8 at the bottom is changed; the input pair P4 and P5 at the top remain unchanged. Therefore, the PTAT characteristic of the PTAT voltage between the gates of this pair of input transistors (i.e., the pair of input terminals of the PTAT op-amp) remains unchanged. As shown in Reference 1, by using the PTAT voltage with the unchanged PTAT characteristic and canceling it out with the BJT's own CTAT (counter proportional to absolute temperature) voltage, a zero-temperature coefficient output voltage Vref is obtained, which will not affect the temperature drift of the reference voltage Vref output by the bandgap reference circuit.

[0036] Please see Figure 1 In existing single-BJT bandgap reference circuits, the output of the PTAT op-amp OTA is connected to the gate of the first NMOS transistor N1. The first NMOS transistor N1 typically uses a high threshold voltage device to reduce the current in its branch. This invention, while maintaining the same connection relationship, replaces the first NMOS transistor N1 with a common threshold voltage device, still maintaining a substantially constant current in the branch containing the first NMOS transistor N1. This is because this invention not only reduces the threshold voltage of the first NMOS transistor N1 but also simultaneously reduces its gate voltage (i.e., the output voltage of the low-voltage output PTAT op-amp). Therefore, the overdrive voltage of the first NMOS transistor N1 remains constant, thereby keeping the current in the branch containing the first NMOS transistor N1 constant and maintaining low power consumption.

[0037] Compared with the prior art, the bandgap reference circuit for ensuring startup proposed in this invention has the following beneficial effects.

[0038] First, the present invention employs... Figure 3 The startup and bias circuit shown replaces the existing bias circuit, avoiding startup failures caused by process variations at a lower cost. It ensures successful startup of the bandgap reference circuit even in the context of process variations during integrated circuit mass production. Furthermore, the startup and bias circuit of this invention does not use MOS transistors operating in the subthreshold region; instead, all MOS transistors operate in the strong inversion region, thereby improving the temperature characteristics of the bandgap reference circuit and significantly reducing temperature drift.

[0039] Second, the present invention changes the first NMOS transistor N1 connected to the output terminal of the PTAT operational amplifier from a high threshold voltage device to a normal threshold voltage device, which is beneficial to the startup of the entire bandgap reference circuit loop. Figure 1 The existing bandgap reference circuit fails to start up because the gate voltage required for N1 is too high. When process variations cause the PTAT op-amp to clamp the output voltage to a lower potential, the branch containing N1 cannot start up properly, and it cannot mirror current to the P1 branch. As a result, the output voltage Vref of the bandgap reference circuit remains low, failing to start up correctly. This invention uses N1 with a standard threshold voltage, thus reducing the startup difficulty of the entire bandgap reference circuit loop. Furthermore, the absence of high threshold voltage devices in the circuit simplifies layout design, reduces chip area, lowers chip power consumption, and consequently reduces manufacturing costs.

[0040] Third, this invention employs Figure 4 The low-voltage output PTAT op-amp shown replaces the existing PTAT op-amp. By replacing the first NMOS transistor N1 connected to the output terminal of the PTAT power amplifier with a common threshold voltage device, it can be ensured that the overdrive voltage of N1 remains basically unchanged, thereby keeping the current and power consumption of the branch where N1 is located basically unchanged.

[0041] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A start-up ensured bandgap reference circuit, characterized by, The bandgap reference circuit comprises a start-up and bias circuit; the start-up and bias circuit further comprises an operational amplifier current source bias circuit and a low-cost start-up circuit; In the operational amplifier current source bias circuit, a diode-connected sixth PMOS tube, a ninth NMOS tube and a third resistor are connected in series between a power supply voltage and ground; the sixth PMOS tube and the ninth NMOS tube both work in a strong inverse type region; the sixth PMOS tube is a current mirror tube and forms a current mirror with a current source device in a PTAT operational amplifier; a gate of the sixth PMOS tube generates a bias voltage for biasing the current source device in the PTAT operational amplifier; A gate of the ninth NMOS tube is biased by a reference voltage output by the bandgap reference circuit; In the low-cost start-up circuit, a diode-connected seventh PMOS tube, a diode-connected twelfth NMOS tube and a diode-connected eleventh NMOS tube are connected in series between the power supply voltage and the ground, and a tenth NMOS tube is further included; the tenth NMOS tube and the ninth NMOS tube are connected in parallel and have the same parameters; a gate of the tenth NMOS tube is connected to a gate of the eleventh NMOS tube and a source of the twelfth NMOS tube.

2. The start-up ensured bandgap reference circuit of claim 1, wherein, The seventh PMOS tube, the twelfth NMOS tube and the eleventh NMOS tube form a start-up branch, and a current in the start-up branch remains constant after the bandgap reference circuit is powered on; the reference voltage output by the bandgap reference circuit when the bandgap reference circuit is powered on is not enough to turn on the ninth NMOS tube to supply power to the PTAT operational amplifier; the gate potential of the tenth NMOS tube in parallel is clamped to an on state by the eleventh NMOS tube in the start-up branch, so that the operational amplifier current source bias circuit remains on through the bypass of the tenth NMOS tube; in this way, the operational amplifier current source bias circuit can output a bias voltage, the bias voltage generates a current, and the current is injected into the entire bandgap reference circuit loop to start the entire bandgap reference circuit.

3. The start-up ensured bandgap reference circuit of claim 2, wherein, After the bandgap reference circuit is started, the reference voltage output by the bandgap reference circuit turns on the ninth NMOS tube; since the gate voltage of the ninth NMOS tube is higher than the gate voltage of the tenth NMOS tube, the tenth NMOS tube is almost in an off state, and almost all the current flows through the ninth NMOS tube; at this time, the low-cost start-up circuit no longer acts on the operational amplifier current source bias circuit.

4. The start-up ensured bandgap reference circuit of claim 1, wherein, The third resistor is replaced by a diode-connected transistor.

5. The start-up ensured bandgap reference circuit of claim 1, wherein, The sixth PMOS tube is replaced by a common-source and common-gate current mirror structure.

6. The start-up ensured bandgap reference circuit of claim 1, wherein, The seventh PMOS tube and the twelfth NMOS tube are both replaced by resistors.

7. The start-up ensured bandgap reference circuit of claim 1, wherein, The PTAT operational amplifier is a low-voltage output PTAT operational amplifier, and the specific circuit structure is: a current source device is connected to a power supply voltage; a gate of the current source device is connected to a bias voltage to provide a current for the whole PTAT operational amplifier; a fourth PMOS tube, an eighth NMOS tube and a sixth NMOS tube are connected in sequence between the current source device and the ground; a fifth PMOS tube, a seventh NMOS tube and a fifth NMOS tube are also connected in sequence; a gate of the fourth PMOS tube and a gate of the fifth PMOS tube serve as a pair of input terminals of the PTAT operational amplifier; a drain of the seventh NMOS tube serves as an output terminal of the PTAT operational amplifier; a gate of the eighth NMOS tube is connected to a gate of the seventh NMOS tube and also connected to a voltage provided by an external circuit; a gate of the sixth NMOS tube is connected to a gate of the fifth NMOS tube and also connected to a drain of the eighth NMOS tube.

8. The start-up ensured bandgap reference circuit of claim 7, wherein, In the low-voltage output PTAT operational amplifier, the minimum voltage of the output terminal is the sum of the overdrive voltage of the fifth NMOS tube and the overdrive voltage of the seventh NMOS tube.

9. The start-up ensured bandgap reference circuit of claim 1, wherein, The first NMOS tube connected to the output terminal of the PTAT operational amplifier is changed from a high-threshold voltage device to a common threshold voltage device.

10. The start-up ensured bandgap reference circuit of claim 9, wherein, The threshold voltage of the first NMOS tube is lowered, the gate voltage of the first NMOS tube is also lowered, and the overdrive voltage of the first NMOS tube remains basically unchanged.

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