Semiconductor devices and their fabrication methods

Abstract

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes a substrate, a gate structure, a dielectric layer, a plug hole, a plug spacer wall, a metal silicide layer, and a plug. The gate structure is disposed on the substrate, and the plug hole is disposed within the dielectric layer and partially extends into the substrate. The plug spacer wall is disposed on the sidewall of the plug hole and exposes the substrate. The metal silicide layer is disposed at the bottom of the plug hole, wherein a portion of the substrate is sandwiched between the metal silicide layer and the plug spacer wall. The plug is disposed within the plug hole and physically contacts a portion of the substrate. Thus, by accurately positioning the formation location and depth of the metal silicide layer through the placement of the plug spacer wall, the performance of the semiconductor device is improved.

Description

Technical Field

[0001] This invention generally relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having a plug structure and a method for manufacturing the same. Background Technology

[0002] In existing metal-oxide-semiconductor transistor (MOS) fabrication processes, contact plugs are typically formed to electrically connect the transistor's gate and source / drain to the circuit. These contact plugs are usually made of metals such as tungsten, aluminum, or copper, while the gate and source / drain are made of materials such as polycrystalline silicon or monocrystalline silicon. However, the conductivity between these metal materials and polycrystalline or monocrystalline silicon is not ideal. To improve the ohmic contact between the contact plug and the gate and source / drain, the industry has proposed forming an additional metal silicide between the contact plug and the gate and source / drain. However, further improvements are needed in the related fabrication processes and designs to effectively enhance the structural reliability and operational performance of the semiconductor devices. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and its manufacturing method, wherein an additional plug gap wall is provided on the sidewall of the plug hole to accurately position the formation location and depth of the metal silicide layer, thereby improving the performance of the semiconductor device.

[0004] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device including a substrate, a gate structure, a dielectric layer, a plug hole, a plug spacer wall, a metal silicide layer, and a plug. The gate structure is disposed on the substrate. The dielectric layer is disposed on the substrate and covers the gate structure. The plug hole is disposed within the dielectric layer and partially extends into the substrate. The plug spacer wall is disposed on the sidewall of the plug hole and exposes a portion of the substrate. The metal silicide layer is disposed at the bottom of the plug hole, wherein the portion of the substrate is sandwiched between the metal silicide layer and the plug spacer wall. The plug is disposed within the plug hole and physically contacts the portion of the substrate.

[0005] Optionally, the sidewalls of the metal silicide layer are flush with the sidewalls of the plug gap wall.

[0006] Optionally, the metal silicide layer may include a discontinuous structure.

[0007] Optionally, the size of the metal silicide layer in the horizontal direction gradually decreases with increasing depth.

[0008] Optionally, the plug gap wall does not directly contact the metal silicide layer.

[0009] Optionally, the vertical sidewall of the plug simultaneously makes physical contact with the substrate of the portion and the plug gap wall.

[0010] Optionally, the gate structure includes: a stacked layer structure; and a gate gap wall disposed on the sidewall of the stacked layer structure and located on one side of the plug gap wall.

[0011] Optionally, the metal silicide layer includes cobalt silicide, cobalt disilicide, titanium silicide, or nickel silicide.

[0012] Optionally, it further includes: doped regions disposed within the substrate and located on opposite sides of the gate structure, wherein the plug physically contacts the doped regions.

[0013] To achieve the above objectives, one embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: providing a substrate, forming a gate structure on the substrate; forming a dielectric layer on the substrate to cover the gate structure; forming a plug hole within the dielectric layer, the plug hole partially extending into the substrate; forming a plug gap wall on the sidewall of the plug hole, exposing a portion of the substrate; forming a metal silicide layer at the bottom of the plug hole, wherein the portion of the substrate is sandwiched between the metal silicide layer and the plug gap wall; and forming a plug within the plug hole.

[0014] Optionally, before forming the metal silicide layer, the method further includes: forming doped regions in the substrate, located on opposite sides of the gate structure; and forming vias in the dielectric layer to expose portions of the doped regions.

[0015] Optionally, forming the metal silicide layer includes: performing a metal silicide fabrication process to form a metal silicide material layer.

[0016] Optionally, the metal silicide fabrication process includes: performing a selective epitaxial growth process to form a metal layer within the via; and reacting the metal layer to generate the metal silicide material layer.

[0017] Optionally, the metal silicide fabrication process includes: performing a deposition process to form a metal layer; reacting the metal layer to generate the metal silicide material layer; and removing the unreacted metal layer after the metal silicide material layer is formed.

[0018] Optionally, it further includes: after the metal silicide fabrication process, partially removing the metal silicide material layer to form the plug hole and the metal silicide layer located at the bottom of the plug hole, wherein the upper half of the plug hole overlaps the perforation.

[0019] Optionally, it also includes: depositing a material layer in the perforation prior to performing the metallization fabrication process; and partially removing the material layer to form the plug gap wall on the sidewall of the perforation.

[0020] Optionally, the plug gap wall does not directly contact the metal silicide layer.

[0021] Optionally, forming a gate structure on the substrate includes: forming a stacked layer structure on the substrate; and forming a gate gap wall located on a sidewall of the stacked layer structure and on one side of the plug gap wall.

[0022] Optionally, the size of the metal silicide layer in the horizontal direction gradually decreases with increasing depth.

[0023] Optionally, the sidewalls of the metal silicide layer are flush with the sidewalls of the plug gap wall. Attached Figure Description

[0024] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0025] Figure 1 The diagram shown is a cross-sectional schematic of a semiconductor device according to an embodiment of the present invention.

[0026] Figures 2 to 7 A schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention is shown; wherein:

[0027] Figure 2 This is a schematic cross-sectional view of a semiconductor device after the dielectric layer has been formed.

[0028] Figure 3 This is a schematic cross-sectional view of a semiconductor device after the plug hole has been formed.

[0029] Figure 4 This is a schematic cross-sectional view of a semiconductor device after the material layer has been formed.

[0030] Figure 5 This is a cross-sectional view of a semiconductor device after an etch-back fabrication process.

[0031] Figure 6 This is a cross-sectional view of a semiconductor device after the metallization fabrication process; and

[0032] Figure 7 This is a cross-sectional schematic diagram of a semiconductor device after an etching process has been performed.

[0033] Figure 8 A schematic diagram illustrating a method for fabricating a semiconductor device according to another embodiment of the present invention is shown.

[0034] Figures 9 to 10 A schematic diagram illustrating a method for fabricating a semiconductor device according to another embodiment of the present invention is shown; wherein:

[0035] Figure 9 This is a cross-sectional view of a semiconductor device after the metallization fabrication process; and

[0036] Figure 10 This is a cross-sectional schematic diagram of a semiconductor device after an etching process has been performed.

[0037] The reference numerals in the attached figures are explained as follows:

[0038] 100 substrate

[0039] 101, 103 Semiconductor Devices

[0040] 102 Shallow Ditch Isolation

[0041] 110 Insulation Layer

[0042] 112 Semiconductor Layer

[0043] 114 Barrier Layer

[0044] 116 Conductive Layer

[0045] 118 cap layer

[0046] 120 Gate spacer

[0047] 122 First gap wall

[0048] 124 Second spacer wall

[0049] 126 Third spacer wall

[0050] 128 Lightly doped source / drain regions

[0051] 130 doped region

[0052] 132 gate structure

[0053] 134 Dielectric Layer

[0054] 136 Insertion Hole

[0055] 136a perforation

[0056] 137 Bottom sidewall

[0057] 138 Plug spacer wall

[0058] 138a material layer

[0059] 139 Bottom

[0060] 140, 244 Metal silicide layers

[0061] 140a, 242 metal silicide material layers

[0062] 142 Plug

[0063] 244a Part 1

[0064] 244b Part Two

[0065] P1 Etching Process

[0066] P2 and P21 metallization fabrication processes

[0067] P3 and P31 Etching Process

[0068] W maximum width Detailed Implementation

[0069] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, along with accompanying drawings, to explain in detail the technical solutions and desired effects of this invention. Those skilled in the art can, without departing from the spirit of this invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0070] Please refer to Figure 1 As shown, Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 101 according to an embodiment of the present invention. Figure 1As shown, the semiconductor device 101 includes a substrate 100, a gate structure 132, a dielectric layer 134, a plug via 136, a plug spacer 138, a metal silicide layer 140, and a plug 142. The substrate 100 may include, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or other suitable materials, but is not limited thereto. The gate structure 132 is disposed on the substrate 100 and covered by the dielectric layer 134. The top surface of the dielectric layer 134 and the top surface of the gate structure 132 may be substantially on the same plane, but are not limited thereto. The insertion hole 136 penetrates the dielectric layer 134 in a vertical direction (not shown) perpendicular to the surface of the substrate 100 and partially extends into the substrate 100. A portion of the substrate 100 is exposed from the sidewall 137 and bottom surface 139 of the insertion hole 136. The insertion plug 142 is disposed within the insertion hole 136 to electrically connect to the doped region 130 within the substrate 100. It should be noted that a spacer wall 138 is disposed on the sidewall of the insertion hole 136 to limit the position of the metal silicide layer 140 to the bottom of the insertion hole 136. A portion of the doped region 130 within the substrate 100 is sandwiched between the metal silicide layer 140 and the spacer wall 138, and physically contacts the insertion plug 142. In other words, the sidewall of the plug 142 in the vertical direction simultaneously makes physical contact with a portion of the doped region 130 within the substrate 100 and the plug gap wall 138, and the bottom surface of the plug 142 simultaneously makes physical contact with a portion of the doped region 130 within the substrate 100 and the metal silicide layer 140. Thus, the placement position and depth of the metal silicide layer 140 are accurately defined by the placement of the plug gap wall 138, allowing the sidewall of the plug 142 to be flush with the sidewall of the metal silicide layer 140. Furthermore, the plug 142 can simultaneously contact the metal silicide layer 140 and a portion of the substrate 100 (i.e., the doped region 130), providing optimized ohmic contact while generating a relatively large lateral contact resistance at the bottom of the sidewall and the bottom surface of the plug 142, thereby improving the electrical performance of the semiconductor device 101.

[0071] Metal silicide layer 140 includes, for example, cobalt silicide (CoSi). xMetal silicide materials such as titanium silicide (TiSi2) or nickel silicide (Ni2Si) are preferred, but not limited to cobalt disilicide (CoSi2). The plug spacer wall 138 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, or a conductive barrier material such as titanium or tantalum, but is not limited to these. Because the plug spacer wall 138 on the sidewall of the plug hole 136 restricts the lateral development of the metal silicide layer 140, the metal silicide layer 140 is precisely defined at the bottom of the plug hole 136, and the dimension of the metal silicide layer 140 in a horizontal direction (not shown) parallel to the surface of the substrate 100 gradually decreases with increasing depth within the substrate 100, having an inverted triangular cross-section. That is, the cross-section of the metal silicide layer 140 has its maximum width W at its top surface and gradually decreases downwards, such as... Figure 1 As shown. In one embodiment, the top surface of the metal silicide layer 140 is lower than the top surface of the substrate 100 and does not physically contact the plug spacer wall 138.

[0072] Specifically, the gate structure 132 is, for example, a polysilicon gate structure, a metal gate structure, or a gate structure formed by integrated memory fabrication processes. The gate structure 132 includes a stacked layer structure and a gate spacer 120 disposed on the sidewall of the stacked layer structure. The stacked layer structure is composed of a semiconductor layer 112, a barrier layer 114, a conductive layer 116, and a capping layer 118, sequentially stacked from bottom to top on the substrate 100. In one embodiment, the semiconductor layer 112 may contain semiconductor materials such as doped polysilicon or doped amorphous silicon; the barrier layer 114 may contain conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide; the conductive layer 116 may contain copper, aluminum, tungsten, or other suitable low-resistivity conductive materials; and the capping layer 118 may contain insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto. The gate spacer 120 is located between the stacked layer structure and the dielectric layer 134, and is located on one side of the plug spacer 138. The gate spacer 120 may have a composite layer structure, including a first spacer 122, a second spacer 124, and a third spacer 126 sequentially disposed on the sidewalls of the stacked structure in the horizontal direction, but is not limited thereto. In one embodiment, the first spacer 122 and the third spacer 126 may include the same insulating material, such as silicon nitride or silicon carbonitride, while the second spacer 124 may include an insulating material different from that of the first spacer 122 and the third spacer 126, such as silicon oxide or silicon oxynitride, but is not limited thereto. In other embodiments, the spacer may also have a single-layer structure, for example, including insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto.

[0073] Semiconductor device 101 further includes a shallow trench isolation 102 disposed within a substrate 100, an insulating layer 110 disposed on the substrate 100, and lightly doped source / drain regions 128 and doped regions 130 also disposed within the substrate 100. In this embodiment, the top surface of the shallow trench isolation 102 is coplanar with the top surface of the substrate 100 to surround and define a plurality of active regions (not shown) within the substrate 100. The shallow trench isolation 102 is fabricated, for example, by a patterning process of the substrate 100, which includes, but is not limited to, the following steps: First, a block substrate (not shown) is patterned using a mask layer (not shown) to form at least one trench (not shown), and then a deposition process is performed to fill the trench with an insulating material to serve as the shallow trench isolation 102. In other embodiments, the top surface of the shallow trench isolation 102 may also be selectively not coplanar with the top surface of the substrate 100 to surround and define the portion of the substrate protruding from the top surface of the shallow trench isolation 102 as fins. The insulating layer 110 is integrally covered on the top surface of the substrate 100 and located between the gate structure 132 and the substrate 100, serving as the gate dielectric layer of the gate structure 132 while isolating other components disposed within or on the substrate 100. In one embodiment, the insulating layer 110 may include, for example, a nitride dielectric material (such as silicon nitride), an oxide dielectric material (such as silicon oxide), a high dielectric constant dielectric material (e.g., a dielectric material with a dielectric constant higher than 3.9 or higher than 4.52), or other suitable dielectric materials. Alternatively, it may include a composite layer structure composed of the nitride dielectric material and the oxide dielectric material, such as an oxide-nitride-oxide (ONO) structure, but is not limited thereto.

[0074] On the other hand, both the lightly doped source / drain regions 128 and 130 are disposed within the substrates 100 on opposite sides of the gate structure 132. The lightly doped source / drain regions 128 and 130 have, for example, the same conductivity type and dopant, and the doping concentration of the dopant in the lightly doped source / drain regions 128 is less than the doping concentration in the 130, such that the 130 serves as the source / drain of the gate structure 132. For example, if the gate structure 132 is expected to form a P-type transistor (PMOS) in a subsequent fabrication process, the lightly doped source / drain regions 128 and 130 may include, for example, P-type dopant such as boron; if the gate structure 132 is expected to form an N-type transistor (NMOS) in a subsequent fabrication process, the lightly doped source / drain regions 128 and 130 may include N-type dopant such as phosphorus, but are not limited thereto.

[0075] In this configuration, the plug 142 disposed within the dielectric layer 134 can be electrically connected to the source / drain (i.e., doped region 130) of the gate structure 132 via the metal silicide layer 140 at the bottom of the plug hole 136. Optimized ohmic contact is provided by the top surface of the metal silicide layer 140, which has a maximum width W. Simultaneously, the gradually decreasing size of the metal silicide layer 140 with increasing depth (i.e., having an inverted triangular cross-section) increases the distance between it and surrounding components, preventing short circuits. On the other hand, since the bottom and bottom surfaces of the plug 142 do not have a metal silicide layer 140 between them and the source / drain, but instead directly contact the source / drain (i.e., doped region 130), a relatively large sheet resistance is generated in the lateral contact. This allows for more efficient current guidance in a specific direction (downward). Therefore, the semiconductor device 101 of this embodiment has a reliable structure and optimized performance, and can be electrically connected to other active components and / or passive components downward and / or upward through other connection components in subsequent manufacturing processes to achieve more optimized operation performance.

[0076] To enable those skilled in the art to easily understand the semiconductor device of the present invention, the following will further describe the method for manufacturing the semiconductor device of the present invention.

[0077] Please see Figures 2 to 7 The diagram shown illustrates a method for fabricating a semiconductor device 101 according to an embodiment of the present invention. First, as... Figure 2 As shown, a gate structure 132 is formed on the insulating layer 110, and lightly doped source / drain regions 128 and doped regions 130 are formed in the substrate 100 on opposite sides of the gate structure 132. The gate structure 132 can be fabricated, for example, using a process similar to that of integrated memory (such as DRAM), and is formed concurrently with the bit line fabrication process, but is not limited thereto. In other embodiments, the gate structure can also be formed using a general gate fabrication process, such as a gate-last fabrication process combined with a high-k last dielectric layer fabrication process. In one embodiment, the lightly doped source / drain regions 128 are formed, for example, after the stacked layer structure of the gate structure 132 is formed, using the stacked layer structure as a doping mask, such that the sidewalls of the lightly doped source / drain regions 128 are flush with the sidewalls of the stacked layer structure in the vertical direction, but is not limited thereto. Furthermore, the doped region 130 is formed after the gate spacer 120 is formed, using the gate spacer 120 as a doping mask. In this way, the sidewall of the doped region 130 will be flush with the sidewall of the gate spacer 120 in the vertical direction, but this is not a limitation.

[0078] Next, for example Figure 2As shown, a dielectric layer 134 is formed on the substrate 100, covering the gate structure 132. The dielectric layer 134 is fabricated, for example, by sequentially performing a dielectric material deposition process and an etch-back process, such that the top surface of the dielectric layer 134 and the top surface of the gate structure 132 are on the same plane. In one embodiment, the dielectric material includes a nitride dielectric material (such as silicon nitride), an oxide dielectric material (such as silicon oxide), or other suitable dielectric materials, preferably including the same material as the second spacer 124, such as silicon oxide, silicon oxynitride, etc., but is not limited thereto.

[0079] like Figure 3 As shown, a through-hole 136a is formed in the dielectric layer 134, penetrating the dielectric layer 134 and the insulating layer 110 in the vertical direction and partially extending into the substrate 100. The bottom surface of the through-hole 136a is lower than the top surface of the substrate 100, exposing a portion of the doped region 130.

[0080] like Figure 4 As shown, a material layer 138a is formed, conformally covering the top surface of the dielectric layer 134 and the bottom surface and sidewalls of the via 136a. That is, the material layer 138a is partially formed within and partially outside the via 136a. In one embodiment, the material layer 138a may include, for example, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, or a high dielectric constant dielectric material, preferably including a material with etch selectivity to the dielectric layer 134 and the gate spacer 120, but is not limited thereto. In other embodiments, the material layer 138a may also include conductive barrier materials such as titanium or tantalum, but is not limited thereto. The material layer 138a can be fabricated using film deposition processes such as chemical vapor deposition, physical vapor deposition, or other suitable methods, but is not limited thereto. In another embodiment, the material layer 138a may selectively include a single film layer or a composite film layer, depending on the actual device requirements.

[0081] like Figure 5 As shown, an etch-back fabrication process P1 is performed to remove the material layer 138a located outside the via 136a and the material layer 138a located on the bottom surface of the via 136a, forming a plug spacer wall 138 located only on the sidewall of the via 136a. Furthermore, after the etch-back fabrication process P1, a portion of the doped region 130 is exposed again from the bottom surface of the via 136a.

[0082] like Figure 6As shown, a metal silicide fabrication process P2 is performed to form a metal silicide material layer 140a at the bottom of the through-hole 136a. The metal silicide fabrication process P2 includes, but is not limited to, the following steps: First, a selective deposition process is performed, involving selective epitaxial growth or selective introduction of metal plasma gas at the bottom of the through-hole 136a, forming a metal layer (not shown) only at the bottom of the through-hole 136a. This metal layer may include, for example, cobalt, titanium, nickel, or other metals suitable for reacting with silicon, preferably cobalt. Then, a heat treatment process is performed to react the metal layer with the exposed portion of the doped region 130 (i.e., substrate 100) to form the metal silicide material layer 140a. In one embodiment, the metal silicide material layer 140a may include, for example, cobalt silicide, titanium silicide, and nickel silicide, preferably cobalt disilicide, but is not limited thereto.

[0083] In detail, because the plug gap wall 138 disposed on the sidewall of the perforation 136a defines the formation range of the metal layer, the metal layer is accurately formed at the bottom of the perforation 136a. Under this operation, the metal layer can be completely reacted into a metal silicide material layer 140a during the heat treatment process, eliminating the need for subsequent removal of the unreacted metal layer. On the other hand, the reaction range of the heat treatment process is also correspondingly limited by the plug gap wall 138, resulting in a metal silicide material layer 140a whose dimensions in the horizontal direction gradually decrease with increasing depth within the substrate 100. That is, the top surface extension range of the metal silicide material layer 140a does not exceed the aperture extension range of the perforation 136a, and the lateral reaction of the metal silicide material layer 140a is limited by the plug gap wall 138, thus having an inverted triangular cross-sectional structure. The two opposite sides of the cross-sectional structure of the metal silicide material layer 140a are exactly flush with the inner sidewall of the plug gap wall 138, such as... Figure 6 As shown, but not limited to.

[0084] Then, as Figure 7As shown, an etching process P3 is performed, such as a dry etching process, to vertically remove a portion of the metal silicide material layer 140a while simultaneously reducing the overall extension range of the metal silicide material layer 140a in the horizontal direction, ultimately forming the metal silicide layer 140. The metal silicide layer 140 has an inverted triangular cross-section, with its top surface having the maximum width W, gradually decreasing downwards. Simultaneously, after removing the portion of the metal silicide material layer 140a, a portion of the doped region 130 (i.e., the substrate 100) is exposed again, forming a plug hole 136 where the bottom sidewall 137 and bottom surface 139 both expose portions of the doped region 130. The diameter extension range of the plug hole 136 is significantly larger than the maximum width W of the metal silicide layer 140, such that the metal silicide layer 140 is positioned directly below the center of the plug hole 136, exposing the top surface of the metal silicide layer 140 with its maximum width W. Figure 7 As shown. It should be noted that the plug hole 136 has an integrally vertical sidewall, and the upper half of the plug hole 136 completely overlaps with... Figure 6 The perforation shown is 136a.

[0085] Subsequently, the following process continues to be formed within the plug hole 136: Figure 1 The plug 142 shown can form as follows: Figure 1 The semiconductor device 101 is shown. In one embodiment, the plug 142 includes, for example, a barrier layer (not shown) formed on the sidewall and bottom surface of the plug hole 136 and a contact metal layer (not shown) filling the plug hole 136, but is not limited thereto. In this embodiment, the semiconductor device 101 accurately defines the location and depth of the metal silicide layer 140 by the provision of the plug gap wall 138, so that the vertical sidewall of the subsequently formed plug 142 can simultaneously contact the plug gap wall 138 and the doped region 130 (i.e., the substrate 100), and the bottom surface of the plug 142 can simultaneously physically contact the metal silicide layer 140 and the doped region 130, thereby improving the structure and performance of the semiconductor device 101. Thus, the fabrication of the semiconductor device 101 in this embodiment is completed. Furthermore, the semiconductor device 101 has a reliable structure and optimized performance, and can be electrically connected to other active and / or passive components downward and / or upward through other connection components in subsequent manufacturing processes to achieve more optimized operation performance.

[0086] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device and its fabrication method of this invention may have other forms or be achieved by other means, and are not limited to the foregoing. The following will further describe other embodiments or variations of the semiconductor device and its fabrication method of this invention. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0087] Please refer to Figure 8 As shown, Figure 8 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to another embodiment of the present invention. The fabrication method in this embodiment is generally the same as that in the foregoing embodiments, with the main difference being that the metal silicide fabrication process in this embodiment includes forming a metal layer 240 through a deposition or sputtering process, and a heat treatment process.

[0088] In detail, in the formation as described above Figure 5 Following the structure shown, the deposition or sputtering process is performed to form a metal layer 240. The metal layer 240 is conformally formed on the top surface of the dielectric layer 134 and the bottom and sidewalls of the via 136a, covering the plug gap wall 138. Thus, the metal layer 240 can be partially formed within and partially outside the via 136a. In one embodiment, the metal layer 240 includes, for example, a metal material suitable for reacting with silicon, such as cobalt, titanium, or nickel, preferably including cobalt, but not limited thereto. Then, a barrier layer (not shown) is selectively conformally formed on the metal layer 240, for example including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, before the heat treatment process is performed. The barrier layer prevents the diffusion of the metal material during the heat treatment process, while allowing the metal layer 240 to be uniformly heated and reacted to form a... Figure 6 The metal silicide material layer 140a shown.

[0089] Subsequently, an additional etching process is performed to remove the barrier layer and the unreacted metal layer 240, followed by the process described above. Figure 7 The etching process shown can also form such a... Figure 7 The plug hole 136 is shown, and the plug hole 136 continues to be formed as shown. Figure 1 The plug 142 shown can form as follows: Figure 1The semiconductor device 101 shown is thus completed. This completes the fabrication of the semiconductor device 101 in this embodiment. Under this operation, the semiconductor device 101 fabricated by the method of this embodiment also has a reliable structure and optimized performance. It can be electrically connected downwards and / or upwards to other active and / or passive components through other connecting components in subsequent fabrication processes to achieve even more optimized operational performance. Please refer to... Figures 9 to 10 The diagram shown illustrates a method for fabricating a semiconductor device 103 according to another embodiment of the present invention. The fabrication method in this embodiment is generally the same as that in the preceding embodiments, with the main difference being that the metal silicide fabrication process P21 in this embodiment controls the operating parameters or conditions of selective epitaxial growth or selective introduction of metal plasma gas to form a metal silicide material layer 242 whose top surface extension exceeds the aperture extension range of the through-hole 136a.

[0090] In detail, such as Figure 9 As shown, during the selective epitaxial growth process or the selective introduction of metal plasma gas, the operating time, operating temperature, or flow rate or ratio of the metal plasma gas are simultaneously adjusted so that the metal silicide material layer 242 also forms an inverted triangular cross-sectional structure. The two opposite sides of the cross-sectional structure of the metal silicide material layer 242 are located, for example, between the inner and outer sidewalls of the plug gap wall 138 in the direction parallel to the substrate 100. Figure 9 As shown, but not limited thereto. Alternatively, in another embodiment, depending on the actual device requirements, the operating time, operating temperature, or flow rate or ratio of the metal plasma gas can be adjusted so that the two opposite sides of the cross-sectional structure of the metal silicide material layer (not shown) are positioned between the outer sidewall of the plug gap wall 138 and the outer sidewall of the gate gap wall 120 in the direction parallel to the substrate 100.

[0091] Subsequently, such as Figure 10 The etching process shown involves etching process P31, such as a dry etching process, where a portion of the metal silicide material layer 242 is removed vertically downwards while simultaneously reducing the overall extension range of the metal silicide material layer 242 in the horizontal direction, ultimately forming a metal silicide layer 244. Furthermore, after removing the portion of the metal silicide material layer 242, a portion of the doped region 130 (i.e., the substrate 100) is exposed again, forming plug holes 136 where the bottom sidewall 137 and bottom surface 139 partially expose the doped region 130. It should be particularly noted that, due to... Figure 9The top surface of the metal silicide layer 242 extends beyond the aperture of the through-hole 136a. During vertical downward etching, the metal silicide layer 242 is cut into two parts, resulting in a discontinuous structure in the metal silicide layer 244. The first part 244a of the metal silicide layer 244 is formed directly below the plug gap wall 138, physically contacting the bottom surface of the plug gap wall 138 and the bottom sidewall 137 of the plug hole 136. The second part 244b has an inverted triangular cross-section and is located directly below the center of the plug hole 136. It should be noted that in this embodiment, the top surface of the second part 244b of the metal silicide layer 244 also has a maximum width W, gradually decreasing downwards. Furthermore, the top surface of the second part 244b is also exposed from the plug hole 136, as shown below. Figure 10 As shown.

[0092] Then, the process continues to be formed within the plug hole 136 as follows: Figure 1 The plug 142 is shown. In this embodiment, the metal silicide layer 244 has a discontinuous structure, with its first portion 244a located directly below the plug gap wall 138, and its second portion 244b having an inverted triangular cross-section and located directly below the center of the plug hole 136, to provide a more optimized ohmic contact. Thus, the fabrication of the semiconductor device 103 in this embodiment is completed. Under this operation, the semiconductor device 103 fabricated by the method of this embodiment also has a reliable structure and optimized performance, and can be electrically connected downwards and / or upwards to other active and / or passive components through other connecting components in subsequent fabrication processes to achieve even more optimized operational performance.

[0093] Overall, the semiconductor device and manufacturing method of the present invention involve additionally providing a plug gap wall on the sidewall of the plug hole to accurately position the formation location and depth of the metal silicide layer, thereby improving the performance of the semiconductor device.

[0094] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized by, Comprising: a substrate; a gate structure disposed on the substrate; a dielectric layer disposed on the substrate and covering the gate structure; a plug hole disposed within the dielectric layer and partially extending into the substrate; a plug spacer disposed on sidewalls of the plug hole and exposing a portion of the substrate; a metal silicide layer disposed on a bottom of the plug hole, the metal silicide layer comprising a discontinuous structure, wherein the portion of the substrate is sandwiched between the metal silicide layer and the plug spacer; and a plug disposed within the plug hole and physically contacting the portion of the substrate; further comprising: a doped region disposed within the substrate and located on opposite sides of the gate structure, the plug physically contacting the doped region.

2. The semiconductor device according to claim 1, wherein Sidewalls of the metal silicide layer are trimmed to sidewalls of the plug spacer.

3. The semiconductor device according to claim 1, wherein The metal silicide layer gradually decreases in size in a horizontal direction as depth increases.

4. The semiconductor device according to claim 1, wherein The plug spacer does not directly contact the metal silicide layer.

5. The semiconductor device according to claim 1, wherein Vertical sidewalls of the plug simultaneously physically contact the portion of the substrate and the plug spacer.

6. The semiconductor device according to claim 1, wherein The gate structure comprises: a stack layer structure; and a gate spacer disposed on sidewalls of the stack layer structure and located on one side of the plug spacer.

7. The semiconductor device according to claim 1, wherein The metal silicide layer comprises cobalt silicide, titanium silicide, or nickel silicide.

8. A method of fabricating a semiconductor device, characterized by Comprising: providing a substrate; forming a gate structure on the substrate; forming a dielectric layer on the substrate and covering the gate structure; forming a plug hole within the dielectric layer, the plug hole partially extending into the substrate; forming a plug spacer on sidewalls of the plug hole and exposing a portion of the substrate; forming a metal silicide layer on a bottom of the plug hole, the metal silicide layer comprising a discontinuous structure, wherein the portion of the substrate is sandwiched between the metal silicide layer and the plug spacer; and forming a plug within the plug hole. Further comprising, before forming the metal silicide layer:

9. The method of claim 8, wherein forming a doped region within the substrate and located on opposite sides of the gate structure; and forming a via within the dielectric layer and exposing a portion of the doped region. Forming the metal silicide layer comprises:

10. A method for manufacturing a semiconductor device according to claim 9, characterized in that, performing a metal silicidation fabrication process to form a metal silicide material layer. The metal silicidation fabrication process comprises:

11. The method of claim 10, wherein performing a selective epitaxial growth fabrication process to form a metal layer within the via; and reacting the metal layer to form the metal silicide material layer. The metal silicidation fabrication process comprises:

12. The method of claim 10, wherein performing a deposition fabrication process to form a metal layer; reacting the metal layer to form the metal silicide material layer; and after forming the metal silicide material layer, removing unreacted metal layer. Further comprising:

13. A method for manufacturing a semiconductor device according to claim 10, characterized in that, after the metal silicidation fabrication process, partially removing the metal silicide material layer to form the plug hole and the metal silicide layer at a bottom of the plug hole, an upper half of the plug hole overlapping the via. Further comprising:

14. The method of claim 10, wherein before performing the metal silicidation fabrication process, depositing a material layer within the via; and partially removing the material layer to form the plug spacer on sidewalls of the via. ​ ​ 15. The method of claim 8, wherein the step of forming the semiconductor device is performed by a process selected from the group consisting of photolithography, etching, deposition, and doping. 15 The plug spacer is not in direct contact with the metal silicide layer.

16. The method of claim 8, wherein Forming a gate structure on the substrate includes: forming a stack structure on the substrate; and forming a gate spacer on a sidewall of the stack structure and on a side of the plug spacer.

17. A method for manufacturing a semiconductor device according to claim 8, characterized in that, The metal silicide layer gradually decreases in size in a horizontal direction as depth increases.

18. The method of claim 8, wherein A sidewall of the metal silicide layer is trimmed to a sidewall of the plug spacer.

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