Overlay target on product

Abstract

The present invention relates to a product comprising a semiconductor substrate having at least first and second thin film layers disposed on the substrate and patterned to define a matrix of die separated by scribe lines and containing active areas circumscribed by the scribe lines. A plurality of overlay targets are formed in the first and second thin film layers within each of the active areas, each overlay target having a size no greater than 10 μm×10 μm in a plane parallel to the substrate. The plurality of overlay targets include a first linear grating formed in the first thin film layer and having a first grating vector, and a second linear grating formed in the second thin film layer, proximate to the first linear grating and having a second grating vector parallel to the first grating vector.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the rights to U.S. Provisional Patent Application No. 63 / 174,045 filed on April 13, 2021, and U.S. Provisional Patent Application No. 63 / 227,295 filed on July 29, 2021, the entireties of which are incorporated herein by reference. Technical Field

[0003] The present invention relates generally to the fabrication of semiconductor devices, and in particular, to methods and target characteristics for semiconductor circuit metrology. Background Art

[0004] Semiconductor circuits are typically manufactured using photolithographic methods. In photolithography, a thin layer of a photosensitive polymer (photoresist) is deposited on a semiconductor substrate and patterned using optical or other radiation so that portions of the substrate are covered by the photoresist. After patterning, the substrate is modified by methods such as etching and ion bombardment to change the material properties or surface topography of the substrate, while portions of the substrate covered by the photoresist are not affected.

[0005] Semiconductor circuit metrology is used to measure properties of patterned photoresists, such as the surface topography and position of the patterned photoresist. The accurate position of the patterned features of the photoresist relative to the previous process layers is critical to ensure a high yield in the photolithography process. Any error in the alignment (misalignment) of the patterned photoresist relative to the underlying process layers is called the "overlay error". For example, in a typical semiconductor circuit with a minimum line width of 10nm to 14nm (the so-called 10nm design rule), the maximum allowable overlay error is 2nm to 3nm. In leading-edge semiconductor circuits, line widths are shrinking to 5nm, and the maximum allowable overlay error is also reduced.

[0006] Overlay error is typically measured using optical overlay metrology tools because optical radiation at visible and near-infrared wavelengths can penetrate photoresist layers and dielectric layers beneath the photoresist. Optical overlay metrology tools, such as the Archer 1000 from KLA, Inc. (Milpitas, CA, USA), are used to measure overlay error. TM AIM series tools (such as AIM from KLA-Tencor) are used to overlay targets located in the scribe lines (lines separating adjacent dies) of a semiconductor substrate. TM An image analysis algorithm is applied to the acquired images to locate the center of symmetry (CoS) of the target feature in the treated layer and the CoS of the target feature in the patterned photoresist layer. The overlay error is calculated as the distance between the centers of symmetry of the target features of the two layers.

[0007] U.S. Patent 7,440,105, the disclosure of which is incorporated herein by reference, describes superposition marks and methods for determining superposition errors. One aspect of this patent relates to continuously varying offset marks. A continuously varying offset mark is a single mark that includes a superimposed periodic structure having an offset that varies according to position. For example, the periodic structure may correspond to a grating with different grating characteristic values ​​(e.g., pitch). Another aspect of the patent relates to a method for determining superposition errors from a continuously varying offset mark.

[0008]

[0043] The terms "optical ray," "optical radiation," "light," and "beam of radiation" as used in the description and claims generally refer to any and all visible, infrared, and ultraviolet radiation. Summary of the invention

[0009] Embodiments of the invention described below provide improved target characteristics and methods for semiconductor circuit metrology.

[0010] Thus, according to an embodiment of the present invention, a product is provided that includes a semiconductor substrate and at least first and second thin film layers disposed on the substrate and patterned to define a matrix of dies separated by scribe lines and containing active areas circumscribed by the scribe lines. A plurality of overlay targets are formed in the first and second thin film layers within each of the active areas, each overlay target having a size no greater than 10 μm×10 μm in a plane parallel to the substrate. The overlay targets include a first linear grating formed in the first thin film layer and having a first grating vector, and a second linear grating formed in the second thin film layer, proximate to the first linear grating and having a second grating vector parallel to the first grating vector.

[0011] In some embodiments, the stacking target has a size no greater than 5 μm×5 μm.

[0012] In an additional embodiment, the plurality of superposition targets include: a first set of superposition targets characterized by a first angular arrangement of the first and second linear gratings; and a second set of superposition targets characterized by a second angular arrangement of the first and second linear gratings, the second angular arrangement being rotated 180° relative to the first angular arrangement around an axis perpendicular to the plane parallel to the semiconductor substrate.

[0013] Additionally or alternatively, the plurality of superposition targets include: a first group of superposition targets characterized by a first angular arrangement of the first and second linear gratings; and a second group of superposition targets characterized by a second angular arrangement of the first and second linear gratings, the second angular arrangement being rotated 90° relative to the first angular arrangement around an axis perpendicular to the plane parallel to the semiconductor substrate.

[0014] In the disclosed embodiment, each of the superposition targets includes exactly one first linear grating and exactly one second linear grating.

[0015] Additionally or alternatively, the second linear grating is adjacent to but not overlapping the first linear grating in the plane parallel to the semiconductor substrate.

[0016] In one embodiment, the first linear grating includes: a first sub-grating having a first pitch; and a second sub-grating adjacent to but not overlapping the first sub-grating, having a second pitch unequal to the first pitch, and the second linear grating includes: a third sub-grating having a third pitch equal to the second pitch and overlapping the first sub-grating; and a fourth sub-grating adjacent to but not overlapping the third sub-grating, having a fourth pitch equal to the first pitch, and overlapping the second sub-grating.

[0017] In some embodiments, the product includes a further overlying target formed within the scribe line and having dimensions greater than 5 μm×5 μm in the plane parallel to the substrate.

[0018] According to an embodiment of the present invention, a method for measuring overlay error is also provided. The method includes depositing and patterning at least first and second thin film layers on a semiconductor substrate to define a matrix of dies separated by scribe lines and containing active areas circumscribed by the scribe lines. A plurality of overlay targets are formed in the first and second thin film layers within each of the active areas, each overlay target having a size no greater than 10 μm×10 μm in a plane parallel to the substrate, and including a first linear grating formed in the first thin film layer and having a first grating vector, and a second linear grating formed in the second thin film layer, adjacent to the first linear grating and having a second grating vector parallel to the first grating vector. The method further includes capturing images of the plurality of overlay targets, processing the images to find a displacement between the first linear grating and the second linear grating, and measuring an overlay error between the first thin film layer and the second thin film layer in response to the displacement.

[0019] According to another embodiment of the present invention, a method for measuring overlay error is additionally provided. The method includes depositing and patterning at least first and second thin film layers on a semiconductor substrate to define a matrix of die separated by scribe lines and containing active areas circumscribed by the scribe lines. A plurality of overlay targets are formed in the first and second thin film layers, each overlay target including a corresponding first target characteristic in the first thin film layer and a corresponding second target characteristic in the second thin film layer. A first image of the plurality of overlay targets is captured at a first angular orientation of the semiconductor substrate relative to a normal to the semiconductor substrate, and the first image is processed to find a corresponding first displacement between the first target characteristic and the second target characteristic. A second image of the plurality of overlay targets is captured at a second angular orientation of the semiconductor substrate, the second angular orientation being rotated relative to the normal to the semiconductor substrate relative to the first angular orientation, and the second image is processed to find a corresponding second displacement between the first target characteristic and the second target characteristic. A model of the overlay error between the first thin film layer and the second thin film layer is calculated based on the first and second displacements, and the overlay error at a given position on the semiconductor substrate is calculated using the model.

[0020] In some embodiments, calculating the model includes applying a scanner model that accounts for both misalignment of the semiconductor substrate between subsequent patterning stages in lithographically patterning the first and second thin film layers and optical distortions in the lithographic patterning.

[0021] In a disclosed embodiment, the second angular orientation is rotated 180° relative to the normal relative to the first angular orientation. Additionally or alternatively, calculating the model includes creating first and second overlay models based on the first and second displacements, respectively, and calculating the overlay error includes calculating a difference between a first overlay error and a second overlay error provided by the first and second overlay models, respectively, at the given location on the semiconductor substrate. Furthermore, additionally or alternatively, calculating the overlay error includes calculating a tool-induced displacement at the given location on the semiconductor substrate by calculating an average of respective values ​​of the first and second overlay errors at the given location.

[0022] In some embodiments, forming the plurality of overlay targets includes forming at least some of the overlay targets within the active area of ​​the die. Additionally or alternatively, each of the overlay targets within the active area has a size no greater than 10 μm×10 μm.

[0023] In a further embodiment, forming the plurality of superposition targets includes forming, in each of the superposition targets, a first linear grating in the first thin film layer and a second linear grating in the second thin film layer proximate to the first linear grating, such that a first set of superposition targets is characterized by a first angular arrangement of the first and second linear gratings, and a second set of superposition targets is characterized by a second angular arrangement of the first and second linear gratings, the second angular arrangement being rotated 180° about the normal to the semiconductor substrate relative to the first angular arrangement.

[0024] In an additional embodiment, forming the multiple superposition targets includes forming a first linear grating in the first thin film layer and a second linear grating in the second thin film layer proximate to the first linear grating in each of the superposition targets, such that a first set of superposition targets is characterized by a first angular arrangement of the first and second linear gratings, and a second set of superposition targets is characterized by a second angular arrangement of the first and second linear gratings, wherein the second angular arrangement is rotated 90° about the normal to the semiconductor substrate relative to the first angular arrangement.

[0025] In an alternative embodiment, calculating the model includes creating a superposition model based on the first displacement, and calculating the superposition error includes calculating a difference between a first superposition error provided by the superposition model and a second superposition error measured based on the second displacement at the given location on the semiconductor substrate.

[0026] The present invention will be more fully understood from the following detailed description of embodiments of the present invention in conjunction with the accompanying drawings, in which: BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic side view of an optical inspection apparatus for measuring overlay errors on a semiconductor substrate according to an embodiment of the present invention;

[0028] Figure 2 is a schematic top view of a semiconductor substrate according to an embodiment of the present invention;

[0029] Figure 3 is a schematic front view of a superimposed target according to an embodiment of the present invention;

[0030] Figure 4 is a schematic front view of a pair of superimposed targets according to an embodiment of the present invention;

[0031] Figure 5 is a schematic front view of two pairs of superimposed targets according to an embodiment of the present invention;

[0032] Figure 6 is a schematic elevation view of a pair of superimposed calibration targets according to an embodiment of the present invention;

[0033] FIG7a is a schematic elevation view of a superimposed target according to an alternative embodiment of the present invention; and

[0034] 7b is a schematic elevation view of a grating used in the construction of the superimposed target of FIG. 7a, according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Overview

[0036] Overlay targets for overlay metrology are typically used to precisely and accurately measure overlay errors between successive patterned layers on a semiconductor substrate. For example, these layers may include a process layer and a resist layer (photoresist), or two process layers in a post-etch application. Thus, although some example embodiments are described below with reference to a process layer and a resist layer, the principles of these embodiments may be applied mutatis mutandis to a first process layer and a second process layer.

[0037] Some overlay targets (such as AIM TM The target) comprises gratings oriented in two orthogonal directions (x and y directions) designed to meet the following requirements:

[0038] 180° rotational symmetry for tool-induced displacement (TIS) measurement, requiring gratings in two quadrants in the x-direction and two quadrants in the y-direction;

[0039] A pitch of more than 1600 nm to achieve sufficient contrast of the grating;

[0040] At least three lines per grating to enable determination of the spatial phase of the grating; and

[0041] - Two gratings per quadrant (one grating for the process layer and one grating for the resist layer, or one grating for each of two consecutive process layers).

[0042] For each layer, the AIM for that layer TM The symmetry center of the target is determined by the correlation between two gratings in the x direction (for x overlay error) and two gratings in the y direction (for y overlay error). Then, the overlay error between the two layers can be accurately estimated based on the distance between the corresponding two symmetry centers in the x and y directions. However, in order to meet the requirements listed above, the size of the overlay target is usually at least 20μm×20μm. Overlay targets of this size can be adapted to the cutting lanes of the semiconductor substrate, but cannot be adapted to the active area (also called the device area) of the die between the cutting lanes. It is expected to reduce the size of the overlay target to a size that can actually fit within the active area so that the overlay error in the active area can be accurately measured.

[0043] Embodiments of the invention described herein address the problem of fitting an overlay target within an active area by providing a target of reduced size. Each overlay target comprises a pair of adjacent linear gratings having parallel grating vectors, wherein one grating is formed in the handle layer and one is formed in the resist layer. (The term "grating vector" refers to a vector in the plane of the grating having a direction perpendicular to the grating lines.) For a grating pitch of 1600 nm, the total size of such an overlay target can be 5 μm x 5 μm or even smaller, thus enabling the ability to fit such an overlay target within the active area.

[0044] The overlay error between two layers is measured based on the shift between the two gratings of the overlay target in the direction of the grating vector. To measure the overlay error in two orthogonal directions (e.g., x and y directions), separate x and y overlay targets are provided with their grating vectors in the x and y directions, respectively.

[0045] To meet the requirement of 180° symmetry for TIS measurement, the first set of x overlay targets may be printed rotated 180° relative to the second set. Similarly, the two sets of y overlay targets may be printed rotated 180° relative to each other. By measuring the overlay target sets with the semiconductor substrate oriented at 0° and 180°, and comparing the measurement results, a TIS correction for measuring overlay error may be calculated. The difference in TIS calculation may be mitigated by printing oppositely rotated target pairs together (to the extent permitted by the device structure) and / or by using an overlay error model calculated from a larger overlay target (e.g., in a scribe line) or separately (as will be described in detail below) from each of the two sets of x and y overlay targets.

[0046] In the disclosed embodiments, at least first and second thin film layers are disposed on a semiconductor substrate and patterned to define a matrix of dies separated by scribe lines and containing active areas circumscribed by the scribe lines. A plurality of overlay targets are formed in the first and second thin film layers within each of the active areas. Each overlay target has dimensions no greater than 10 μm x 10 μm in a plane parallel to the substrate and includes a first linear grating formed in the first thin film layer and a second linear grating formed in the second thin film layer, which are adjacent to each other and have parallel grating vectors. In additional embodiments, the overlay target may have dimensions no greater than 5 μm x 5 μm.

[0047] System Description

[0048] Figure 1 is a schematic side view of an optical inspection apparatus 10 for measuring overlay errors on a semiconductor substrate 12 in accordance with an embodiment of the present invention.

[0049] The optical inspection apparatus 10 includes an imaging assembly 14, an illumination assembly 16, a controller 18, and a stage 20 on which the substrate 12 is mounted. The imaging assembly 14 includes an objective lens 22, a cubic beam splitter 24, and an imaging lens 26. The imaging assembly 14 further includes a sensor 28, including, for example, a complementary metal oxide semiconductor (CMOS) detector having a two-dimensional pixel array 30.

[0050] Illumination assembly 16 includes a light source 32 that emits optical radiation and a lens 34. Stage 20 is located near objective lens 22 and includes an actuator controlled by controller 18 that can move the stage linearly in x, y, and z directions (referenced to Cartesian coordinates 36), as well as rotate the stage about the z-axis. Cartesian coordinates 36 are shown in this and subsequent figures to make the orientation of these figures relative to apparatus 10 clearer.

[0051] In the illustrated embodiment, the first thin film layer 38 and the second thin film layer 40 have been deposited on the semiconductor substrate 12 and patterned in a photolithography process, as shown in the following figure. In this example, the first layer 38 is a processing layer, and the second layer 40 is a resist layer deposited on the processing layer. Alternatively, both layers 38 and 40 can be processing layers.

[0052] To measure the overlay error between the pattern in layer 40 and the pattern in the bottom layer 38 on substrate 12, as shown in the following figure, the target features have been formed in layers 38 and 40 by photolithographic processing. Substrate 12 is positioned on stage 20 so that the combined optics of lens 22 and lens 26 images the substrate onto sensor 28, i.e., the substrate and sensor are located at optically conjugate planes.

[0053] Controller 18 is coupled to receive images from sensor 28 and adjust the position and orientation of stage 20. Controller 18 typically includes a programmable processor that is programmed with software and / or firmware to perform the functions described herein, and suitable digital and / or analog interfaces for connecting to other components of apparatus 10. Alternatively or additionally, controller 18 includes hardwired and / or programmable hardware logic circuitry that performs at least some of the functions of the controller. Although controller 18 is not described in detail for simplicity, Figure 1 The controller is shown as a single monolithic functional block in the figure, but in practice, the controller may include a plurality of interconnected control units with suitable interfaces for receiving and outputting the signals illustrated in the figure and described in the text. Program instructions implementing the methods described herein may be transmitted via or stored on a carrier medium. The carrier medium may include a storage medium such as a read-only memory, a random access memory, a magnetic or optical disk, a non-volatile memory, a solid-state memory, a magnetic tape, and the like.

[0054] To capture an image of an overlay target on semiconductor substrate 12, light source 32 projects a beam of optical radiation to lens 34, which further projects the beam to cube beam splitter 24. Beam splitter 24 reflects the beam into objective 22, which projects the beam onto substrate 12. Radiation impinging on substrate 12 is scattered back to objective 22 and passes to beam splitter 24, transmitted to lens 26, and focused onto sensor 28. Controller 18 reads the image captured by sensor 28 and processes the image to identify corresponding locations of features of the overlay target in layer 40 and bottom layer 38 on substrate 12. Controller 18 measures the overlay error between the two patterned layers based on the displacement between the corresponding locations of the target features.

[0055] Figure 2 1 is a schematic top view (from the z direction) of a semiconductor substrate 12 according to an embodiment of the present invention. In a photolithographic process, a matrix 100 of die 102 is formed on the substrate 12. The die 102 are separated by scribe lines 104 and contain active areas 106 circumscribed by the scribe lines. The semiconductor substrate 12 typically has a diameter of 300 mm. Each die 102 is typically a square, for example, having dimensions of 20 mm×20 mm, but other sizes and shapes are used alternatively. The scribe lines 104 typically have a width of about 100 μm. The active areas 106 include densely packed circuit components 108 with feature sizes as low as a few nanometers.

[0056] The thin film layer (e.g., Figure 1 104) are patterned to define overlay targets 112 interspersed between circuit elements 108 within each of the active regions 106. To avoid occupying valuable circuit "real estate", each overlay target 112 has dimensions in the xy plane no greater than 10 μm x 10 μm and possibly even no greater than 5 μm x 5 μm. In the illustrated embodiment, the thin film layers are also patterned to define further overlay targets 114 within the scribe line 104, which have dimensions in the xy plane greater than 5 μm x 5 μm. The design of the overlay targets 112 and 114 and the method of measuring overlay errors using these overlay targets are further described below.

[0057] Overlay Target

[0058] Figure 31 is a schematic elevational view of a superimposed target 120 according to an embodiment of the present invention. Target 120 includes: a first linear grating 122, which includes parallel equally spaced grating lines 130 formed in layer 38 and has a first grating vector 124; and a second linear grating 126, which includes parallel equally spaced grating lines 132 formed in layer 40 and has a second grating vector 128. Gratings 122 and 126 are adjacent to each other but not superimposed. The two gratings have the same grating pitch P. With respect to the target design described in the current embodiment, the grating pitch P can exceed 1600nm in order to provide sufficient contrast in the grating image captured by the commonly used superimposed metrology equipment. However, if sufficient contrast is achieved by the metrology equipment used to capture the grating image, a pitch less than 1600nm can also be printed. Grating vectors 124 and 128 are vectors perpendicular to the corresponding grating lines 130 and 132, and each vector has a length inversely proportional to the grating pitch P.

[0059] The gratings 122 and 126 are designed and printed on the substrate 12 in a lithographic process for producing structures in the active area 106 so that the individual lines 130 and 132 of the two gratings, respectively, will be aligned relative to each other in the x-direction for zero overlay error in the x-direction between the layers 38 and 40. Any overlay error in the x-direction manifests as a relative shift Δx between the two gratings.

[0060] This shift is controlled by the controller 18 ( Figure 1 ) is measured by capturing images of gratings 122 and 126 and comparing the phase of the two gratings (e.g., by calculating the correlation between the captured images based on the relative shift of the two images). For gratings 122 and 126 with as few as three corresponding lines 130 and 132, an accurate calculation of the relative phase can be made. Thus, for example, using a line width of 1600 nm, the width L of the superimposed target 120 in the x direction is x By using short lines 130 and 132 in the y direction, for example 2 μm, the width L of the target 120 can be less than 5 μm. y The target size will also be less than 5 μm, so that the size of the target is less than 5 μm×5 μm in the xy plane (i.e., the plane parallel to the substrate 12). This small size enables the target 120 to be interspersed with the circuit components 108 ( Figure 2 ), has the advantage of measuring overlay errors within the circuit. In addition, placing multiple targets 120 within each active area 106 enables accurate modeling of overlay errors attributable to optical distortions in the lithographic process within the active area.

[0061] Figure 41 is a schematic elevation view of a pair of superimposed targets 120 and 140 printed on substrate 12 according to an embodiment of the present invention, wherein one target is rotated 180° relative to the other target. Superimposed target 140 is similar to target 120 ( Figure 3 ), but in an angular arrangement that is rotated 180° about the z-axis relative to the angular arrangement of the target 120, i.e., about an axis that is perpendicular to the plane of the substrate 12.

[0062] By rotating the substrate 12 180° about the z-axis (e.g., in stage 20, as Figure 1 ), the target 140 is brought into nominally the same orientation as the target 120 oriented at 0°, and thus the controller 18 can calculate the tool induced shift (TIS) in the x-direction. To do this, the controller 18 measures the overlay error OVL of the target 120 before the substrate 12 is rotated. x,0° , and the overlay error OVL of the target 140 is measured after the substrate is rotated 180° x,180° Next, the controller 18 adjusts the TIS (TIS x ) is calculated as TIS x =(OVL x,0° +OVL x,180° ) / 2, and the TIS correction stacking error OVL x,corr Calculated as OVL x,corr =(OVL x,0° -OVL x,180° ) / 2. Additionally or alternatively, the OVL may be measured from the target 140 before rotating the substrate 12 x,0° , and after rotation the OVL is measured from the target 120 x,180° , followed by TIS as described above x Calculation and OVL x,corr calculate.

[0063] By placing target 120 and target 140 close to each other, their respective stacking errors and TIS values ​​are close to each other, thus reducing the amount of data to be sampled to only measure, for example, the OVL from target 120 x,0° and OVL from Target 140 x,180° .

[0064] Figure 51 is a schematic elevation view of a pair of overlay targets 120 and 140 for measuring overlay error in the x-direction and a pair of overlay targets 150 and 152 for measuring overlay error in the y-direction printed on substrate 12 according to an embodiment of the present invention. Targets 150 and 152 are similar to targets 120 and 140, respectively, but rotated 90°, wherein target 152 is nominally the same as target 150 after substrate 12 is rotated 180°. Similar to targets 120 and 140 being sensitive to overlay error in the x-direction, targets 150 and 152 are sensitive to overlay error in the y-direction. Therefore, controller 18 is based on the overlay error OVL measured from target 150 before rotating substrate 12. y,0° and the overlay error OVL measured from the target 152 after rotating the substrate 180° y,180° , the TIS in the y direction (TIS y ) is calculated as TIS y =(OVL y,0° +OVL y,180° ) / 2. The controller 18 further corrects the TIS stacking error OVL in the y direction y,corr Calculated as OVL y,corr =(OVL y,0° -OVL y,180° Similar to the measurement in the x direction with respect to the targets 120 and 140 , the measurement in the y direction may be accomplished by switching the roles of the targets 150 and 152 .

[0065] By appropriately disposing targets 120, 140, 150, and 152 between circuit elements 108 in active area 106, both TIS and TIS-corrected overlay errors may be measured in both x- and y-directions.

[0066] Superposition model and calibration

[0067] In some embodiments of the present invention, a scanner model is applied to the measurements of overlay errors across the die 102 and substrate 12 in order to calculate an overlay model. The scanner model takes into account both substrate-induced overlay errors due to linear and rotational misalignment of the substrate 12 between subsequent patterning stages in the lithography process, and overlay errors within each die 102 due to optical distortions of the optical system (scanner) responsible for lithographic patterning. In turn, the calculated overlay model predicts the actual overlay error at each point in each die 102 on the substrate 12, as will be further explained below. Although this technique is described herein with reference to certain specific kinds of overlay targets shown in the figures for the sake of specificity and clarity, the principles of the present embodiments may be similarly applied using other suitable types of targets both within the active regions of the die 102 and in the scribe lines 104.

[0068] The controller 18 applies the scanner model to calculate the x-overlay error OVL based on the x-overlay error OVL of the targets 120 and 150 at a 0° orientation of the substrate 12. x,0° and y stacking error OVL y,0° The two-component 0° superposition model M is calculated by measuring 0° =[M x,0°- (x,y),M y,0° (x, y)]. Typically, the x and y overlay errors are measured on multiple dies 102 in order to find both substrate-induced and scanner-induced overlay errors. 0° Overlay Model M 0° Each point (x, y) within each die 102 gives the x and y overlay errors M respectively. x,0° (x,y) and M y,0° The controller 18 similarly calculates the x-overlay error OVL among the plurality of dies 102 based on the 180° orientation of the substrate 12 using the targets 140 and 152 , respectively. x,180° and y superimposed OVL y,180° The measurement is used to calculate the 180° superposition model M 180° =[M x,180° (x,y),M y,180° (x,y)]. 180° superposition model M 180° The x and y overlay errors M are given at each point (x, y) within each die 102 modeled from the 180° overlay error measurement, respectively. x,180° (x,y) and M y,180° (x,y).

[0069] Alternatively, the model M can be superimposed by using the 0° at this point 0° =[M x,0° (x 180 ,y 180 ),M y,0° (x 180 ,y 180 )] and the measured superposition error to calculate the point (x 180 ,y 180 ) where the corrected stacking error is OVL x,180° and y superimposed OVL y,180° has been measured. Therefore, the corrected stacking error can be calculated as [OVL corr x,180° ,OVL corr y,180° ]=1 / 2[M x,0° (x 180 ,y 180 )-OVL x,180° ,M y,0° (x 180 ,y 180 )-OVLy,180° ].

[0070] At each given point (x, y), the controller 18 models the TIS, (TIS mod =[TIS x,mod ,TIS y,mod ]) calculated as TIS mod =(M 0° +M 180° ) / 2, and the TIS correction modeling stacking error OVL mod =[OVL x,mod ,OVL y,mod ] calculated as OVL mod =(M 0° -M 180° ) / 2. Using the superposition model M 0° and M 180° The corresponding components of the TIS are performed in both the x and y directions. mod and OVL mod Calculation.

[0071] Calculating values ​​for tool-induced shift and overlay errors from modeled values ​​yields these values ​​at any location of the modeled region on substrate 12. In addition, the errors due to spatial offsets between overlay targets (e.g., targets 120 and 140) can be eliminated. Figure 4 ) between the offset and the potential errors in the values ​​of the TIS and overlay error.

[0072] Figure 6 1 is a schematic elevation view of a pair of stacked calibration targets 160 and 162 according to an embodiment of the present invention. Calibration targets 160 and 162 are larger than the stacked targets shown in the previous figure and are therefore placed in the scribe line 104 rather than the active area 106 ( Figure 2 ). Targets 160 and 162 may be used to measure TIS on substrate 12. x,scribe and corrected stacked OVL x,scribe,corr Similarly, the plurality of targets 162 in the scribe line 104 may be used to measure the TIS on the substrate 12. y,scribe and corrected stacked OVL y,scribe,corr .TIS x,scribe , OVL x,scribe,corr 、TIS y,scribe and OVL y,scribe,corr These values ​​can be used with the stacking targets in the active region 106 to model the TIS values. mod and OVL mod further calibration.

[0073] The calibration target 160 is composed of targets 120 and 140 ( Figure 5), and calibration target 162 is formed by targets 150 and 152 similarly joined together. Due to the rotational symmetry between target 120 and target 140, calibration target 160 has a symmetry of 180° rotation. Similarly, calibration target 162 has a symmetry of 180° rotation. Since calibration target 160 is formed by overlay targets 120 and 140, the TIS in the x-direction measured from the calibration target faithfully reproduces the TIS measured from the overlay target within die 102, except for the effect that may be caused to the TIS due to the position of the calibration target in scribe line 104. Similarly, the TIS measured in the y-direction from calibration target 162 faithfully reproduces the TIS measured from the overlay targets 150 and 152 within die 102.

[0074] Alternatively or additionally, a standard overlay target (eg, AIM in the scribe line 104) may be used. TM target) can be used for calibration.

[0075] Superimposed target on products with superimposed gratings

[0076] 7a and 7b show an overlay target 200 and its structure according to an alternative embodiment of the present invention. FIG. 7a is a schematic elevation view of overlay target 200, while FIG. 7b is a schematic elevation view of gratings 206 and 212 used in the construction of the overlay target of FIG. 7a. Overlay target 200 may be designed and used to measure overlay errors, for example, using the manner described in the aforementioned U.S. Patent 7,440,105. However, in contrast to the target in this patent, target 200 may be manufactured to be smaller than 10 μm×10 μm, and may even be smaller than 5 μm×5 μm, and may be placed on die 102 ( Figure 2 ) in the active region 106.

[0077] As shown in FIG. 7 b , the target 200 of FIG. 7 a includes a first linear grating 206 and a second linear grating 212 formed in layers 38 and 40, respectively. The first grating 206 includes adjacent (but not overlapping) sub-gratings 208 and 210 having respective grating pitches P and Q and grating vectors 209 and 211, where the pitches differ by a small amount. For example, the pitch Q is given by Q=k×P, where k may be 0.99, 0.999, or 1.02, or some other factor close to 1. The second grating 212 includes adjacent (but not overlapping) sub-gratings 214 and 216, whose xy positions correspond to the xy positions of sub-gratings 208 and 210, respectively, so that the sub-gratings can be used in the fabrication of layers 38 and 40 ( Figure 17b ). Sub-gratings 214 and 216 have the pitch of respective grating vectors 215 and 217 and Q and P, i.e., the same as the pitch of sub-gratings 208 and 210, but in the opposite spatial order. All four grating vectors 209, 211, 215 and 217 are parallel to each other. Although gratings 206 and 212 are shown in FIG. 7b as if they were spatially separated in the xy plane for clarity, in an actual lithographic process, sub-grating 214 is superimposed on sub-grating 208, resulting in grating-like structure 204; and sub-grating 216 is superimposed on sub-grating 210, resulting in grating-like structure 202. (Herein we refer to a "grating-like structure" as an array of parallel lines, but with different line widths and / or line-to-line separations.)

[0078] As described in the aforementioned US Pat. No. 7,440,105, each grating-like structure 202 and 204 has a corresponding symmetry center 218 and 220 in the x-direction. x , the centers of symmetry 218 and 220 are aligned. However, OVL x The non-zero overlay error OVL results in a shift Δx between the symmetry centers 218 and 220, where the overlay error OVL x Amplified by the amplification factor M to a shift Δx, so that Δx = M × OVL x In turn, the magnification factor M is given by M=P / (PQ). Since only the respective symmetry centers 218 and 220 of the grating-like structures 202 and 204 need to be identified, rather than every line of the gratings 208, 210, 214, and 216, the pitches P and Q can be much smaller than, for example, the gratings 122 and 126 ( Figure 3 ). Thus, the pitches P and Q can be advantageously reduced to a pitch that is more compatible with the photolithography process used to pattern the circuit elements 108 within the active area 106 than a pitch of 1600 nm (or greater).

[0079] The controller 18 calculates the overlay error OVL between the layer 38 and the layer 40 through the above steps. x : Identify the respective symmetry centers 218 and 220 of the grating-like structures 202 and 204 in the x-direction, calculate the shift Δx between the symmetry centers, and calculate OVL from Δx x =Δx / M.

[0080] The function of the superimposed object 200 is similar to that of the superimposed object 120 ( Figure 3 ) has the same function. Therefore, similar to the above Figure 4 , the overlay target 200 can be paired with a second overlay target that is rotated 180° relative to the target 200 to achieve TIS x In addition, similar to the above Figure 5 , two additional overlay targets rotated 90° may be provided for measuring both TIS and overlay error in the y direction. For the targets shown in FIGS. 7a-7b , TIS is reduced by the magnification factor M, and thus measurements at a 180° orientation of the substrate 12 may not be required.

[0081] Alternatively, as described in the aforementioned U.S. Patent 7,440,105, a similar shift in the center of the gratings may be achieved by forming superimposed gratings having the same pitch but rotated by a small angle relative to each other in the xy plane in layers 38 and 40. For example, grating 214 may be rotated by angle θ relative to grating 208, such that grating vector 215 is rotated by angle θ relative to grating vector 209. Furthermore, grating 216 is rotated by angle -θ relative to grating 210, such that grating vector 217 is rotated by angle -θ relative to grating vector 211.

[0082] It should be understood that the embodiments described above are cited as examples, and the present invention is not limited to the contents specifically shown and described above. On the contrary, the scope of the present invention includes both the combination and sub-combination of each of the characteristics described above, and changes and modifications that will occur to those skilled in the art when reading the foregoing description and are not disclosed in the prior art.

Claims

1. A product for measuring superposition error, comprising: Semiconductor substrate; at least first and second thin film layers disposed on the substrate and patterned to define a matrix of dies separated by scribe lines and containing active areas circumscribed by the scribe lines; and a plurality of overlay targets formed in the first and second thin film layers within each of the active regions, each overlay target having a size no greater than 10 μm×10 μm in a plane parallel to the substrate, and comprising: a first linear grating formed in the first thin film layer and having a first grating vector; and A second linear grating is formed in the second thin film layer, is adjacent to the first linear grating and has a second grating vector parallel to the first grating vector.

2. The product according to claim 1, comprising a superimposed object having dimensions no greater than 5 μm x 5 μm.

3. The product of claim 1, wherein the plurality of overlay targets comprises: A first set of superimposed targets characterized by a first angular arrangement of the first and second linear gratings; and a second set of superimposed targets characterized by a second angular arrangement of the first and second linear gratings, wherein the second angular arrangement is rotated 180° relative to the first angular arrangement around an axis perpendicular to the plane parallel to the semiconductor substrate.

4. The product of claim 1, wherein the plurality of overlay targets comprises: A first set of superimposed targets characterized by a first angular arrangement of the first and second linear gratings; and a second set of superimposed targets characterized by a second angular arrangement of the first and second linear gratings, wherein the second angular arrangement is rotated 90° relative to the first angular arrangement around an axis perpendicular to the plane parallel to the semiconductor substrate.

5. The product of claim 1, wherein each of the superimposed targets comprises exactly one first linear grating and exactly one second linear grating.

6. The product of claim 1 wherein the second linear grating is adjacent to but not overlapping the first linear grating in the plane parallel to the semiconductor substrate.

7. The product of claim 1, wherein the first linear grating comprises: a first sub-grating having a first pitch; and a second sub-grating adjacent to but not overlapping the first sub-grating and having a second pitch not equal to the first pitch, and The second linear grating includes: a third sub-grating, which has a third pitch equal to the second pitch and is superimposed on the first sub-grating; and a fourth sub-grating, which is adjacent to the third sub-grating but not superimposed, has a fourth pitch equal to the first pitch, and is superimposed on the second sub-grating.

8. The product of claim 1, comprising a further overlay target formed within the scribe line and having dimensions greater than 5 μm x 5 μm in the plane parallel to the substrate.

9. A method for measuring superposition error, comprising: depositing and patterning at least first and second thin film layers on a semiconductor substrate to define a matrix of dies separated by scribe lines and containing active areas circumscribed by the scribe lines; forming a plurality of superimposed targets in the first and second thin film layers within each of the active regions, each superimposed target having a size no greater than 10 μm×10 μm in a plane parallel to the substrate and including a first linear grating formed in the first thin film layer and having a first grating vector, and a second linear grating formed in the second thin film layer proximate to the first linear grating and having a second grating vector parallel to the first grating vector; capturing images of the plurality of superimposed targets; processing the image to find a displacement between the first linear grating and the second linear grating; and An overlay error between the first film layer and the second film layer is measured in response to the displacement. 10 . The method according to claim 9 , wherein the superposition target has a size of no greater than 5 μm×5 μm.

11. The method of claim 9, wherein forming the plurality of superimposed targets comprises forming a first set of superimposed targets characterized by a first angular arrangement of the first and second linear gratings, and a second set of superimposed targets characterized by a second angular arrangement of the first and second linear gratings, the second angular arrangement being rotated 180° relative to the first angular arrangement about an axis perpendicular to the plane parallel to the semiconductor substrate.

12. The method of claim 9, wherein forming the plurality of superimposed targets comprises forming a first set of superimposed targets characterized by a first angular arrangement of the first and second linear gratings, and a second set of superimposed targets characterized by a second angular arrangement of the first and second linear gratings, the second angular arrangement being rotated 90° relative to the first angular arrangement about an axis perpendicular to the plane parallel to the semiconductor substrate.

13. The method of claim 9, wherein forming the plurality of overlay targets comprises forming exactly one first linear grating and exactly one second linear grating in each of the overlay targets.

14. The method of claim 9, wherein forming the plurality of overlay targets comprises: In each of the superposition targets, the second linear grating is placed adjacent to but not superimposed with the first linear grating in the plane parallel to the semiconductor substrate.

15. The method of claim 9, wherein forming the plurality of overlay targets comprises: The first linear grating is formed by manufacturing a first sub-grating having a first pitch and a second sub-grating adjacent to but not overlapping the first sub-grating and having a second pitch not equal to the first pitch in the first thin film layer, and The second linear grating is formed by manufacturing in the second thin film layer a third sub-grating having a third pitch equal to the second pitch and superimposed on the first sub-grating, and a fourth sub-grating adjacent to but not superimposed on the third sub-grating and having a fourth pitch equal to the first pitch and superimposed on the second sub-grating.

16. The method of claim 9, comprising forming a further overlay target within the scribe line, the further overlay target having a size greater than 5 μm x 5 μm in the plane parallel to the substrate.

17. A method for measuring superposition error, the method comprising: depositing and patterning at least first and second thin film layers on a semiconductor substrate to define a matrix of dies separated by scribe lines and containing active areas circumscribed by the scribe lines; forming a plurality of superimposed targets in the first and second thin film layers, each superimposed target including a corresponding first target characteristic in the first thin film layer and a corresponding second target characteristic in the second thin film layer; capturing a first image of the plurality of superimposed targets at a first angular orientation of the semiconductor substrate relative to a normal to the semiconductor substrate; processing the first image to find a corresponding first displacement between the first target characteristic and a second target characteristic; capturing a second image of the plurality of superimposed objects at a second angular orientation of the semiconductor substrate rotated relative to the normal to the semiconductor substrate relative to the first angular orientation; processing the second image to find a corresponding second displacement between the first target characteristic and a second target characteristic; a model for calculating a stacking error between the first film layer and the second film layer based on the first and second displacements; and The overlay error at a given location on the semiconductor substrate is calculated using the model.

18. The method of claim 17, wherein calculating the model comprises applying a scanner model that accounts for misalignment of the semiconductor substrate between subsequent patterning stages in lithographically patterning the first and second thin film layers and optical distortions in the lithographic patterning.

19. The method of claim 17, wherein the second angular orientation is rotated 180° relative to the normal relative to the first angular orientation.

20. The method of claim 19, wherein calculating the model comprises creating first and second overlay models based on the first and second displacements, respectively, and wherein calculating the overlay error comprises calculating a difference between a first overlay error and a second overlay error provided by the first and second overlay models, respectively, at the given location on the semiconductor substrate.

21. The method of claim 20, wherein calculating the overlay error comprises calculating a tool-induced shift at the given location on the semiconductor substrate by calculating an average of respective values ​​of the first and second overlay errors at the given location.

22. The method of claim 17, wherein forming the plurality of overlay targets comprises forming at least some of the overlay targets within the active area of ​​the die.

23. The method of claim 22, wherein each of the overlay targets within the active area has a size no greater than 10 μm x 10 μm.

24. The method of claim 17 , wherein forming the plurality of superposition targets comprises forming, in each of the superposition targets, a first linear grating in the first thin film layer and a second linear grating in the second thin film layer proximate to the first linear grating, such that a first set of superposition targets is characterized by a first angular arrangement of the first and second linear gratings, and a second set of superposition targets is characterized by a second angular arrangement of the first and second linear gratings, the second angular arrangement being rotated 180° about the normal to the semiconductor substrate relative to the first angular arrangement.

25. The method of claim 17, wherein forming the plurality of superposition targets comprises forming, in each of the superposition targets, a first linear grating in the first thin film layer and a second linear grating in the second thin film layer proximate to the first linear grating, such that a first set of superposition targets is characterized by a first angular arrangement of the first and second linear gratings, and a second set of superposition targets is characterized by a second angular arrangement of the first and second linear gratings, the second angular arrangement being rotated 90° about the normal to the semiconductor substrate relative to the first angular arrangement.

26. The method of claim 17, wherein calculating the model comprises creating a superposition model based on the first displacement, and wherein calculating the superposition error comprises calculating a difference between a first superposition error provided by the superposition model and a second superposition error measured based on the second displacement at the given location on the semiconductor substrate.

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