Display substrate, preparation method thereof and display device

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a plurality of sub-pixels, at least one of which includes a driving circuit layer and a light-emitting structure layer disposed on the driving circuit layer; the driving circuit layer includes a pixel driving circuit, and the light-emitting structure layer includes a light-emitting device connected to the pixel driving circuit; the pixel driving circuit includes a reset sub-circuit, a write sub-circuit, a driving sub-circuit, a compensation sub-circuit, an energy storage sub-circuit, and a light-emitting control sub-circuit; at least one of the reset sub-circuit, the compensation sub-circuit, and the write sub-circuit includes an oxide transistor and a unidirectional conduction device.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, a method for preparing the same, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate including a plurality of sub-pixels, at least one sub-pixel including a driving circuit layer and a light-emitting structure layer disposed on the driving circuit layer; the driving circuit layer includes a pixel driving circuit, and the light-emitting structure layer includes a light-emitting device connected to the pixel driving circuit; the pixel driving circuit includes a reset sub-circuit, a writing sub-circuit, a driving sub-circuit, a compensation sub-circuit, an energy storage sub-circuit, and a light-emitting control sub-circuit.

[0005] The reset sub-circuit is connected to the second scan signal line, the initial signal line, the first node, and the fourth node, respectively, and is configured to provide the initial voltage output by the initial signal line to the first node and the fourth node under the control of the second scan signal line.

[0006] The writing sub-circuit is connected to the first scan signal line, the data signal line, and the second node, respectively, and is configured to provide the data voltage output by the data signal line to the second node under the control of the first scan signal line.

[0007] The driving sub-circuit is connected to the first node, the second node and the third node respectively, and is configured to provide the voltage of the second node to the third node under the control of the first node;

[0008] The compensation sub-circuit is connected to the first scan signal line, the first node, and the third node respectively, and is configured to provide the voltage of the third node to the first node under the control of the first scan signal line in order to compensate the first node until the voltage of the first node meets the threshold condition.

[0009] The energy storage sub-circuit is connected to the first power line and the first node respectively, and is configured to store the voltage difference between the first power supply voltage output by the first power line and the first node.

[0010] The light-emitting control sub-circuit is connected to the light-emitting control line, the first power line, the second node, the third node, and the fourth node, respectively, and is configured to provide the second node with the first power supply voltage output by the first power line and the fourth node with the voltage of the third node under the control of the light-emitting control line.

[0011] At least one of the reset sub-circuit, compensation sub-circuit, and write sub-circuit includes an oxide transistor and a unidirectional conducting device.

[0012] In an exemplary embodiment, the write sub-circuit includes a fourth transistor and a first diode as a unidirectional conducting device, or the write sub-circuit includes a fourth transistor and a first transistor as a unidirectional conducting device; the fourth transistor is an oxide transistor.

[0013] The control electrode of the fourth transistor is connected to the first scan signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the second node;

[0014] The positive terminal of the first diode is connected to the data signal line, and the negative terminal is connected to the second node; the control terminal and the first terminal of the first transistor are both connected to the data signal line, and the second terminal is connected to the second node N2.

[0015] In an exemplary embodiment, the write sub-circuit includes a PMOS transistor and an NMOS transistor; the control electrode of the PMOS transistor is connected to the first scan signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the second node; the control electrode of the NMOS transistor is connected to the first scan signal line, the first electrode is connected to the first power supply line, and the second electrode is connected to the second node.

[0016] In an exemplary embodiment, the compensation sub-circuit includes a second transistor and a second diode as a unidirectional conducting device, or the compensation sub-circuit includes a second transistor and a second transistor as a unidirectional conducting device; the second transistor is an oxide transistor;

[0017] The control electrode of the second transistor is connected to the first scan signal line, the first electrode is connected to the third node, and the second electrode is connected to the first node;

[0018] The positive terminal of the second diode is connected to the third node, and the negative terminal is connected to the first node; the control terminal and the first terminal of the second transistor are both connected to the third node, and the second terminal is connected to the first node.

[0019] In an exemplary embodiment, the reset sub-circuit includes a first transistor, a seventh transistor, and a third diode as a unidirectional conducting device; or, the reset sub-circuit includes a first transistor, a seventh transistor, and a third transistor as a unidirectional conducting device; the first transistor and the seventh transistor are oxide transistors.

[0020] The control electrode of the first transistor is connected to the second scan signal line, the first electrode is connected to the initial signal line, and the second electrode is connected to the fifth node; the control electrode of the seventh transistor is connected to the second scan signal line, the first electrode is connected to the fifth node, and the second electrode is connected to the first node.

[0021] The positive terminal of the third diode is connected to the fifth node, and the negative terminal is connected to the first node; the control terminal and the first terminal of the third transistor are both connected to the fifth node, and the second terminal is connected to the first node N1.

[0022] In an exemplary embodiment, the driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a substrate. The first semiconductor layer includes an active layer of a plurality of polysilicon transistors. The first conductive layer includes gate electrodes of a plurality of polysilicon transistors and a first plate of a storage capacitor. The second conductive layer includes gate electrodes of a plurality of oxide transistors and a second plate of a storage capacitor. The second semiconductor layer includes an active layer of a plurality of oxide transistors. The third conductive layer includes an initial signal line and a plurality of connection electrodes. The fourth conductive layer includes a data signal line and a first power supply line.

[0023] In an exemplary embodiment, the first semiconductor layer includes an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a sixth transistor, an active layer of an NMOS transistor, and a first connection electrode; the first conductive layer includes the gate electrode of the third transistor, the gate electrode of the fifth transistor, the gate electrode of the sixth transistor, and the gate electrode of the NMOS transistor, which serve as a first electrode plate; the second semiconductor layer includes the active layer of the first transistor, the active layer of the second transistor, the active layer of the fourth transistor, and the active layer of the seventh transistor, wherein a second region of the active layer of the first transistor is connected to a first region of the active layer of the seventh transistor; the second conductive layer includes a second electrode plate, the gate electrode of the first transistor, the gate electrode of the second transistor, the gate electrode of the fourth transistor, and the gate electrode of the seventh transistor.

[0024] In an exemplary embodiment, the plurality of connection electrodes includes a second connection electrode and a third connection electrode; the initial signal line is connected to the first region of the active layer of the first transistor through a via, the second connection electrode is connected to the second region of the active layer of the seventh transistor, the second region of the active layer of the second transistor, and the first electrode plate through vias, respectively, and the third connection electrode is connected to the second region of the active layer of the third transistor and the first region of the active layer of the second transistor through vias, respectively.

[0025] In an exemplary embodiment, the plurality of connection electrodes further includes a fourth connection electrode, a fifth connection electrode, and a sixth connection electrode; the fourth connection electrode is connected to the first connection electrode through a via, the fifth connection electrode is connected to the first connection electrode, the first region of the active layer of the fourth transistor, the first region of the active layer of the NMOS transistor, and the gate electrode of the NMOS transistor through vias, respectively, and the sixth connection electrode is connected to the second region of the active layer of the fourth transistor and the second region of the active layer of the NMOS transistor through vias, respectively.

[0026] In an exemplary embodiment, the data signal line of the fourth conductive layer is connected to the fourth connection electrode through a via.

[0027] In an exemplary embodiment, the plurality of connection electrodes includes a seventh connection electrode, which is connected to the second electrode plate through a via, and the first power line of the fourth conductive layer is connected to the seventh connection electrode through a via.

[0028] In an exemplary embodiment, the plurality of connection electrodes includes an eighth connection electrode, which is connected to the first region of the active layer of the fifth transistor through a via, and the first power line of the fourth conductive layer is connected to the eighth connection electrode through a via.

[0029] In an exemplary embodiment, the plurality of connection electrodes includes a ninth connection electrode, which is connected to the second region of the active layer of the sixth transistor through a via. The fourth conductive layer also includes an anode connection electrode, which is connected to the eighth connection electrode through a via.

[0030] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0031] In another aspect, this disclosure also provides a method for fabricating a display substrate, the display substrate comprising a plurality of sub-pixels; the fabrication method comprising:

[0032] A driving circuit layer is formed in at least one sub-pixel, the driving circuit layer including a pixel driving circuit;

[0033] A light-emitting structure layer is formed on the driving circuit layer, and the light-emitting structure layer includes a light-emitting device connected to the pixel driving circuit.

[0034] The pixel driving circuit includes a reset sub-circuit, a writing sub-circuit, a driving sub-circuit, a compensation sub-circuit, an energy storage sub-circuit, and a light emission control sub-circuit.

[0035] The reset sub-circuit is connected to the second scan signal line, the initial signal line, the first node, and the fourth node, respectively, and is configured to provide the initial voltage output by the initial signal line to the first node and the fourth node under the control of the second scan signal line.

[0036] The writing sub-circuit is connected to the first scan signal line, the data signal line, and the second node, respectively, and is configured to provide the data voltage output by the data signal line to the second node under the control of the first scan signal line.

[0037] The driving sub-circuit is connected to the first node, the second node and the third node respectively, and is configured to provide the voltage of the second node to the third node under the control of the first node;

[0038] The compensation sub-circuit is connected to the first scan signal line, the first node, and the third node respectively, and is configured to provide the voltage of the third node to the first node under the control of the first scan signal line in order to compensate the first node until the voltage of the first node meets the threshold condition.

[0039] The energy storage sub-circuit is connected to the first power line and the first node respectively, and is configured to store the voltage difference between the first power supply voltage output by the first power line and the first node.

[0040] The light-emitting control sub-circuit is connected to the light-emitting control line, the first power line, the second node, the third node, and the fourth node, respectively, and is configured to provide the second node with the first power supply voltage output by the first power line and the fourth node with the voltage of the third node under the control of the light-emitting control line.

[0041] At least one of the reset sub-circuit, compensation sub-circuit, and write sub-circuit includes an oxide transistor and a unidirectional conducting device.

[0042] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0043] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0044] Figure 1 This is a schematic diagram of the structure of a display device;

[0045] Figure 2 This is a schematic diagram of a planar structure of a display substrate, which is an exemplary embodiment of the present disclosure.

[0046] Figure 3 This is a schematic cross-sectional view of a display substrate as an exemplary embodiment of the present disclosure;

[0047] Figure 4 An equivalent circuit diagram of a pixel driving circuit is provided as an exemplary embodiment of this disclosure.

[0048] Figure 5 An equivalent circuit diagram of a write sub-circuit is provided as an exemplary embodiment of this disclosure;

[0049] Figure 6 An equivalent circuit diagram of another write sub-circuit as an exemplary embodiment of this disclosure;

[0050] Figure 7 This is an equivalent circuit diagram of another write sub-circuit as an exemplary embodiment of the present disclosure;

[0051] Figure 8 An equivalent circuit diagram of a compensation sub-circuit is provided as an exemplary embodiment of this disclosure;

[0052] Figure 9 An equivalent circuit diagram of another compensation sub-circuit as an exemplary embodiment of this disclosure;

[0053] Figure 10 An equivalent circuit diagram of a reset sub-circuit is provided for an exemplary embodiment of this disclosure;

[0054] Figure 11 An equivalent circuit diagram of another reset sub-circuit as an exemplary embodiment of this disclosure;

[0055] Figure 12 An equivalent circuit diagram of another pixel driving circuit as an exemplary embodiment of this disclosure;

[0056] Figure 13 This is a timing diagram of the pixel driving circuit of an exemplary embodiment of the present disclosure;

[0057] Figure 14 This is an equivalent circuit diagram of yet another pixel driving circuit as an exemplary embodiment of the present disclosure;

[0058] Figure 15 This is a schematic diagram of the structure of a driving circuit layer as an exemplary embodiment of the present disclosure;

[0059] Figure 16 This is a schematic diagram showing the formation of the first semiconductor layer pattern according to an embodiment of the present disclosure;

[0060] Figure 17a and Figure 17b This is a schematic diagram showing the formation of the first conductive layer pattern according to an embodiment of the present disclosure;

[0061] Figure 18a and Figure 18b This is a schematic diagram showing the formation of the second conductive layer pattern according to an embodiment of the present disclosure;

[0062] Figure 19a and Figure 19b This is a schematic diagram showing the formation of the second semiconductor layer pattern according to a disclosed embodiment;

[0063] Figure 20a and Figure 20b This is a schematic diagram showing the formation of the fifth insulating layer pattern according to an embodiment of the present disclosure;

[0064] Figure 21a and Figure 21b This is a schematic diagram showing the formation of the third conductive layer pattern according to an embodiment of the present disclosure;

[0065] Figure 22a and Figure 22b This is a schematic diagram showing the formation of the sixth insulating layer pattern according to an embodiment of the present disclosure;

[0066] Figure 23a and Figure 23b This is a schematic diagram of the fourth conductive layer pattern formed according to an embodiment of this disclosure.

[0067] Explanation of reference numerals in the attached figures:

[0068] 11—First active layer; 12—Second active layer; 13—Third active layer;

[0069] 14—Fourth active layer; 15—Fifth active layer; 16—Sixth active layer;

[0070] 17—Seventh active layer; 18—NMOS active layer; 19—First connection electrode;

[0071] 21—Light emission control line; 22—NMOS gate electrode; 23—First plate;

[0072] 31—First scan signal line; 32—Second scan signal line; 33—Third scan signal line;

[0073] 34—Second electrode plate; 35—Electrode plate connecting line; 36—Opening;

[0074] 41—Initial signal line; 42—Second connection electrode; 43—Third connection electrode;

[0075] 44—Fourth connecting electrode; 45—Fifth connecting electrode; 46—Sixth connecting electrode;

[0076] 47—Seventh connecting electrode; 48—Eighth connecting electrode; 49—Ninth connecting electrode;

[0077] 410—Tenth connecting electrode; 51—Data signal line; 52—First power supply line;

[0078] 53—Anode connection electrode; 101—Substrate; 102—Drive circuit layer;

[0079] 103—Light-emitting structural layer; 104—Encapsulation layer; 301—Anode;

[0080] 302—Pixel definition layer; 303—Organic light-emitting layer; 304—Cathode;

[0081] 401—First encapsulation layer; 402—Second encapsulation layer; 403—Third encapsulation layer. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0083] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0084] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0085] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0086] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0087] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0088] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged. Furthermore, the transistor includes both P-type and N-type transistors. A P-type transistor conducts when the gate is low and is cut off when the gate is high, while an N-type transistor conducts when the gate is high and is cut off when the gate is low.

[0089] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0090] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0091] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0092] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0093] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), multiple light emission signal lines (E1 to Eo), and multiple sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, clock signals, scan start signals, etc. of specifications suitable for the scan signal driver to the scan signal driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driver to the light emission signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages that will be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver may sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number. The scan signal driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from a timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light emission signal driver can generate transmit signals to be provided to light emission signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light emission signal driver can sequentially provide transmit signals with off-level pulses to light emission signal lines E1 to Eo. For example, the light emission signal driver can be configured as a shift register and can generate light emission signals by sequentially transmitting light emission stop signals in the form of off-level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. The pixel array can include multiple sub-pixels Pxij. Each sub-pixel Pxij can be connected to the corresponding data signal line, the corresponding scan signal line, and the corresponding light emission signal line, where i and j can be natural numbers. A sub-pixel Pxij can refer to a sub-pixel whose transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0094] Figure 2 This is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 2As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit in at least one sub-pixel is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0095] In an exemplary embodiment, a pixel unit P may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, or it may include red, green, blue, and white sub-pixels; this disclosure does not limit the scope of the invention. In an exemplary embodiment, the shape of the sub-pixels in a pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement; this disclosure does not limit the scope of the invention.

[0096] Figure 3 This is a schematic cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of three sub-pixels of the display substrate. For example... Figure 3 As shown, on a plane perpendicular to the display substrate, each sub-pixel in the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate.

[0097] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 of each sub-pixel may include a light-emitting device composed of multiple film layers. The multiple film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the pixel driving circuit, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the driving of the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting structure layer 103.

[0098] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a light-emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layer and electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer and electron transport layer of all sub-pixels may be a common layer connected together, and the hole blocking layer of all sub-pixels may be a common layer connected together. The light-emitting layer and electron blocking layer of adjacent sub-pixels may have a small overlap or may be isolated.

[0099] In some possible implementations, the display substrate may include other film layers, which are not limited herein.

[0100] With the development of OLED display technology, in order to reduce product power consumption, especially the power consumption of pixel driving circuits, Low Temperature Polycrystalline Oxide (LTPO) display technology has been adopted to reduce the leakage current of the driving transistors in the light-emitting stage, thereby achieving the goal of reducing the power consumption of the pixel driving circuit. LTPO display technology integrates Low Temperature Poly-Silicon (LTPS) transistors and oxide transistors into a single pixel driving circuit. LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS and oxide transistors can utilize the advantages of both, enabling low-frequency driving, reducing power consumption (saving 5% to 15% of power), and improving display quality. However, research shows that the lower turn-on current and mobility of oxide transistors result in insufficient capacitor charging during signal writing, leading to poor display quality.

[0101] Figure 4 This is an equivalent circuit diagram of a pixel driving circuit as an exemplary embodiment of the present disclosure, illustrating the circuit structure of the pixel driving circuit in a sub-pixel. For example... Figure 4 As shown, the pixel driving circuit may include a reset sub-circuit, a writing sub-circuit, a driving sub-circuit, a compensation sub-circuit, an energy storage sub-circuit, and a light emission control sub-circuit. Among them,

[0102] The reset circuit is connected to the second scan signal line S2, the initial signal line INIT, the first node N1, and the fourth node N4, respectively, and is configured to provide the initial voltage output by the initial signal line to the first node N1 and the fourth node N4 under the control of the second scan signal line S2.

[0103] The write sub-circuit is connected to the first scan signal line S1, the data signal line D, and the second node N2, respectively, and is configured to provide the data voltage output by the data signal line D to the second node N2 under the control of the first scan signal line S1.

[0104] The driving sub-circuit is connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide the voltage of the second node N2 to the third node N3 under the control of the first node N1.

[0105] The compensation sub-circuit is connected to the first scan signal line S1, the first node N1 and the third node N3 respectively, and is configured to provide the voltage of the third node N3 to the first node N1 under the control of the first scan signal line S1, so as to compensate the first node N1 until the voltage of the first node N1 meets the threshold condition.

[0106] The energy storage sub-circuit is connected to the first power line VDD and the first node N1 respectively, and is configured to store the voltage difference between the first power supply voltage output by the first power line VDD and the first node N1.

[0107] The light-emitting control sub-circuit is connected to the light-emitting control line E, the first power supply line VDD, the second node N2, the third node N3, and the fourth node N4, respectively. It is configured to provide the first power supply voltage output from the first power supply line VDD to the second node N2 and the voltage of the third node N3 to the fourth node N4 under the control of the light-emitting control line E.

[0108] In an exemplary embodiment, the light-emitting device is connected to the fourth node N4 and the second power line VSS, respectively, and is configured to be reset or emit light under the control of the fourth node N4.

[0109] In an exemplary embodiment, the signals output by the first scan signal line S1, the second scan signal line S2, and the light emission control line E can be pulse signals. The signal output by the first power line VDD can be a continuous high-level signal, and the signals output by the second power line VSS and the initial signal line INIT can be continuous low-level signals. The signal of the second power line VSS and the signal of the initial signal line INIT can be the same or different.

[0110] In an exemplary embodiment, the signal output by the initial signal line INIT can be a signal with a voltage value of 0V, configured to reset the first node N1 and the first electrode of the light-emitting device.

[0111] In an exemplary embodiment, the light-emitting device can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). The anode of the OLED or QLED is connected to the light-emitting control sub-circuit, and the cathode is connected to the second power supply terminal VSS.

[0112] Figure 5 An equivalent circuit diagram of a write sub-circuit is provided as an exemplary embodiment of this disclosure. For example... Figure 5 As shown, in an exemplary embodiment, the write sub-circuit may include a fourth transistor T4 and a unidirectional first diode D1. The fourth transistor T4 may include an oxide transistor, and the unidirectional first diode D1 may include a PN junction diode.

[0113] In an exemplary embodiment, the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the second node N2. The anode of the unidirectional first diode D1 is connected to the data signal line D, and the cathode of the unidirectional first diode D1 is connected to the second node N2. The fourth transistor T4 is configured to provide the data voltage output from the data signal line D to the second node N2 during the writing phase under the control of the first scan signal line S1. The unidirectional first diode D1 is configured to provide the data voltage output from the data signal line D to the second node N2 during the writing phase to compensate for the low on-state current and mobility of the fourth transistor T4, avoid insufficient charging of the storage capacitor during signal writing, and improve the display effect.

[0114] In an exemplary embodiment, taking the fourth transistor T4 as a P-type oxide transistor as an example, the operation of the pixel driving circuit in the exemplary embodiment of this disclosure may include:

[0115] The first stage, A1, is called the reset stage. The signal on the second scan signal line S2 is low, turning on the reset sub-circuit. The initial voltage of the initial signal line INIT is provided to the first node N1 and the fourth node N4 to initialize the energy storage sub-circuit and the fourth node N4, clearing the data voltage of the energy storage sub-circuit and the pre-stored voltage of the first electrode of the light-emitting device, thus completing the initialization. The signals on the first scan signal line S1 and the light-emitting signal line E are high, turning off the write sub-circuit, drive sub-circuit, compensation sub-circuit, and light-emitting control sub-circuit. During this stage, the light-emitting device does not emit light.

[0116] The second stage, A2, is called the data writing stage or threshold compensation stage. The signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light-emitting signal line E are high. The data signal line D outputs a data voltage. During this stage, since the first node N1 is low, the driving sub-circuit is turned on. Because the first diode D1 is unidirectionally conductive from the data signal line D to the second node N2, the low signal on the first scan signal line S1 causes the fourth transistor T4 in the writing sub-circuit to conduct. Therefore, the data voltage output from the data signal line D is provided to the second node N2 through the fourth transistor T4 and the unidirectionally conductive first diode D1. This exemplary embodiment of the present disclosure, by setting a unidirectionally conductive diode in the writing sub-circuit, allows for rapid data voltage writing during the writing stage. This compensates for the low on-state current and mobility of the fourth transistor T4, avoids insufficient charging of the storage capacitor during signal writing, and improves the display effect.

[0117] The low-level signal on the first scan signal line S1 turns on the compensation sub-circuit, allowing the data voltage to pass through the turned-on drive sub-circuit, the third node N3, and the turned-on compensation sub-circuit to the first node N1. The difference between the data voltage output from the data signal line D and the threshold voltage of the drive sub-circuit is then charged into the energy storage sub-circuit. The high-level signal on the second scan signal line S2 turns off the reset sub-circuit, and the high-level signal on the light-emitting signal line E turns off the light-emitting control sub-circuit. During this stage, the light-emitting device does not emit light.

[0118] The third stage, A3, is called the light-emitting stage. The signal on the light-emitting signal line E is low, turning on the light-emitting control sub-circuit. The power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device through the turned-on light-emitting control sub-circuit, driving the light-emitting device to emit light. The signals on the first scan signal line S1 and the second scan signal line S2 are high, turning off the write sub-circuit, compensation sub-circuit, and reset sub-circuit. In this exemplary embodiment, by setting a unidirectional diode in the write sub-circuit, since the first diode D1 is cut off from the second node N2 in the direction of the data signal line D, the first diode D1 can stabilize the voltage of the second node N2 during the light-emitting stage, avoiding leakage current in the driving sub-circuit.

[0119] Figure 6 This is an equivalent circuit diagram of another write sub-circuit as an exemplary embodiment of this disclosure. For example... Figure 6 As shown, in an exemplary embodiment, the write sub-circuit may include a fourth transistor T4 and a unidirectional first transistor E1. The fourth transistor T4 may include an oxide transistor, and the unidirectional first transistor E1 may include an N-type metal-oxide-semiconductor (NMOS) transistor.

[0120] In an exemplary embodiment, the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the second node N2. The control electrode and the first electrode of the unidirectional first transistor E1 are both connected to the data signal line D, and the second electrode of the unidirectional first transistor E1 is connected to the second node N2. That is, the control electrode and the first electrode of the unidirectional first transistor E1 are short-circuited. The fourth transistor T4 is configured to provide the data voltage output from the data signal line D to the second node N2 during the writing phase under the control of the first scan signal line S1. The unidirectional first transistor E1 is configured to provide the data voltage output from the data signal line D to the second node N2 during the writing phase to compensate for the low on-state current and mobility of the fourth transistor T4, avoid insufficient charging of the storage capacitor during signal writing, and improve the display effect.

[0121] In an exemplary embodiment, taking the fourth transistor T4 as a P-type oxide transistor as an example, the operation of the pixel driving circuit in the exemplary embodiment of this disclosure may include:

[0122] Phase 1 A1, and Figure 5 The working process of the exemplary embodiments is the same.

[0123] In the second stage A2, the signal of the first scan signal line S1 is a low-level signal, while the signals of the second scan signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs data voltage. During this stage, since the first node N1 is low-level, the driving sub-circuit is turned on. Because the first transistor E1 is unidirectionally conducting from the data signal line D to the second node N2, the low-level signal of the first scan signal line S1 causes the fourth transistor T4 in the writing sub-circuit to conduct. Therefore, the data voltage output from the data signal line D is provided to the second node N2 through the fourth transistor T4 and the unidirectionally conducting first transistor E1. This exemplary embodiment of the present disclosure, by setting a unidirectionally conducting transistor in the writing sub-circuit, enables rapid data voltage writing during the writing stage, compensating for the low on-state current and mobility of the fourth transistor T4, avoiding insufficient charging of the storage capacitor during signal writing, and improving the display effect.

[0124] The low-level signal on the first scan signal line S1 turns on the compensation sub-circuit, allowing the data voltage to pass through the turned-on drive sub-circuit, the third node N3, and the turned-on compensation sub-circuit to the first node N1. The difference between the data voltage output from the data signal line D and the threshold voltage of the drive sub-circuit is then charged into the energy storage sub-circuit. The high-level signal on the second scan signal line S2 turns off the reset sub-circuit, and the high-level signal on the light-emitting signal line E turns off the light-emitting control sub-circuit. During this stage, the light-emitting device does not emit light.

[0125] Phase 3 A3, and Figure 5 The operation process of the exemplary embodiments is the same. The exemplary embodiments of this disclosure, by setting a unidirectional transistor in the writing sub-circuit, can stabilize the voltage of the second node N2 during the light-emitting stage because the first transistor E1 is cut off in the direction from the second node N2 to the data signal line D, thus avoiding leakage current in the driving sub-circuit.

[0126] Figure 7 This is an equivalent circuit diagram of another write sub-circuit as an exemplary embodiment of the present disclosure. For example... Figure 7 As shown, in an exemplary embodiment, the writing sub-circuit may include a four-terminal metal-oxide-semiconductor (MOS) circuit, which may include a PMOS transistor F1 and an NMOS transistor F2.

[0127] In an exemplary embodiment, the control electrode of PMOS transistor F1 is connected to the first scan signal line S1, the first electrode of PMOS transistor F1 is connected to the data signal line D, and the second electrode of PMOS transistor F1 is connected to the second node N2. The control electrode of NMOS transistor F2 is connected to the first scan signal line S1, the first electrode of NMOS transistor F2 is connected to the first power supply line VDD, and the second electrode of NMOS transistor F2 is connected to the second node N2. That is, the control electrodes of PMOS transistors F1 and F2 are short-circuited and connected to the first scan signal line S1, and the second electrodes of PMOS transistors F1 and F2 are short-circuited and connected to the second node N2. PMOS transistor F1 is configured to provide the data voltage output from the data signal line D to the second node N2 during the write phase under the control of the first scan signal line S1. NMOS transistor F2 is configured to stabilize the voltage of the second node N2 during the light emission phase under the control of the first scan signal line S1.

[0128] In an exemplary embodiment, the operation of the pixel driving circuit of this exemplary embodiment may include:

[0129] Phase 1 A1, and Figure 5 The working process of the exemplary embodiments is the same.

[0130] In the second stage A2, the signal of the first scan signal line S1 is a low-level signal, while the signals of the second scan signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. During this stage, since the first node N1 is low, the driving sub-circuit is turned on. The low-level signal of the first scan signal line S1 causes the PMOS transistor F1 in the writing sub-circuit to turn on, and the NMOS transistor F2 in the writing sub-circuit to turn off. The data voltage output by the data signal line D is provided to the second node N2 through the PMOS transistor F1. This exemplary embodiment of the present disclosure, by setting a four-terminal MOS circuit in the writing sub-circuit, overcomes the problems of low on-state current and low mobility of oxide transistors due to the fast turn-on speed of the four-terminal MOS circuit, preventing insufficient charging of the storage capacitor during signal writing and improving the display effect.

[0131] The low-level signal on the first scan signal line S1 turns on the compensation sub-circuit, allowing the data voltage to pass through the turned-on drive sub-circuit, the third node N3, and the turned-on compensation sub-circuit to the first node N1. The difference between the data voltage output from the data signal line D and the threshold voltage of the drive sub-circuit is then charged into the energy storage sub-circuit. The high-level signal on the second scan signal line S2 turns off the reset sub-circuit, and the high-level signal on the light-emitting signal line E turns off the light-emitting control sub-circuit. During this stage, the light-emitting device does not emit light.

[0132] In the third stage A3, the signal on the light-emitting signal line E is low, turning on the light-emitting control sub-circuit. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device through the turned-on light-emitting control sub-circuit, driving the light-emitting device to emit light. The signals on the first scan signal line S1 and the second scan signal line S2 are high, turning off the compensation sub-circuit and the reset sub-circuit. The NMOS transistor F2 in the writing sub-circuit turns on, and the power supply voltage output from the first power supply line VDD is provided to the second node N2, allowing the voltage of the second node N2 to be stabilized at the power supply voltage. This exemplary embodiment of the present disclosure, by setting a four-terminal MOS circuit in the writing sub-circuit, can stabilize the voltage of the second node N2 during the light-emitting stage, avoiding leakage current in the driving sub-circuit.

[0133] Figure 8 An equivalent circuit diagram of a compensation sub-circuit is provided for an exemplary embodiment of this disclosure. For example... Figure 8 As shown, in an exemplary embodiment, the compensation sub-circuit may include a second transistor T2 and a unidirectional second diode D2. The second transistor T2 may include an oxide transistor, and the unidirectional second diode D2 may include a PN junction diode.

[0134] In an exemplary embodiment, the control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1. The anode of the unidirectional second diode D2 is connected to the third node N3, and the cathode of the unidirectional second diode D2 is connected to the first node N1. The second transistor T2 is configured to provide the voltage of the third node N3 to the first node N1 during the writing phase under the control of the first scan signal line S1, to compensate for the first node N1 until the voltage of the first node N1 meets the threshold condition. The unidirectional second diode D2 is configured to provide the voltage of the third node N3 to the first node N1 during the writing phase to compensate for the low on-state current and mobility of the second transistor T2, avoid insufficient charging of the storage capacitor during signal writing, and improve the display effect.

[0135] In an exemplary embodiment, taking a P-type oxide transistor as an example, the operation of the pixel driving circuit in this exemplary embodiment may include:

[0136] Phase 1 A1, and Figure 5 The working process of the exemplary embodiments is the same.

[0137] In the second stage A2, the signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light-emitting signal line E are high. The data signal line D outputs data voltage. The high signal on the second scan signal line S2 disconnects the reset sub-circuit, and the high signal on the light-emitting signal line E disconnects the light-emitting control sub-circuit. The low signal on the first scan signal line S1 turns on the write sub-circuit. During this stage, the first node N1 is low, turning on the drive sub-circuit. Therefore, the data voltage output from the data signal line D is supplied to the third node N3 through the write sub-circuit, the second node N2, and the drive sub-circuit. Because the second diode D2 is unidirectionally conducting from the third node N3 to the first node N1, the signal on the first scan signal line S1 is a low-level signal, causing the second transistor T2 in the compensation sub-circuit to conduct. Therefore, the voltage of the third node N3 is supplied to the first node N1 through the second transistor T2 and the unidirectional second diode D2 to compensate for the first node N1 until the voltage of the first node N1 meets the threshold condition. The difference between the data voltage output from the data signal line D and the threshold voltage of the driving sub-circuit is then charged into the energy storage sub-circuit. This exemplary embodiment of the present disclosure, by setting a unidirectional second diode D2 in the compensation sub-circuit, enables rapid data voltage writing during the writing phase. This compensates for the low on-state current and mobility of the second transistor T2, avoids insufficient charging of the storage capacitor during signal writing, and improves the display effect.

[0138] Phase 3 A3, and Figure 5 The operation process of the exemplary embodiments is the same. In this exemplary embodiment, by setting a unidirectional second diode D2 in the compensation sub-circuit, since the second diode D2 is cut off from the first node N1 to the third node N3, the voltage of the first node N1 can be stabilized during the light-emitting phase, thus avoiding leakage current in the driving sub-circuit.

[0139] Figure 9 This is an equivalent circuit diagram of another compensation sub-circuit as an exemplary embodiment of this disclosure. For example... Figure 9 As shown, in an exemplary embodiment, the compensation sub-circuit may include a second transistor T2 and a unidirectional second transistor E2. The second transistor T2 may include an oxide transistor, and the unidirectional second transistor E2 may include an NMOS transistor.

[0140] In an exemplary embodiment, the control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1. The control electrode and the first electrode of the unidirectional second transistor E2 are both connected to the third node N3, and the second electrode of the unidirectional second transistor E2 is connected to the first node N1. The second transistor T2 is configured to provide the voltage of the third node N3 to the first node N1 during the writing phase under the control of the first scan signal line S1, to compensate for the low on-state current and mobility of the second transistor T2, avoiding insufficient charging of the storage capacitor during signal writing, and improving the display effect.

[0141] In an exemplary embodiment, taking a P-type oxide transistor as an example, the operation of the pixel driving circuit in this exemplary embodiment may include:

[0142] Phase 1 A1, and Figure 5 The working process of the exemplary embodiments is the same.

[0143] In the second stage A2, the signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light-emitting signal line E are high. The data signal line D outputs data voltage. The high signal on the second scan signal line S2 disconnects the reset sub-circuit, and the high signal on the light-emitting signal line E disconnects the light-emitting control sub-circuit. The low signal on the first scan signal line S1 turns on the write sub-circuit. During this stage, the first node N1 is low, turning on the drive sub-circuit. Therefore, the data voltage output from the data signal line D is supplied to the third node N3 through the write sub-circuit, the second node N2, and the drive sub-circuit. Because the second transistor E2 is unidirectionally conducting from the third node N3 to the first node N1, the signal on the first scan signal line S1 is a low-level signal, causing the second transistor T2 in the compensation sub-circuit to conduct. Therefore, the voltage of the third node N3 is supplied to the first node N1 through the second transistor T2 and the unidirectionally conducting second transistor E2 to compensate for the voltage of the first node N1 until the voltage of the first node N1 meets the threshold condition. The difference between the data voltage output from the data signal line D and the threshold voltage of the driving sub-circuit is then charged into the energy storage sub-circuit. This exemplary embodiment of the present disclosure, by setting a unidirectionally conducting transistor in the compensation sub-circuit, enables rapid data voltage writing during the writing phase, compensating for the low on-state current and mobility of the second transistor T2, avoiding insufficient charging of the storage capacitor during signal writing, and improving the display effect.

[0144] Phase 3 A3, and Figure 5The working process of the exemplary embodiments is the same. The exemplary embodiments of this disclosure, by setting a unidirectional transistor in the compensation sub-circuit, can stabilize the voltage of the first node N1 during the light-emitting stage, and avoid leakage current in the driving sub-circuit, since the second transistor E2 is cut off in the direction from the first node N1 to the third node N3.

[0145] Figure 10 An equivalent circuit diagram of a reset sub-circuit is provided for an exemplary embodiment of this disclosure. For example... Figure 10 As shown, in an exemplary embodiment, the reset sub-circuit may include a first transistor T1, a seventh transistor T7, and a unidirectional third diode D3. The first transistor T1 and the seventh transistor T7 may be oxide transistors, and the unidirectional third diode D3 may be a PN junction diode.

[0146] In an exemplary embodiment, the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor T1 is connected to the fifth node N5. The control electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the fifth node N5, and the second electrode of the seventh transistor T7 is connected to the first node N1. The positive electrode of the unidirectional conducting third diode D3 is connected to the fifth node N5, and the negative electrode of the unidirectional conducting third diode D3 is connected to the first node N1. The first transistor T1 and the seventh transistor T7 are configured to provide the initial voltage output by the initial signal line to the first node N1 during the reset phase under the control of the second scan signal line S2, to initialize the energy storage sub-circuit and clear the data voltage of the energy storage sub-circuit. The unidirectional conducting third diode D3 is configured to provide the voltage of the fifth node N5 to the first node N1 during the reset phase to compensate for the low on-state current and mobility of the seventh transistor T7, avoid untimely initialization and insufficient discharge of the storage capacitor when the initial voltage is written, and improve the display effect.

[0147] In an exemplary embodiment, taking both the first transistor T1 and the seventh transistor T7 as examples, the operation of the pixel driving circuit in this exemplary embodiment may include:

[0148] In the first stage A1, the signal of the second scan signal line S2 is a low-level signal, turning on the first transistor T1. The initial voltage of the initial signal line INIT is provided to the fifth node N5. Since the third diode D3 is unidirectionally conductive from the fifth node N5 to the first node N1, the low-level signal of the second scan signal line S2 turns on the seventh transistor T7 in the reset sub-circuit. Therefore, the voltage of the fifth node N5 is provided to the first node N1 through the seventh transistor T7 and the unidirectionally conductive third diode D3, initializing the energy storage sub-circuit and clearing the data voltage of the energy storage sub-circuit. The signals of the first scan signal line S1 and the light emission signal line E are high-level signals, turning off the writing sub-circuit, driving sub-circuit, compensation sub-circuit, and light emission control sub-circuit. During this stage, the light emission device does not emit light. The exemplary embodiment of this disclosure, by setting the unidirectionally conductive third diode D3 in the reset sub-circuit, allows the initial voltage to be written quickly during the reset stage. This can compensate for the low on-state current and mobility of the seventh transistor T7, avoid untimely initialization and insufficient discharge of the storage capacitor during the initial voltage writing, and improve the display effect.

[0149] In the second stage A2, the signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light emission signal line E are high. The data signal line D outputs data voltage. During this stage, since the first node N1 is low, the driving sub-circuit is activated. The low signal on the first scan signal line S1 activates the write sub-circuit and the compensation sub-circuit, allowing the data voltage to be supplied to the first node N1 via the activated write sub-circuit, the second node N2, the activated driving sub-circuit, the third node N3, and the activated compensation sub-circuit. The difference between the data voltage output from the data signal line D and the threshold voltage of the driving sub-circuit is then charged into the energy storage sub-circuit. The high signal on the second scan signal line S2 deactivates the reset sub-circuit, and the high signal on the light emission signal line E deactivates the light emission control sub-circuit.

[0150] In the third stage A3, the signal on the light-emitting signal line E is low, turning on the light-emitting control sub-circuit. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device through the turned-on light-emitting control sub-circuit, driving the light-emitting device to emit light. The signals on the first scan signal line S1 and the second scan signal line S2 are high, turning off the write sub-circuit, the compensation sub-circuit, and the reset sub-circuit. In this exemplary embodiment, by setting a unidirectional third diode D3 in the reset sub-circuit, since the third diode D3 is cut off from the first node N1 to the fifth node N5, the third diode D3 can stabilize the voltage of the first node N1 during the write and light-emitting stages, avoiding leakage current in the drive sub-circuit.

[0151] In an exemplary embodiment, the fifth node N5 can be connected to the fourth node N4. In the first stage A1, the initial voltage of the initial signal line INIT is provided to the fourth node N4 to initialize the light-emitting device, clear the pre-stored voltage of the first electrode of the light-emitting device, and complete the initialization.

[0152] Figure 11 This is an equivalent circuit diagram of another reset sub-circuit as an exemplary embodiment of this disclosure. (See diagram below.) Figure 11 As shown, in an exemplary embodiment, the reset sub-circuit may include a first transistor T1, a seventh transistor T7, and a unidirectional third transistor E3. The first transistor T1 and the seventh transistor T7 may be oxide transistors, and the unidirectional third transistor E3 may be an NMOS transistor.

[0153] In an exemplary embodiment, the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor T1 is connected to the fifth node N5. The control electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the fifth node N5, and the second electrode of the seventh transistor T7 is connected to the first node N1. The control electrode and the first electrode of the unidirectional third transistor E3 are both connected to the fifth node N5, and the second electrode of the unidirectional third transistor E3 is connected to the first node N1. The first transistor T1 and the seventh transistor T7 are configured to provide the initial voltage output by the initial signal line to the first node N1 during the reset phase under the control of the second scan signal line S2, to initialize the energy storage sub-circuit and clear the data voltage of the energy storage sub-circuit. The unidirectional third transistor E3 is configured to provide the voltage of the fifth node N5 to the first node N1 during the reset phase, in order to compensate for the low on-state current and mobility of the seventh transistor T7, avoid untimely initialization and insufficient discharge of the storage capacitor when the initial voltage is written, and improve the display effect.

[0154] In an exemplary embodiment, taking both the first transistor T1 and the seventh transistor T7 as examples, the operation of the pixel driving circuit in this exemplary embodiment may include:

[0155] In the first stage A1, the signal of the second scan signal line S2 is low, turning on the first transistor T1 and providing the initial voltage of the initial signal line INIT to the fifth node N5. Since the third transistor E3 is unidirectionally conducting from the fifth node N5 to the first node N1, the low signal of the second scan signal line S2 turns on the seventh transistor T7 in the reset sub-circuit. Therefore, the voltage of the fifth node N5 is provided to the first node N1 through the seventh transistor T7 and the unidirectionally conducting third transistor E3, initializing the energy storage sub-circuit and clearing its data voltage. The signals of the first scan signal line S1 and the light-emitting signal line E are high, causing the writing sub-circuit, driving sub-circuit, compensation sub-circuit, and light-emitting control sub-circuit to disconnect. During this stage, the light-emitting device does not emit light. This exemplary embodiment of the present disclosure, by setting a unidirectionally conducting third transistor E3 in the reset sub-circuit, allows for rapid initial voltage writing during the reset stage. This compensates for the low on-state current and mobility of the seventh transistor T7, avoids untimely initialization and insufficient discharge of the storage capacitor during initial voltage writing, and improves the display effect.

[0156] Phase 2 A2, and Figure 10 The working process of the exemplary embodiments is the same.

[0157] Phase 3 A3, and Figure 10 The working process of the exemplary embodiments is the same. The exemplary embodiment of this disclosure sets a unidirectional transistor in the reset sub-circuit. Since the third transistor E3 is cut off in the direction from the first node N1 to the fifth node N5, the voltage of the first node N1 can be stabilized during the writing and light-emitting stages, avoiding leakage current in the driving sub-circuit.

[0158] Figure 12 The equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure illustrates a 7T1C circuit structure. In an exemplary embodiment, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 3 diodes (first diode D1 to third diode D3), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS).

[0159] In an exemplary embodiment, the write sub-circuit may include a fourth transistor T4 and a first diode D1. The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the second node N2. The anode of the first diode D1 is connected to the data signal line D, and the cathode of the first diode D1 is connected to the second node N2.

[0160] In an exemplary embodiment, the compensation sub-circuit may include a second transistor T2 and a second diode D2. The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1. The anode of the second diode D2 is connected to the third node N3, and the cathode of the second diode D2 is connected to the first node N1.

[0161] In an exemplary embodiment, the reset sub-circuit may include a first transistor T1, a seventh transistor T7, and a third diode D3. The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the fifth node N5. The control electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the fifth node N5, and the second electrode of the seventh transistor T7 is connected to the first node N1. The anode of the third diode D3 is connected to the fifth node N5, and the cathode of the third diode D3 is connected to the first node N1.

[0162] In an exemplary embodiment, the energy storage subcircuit may include a storage capacitor C. A first terminal of the storage capacitor C is connected to a first power line VDD, and a second terminal of the storage capacitor C is connected to a first node N1.

[0163] In an exemplary embodiment, the driving sub-circuit may include a third transistor T3. The control electrode of the third transistor T3 is connected to the first node N1, that is, the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as the driving transistor and is configured to determine the current driving the light-emitting device.

[0164] In an exemplary embodiment, the light-emitting control sub-circuit may include a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the third node N3. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, and the first electrode of the sixth transistor T6 is connected to the second node N2. The second electrode of the sixth transistor T6 is connected to the fourth node N4 (the first electrode of the light-emitting device).

[0165] In an exemplary embodiment, the fourth node N4 can be connected to the fifth node N5, and the light-emitting device can be an OLED, including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0166] In an exemplary embodiment, the third transistor T3 can be a driving transistor, and the first transistor T1, second transistor T2, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 can be switching transistors. The first transistor T1, second transistor T2, fourth transistor T4, and seventh transistor T7 can be oxide transistors, while the third transistor T3, fifth transistor T5, and sixth transistor T6 can be low-temperature polysilicon transistors, forming an LTPO pixel driving circuit. This circuit enables low-frequency driving, reduces power consumption, and improves display quality.

[0167] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0168] Figure 13 This is a timing diagram of the pixel driving circuit as an exemplary embodiment of this disclosure. The following is an example of its operation. Figure 13 Example of working sequence description Figure 12 The pixel driving circuit shown operates with all seven transistors being P-type transistors. In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0169] The first stage, A1, is called the reset stage. The signal on the second scan signal line S2 is low, while the signals on the first scan signal line S1 and the light-emitting signal line E are high. The high signals on the first scan signal line S1 and the light-emitting signal line E disconnect the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The low signal on the second scan signal line S2 turns on the first transistor T1, providing the initial voltage of the initial signal line INIT to the fourth node N4 and the fifth node N5 to initialize the light-emitting device, clearing the pre-stored voltage at the first electrode of the light-emitting device, thus completing the initialization. Since the third diode D3 conducts unidirectionally from the fifth node N5 to the first node N1, the low signal on the second scan signal line S2 turns on the seventh transistor T7. Therefore, the voltage (initial voltage) at the fifth node N5 is provided to the first node N1 through the seventh transistor T7 and the third diode D3, initializing the storage capacitor C and clearing the original data voltage in the storage capacitor C. During this stage, the OLED does not emit light.

[0170] An exemplary embodiment of this disclosure sets a third diode D3 on the path for initializing the storage capacitor. The third diode D3 and the seventh transistor T7 form a dual write channel. During the reset phase, the third diode D3 enables the initial voltage to be quickly written to the first node N1, ensuring rapid initialization. This can compensate for the low on-state current and mobility of the seventh transistor T7, and avoid untimely initialization and insufficient discharge of the storage capacitor when the initial voltage is written, thereby improving the display effect.

[0171] The second stage, A2, is called the data writing stage or threshold compensation stage. The signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light-emitting signal line E are high. The data signal line D outputs a data voltage. The high signal on the second scan signal line S2 disconnects the first transistor T1 and the seventh transistor T7. The high signal on the light-emitting signal line E disconnects the fifth transistor T5 and the sixth transistor T6. Because the first diode D1 is unidirectionally conducting from the data signal line D to the second node N2, the low signal on the first scan signal line S1 turns on the fourth transistor T4. The data voltage output from the data signal line D is supplied to the second node N2 through the fourth transistor T4 and the first diode D1. During this stage, since the first node N1 is low, the third transistor T3 is on; therefore, the voltage at the second node N2 is supplied to the third node N3 through the third transistor T3. Because the second diode D2 is unidirectionally conducting from the third node N3 to the first node N1, the signal on the first scan signal line S1 is a low-level signal, causing the second transistor T2 to conduct. Therefore, the voltage of the third node N3 is supplied to the first node N1 through the second transistor T2 and the second diode D2 to compensate for the voltage of the first node N1 until the voltage of the first node N1 meets the threshold condition. The difference between the data voltage output from the data signal line D and the threshold voltage of the driving sub-circuit is then charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (first node N1) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3.

[0172] An exemplary embodiment of this disclosure provides a first diode D1 and a second diode D2 along the path of the data voltage transmission. The first diode D1 and the fourth transistor T4 form a dual write channel, and the second diode D2 and the second transistor T2 also form a dual write channel. During the writing phase, the first diode D1 and the second diode D2 enable the data voltage to be written quickly, which can compensate for the low on-state current and mobility of the second transistor T2 and the fourth transistor T4, avoid insufficient charging of the storage capacitor during signal writing, and improve the display effect.

[0173] The third stage, A3, is called the light-emitting stage. The signals on the first scan signal line S1 and the second scan signal line S2 are high-level signals, while the signal on the light-emitting signal line E is low-level. The high-level signals on the first scan signal line S1 and the second scan signal line S2 cause the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 to turn off. The low-level signal on the light-emitting signal line E causes the fifth transistor T5 and the sixth transistor T6 to turn on. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the fifth transistor T5, the third node N3, the third transistor T3, the second node N2, the sixth transistor T6, and the fourth node N4, driving the OLED to emit light.

[0174] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0175] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0176] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED; K is a constant that is related to the process parameters and geometry of the third transistor T3; Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3; Vth is the threshold voltage of the third transistor T3; Vd is the data voltage output by the data signal line D; and Vdd is the power supply voltage output by the first power supply line VDD.

[0177] As can be seen from the above current formula, during the light-emitting stage, the driving current output by the third transistor T3 is not affected by the threshold voltage of the third transistor T3, but is only related to the data voltage. This eliminates the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the overall display effect of the display product.

[0178] During the light-emitting phase, the voltage of the second node N2 is the power supply voltage Vdd output from the first power supply line VDD. Since the first diode D1 is cut off from the second node N2 to the data signal line D, the first diode D1 can stabilize the voltage of the second node N2 during the light-emitting phase. Since the second diode D2 is cut off from the first node N1 to the third node N3, the second diode D2 can stabilize the voltage of the first node N1 during the light-emitting phase. Since the third diode D3 is cut off from the first node N1 to the fifth node N5, the third diode D3 can stabilize the voltage of the first node N1 during both the writing and light-emitting phases. This exemplary embodiment of the present disclosure, by setting the first diode D1, the second diode D2, and the third diode D3, ensures the voltage of the first node N1 and the second node N2, avoids leakage current of the third transistor T3 during the light-emitting phase, and guarantees the display effect.

[0179] Figure 14 This is an equivalent circuit diagram illustrating an 8T1C circuit structure, representing another exemplary embodiment of the pixel driving circuit disclosed herein. In an exemplary embodiment, the pixel driving circuit may include 8 transistors (first transistor T1 to seventh transistor T8), 3 NMOS transistors (first NMOS transistor E1 to third NMOS transistor E3), 1 storage capacitor C, and 8 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, first initial signal line INIT1, second initial signal line INIT2, first power supply line VDD, and second power supply line VSS).

[0180] In an exemplary embodiment, the write sub-circuit may include a fourth transistor T4 and a first NMOS transistor E1. The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the second node N2. The control electrode and the first electrode of the first NMOS transistor E1 are connected to the data signal line D, and the second electrode of the first NMOS transistor E1 is connected to the second node N2.

[0181] In an exemplary embodiment, the compensation sub-circuit may include a second transistor T2 and a second NMOS transistor E2. The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1. The control electrode and the first electrode of the second NMOS transistor E2 are connected to the third node N3, and the second electrode of the second NMOS transistor E2 is connected to the first node N1.

[0182] In an exemplary embodiment, the reset sub-circuit may include a first transistor T1, a seventh transistor T7, an eighth transistor T8, and a third NMOS transistor E3. The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the fifth node N5. The control electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the fifth node N5, and the second electrode of the seventh transistor T7 is connected to the first node N1. The control electrode of the eighth transistor T8 is connected to the first scan signal line S1, the first electrode of the eighth transistor T8 is connected to the second initial signal line INIT2, and the second electrode of the eighth transistor T8 is connected to the fourth node N4. The control electrode and the first electrode of the third NMOS transistor E3 are connected to the fifth node N5, and the second electrode of the third NMOS transistor E3 is connected to the first node N1.

[0183] In an exemplary embodiment, the energy storage subcircuit may include a storage capacitor C. A first terminal of the storage capacitor C is connected to a first power line VDD, and a second terminal of the storage capacitor C is connected to a first node N1.

[0184] In an exemplary embodiment, the driving sub-circuit may include a third transistor T3. The control electrode of the third transistor T3 is connected to the first node N1, that is, the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0185] In an exemplary embodiment, the light-emitting control sub-circuit may include a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4 (the first electrode of the light-emitting device).

[0186] In an exemplary embodiment, the light-emitting device may be an OLED, including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0187] In an exemplary embodiment, the third transistor T3 can be a driving transistor, and the first transistor T1, second transistor T2, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 can be switching transistors. The first transistor T1, second transistor T2, fourth transistor T4, and seventh transistor T7 can be oxide transistors, while the third transistor T3, fifth transistor T5, sixth transistor T6, and eighth transistor T8 can be low-temperature polysilicon transistors, forming an LTPO pixel driving circuit. This circuit enables low-frequency driving, reduces power consumption, and improves display quality.

[0188] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include both P-type and N-type transistors.

[0189] The following is based on Figure 13 Example of working sequence description Figure 14 The pixel driving circuit shown operates with all eight transistors being P-type transistors. In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0190] In the first stage A1, the signal of the second scan signal line S2 is low, while the signals of the first scan signal line S1 and the light-emitting signal line E are high. The high-level signals of the first scan signal line S1 and the light-emitting signal line E disconnect the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The low-level signal of the second scan signal line S2 turns on the first transistor T1, providing the initial voltage of the first initial signal line INIT1 to the fifth node N5. Since the third NMOS transistor E3 is unidirectionally conducting from the fifth node N5 to the first node N1, the low-level signal of the second scan signal line S2 turns on the seventh transistor T7. Therefore, the voltage (initial voltage) of the fifth node N5 is provided to the first node N1 through the seventh transistor T7 and the third NMOS transistor E3, initializing the storage capacitor C and clearing the original data voltage in the storage capacitor C. During this stage, the OLED does not emit light.

[0191] An exemplary embodiment of this disclosure sets a third NMOS transistor E3 on the path for initializing the storage capacitor. The third NMOS transistor E3 and the seventh transistor T7 form a dual write channel. During the reset phase, the third NMOS transistor E3 can quickly write the initial voltage to the first node N1, ensuring rapid initialization. This can compensate for the low on-state current and mobility of the seventh transistor T7, avoid untimely initialization and insufficient discharge of the storage capacitor during signal writing, and improve the display effect.

[0192] In the second stage A2, the signals of the second scan signal line S2 and the light emission signal line E are at a high level, and the data signal line D outputs a data voltage. The high level of the second scan signal line S2 disconnects the first transistor T1 and the seventh transistor T7. The high level of the light emission signal line E disconnects the fifth transistor T5 and the sixth transistor T6. The low level of the first scan signal line S1 turns on the eighth transistor T8, and the second initial voltage of the second initial signal line INIT2 is provided to the first electrode of the OLED to initialize it, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. Since the first NMOS transistor E1 is unidirectionally conducting from the data signal line D to the second node N2, the low level of the first scan signal line S1 turns on the fourth transistor T4, and the data voltage output from the data signal line D is provided to the second node N2 through the fourth transistor T4 and the first NMOS transistor E1. During this stage, since the first node N1 is at a low level, the third transistor T3 is turned on, so the voltage of the second node N2 is provided to the third node N3 through the third transistor T3. Since the second NMOS transistor E2 is unidirectionally conducting from the third node N3 to the first node N1, the signal of the first scan signal line S1 is a low-level signal, causing the second transistor T2 to conduct. Therefore, the voltage of the third node N3 is provided to the first node N1 through the second transistor T2 and the second NMOS transistor E2 to compensate the first node N1 until the voltage of the first node N1 meets the threshold condition. The difference between the data voltage output by the data signal line D and the threshold voltage of the driving sub-circuit is charged into the storage capacitor C. The voltage at the second terminal (first node N1) of the storage capacitor C is Vd-|Vth|.

[0193] An exemplary embodiment of this disclosure sets up a first NMOS transistor E1 and a second NMOS transistor E2 on the path of transmitting data voltage. The first NMOS transistor E1 and the fourth transistor T4 form a dual write channel, and the second NMOS transistor E2 and the second transistor T2 form a dual write channel. During the writing stage, the first NMOS transistor E1 and the second NMOS transistor E2 can enable the data voltage to be written quickly, which can compensate for the low on-state current and mobility of the second transistor T2 and the fourth transistor T4, avoid insufficient charging of the storage capacitor when writing the signal, and improve the display effect.

[0194] Phase 3 A3, and Figure 12 The working process of the exemplary embodiments is the same.

[0195] During the light-emitting phase, since the first NMOS transistor E1 is cut off from the second node N2 to the data signal line D, the first NMOS transistor E1 can stabilize the voltage of the second node N2 during the light-emitting phase. Since the second NMOS transistor E2 is cut off from the first node N1 to the third node N3, the second NMOS transistor E2 can stabilize the voltage of the first node N1 during the light-emitting phase. Since the third NMOS transistor E3 is cut off from the first node N1 to the fifth node N5, the third NMOS transistor E3 can stabilize the voltage of the first node N1 during both the writing and light-emitting phases. This exemplary embodiment of the present disclosure, by setting the first NMOS transistor E1, the second NMOS transistor E2, and the third NMOS transistor E3, ensures the voltage of the first node N1 and the second node N2, avoids leakage current of the third transistor T3 during the light-emitting phase, and guarantees the display effect.

[0196] As can be seen from the foregoing exemplary embodiments, this disclosure, by setting a unidirectional conducting device on the path for initializing the storage capacitor, forms a dual write channel with the unidirectional conducting device and the seventh transistor T7. During the reset phase, this allows the initial voltage to be quickly written to the first node N1, ensuring rapid initialization. This compensates for the low on-state current and mobility of the seventh transistor T7, avoiding untimely initialization and insufficient discharge of the storage capacitor during initial voltage writing, thus improving the display effect. This disclosure, by setting a unidirectional conducting device on the path for transmitting the data voltage, can form a dual write channel with the second transistor T2, and / or with the fourth transistor T4. During the writing phase, this allows the data voltage to be quickly written, compensating for the low on-state current and mobility of the second transistor T2 and the fourth transistor T4, avoiding insufficient charging of the storage capacitor during signal writing, and improving the display effect. This disclosure, by setting a unidirectional conducting device on the oxide transistor related to the leakage current of the control electrode of the driving transistor in the storage capacitor signal writing path, ensures the voltage of the first node N1 and the second node N2. During the light-emitting phase, this avoids leakage current of the third transistor T3, ensuring the display effect. The pixel driving circuit provided in the exemplary embodiments of this disclosure reduces power consumption while ensuring fast initialization and fast data voltage writing, and avoids leakage current during the light emission stage, thereby improving the display effect.

[0197] The pixel driving circuit structure shown in this disclosure is merely an exemplary illustration. In the exemplary embodiment, the corresponding structure can be modified according to actual needs. For example, the unidirectional conducting device can be only provided in the write sub-circuit, or only in the compensation sub-circuit, or only in the reset sub-circuit, or only in both the write and compensation sub-circuits, or only in both the write and reset sub-circuits, or only in both the compensation and reset sub-circuits, etc. Furthermore, the unidirectional conducting device in the write sub-circuit can be any one of a diode, an NMOS transistor, and a four-terminal MOS circuit; the unidirectional conducting device in the compensation sub-circuit can be any one of a diode and an NMOS transistor; and the unidirectional conducting device in the reset sub-circuit can be any one of a diode and an NMOS transistor. Moreover, the pixel driving circuit can be other structural forms of 7T1C or 8T1C, or 5T1C, 6T1C, 8T2C, 9T2C, etc., which are not limited herein.

[0198] Figure 15 This is a schematic diagram of a driving circuit layer according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the driving circuit layer in three sub-pixels, where the three sub-pixels are the sub-pixel in the Nth column, the sub-pixel in the (N+1)th column, and the sub-pixel in the (N+2)th column. Figure 15As shown, in a plane parallel to the display substrate, the driving circuit layer may include a light emission control line 21, a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, an initial signal line 41, a data signal line 51, a first power supply line 52, and a pixel driving circuit. The pixel driving circuit may include seven transistors, an NMOS transistor, and a storage capacitor. The seven transistors may include the first transistor T1 to the seventh transistor T7, the third transistor T3 is a driving transistor, and the storage capacitor may include a first plate and a second plate.

[0199] In a plane perpendicular to the display substrate, the driving circuit layer may include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. In an exemplary embodiment, the first semiconductor layer may include the active layer of the third transistor T3, the active layer of the fifth transistor T5, the active layer of the sixth transistor T6, the NMOS active layer of the NMOS transistor E1, and a first connection electrode. The first conductive layer may include a light-emitting control line 21, the gate electrode of the third transistor T3, the gate electrode of the fifth transistor T5, the gate electrode of the sixth transistor T6, and the NMOS gate electrode of the NMOS transistor E1. The gate electrode of the third transistor T3 also serves as the first plate of the storage capacitor. The second conductive layer may include a first scan signal line 31, a second scan signal line 32, and a third scan signal line 33. The second semiconductor layer may include the active layer of the first transistor T1, the active layer of the second transistor T2, the active layer of the fourth transistor T4, the active layer of the seventh transistor T7, and the second plate of the storage capacitor. The third conductive layer may include the initial signal line 41 and multiple connection electrodes serving as the first and second electrodes of the multiple transistors. The fourth conductive layer may include the data signal line 51 and the first power supply line 52.

[0200] In an exemplary embodiment, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 may be polysilicon transistors, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 may be oxide transistors.

[0201] In an exemplary embodiment, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer. The first insulating layer is disposed between the substrate and the first semiconductor layer, the second insulating layer is disposed between the first semiconductor layer and the first conductive layer, the third insulating layer is disposed between the first conductive layer and the second conductive layer, the fourth insulating layer is disposed between the second conductive layer and the second semiconductor layer, the fifth insulating layer is disposed between the second semiconductor layer and the third conductive layer, and the sixth insulating layer is disposed between the third conductive layer and the fourth conductive layer.

[0202] In an exemplary embodiment, the gate electrode of the first transistor T1 is directly connected to the second scan signal line 32, the first terminal of the first transistor T1 is connected to the initial signal line 52 through a via, and the second terminal of the first transistor T1 is directly connected to the first terminal of the seventh transistor T7. The gate electrode of the second transistor T2 is directly connected to the first scan signal line 31, and the first terminal of the second transistor T2 is connected to the second terminals of the third transistor T3 and the fifth transistor T5 through a third connection electrode. The second terminal of the second transistor T2 is connected to the gate electrode of the third transistor T3 and the second terminal of the seventh transistor T7 through a second connection electrode. The gate electrode of the third transistor T3 serves as the first plate of the storage capacitor, and is connected to the second terminals of the second transistor T2 and the seventh transistor T7 through a second connection electrode. The first terminal of the third transistor T3 is directly connected to the second terminal of the NMOS transistor E1, and is directly connected to the second terminal of the fifth transistor T5, and is also connected to the second terminal of the second transistor T2 through a third connection electrode. The gate electrode of the fourth transistor T4 is directly connected to the first scan signal line 31. The first terminal of the fourth transistor T4 is connected to the data signal line 51 through the fifth connection electrode, the first connection electrode, and the fourth connection electrode. The second terminal of the fourth transistor T4 is connected to the first terminal of the third transistor T3 through the sixth connection electrode. The gate electrode of the fifth transistor T5 is directly connected to the light-emitting control line 21. The first terminal of the fifth transistor T5 is connected to the first power supply line 52 through the eighth connection electrode. The second terminal of the fifth transistor T5 is directly connected to the second terminal of the third transistor T3. The gate electrode of the sixth transistor T6 is directly connected to the light-emitting signal line 21. The first terminal of the sixth transistor T6 is connected to the first terminal of the third transistor T3. The second terminal of the sixth transistor T6 is connected to the anode of the light-emitting device through the ninth connection electrode and the anode connection electrode. The gate electrode of the seventh transistor T7 is directly connected to the third scan signal line 33. The first terminal of the seventh transistor T7 is directly connected to the second terminal of the first transistor T1. The second terminal of the seventh transistor T7 is connected to the gate electrode of the third transistor T3 and the second terminal of the second transistor T2 through the second connection electrode. The NMOS gate electrode and the first terminal of NMOS transistor E1 are connected through the fifth connection electrode. The second terminal of NMOS transistor E1 is directly connected to the first terminal of the third transistor T3 and the first terminal of the sixth transistor T6, and is connected to the second terminal of the fourth transistor T4 through the sixth connection electrode.

[0203] In an exemplary embodiment, the third conductive layer may include a second connection electrode and a third connection electrode. The initial signal line is connected to the first region of the active layer of the first transistor T1 via a via. The second connection electrode is connected to the second region of the active layer of the seventh transistor T7, the second region of the active layer of the second transistor T2, and the first electrode plate via vias. The third connection electrode is connected to the second region of the active layer of the third transistor T3 and the first region of the active layer of the second transistor T2 via vias.

[0204] In an exemplary embodiment, the third conductive layer may include a fourth connection electrode, a fifth connection electrode, and a sixth connection electrode. The fourth connection electrode is connected to the first connection electrode via a via. The fifth connection electrode is connected to the first connection electrode, the first region of the active layer of the fourth transistor T4, the first region of the active layer of the NMOS transistor E1, and the gate electrode of the NMOS transistor E1 via vias. The sixth connection electrode is connected to the second region of the active layer of the fourth transistor T4 and the second region of the active layer of the NMOS transistor E1 via vias. The data signal line 51 of the fourth conductive layer is connected to the fourth connection electrode via a via.

[0205] In an exemplary embodiment, the third conductive layer may include a seventh connection electrode, which is connected to the second electrode plate through a via, and the first power line 52 of the fourth conductive layer is connected to the seventh connection electrode through a via.

[0206] In an exemplary embodiment, the third conductive layer may include an eighth connection electrode, which is connected to the first region of the active layer of the fifth transistor T5 through a via, and the first power line 52 of the fourth conductive layer is connected to the eighth connection electrode through a via.

[0207] In an exemplary embodiment, the third conductive layer may include a ninth connection electrode, which is connected to the second region of the active layer of the sixth transistor T6 through a via, and the fourth conductive layer may include an anode connection electrode, which is connected to an eighth connection electrode through a via.

[0208] The following is an illustrative description of the fabrication process of a pixel driving circuit. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. "The orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0209] The following example uses a pixel driving circuit with three sub-pixels to illustrate the fabrication process of the pixel driving circuit. In each sub-pixel, the first transistor T1 to the seventh transistor T7 are P-type transistors; the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are oxide transistors; the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are low-temperature polysilicon transistors; and the driving sub-circuit includes the fourth transistor T4 and the NMOS transistor E1.

[0210] In an exemplary embodiment, the fabrication process of the pixel driving circuit may include the following operations.

[0211] (1)Form a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a first semiconductor layer disposed on the first insulating layer. The first semiconductor layer of each sub-pixel includes at least a third active layer 13 of a third transistor T3, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, an NMOS active layer 18 of an NMOS transistor E1, and a first connection electrode 19. The third active layer 13, the fifth active layer 15, the sixth active layer 16, and the NMOS active layer 18 are an integrally connected structure, as Figure 16 shown.

[0212] In an exemplary embodiment, the shape of the third active layer 13 may be in a "Ji" shape, and the shapes of the fifth active layer 15 and the sixth active layer 16 may be in a "1" shape.

[0213] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region 13-1 of the third active layer 13 serves as the first region 16-1 of the sixth active layer 16 and the second region 18-2 of the NMOS active layer 18 at the same time, that is, the first region 13-1 of the third active layer 13, the first region 16-1 of the sixth active layer 16, and the second region 18-2 of the NMOS active layer 18 are connected to each other. The second region 13-2 of the third active layer 13 serves as the second region 15-2 of the fifth active layer 15 at the same time, that is, the second region 13-2 of the third active layer 13 and the second region 15-2 of the fifth active layer 15 are connected to each other. The first region 15-1 of the fifth active layer 15 and the second region 16-2 of the sixth active layer 16 are separately provided.

[0214] In an exemplary embodiment, the first connection electrode 19 is separately provided, and the first connection electrode 19 is configured to be connected to the first pole of a fourth transistor, the gate electrode and the first pole of an NMOS transistor, and a data signal line formed subsequently, respectively.

[0215] In an exemplary embodiment, the first semiconductor layer may be made of polysilicon (p-Si), that is, the third transistor, the fifth transistor, and the sixth transistor are LTPS thin film transistors.

[0216] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on a substrate on which the aforementioned pattern is formed; patterning the first metal film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer. The first conductive layer pattern of each sub-pixel includes at least: a light-emitting control line 21, an NMOS gate electrode 22 of an NMOS transistor, and a first electrode 23 of a storage capacitor, such as... Figure 17a and Figure 17b As shown, Figure 17b for Figure 17a A planar schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE 1) layer.

[0217] In an exemplary embodiment, the light-emitting control line 21 may extend along the first direction X, the region where the light-emitting control line 21 overlaps with the fifth active layer serves as the gate electrode of the fifth transistor T5, and the region where the light-emitting control line 21 overlaps with the sixth active layer serves as the gate electrode of the sixth transistor T6.

[0218] In an exemplary embodiment, the NMOS gate electrode 22 is disposed on the side of the first electrode plate 23 away from the light-emitting control line 21, and the orthogonal projection of the NMOS gate electrode 22 on the substrate overlaps with the orthogonal projection of the NMOS active layer 18 on the substrate.

[0219] In an exemplary embodiment, the first electrode 23 is disposed between the light-emitting control line 21 and the NMOS gate electrode 22. The first electrode 23 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode 23 on the substrate overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. The first electrode 23 also serves as the gate electrode of the third transistor T3.

[0220] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel regions of the fifth transistor T5, the sixth transistor T6, and the NMOS transistor E1. The first semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first and second regions of the fifth transistor T5 and the sixth transistor T6, the second region of the NMOS transistor E1, and the first connection electrode 19 are all conducted.

[0221] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on a substrate on which the aforementioned pattern is formed; patterning the second metal film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer. The second conductive layer pattern of each sub-pixel includes at least: a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a second electrode 34 of a storage capacitor, and an electrode connection line 35, such as... Figure 18a and Figure 18b As shown, Figure 18b for Figure 18a A schematic planar view of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE 2) layer.

[0222] In an exemplary embodiment, the first scan signal line 31, the second scan signal line 32, and the third scan signal line 33 can extend along a first direction X. The first scan signal line 31 is disposed on the side of the NMOS gate electrode 22 away from the light-emitting control line 21, the second scan signal line 32 is disposed on the side of the light-emitting control line 21 away from the second electrode 34, and the third scan signal line 33 is disposed between the light-emitting control line 21 and the second electrode 34. In an exemplary embodiment, the second scan signal line 32 and the third scan signal line 33 can be connected to the same signal source and transmit the same signal; they can be referred to as reset signal lines.

[0223] In an exemplary embodiment, the second electrode 34 of the storage capacitor is disposed between the first scan signal line 31 and the third scan signal line 33. The outline of the second electrode 34 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode 34 on the substrate overlaps with the orthographic projection of the first electrode 23 on the substrate. An opening 36 is provided on the second electrode 34, which can be rectangular, so that the second electrode 34 forms an annular structure. The opening 36 exposes the third insulating layer covering the first electrode 23, and the orthographic projection of the first electrode 23 on the substrate includes the orthographic projection of the opening 36 on the substrate. In an exemplary embodiment, the opening 36 is configured to accommodate a subsequently formed first via, which is located within the opening 36 and exposes the first electrode 23, so that the second electrode of the subsequently formed seventh transistor T7 is connected to the first electrode 23.

[0224] In an exemplary embodiment, the electrode connection line 35 is disposed between the second electrodes 34 of adjacent sub-pixels in the first direction X or the opposite direction of the first direction X. The first end of the electrode connection line 35 is connected to the second electrode 34 of the sub-pixel, and the second end of the electrode connection line 35 extends along the first direction X or the opposite direction of the first direction X and is connected to the second electrode 34 of the adjacent sub-pixel in the first direction X or the opposite direction of the first direction X. That is, the electrode connection line 35 is configured to connect the second electrodes of adjacent sub-pixels in the first direction X. In an exemplary embodiment, the electrode connection line 35 forms an interconnected integrated structure of the second electrodes in adjacent sub-pixels. The integrated structure of the second electrodes can be reused as a power signal line, ensuring that the second electrodes in adjacent sub-pixels have the same potential. This improves the uniformity of the panel, avoids display defects in the display substrate, and ensures the display effect of the display substrate.

[0225] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on a substrate on which the aforementioned pattern is formed; patterning the second semiconductor film using a patterning process to form a fourth insulating layer covering the substrate; and a second semiconductor layer disposed on the fourth insulating layer. The second semiconductor layer of each sub-pixel includes at least a first active layer 11 of the first transistor T1, a second active layer 12 of the second transistor T2, a fourth active layer 14 of the fourth transistor T4, and a seventh active layer 17 of the seventh transistor T7, such as... Figure 19a and Figure 19b As shown, Figure 19b for Figure 19a A planar schematic diagram of the second semiconductor layer.

[0226] In an exemplary embodiment, the first active layer 11 and the seventh active layer 17 may be in the shape of an "I", and the first active layer 11 and the seventh active layer 17 may be an integral structure that is interconnected and extends along the second direction Y. The region where the second scan signal line 32 overlaps with the first active layer 11 serves as the gate electrode of the first transistor T1, and the region where the third scan signal line 33 overlaps with the seventh active layer 17 serves as the gate electrode of the seventh transistor T7.

[0227] In an exemplary embodiment, the second active layer 12 and the fourth active layer 14 may be in the shape of an "I", and the second active layer 12 and the fourth active layer 14 are arranged sequentially along the first direction X. The region where the first scan signal line 31 overlaps with the second active layer 12 serves as the gate electrode of the second transistor T2, and the region where the first scan signal line 31 overlaps with the fourth active layer 14 serves as the gate electrode of the fourth transistor T4.

[0228] In an exemplary embodiment, the second region 11-2 of the first active layer 11 also serves as the first region 17-1 of the seventh active layer 17. The first region 11-1 of the first active layer 11 is set separately and located on the side of the second scan signal line 32 away from the third scan signal line 33. The second region 17-2 of the seventh active layer 17 is set separately and located on the side of the third scan signal line 33 away from the second scan signal line 32.

[0229] In an exemplary embodiment, the first region and the second region of the second active layer 12 and the fourth active layer 14 are separately provided. The first region 12-1 of the second active layer 12 and the first region 14-1 of the fourth active layer 14 are located on the side of the first scan signal line 31 away from the second electrode plate 34, and the second region 12-2 of the second active layer 12 and the second region 14-2 of the fourth active layer 14 are located on the side of the first scan signal line 31 close to the second electrode plate 34.

[0230] In an exemplary embodiment, the second semiconductor layer may be an oxide layer, i.e., the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are all oxide thin-film transistors.

[0231] (5) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the fifth insulating layer, and the plurality of vias for each sub-pixel include at least: a first via V1 to a seventeenth via V17, such as... Figure 20a and Figure 20b As shown, Figure 20b for Figure 20a A planar schematic diagram of multiple vias.

[0232] In an exemplary embodiment, a first via V1 is located within an opening 36 of the second electrode plate 34. The orthographic projection of the first via V1 onto the substrate lies within the range of the orthographic projection of the opening 36 onto the substrate. The fifth, fourth, and third insulating layers within the first via V1 are etched away, exposing the surface of the first electrode plate 23. The first via V1 is configured to connect the second electrode of the subsequently formed seventh transistor T7 to the first electrode plate 23 via the via V1.

[0233] In an exemplary embodiment, the second via V2 is located in the region where the second electrode plate 34 is located. The orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second electrode plate 34 onto the substrate. The fifth and fourth insulating layers within the second via V2 are etched away, exposing the surface of the second electrode plate 34. The second via V2 is configured to allow a subsequently formed first power line to connect to the second electrode plate 34 through the via. In an exemplary embodiment, multiple second vias V2 may be included as power vias, and these multiple second vias V2 may be arranged sequentially along the second direction Y, increasing the reliability of the connection between the first power line and the second electrode plate 34.

[0234] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the range of the orthographic projection of the fifth active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the third via V3 are etched away, exposing the surface of the first region of the fifth active layer. The third via V3 is configured to allow a subsequently formed first power line to connect to the fifth active layer through the via.

[0235] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the range of the orthographic projection of the first active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the fourth via V4 are etched away, exposing the surface of the first region of the first active layer. The fourth via V4 is configured to allow subsequently formed initial signal lines to connect to the first active layer through this via.

[0236] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the range of the orthographic projection of the first active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the fifth via V5 are etched away, exposing the surface of the second region of the first active layer (which is also the first region of the seventh active layer). The fifth via V5 is configured to allow the second terminal of the subsequently formed first transistor T1 (which is also the first terminal of the seventh transistor T7) to be connected to the first active layer through this via.

[0237] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate lies within the orthographic projection of the seventh active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the second region of the seventh active layer. The sixth via V6 is configured to allow the second electrode of the subsequently formed seventh transistor T7 to be connected to the seventh active layer through this via.

[0238] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the range of the orthographic projection of the sixth active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the second region of the sixth active layer. The seventh via V7 is configured to allow a subsequently formed anode connection electrode to be connected to the sixth active layer through this via.

[0239] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the range of the orthographic projection of the third active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the second region of the third active layer. The eighth via V8 is configured to allow the first electrode of the subsequently formed second transistor T2 to be connected to the third active layer through the via.

[0240] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate lies within the range of the orthographic projection of the second active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the second active layer. The ninth via V9 is configured to allow the first electrode of the subsequently formed second transistor T2 to be connected to the second active layer through the via.

[0241] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate lies within the range of the orthographic projection of the second active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the tenth via V10 are etched away, exposing the surface of the second region of the second active layer. The tenth via V10 is configured to allow the second electrode of the subsequently formed second transistor T2 to be connected to the second active layer through the via.

[0242] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projection of the fourth active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the first region of the fourth active layer. The eleventh via V11 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the fourth active layer through the via.

[0243] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate lies within the range of the orthographic projection of the fourth active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the twelfth via V12 are etched away, exposing the surface of the second region of the fourth active layer. The twelfth via V12 is configured to allow the second electrode of the subsequently formed fourth transistor T4 to be connected to the fourth active layer through the via.

[0244] In an exemplary embodiment, the orthogonal projection of the thirteenth via V13 onto the substrate lies within the orthogonal projection of the NMOS active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the thirteenth via V13 are etched away, exposing the surface of the first region of the NMOS active layer. The thirteenth via V13 is configured to allow the first terminal of a subsequently formed NMOS transistor to be connected to the NMOS active layer through this via.

[0245] In an exemplary embodiment, the orthogonal projection of the fourteenth via V14 onto the substrate lies within the orthogonal projection of the NMOS active layer onto the substrate. The fifth, fourth, third, and second insulating layers within the fourteenth via V14 are etched away, exposing the surface of the second region of the NMOS active layer. The fourteenth via V14 is configured to allow the second terminal of a subsequently formed NMOS transistor to be connected to the NMOS active layer through this via.

[0246] In an exemplary embodiment, the orthogonal projection of the fifteenth via V15 onto the substrate lies within the orthogonal projection of the NMOS gate electrode 22 onto the substrate. The fifth, fourth, and third insulating layers within the fifteenth via V15 are etched away, exposing the surface of the NMOS gate electrode 22. The fifteenth via V15 is configured to allow the first electrode of a subsequently formed NMOS transistor to be connected to the NMOS gate electrode 22 through this via.

[0247] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate lies within the range of the orthographic projection of the first connection electrode 19 onto the substrate. The fifth, fourth, third, and second insulating layers within the sixteenth via V16 are etched away, exposing the surface of the first connection electrode 19. The sixteenth via V16 is configured to allow subsequently formed data connection electrodes to be connected to the first connection electrode 19 through this via.

[0248] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate lies within the range of the orthographic projection of the first connection electrode 19 onto the substrate. The fifth, fourth, third, and second insulating layers within the seventeenth via V17 are etched away, exposing the surface of the first connection electrode 19. The seventeenth via V17 is configured to allow the first electrode (which is also the first electrode of the NMOS transistor) of the subsequently formed fourth transistor T4 to be connected to the first connection electrode 19 through the via.

[0249] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third metal thin film on a substrate on which the aforementioned pattern is formed, and patterning the third metal thin film using a patterning process to form a third conductive layer pattern disposed on a fifth insulating layer. The third conductive layer pattern includes at least: an initial signal line 41, and a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode 47, an eighth connection electrode 48, a ninth connection electrode 49, and a tenth connection electrode 410 disposed in each sub-pixel. Figure 21a and Figure 21b As shown, Figure 21b for Figure 21a A schematic planar view of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0250] In an exemplary embodiment, the initial signal line 41 may extend along the first direction X. The initial signal line 41 is connected to the first region of the first active layer through the fourth via V4 in each sub-pixel, so that the initial signal line 41 inputs an initial voltage to the first electrode of the first transistor T1.

[0251] In an exemplary embodiment, the second connection electrode 42 may be a straight segment extending along the second direction Y. The first end of the second connection electrode 42 near the initial signal line 41 is connected to the second region of the seventh active layer via a sixth via V6. The second end of the second connection electrode 42 away from the initial signal line 41 is connected to the second region of the second active layer via a tenth via V10. The region between the first and second ends of the second connection electrode 42 is connected to the first electrode plate 23 via a first via V1, such that the first electrode plate 23 (the gate electrode of the third transistor T3), the second electrode of the second transistor T2, and the second electrode of the seventh transistor T7 have the same potential (first node N1). In an exemplary embodiment, the second connection electrode 42 may serve as the second electrode of both the second transistor T2 and the seventh transistor T7.

[0252] In an exemplary embodiment, the third connection electrode 43 can be a broken line segment. One end of the third connection electrode 43 is connected to the second region of the third active layer through the eighth via V8, and the other end of the third connection electrode 43 is connected to the first region of the second active layer through the ninth via V9, such that the first electrode of the second transistor T2 and the second electrode of the third transistor T2 have the same potential (third node N3). In an exemplary embodiment, the third connection electrode 43 can serve as both the first electrode of the second transistor T2 and the second electrode of the third transistor T2.

[0253] In an exemplary embodiment, the fourth connection electrode 44 may be a straight line segment extending along the first direction X, and the fourth connection electrode 44 is connected to the first connection electrode 19 through a sixteenth via V16. In an exemplary embodiment, the fourth connection electrode 44 may serve as a data connection electrode, configured to connect to a subsequently formed data signal line.

[0254] In an exemplary embodiment, the fifth connection electrode 45 can be a broken line segment. The first end of the fifth connection electrode 45 is connected to the first region of the fourth active layer through the eleventh via V11, the second end of the fifth connection electrode 45 is connected to the first connection electrode 19 through the seventeenth via V17, the third end of the fifth connection electrode 45 is connected to the first region of the NMOS active layer through the thirteenth via V13, and the fourth end of the fifth connection electrode 45 is connected to the NMOS gate electrode 22 through the fifteenth via V15. This ensures that the first electrode of the fourth transistor T4, the NMOS gate electrode 22 of the NMOS transistor E1, and the first electrode of the NMOS transistor E1 have the same potential. The data signal line formed subsequently can input data voltage to the fourth transistor T4 and the NMOS transistor E1 through the fourth connection electrode 44 and the first connection electrode 19. In an exemplary embodiment, the fifth connection electrode 45 can serve as the first electrode of the fourth transistor T4 and the first electrode of the NMOS transistor E1, and the gate electrode and the first electrode of the NMOS transistor E1 are shorted through the fifth connection electrode 45, forming a unidirectional conduction structure.

[0255] In an exemplary embodiment, the sixth connection electrode 46 can be a broken line segment. One end of the sixth connection electrode 46 is connected to the second region of the fourth active layer through the twelfth via V12, and the other end of the sixth connection electrode 46 is connected to the second region of the NMOS active layer through the fourteenth via V14. Since the second region of the NMOS active layer, the first region of the third active layer, and the first region of the sixth active layer are interconnected as a single structure, the sixth connection electrode 46 causes the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, the second terminal of the NMOS transistor E1, and the first terminal of the sixth transistor T6 to have the same potential (second node N2). In an exemplary embodiment, the sixth connection electrode 46 can serve as the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, the second terminal of the NMOS transistor E1, and the first terminal of the sixth transistor T6.

[0256] In an exemplary embodiment, the seventh connecting electrode 47 may be rectangular, and the seventh connecting electrode 47 is connected to the second electrode plate 34 through the second via V2. In an exemplary embodiment, the seventh connecting electrode 47 may serve as a power connection electrode, configured to connect to a subsequently formed first power line.

[0257] In an exemplary embodiment, the eighth connection electrode 48 may be rectangular, and the eighth connection electrode 48 is connected to the first region of the fifth active layer through the third via V3. In an exemplary embodiment, the eighth connection electrode 48 may serve as the first electrode of the fifth transistor T5, configured to be connected to the subsequently formed first power line.

[0258] In an exemplary embodiment, the ninth connection electrode 49 may be rectangular, and the ninth connection electrode 49 is connected to the second region of the sixth active layer through the seventh via V7. In an exemplary embodiment, the ninth connection electrode 49 may serve as the second electrode (fourth node N4) of the sixth transistor T6, configured to be connected to the subsequently formed anode connection electrode.

[0259] In an exemplary embodiment, the tenth connection electrode 410 may be rectangular. The tenth connection electrode 410 is connected to the second region of the first active layer (which is also the first region of the seventh active layer) through the fifth via V5, such that the second electrode of the first transistor T1 and the first electrode of the seventh transistor T7 have the same potential (fifth node N5). In an exemplary embodiment, the tenth connection electrode 410 may serve as the second electrode of the first transistor T1 and the first electrode of the seventh transistor T7.

[0260] (7) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the sixth insulating layer, and the plurality of vias of each sub-pixel include at least the twenty-first via V21 to the twenty-fourth via V24, such as... Figure 22a and Figure 22b As shown, Figure 22b for Figure 22a A planar schematic diagram of multiple vias.

[0261] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the fourth connection electrode 44 onto the substrate. The sixth insulating layer within the 21st via V21 is etched away, exposing the surface of the fourth connection electrode 44. The 21st via V21 is configured to allow subsequently formed data signal lines to be connected to the fourth connection electrode 44 through the via.

[0262] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the fourth connection electrode 44 onto the substrate. The sixth insulating layer within the 21st via V21 is etched away, exposing the surface of the fourth connection electrode 44. The 21st via V21 is configured to allow subsequently formed data signal lines to be connected to the fourth connection electrode 44 through the via.

[0263] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate is within the range of the orthographic projection of the 7th connecting electrode 47 onto the substrate. The 6th insulating layer within the 22nd via V22 is etched away, exposing the surface of the 7th connecting electrode 47. The 22nd via V22 is configured to allow a subsequently formed first power line to be connected to the 7th connecting electrode 47 through the via.

[0264] In an exemplary embodiment, the orthographic projection of the 23rd via V23 onto the substrate is within the range of the orthographic projection of the 8th connection electrode 48 onto the substrate. The 6th insulating layer within the 23rd via V23 is etched away, exposing the surface of the 8th connection electrode 48. The 23rd via V23 is configured to allow a subsequently formed first power line to be connected to the 8th connection electrode 48 through the via.

[0265] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate is within the range of the orthographic projection of the 9th connection electrode 49 onto the substrate. The 6th insulating layer within the 24th via V24 is etched away, exposing the surface of the 9th connection electrode 49. The 24th via V24 is configured to allow a subsequently formed anode connection electrode to be connected to the 9th connection electrode 49 through the via.

[0266] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth metal thin film on a substrate on which the aforementioned pattern is formed, patterning the fourth metal thin film using a patterning process to form a fourth conductive layer disposed on a sixth insulating layer. The fourth conductive layer includes at least: a data signal line 51, a first power line 52, and an anode connection electrode 53 disposed in each sub-pixel, such as... Figure 23a and Figure 23b As shown, Figure 23b for Figure 23a A schematic planar view of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0267] In an exemplary embodiment, the data signal line 51 can extend along the second direction Y, and the data signal line 51 is connected to the fourth connection electrode 44 through the twenty-first via V21. Since the fourth connection electrode 44 is connected to the first connection electrode 19 through the via, and the first connection electrode 19 is connected to the fifth connection electrode 45 through the via, and the fifth connection electrode 45 serves as both the first electrode of the fourth transistor T4 and the first electrode of the NMOS transistor E1, the data signal line 51 can be simultaneously connected to the first electrode of the fourth transistor T4 and the first electrode of the NMOS transistor E1 through the fourth connection electrode 44 and the first connection electrode 19. During the data writing phase, the data voltage output by the data signal line 51 is provided to the second node N2 through the fourth transistor T4 and the NMOS transistor E1.

[0268] In an exemplary embodiment, the first power line 52 may extend integrally along the second direction Y. The first power line 52 is connected to the seventh connecting electrode 47 through the twenty-second via V22 and to the eighth connecting electrode 48 through the twenty-third via V23. Since the seventh connecting electrode 47 is connected to the second electrode plate 34 through the via, and the eighth connecting electrode 48 is connected to the first electrode of the fifth transistor T5 through the via, the second electrode plate 34 of the storage capacitor and the first electrode of the fifth transistor T5 have the same potential.

[0269] In an exemplary embodiment, the anode connection electrode 53 in each sub-pixel can be rectangular. The anode connection electrode 53 is connected to the ninth connection electrode 49 through the twenty-fourth via V24, and the anode connection electrode 53 is configured to be connected to the subsequently formed anode. Since the ninth connection electrode 49 is connected to the second electrode of the sixth transistor T6 through the via, the subsequent anode is connected to the second electrode of the sixth transistor T6, thus enabling the pixel driving circuit to drive the light-emitting device to emit light.

[0270] As can be seen from the structure and fabrication process of the pixel driving circuit described above, the pixel driving circuit provided in this disclosure forms an NMOS transistor with unidirectional conduction performance while forming multiple transistors. During the data writing stage, the data voltage output from the data signal line can be provided to the second node through the NMOS transistor. This allows for rapid data writing, compensating for the low on-state current and mobility of the fourth transistor T4, avoiding insufficient charging of the storage capacitor during signal writing, and improving the display effect. Simultaneously, it stabilizes the voltage of the second node N2 during the light-emitting stage, preventing leakage current in the driving sub-circuit. The fabrication process of this disclosure is highly compatible with existing fabrication processes, is simple to implement, easy to execute, has high production efficiency, low production cost, and high yield.

[0271] The structure and fabrication process of the pixel driving circuit described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be modified and increased or decreased according to actual needs. For example, a second NMOS transistor can be set in the compensation sub-circuit, and a third NMOS transistor can be set in the reset sub-circuit. Furthermore, unidirectional PN junction diodes can be set in the write sub-circuit, compensation sub-circuit, and / or reset sub-circuit, etc., which are not limited herein.

[0272] This disclosure also provides a method for fabricating a display substrate, configured to fabricate the aforementioned display substrate. In an exemplary embodiment, the display substrate includes a plurality of sub-pixels, and the driving method may include:

[0273] S1. A driving circuit layer is formed in at least one sub-pixel, the driving circuit layer including a pixel driving circuit;

[0274] S2. A light-emitting structure layer is formed on the driving circuit layer, the light-emitting structure layer including a light-emitting device connected to the pixel driving circuit;

[0275] The reset sub-circuit is connected to the second scan signal line, the initial signal line, the first node, and the fourth node, respectively, and is configured to provide the initial voltage output by the initial signal line to the first node and the fourth node under the control of the second scan signal line.

[0276] The writing sub-circuit is connected to the first scan signal line, the data signal line, and the second node, respectively, and is configured to provide the data voltage output by the data signal line to the second node under the control of the first scan signal line.

[0277] The driving sub-circuit is connected to the first node, the second node and the third node respectively, and is configured to provide the voltage of the second node to the third node under the control of the first node;

[0278] The compensation sub-circuit is connected to the first scan signal line, the first node, and the third node respectively, and is configured to provide the voltage of the third node to the first node under the control of the first scan signal line in order to compensate the first node until the voltage of the first node meets the threshold condition.

[0279] The energy storage sub-circuit is connected to the first power line and the first node respectively, and is configured to store the voltage difference between the first power supply voltage output by the first power line and the first node.

[0280] The light-emitting control sub-circuit is connected to the light-emitting control line, the first power line, the second node, the third node, and the fourth node, respectively, and is configured to provide the second node with the first power supply voltage output by the first power line and the fourth node with the voltage of the third node under the control of the light-emitting control line.

[0281] At least one of the reset sub-circuit, compensation sub-circuit, and write sub-circuit includes an oxide transistor and a unidirectional conducting device.

[0282] This disclosure also provides a display device, including the pixel driving circuit of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0283] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate comprising a plurality of sub-pixels, at least one sub-pixel comprising a driving circuit layer and a light-emitting structure layer disposed on the driving circuit layer; the driving circuit layer comprising a pixel driving circuit, the light-emitting structure layer comprising a light-emitting device connected to the pixel driving circuit; the pixel driving circuit comprising a reset sub-circuit, a write sub-circuit, a driving sub-circuit, a compensation sub-circuit, an energy storage sub-circuit, and a light-emitting control sub-circuit; The reset sub-circuit is connected to the second scan signal line, the initial signal line, the first node, and the fourth node, respectively, and is configured to provide the initial voltage output by the initial signal line to the first node and the fourth node under the control of the second scan signal line. The writing sub-circuit is connected to the first scan signal line, the data signal line, and the second node, respectively, and is configured to provide the data voltage output by the data signal line to the second node under the control of the first scan signal line. The driving sub-circuit is connected to the first node, the second node and the third node respectively, and is configured to provide the voltage of the second node to the third node under the control of the first node; The compensation sub-circuit is connected to the first scan signal line, the first node, and the third node respectively, and is configured to provide the voltage of the third node to the first node under the control of the first scan signal line in order to compensate the first node until the voltage of the first node meets the threshold condition. The energy storage sub-circuit is connected to the first power line and the first node respectively, and is configured to store the voltage difference between the first power supply voltage output by the first power line and the first node. The light-emitting control sub-circuit is connected to the light-emitting control line, the first power line, the second node, the third node, and the fourth node, respectively, and is configured to provide the second node with the first power supply voltage output by the first power line and the fourth node with the voltage of the third node under the control of the light-emitting control line. At least one of the reset sub-circuit, compensation sub-circuit, and write sub-circuit includes an oxide transistor and a unidirectional conducting device; wherein... The write sub-circuit includes a fourth transistor and a first diode or a first transistor as a unidirectional conducting device. The fourth transistor is an oxide transistor. The control electrode of the fourth transistor is connected to the first scan signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the second node. The positive electrode of the first diode is connected to the data signal line, and the negative electrode is connected to the second node. The control electrode and the first electrode of the first transistor are both connected to the data signal line, and the second electrode is connected to the second node N2. The compensation sub-circuit includes a second transistor and a second diode or a second transistor as a unidirectional conducting device. The second transistor is an oxide transistor. The control electrode of the second transistor is connected to the first scan signal line, the first electrode is connected to the third node, and the second electrode is connected to the first node. The positive electrode of the second diode is connected to the third node, and the negative electrode is connected to the first node. The control electrode and the first electrode of the second transistor are both connected to the third node, and the second electrode is connected to the first node. The reset circuit includes a first transistor, a seventh transistor, and a third diode or a third transistor as a unidirectional conducting device. The first transistor and the seventh transistor are oxide transistors. The control electrode of the first transistor is connected to the second scan signal line, the first electrode is connected to the initial signal line, and the second electrode is connected to the fifth node. The control electrode of the seventh transistor is connected to the second scan signal line, the first electrode is connected to the fifth node, and the second electrode is connected to the first node. The positive electrode of the third diode is connected to the fifth node, and the negative electrode is connected to the first node. The control electrode and the first electrode of the third transistor are both connected to the fifth node, and the second electrode is connected to the first node N1.

2. The display substrate according to claim 1, wherein, The driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a substrate. The first semiconductor layer includes an active layer of multiple polysilicon transistors. The first conductive layer includes gate electrodes of multiple polysilicon transistors and a first plate of a storage capacitor. The second conductive layer includes gate electrodes of multiple oxide transistors and a second plate of a storage capacitor. The second semiconductor layer includes an active layer of multiple oxide transistors. The third conductive layer includes an initial signal line and multiple connection electrodes. The fourth conductive layer includes a data signal line and a first power supply line.

3. The display substrate according to claim 2, wherein, The first semiconductor layer includes the active layer of the third transistor, the active layer of the fifth transistor, the active layer of the sixth transistor, the active layer of the NMOS transistor, and a first connection electrode; the first conductive layer includes the gate electrode of the third transistor, the gate electrode of the fifth transistor, the gate electrode of the sixth transistor, and the gate electrode of the NMOS transistor, which serve as the first electrode plate; the second semiconductor layer includes the active layer of the first transistor, the active layer of the second transistor, the active layer of the fourth transistor, and the active layer of the seventh transistor, wherein the second region of the active layer of the first transistor is connected to the first region of the active layer of the seventh transistor; the second conductive layer includes a second electrode plate, the gate electrode of the first transistor, the gate electrode of the second transistor, the gate electrode of the fourth transistor, and the gate electrode of the seventh transistor.

4. The display substrate according to claim 3, wherein, The plurality of connection electrodes include a second connection electrode and a third connection electrode; the initial signal line is connected to the first region of the active layer of the first transistor through a via, the second connection electrode is connected to the second region of the active layer of the seventh transistor, the second region of the active layer of the second transistor and the first electrode plate through vias respectively, and the third connection electrode is connected to the second region of the active layer of the third transistor and the first region of the active layer of the second transistor through vias respectively.

5. The display substrate according to claim 4, wherein, The plurality of connection electrodes further includes a fourth connection electrode, a fifth connection electrode, and a sixth connection electrode; the fourth connection electrode is connected to the first connection electrode through a via, the fifth connection electrode is connected to the first connection electrode, the first region of the active layer of the fourth transistor, the first region of the active layer of the NMOS transistor, and the gate electrode of the NMOS transistor through vias, and the sixth connection electrode is connected to the second region of the active layer of the fourth transistor and the second region of the active layer of the NMOS transistor through vias.

6. The display substrate according to claim 5, wherein, The data signal line of the fourth conductive layer is connected to the fourth connection electrode through a via.

7. The display substrate according to claim 3, wherein, The plurality of connecting electrodes includes a seventh connecting electrode, which is connected to the second electrode plate through a via, and the first power line of the fourth conductive layer is connected to the seventh connecting electrode through a via.

8. The display substrate according to claim 3, wherein, The plurality of connection electrodes includes an eighth connection electrode, which is connected to the first region of the active layer of the fifth transistor through a via, and the first power line of the fourth conductive layer is connected to the eighth connection electrode through a via.

9. The display substrate according to claim 3, wherein, The plurality of connection electrodes includes a ninth connection electrode, which is connected to the second region of the active layer of the sixth transistor through a via. The fourth conductive layer also includes an anode connection electrode, which is connected to the ninth connection electrode through a via.

10. A display device comprising a display substrate as described in any one of claims 1 to 9.

11. A method for fabricating a display substrate, the display substrate comprising a plurality of sub-pixels; the fabrication method comprising: A driving circuit layer is formed in at least one sub-pixel, the driving circuit layer including a pixel driving circuit; A light-emitting structure layer is formed on the driving circuit layer, and the light-emitting structure layer includes a light-emitting device connected to the pixel driving circuit. The pixel driving circuit includes a reset sub-circuit, a writing sub-circuit, a driving sub-circuit, a compensation sub-circuit, an energy storage sub-circuit, and a light emission control sub-circuit. The reset sub-circuit is connected to the second scan signal line, the initial signal line, the first node, and the fourth node, respectively, and is configured to provide the initial voltage output by the initial signal line to the first node and the fourth node under the control of the second scan signal line. The writing sub-circuit is connected to the first scan signal line, the data signal line, and the second node, respectively, and is configured to provide the data voltage output by the data signal line to the second node under the control of the first scan signal line. The driving sub-circuit is connected to the first node, the second node and the third node respectively, and is configured to provide the voltage of the second node to the third node under the control of the first node; The compensation sub-circuit is connected to the first scan signal line, the first node, and the third node respectively, and is configured to provide the voltage of the third node to the first node under the control of the first scan signal line in order to compensate the first node until the voltage of the first node meets the threshold condition. The energy storage sub-circuit is connected to the first power line and the first node respectively, and is configured to store the voltage difference between the first power supply voltage output by the first power line and the first node. The light-emitting control sub-circuit is connected to the light-emitting control line, the first power line, the second node, the third node, and the fourth node, respectively, and is configured to provide the second node with the first power supply voltage output by the first power line and the fourth node with the voltage of the third node under the control of the light-emitting control line. At least one of the reset sub-circuit, compensation sub-circuit, and write sub-circuit includes an oxide transistor and a unidirectional conducting device; wherein... The write sub-circuit includes a fourth transistor and a first diode or a first transistor as a unidirectional conducting device. The fourth transistor is an oxide transistor. The control electrode of the fourth transistor is connected to the first scan signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the second node. The positive electrode of the first diode is connected to the data signal line, and the negative electrode is connected to the second node. The control electrode and the first electrode of the first transistor are both connected to the data signal line, and the second electrode is connected to the second node N2. The compensation sub-circuit includes a second transistor and a second diode or a second transistor as a unidirectional conducting device. The second transistor is an oxide transistor. The control electrode of the second transistor is connected to the first scan signal line, the first electrode is connected to the third node, and the second electrode is connected to the first node. The positive electrode of the second diode is connected to the third node, and the negative electrode is connected to the first node. The control electrode and the first electrode of the second transistor are both connected to the third node, and the second electrode is connected to the first node. The reset circuit includes a first transistor, a seventh transistor, and a third diode or a third transistor as a unidirectional conducting device. The first transistor and the seventh transistor are oxide transistors. The control electrode of the first transistor is connected to the second scan signal line, the first electrode is connected to the initial signal line, and the second electrode is connected to the fifth node. The control electrode of the seventh transistor is connected to the second scan signal line, the first electrode is connected to the fifth node, and the second electrode is connected to the first node. The positive electrode of the third diode is connected to the fifth node, and the negative electrode is connected to the first node. The control electrode and the first electrode of the third transistor are both connected to the fifth node, and the second electrode is connected to the first node N1.

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