Method for achieving flash uniform wear by simulating general memory

Abstract

The application provides a method for realizing FLASH uniform wear by simulating general memory, comprising the following steps: based on FLASH simulating general memory, configuring an information table for each page of the general memory; when requesting to write data into FLASH, generating a page mapping table based on the information table of each page, determining a target write page based on the page mapping table, and writing data into the target write page; when requesting to read data from FLASH, generating a page mapping table based on the information table of each page, determining a target read page based on the page mapping table, and reading data from the target read page. The application establishes a controllable logic layer on the basis of a standard Flash ROM memory chip, maps the unbalanced Flash ROM memory chip into an address access optimized general memory space, saves special storage peripherals, and realizes the wear degree of balanced FLASH quickly and conveniently based on the page mapping table for writing or reading data.

Description

Technical Field

[0001] This invention relates to the field of FLASH storage, and more specifically, to a method for achieving uniform wear of FLASH memory by simulating general-purpose memory. Background Technology

[0002] Currently, combustible gas monitoring equipment and ambient gas monitoring equipment typically have data recording functions. Considering stability and power consumption, these monitoring devices usually use a microcontroller as the main controller. The microcontroller program and other non-lossable data (such as monitoring results) are usually stored in the microcontroller's internal EEPROM. EEPROM memory has good write resistance but small capacity. With the development of society, the intelligence level of these smart instruments is becoming higher and higher, and the total amount of programs and non-lossable data is becoming larger and larger. EEPROM can no longer meet the storage capacity requirements, and manufacturers have begun to consider using Flash ROM as the memory chip.

[0003] Flash ROM memory inherently suffers from wear and tear, so many flash memory cards include wear leveling features. However, for data security reasons, microcontroller programs and other non-lossable data cannot be stored in external memory with wear leveling capabilities. Furthermore, microcontrollers do not have a traditional operating system; instead, the software directly accesses data and program memory. In terms of access method, microcontrollers do not access memory in the traditional file access manner, but rather access specific memory locations by address. Therefore, once the microcontroller program determines to read or write to a particular memory location, it will always access that location within that specific code segment.

[0004] During the operation of monitoring equipment, a large amount of data is often generated that needs to be stored. This means that a large amount of data needs to be written or rewritten frequently. If the physical address of the data being written is not managed, a memory cell may experience significant wear due to frequent writing or rewriting, shortening the lifespan of the equipment and increasing the cost of use.

[0005] Therefore, there is an urgent need for a method to manage the physical address of the data written to the FLASH chip, so that the wear of each address range of the FLASH chip is more uniform, thereby extending the service life of the device chip.

[0006] In order to solve the above problems, people have been seeking an ideal technological solution. Summary of the Invention

[0007] The purpose of this invention is to address the shortcomings of existing technologies by providing a method for achieving uniform wear of FLASH memory through simulating general-purpose memory.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is: a method for achieving uniform wear of FLASH memory by simulating general-purpose memory, comprising the following steps:

[0009] Based on FLASH-simulated general-purpose memory, an information table is configured for each page of the general-purpose memory. The information table includes the page's erase count, address range, checksum, and write serial number (SN). The checksum indicates the page's state, including two values: invalid and valid. The address range is the logical address interval of the data simulated by the page, and the length of each address range is the page length minus the length of the information table. The erase count is the number of times the page has been erased. The write serial number (SN) is the sum of the erase counts for all pages.

[0010] When requesting to write data to FLASH, a page mapping table is generated based on the information table of each page, and the target page to be written is determined based on the page mapping table, and the data is written to the target page.

[0011] When requesting to read data from FLASH, a page mapping table is generated based on the information table of each page, and the target page to be read is determined based on the page mapping table, and data is read from the target page.

[0012] This invention establishes a controllable logic layer on top of a standard Flash ROM memory chip, mapping the unbalanced Flash ROM chip into a general-purpose memory space with optimized address access, eliminating the need for dedicated storage peripherals. When requesting to write data, only the logical start address and data length are provided. Then, based on the page mapping table, the page with the least wear is determined as the target page, and the data is written to the target page. When requesting to read data, similarly, only the logical start address and data length are provided. Then, the corresponding page address is found according to the page mapping table as the target page for reading, and the data is read out. Ultimately, this achieves balanced wear of the Flash memory.

[0013] In one embodiment, determining the target write page based on a page mapping table and writing data to the target write page includes the following steps:

[0014] Based on the page mapping table, the information of the data to be written is converted into an address segment, the byte address within the segment, and the length of data available in that address segment;

[0015] Determine if there is a page address range that matches it. If so, determine the page status of each matching page based on the page mapping table. The page status includes valid page, invalid page, and free page.

[0016] Determine the target page to write to based on the page status of each matching page, and update its information table;

[0017] The target data to be written to the page is read into the internal buffer, and the data to be written is written to the end of the internal buffer according to the byte address in the segment.

[0018] Write all the data in the internal cache to the target write page, and subtract the length of the data to be written from the length of the data to be written.

[0019] Repeat the above steps multiple times until all data to be written has been written.

[0020] Furthermore, this embodiment uses a blocking method to write data, utilizing the relay function of the internal cache to write the data to be written into the FLASH. During this process, since the requested data does not directly modify the old page, even if the power is interrupted during the writing of new data, the old data can still be recovered and will not be lost, making the storage safer.

[0021] In one embodiment, determining the page state of each page based on the page mapping table includes the following steps:

[0022] The page status is determined based on the checksum in the information table of each matching page. If the checksum is incorrect, the page status is determined to be invalid; if the checksum is correct, the page status is determined to be valid.

[0023] Compare the write serial number (SN) of each valid matching page with the write serial number (SN) of other valid matching pages with the same address range. The matching page with the larger SN is determined to be a valid page; otherwise, it is a free page.

[0024] In one embodiment, after determining the page status of each matching page based on the page mapping table, an invalid page or a free page with the fewest erase counts is selected as the target page to be written this time.

[0025] Invalid pages have the highest priority, while free pages have the highest priority in ascending order of the number of erases.

[0026] In one embodiment, determining the target page to be read based on a page mapping table and reading data from the target page includes the following steps:

[0027] Based on the page mapping table, the information of the data to be read is converted into an address segment, the byte address within the segment, and the length of data available in that address segment;

[0028] The page address is located based on the page mapping table as the target page to be read.

[0029] The data to be read is located from the target page based on the byte address and data length within the segment, read into the internal buffer, and then read from the internal buffer.

[0030] Subtract the length of the current data to be read from the length of the data to be read.

[0031] Repeat the above steps multiple times until all the data to be read has been read.

[0032] In one embodiment, when writing data to FLASH, it is determined whether the length of the data to be written exceeds the maximum length of the analog memory. If it does, the writing step is terminated.

[0033] When reading data from FLASH, it is determined whether the length of the data to be read exceeds the limit. If it does, the reading step ends.

[0034] In one embodiment, for each write request, it is determined whether to perform static wear leveling.

[0035] The present invention also provides a computer storage medium storing a computer program that, when executed by a processor, implements the steps of the aforementioned method for achieving uniform wear of FLASH memory by simulating general-purpose memory.

[0036] The present invention also provides a combustible gas monitoring device, which has the aforementioned computer storage medium built in.

[0037] The present invention also provides an environmental gas monitoring device, which has the aforementioned computer storage medium built in. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating the present invention.

[0039] Figure 2 This is a schematic diagram of the page content of the present invention.

[0040] Figure 3 This is a diagram of the logical address range.

[0041] Figure 4 This is a diagram illustrating the logical relationship between a page and its physical address.

[0042] Figure 5 This is a diagram of the page mapping table.

[0043] Figure 6 This is a flowchart illustrating the writing process. Detailed Implementation

[0044] The technical solution of the present invention will be further described in detail below through specific embodiments.

[0045] Example 1

[0046] like Figure 1 As shown, a method for achieving uniform wear of FLASH memory by simulating general-purpose memory includes the following steps:

[0047] Based on FLASH simulation of general-purpose memory.

[0048] In practice, the number of pages and the length of a single page in the general-purpose memory management system can be freely defined. The maximum page length is 512 bytes, and the maximum number of pages is 256.

[0049] An information table is configured for each page of the general-purpose memory. The information table includes the page's erase count, address range, checksum, and write serial number (SN). Figure 2 The page content structure is shown. It can be seen that in addition to the information table, the page content also includes a data storage area. When the page length is 512 bytes, the data storage area includes 504 bytes, the information table is 8 bytes, of which the erase count occupies 20 bits, the address field occupies 8 bits, the checksum occupies 4 bits, and the serial number SN occupies 32 bits.

[0050] Specifically, the address range of the information table is used to represent the logical address range of the data simulated by the page. The length of each address range is the page length minus the length of the information table. For example, if the total number of pages is 4, and each page is 512 bytes long; the information table length is fixed at 8 bytes, and the address range = n, then the logical starting address of the page is: (512-8)*n = 504n, and the logical ending address is: (512-8)*(n+1)-1 = 504n+503. Figure 3 As shown.

[0051] That is, the logical address is related to the address range in the information table. One logical address corresponds to multiple pages, and the page number corresponds one-to-one with the physical address, such as... Figure 4 As shown.

[0052] The number of times the information table is erased is a local variable, which refers to the cumulative number of times the corresponding page n is erased, that is, the wear and tear of the corresponding page.

[0053] The verification key in the information table is used to indicate whether the page information is valid. Specifically, the verification key has two values: invalid and valid.

[0054] The write serial number SN in the information table represents the total number of erases and writes. Its value is a global variable; after data is written to a page, the write serial number SN is incremented by 1. Therefore, this value is the sum of all page erase counts. A larger SN value indicates newer data. For example, if pages 0, 1, and 2 all have an address range of 2, it means the pages correspond to the same logical address. In this case, the page with the largest write serial number SN contains the newest data, while the other two pages contain older data.

[0055] As can be seen, although the content of the information table is simple, it contains a lot of information. Therefore, a page mapping table can be generated based on the information table in the future, making it easier to manage the wear and tear of the FLASH.

[0056] After the general-purpose memory simulation is completed, when a request is made to write data to the FLASH, a page mapping table is generated based on the information table of each page, such as... Figure 5 As shown, the target write page is determined based on the page mapping table, and the data is written to the target write page.

[0057] Specifically, such as Figure 6 As shown, determining the target write page based on the page mapping table and writing data to the target write page includes the following steps:

[0058] Based on the page mapping table, the information of the data to be written is converted into an address segment, the byte address within the segment, and the length of data available in that address segment.

[0059] Determine if there is a matching page address range. If so, determine the page status of each matching page based on the page mapping table. The page status includes valid page, invalid page, and free page. Invalid means that the page data and page information are invalid. Free means that the page data and page information are valid, but not the latest data. Valid means that the page data and page information are valid and have been recently written.

[0060] Determining the page state of each page based on the page mapping table includes the following steps:

[0061] The page status is determined based on the checksum in the information table of each matching page. If the checksum is incorrect, the page status is determined to be invalid; if the checksum is correct, the page status is determined to be valid.

[0062] Compare the write serial number (SN) of each valid matching page with the write serial number (SN) of other valid matching pages with the same address range. The matching page with the larger SN is determined to be a valid page; otherwise, it is a free page.

[0063] The target page to be written is determined based on the page status of each matching page, and its information table is updated. Specifically, an invalid page or a free page with the fewest erase counts is selected as the target page to be written. Among them, invalid pages have the highest priority, and the priority order of free pages is from smallest to largest erase count.

[0064] The target data to be written to the page is read into the internal buffer, and the data to be written is written to the end of the internal buffer according to the byte address in the segment.

[0065] Write all data in the internal cache to the target write page, and subtract the length of the data to be written from the length of the data to be written.

[0066] Repeat the above steps multiple times until all data to be written has been written.

[0067] When requesting to read data from FLASH, a page mapping table is generated based on the information table of each page, and the target page to be read is determined based on the page mapping table, and data is read from the target page.

[0068] The process of determining the target page based on the page mapping table and reading data from the target page includes the following steps:

[0069] Based on the page mapping table, the information of the data to be read is converted into an address segment, the byte address within the segment, and the length of data available in that address segment;

[0070] The page address is located based on the page mapping table as the target page to be read.

[0071] The data to be read is located from the target page based on the byte address and data length within the segment, read into the internal buffer, and then read from the internal buffer.

[0072] Subtract the length of the current data to be read from the length of the data to be read.

[0073] Repeat the above steps multiple times until all the data to be read has been read.

[0074] As can be seen, this invention establishes a controllable logic layer on top of a standard Flash ROM memory chip, mapping the unbalanced Flash ROM chip into a general-purpose memory space with optimized address access, eliminating the need for dedicated storage peripherals. When requesting to write data, only the logical start address and data length are provided. Then, based on the page mapping table, the page with the least wear is determined as the target page, and the data is written to the target page. When requesting to read data, the logical start address and data length are provided in the same order, and then the target page is determined based on the page mapping table for data reading.

[0075] Furthermore, during data writing, this embodiment employs a blocking method, utilizing the internal cache as an intermediary to write the data to be written into the FLASH. Since the requested data does not directly modify the old pages during this process, even if a power outage occurs while new data is being written, the old data can still be recovered and will not be lost, making storage more secure. During data reading, this embodiment also employs a blocking method. Based on the mapping table and logical address, the data is first read into the internal cache, and then read out from the internal cache all at once. The advantage of this is that even a power outage during the reading process will not cause any impact. Because if actions are taken simultaneously while reading, a power outage can easily result in only part of the action being executed; however, reading into the internal cache first and then reading out from the internal cache all at once reduces this possibility. This is because using memory for data is the most efficient method.

[0076] It is understandable that when writing data to FLASH, it is also possible to first determine whether the length of the data to be written exceeds the maximum length of the analog memory. If it does not exceed the maximum length, there is no data overflow, and a page mapping table is generated based on the information table of each page. If it exceeds the maximum length, there is a data overflow, the corresponding error message is returned, and the writing step ends.

[0077] Similarly, when reading data from FLASH, it is possible to first determine whether the length of the data to be read exceeds the limit. If it does, the reading step is terminated; if it does not exceed the limit, a page mapping table is generated based on the information table of each page.

[0078] It is important to note that the method for achieving uniform FLASH wear by simulating general-purpose memory described in this embodiment is dynamic wear balancing. Dynamic wear balancing refers to writing new data to a special page with fewer erase cycles when data in a page needs to be changed, while marking the original page as invalid. The disadvantage of dynamic wear balancing is that if the data just written is quickly updated again, the newly updated data block will soon become invalid again. Frequent updates will undoubtedly result in blocks storing cold data being erased very infrequently, adversely affecting the overall lifespan of the flash memory. Early solid-state drive controllers mostly used dynamic wear balancing algorithms. Now, research is more focused on using both dynamic and static methods. Static wear balancing considers blocks with very low frequency (cold data), such as the blocks containing system data or certain read-only data. These blocks containing cold data are updated much less frequently than the blocks containing hot data. The static wear balancing algorithm includes these blocks containing cold data in the wear balancing process, increasing the overall lifespan of the flash memory.

[0079] Therefore, in this embodiment, for each write request, it is necessary to determine whether to perform static wear leveling. Specifically, the static wear leveling process is as follows:

[0080] The first step is to find the valid page with the fewest erase counts. The data stored at the physical address of this page is valid and has a low usage rate.

[0081] The second step is to find the free page with the most erases. The physical address of this page can be used to store data and has a high utilization rate.

[0082] The third step is to analyze whether the difference in the number of erases between the two pages is greater than a set threshold. If it is, the data of the page found in the first step is stored in the internal cache, and the data is cached from the internal cache to the page found in the second step, thereby achieving static wear leveling. Otherwise, no action is taken.

[0083] Example 2

[0084] This embodiment provides a computer storage medium storing a computer program. When the program is executed by a processor, it implements the steps of the method for achieving uniform wear of FLASH by simulating general-purpose memory as described in Embodiment 1.

[0085] Example 3

[0086] This embodiment also provides a combustible gas monitoring device, which has a built-in computer storage medium as described in Embodiment 2.

[0087] This embodiment also provides an environmental gas monitoring device, which has a built-in computer storage medium as described in Embodiment 2.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A method for achieving FLASH wear leveling by emulating a general purpose memory, the method comprising: The method comprises the following steps: ​ configuring an information table for each page of the general memory based on the FLASH analog general memory, the information table comprising the erasing times, address segment, check word and write serial number SN of the page; the check word representing the page state of the page, comprising two values of invalid and valid; the address segment being the logical address interval of the data storage simulated by the page, the length of each address segment being the page length minus the length of the information table; the erasing times being the erasing times of the page; the write serial number SN being the sum of the erasing times of all pages; generating a page mapping table based on the information table of each page when requesting to write data into the FLASH, and determining a target write page based on the page mapping table and writing data into the target write page; determining the target write page based on the page mapping table and writing data into the target write page comprises the following steps: converting the information of the data to be written into the address segment, byte address in the segment and data length available in the address segment based on the page mapping table; determining whether there is a page matching the address segment, if yes, determining the page state of each matching page based on the page mapping table, the page state comprising valid page, invalid page and free page; determining the target write page according to the page state of each matching page and updating the information table thereof; reading the data of the target write page to an internal cache area and writing the data to be written to the tail of the internal cache area according to the byte address in the segment; writing all the data in the internal cache area into the target write page and subtracting the length of the data written this time from the data length of the data to be written; repeating the above steps multiple times until all the data to be written is written; generating a page mapping table based on the information table of each page when requesting to read data from the FLASH, and determining a target read page based on the page mapping table and reading data from the target read page; determining the target read page based on the page mapping table and reading data from the target read page comprises the following steps: converting the information of the data to be read into the address segment, byte address in the segment and data length available in the address segment based on the page mapping table; finding the corresponding page address as the target read page according to the page mapping table; finding the data to be read from the target read page according to the byte address in the segment and the data length and reading to the internal cache area, and then reading the data from the internal cache area; subtracting the length of the data to be read this time from the length of the data to be read; repeating the above steps multiple times until all the data to be read is read out.

2. The method for achieving FLASH uniform wear by simulating general memory according to claim 1, wherein, determining the page state of each page based on the page mapping table comprises the following steps: judging the page state according to the check word in the information table of each matching page, if the check word is wrong, determining the page state as invalid; if the check word is correct, determining the page state as valid; comparing the write serial number SN of each matching page with the page state valid with the write serial number SN of other matching pages with the same address segment and the page state valid, the matching page with the larger SN being determined as the valid page, otherwise as the free page.

3. The method for achieving FLASH uniform wear by simulating general memory according to claim 1, characterized in that: after determining the page state of each matching page based on the page mapping table, selecting the invalid page or the free page with the smallest erasing times as the target write page this time; Among them, the invalid page has the highest priority, and the priority of the free page is in order from small to large according to the number of erasures.

4. The method for achieving FLASH uniform wear by simulating general memory according to any one of claims 1 to 3, characterized in that, When writing data into the FLASH, it is judged whether the data length of the data to be written exceeds the maximum length of the analog memory, and if it exceeds, the writing step is ended; When reading data from the FLASH, it is judged whether the length of the data to be read is out of bounds, and if it is out of bounds, the reading step is ended.

5. The method for achieving FLASH uniform wear by simulating general memory according to any one of claims 1 to 3, characterized in that, Static wear leveling is judged whether to be executed every time a write request occurs.

6. A computer storage medium, characterized in that The computer storage medium has a computer program stored thereon, which, when executed by a processor, implements the steps of the method for achieving uniform wear of the FLASH by simulating a general memory according to any one of claims 1 to 5.

7. A combustible gas monitoring apparatus characterized by comprising: The computer storage medium according to claim 6 is built-in.

8. An ambient gas monitoring apparatus characterized by comprising: The computer storage medium according to claim 6 is built-in.

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