Sample-and-hold circuit for slope analog-to-digital conversion

Abstract

A sample-and-hold readout system and method for ramp analog-to-digital conversion is presented, in which a sample-and-hold circuit is used to read out an optical array such that each sample is used to charge a sample-and-hold capacitor and is read out during a hold phase using an amplifier driving a ramp analog-to-digital converter. The sample-and-hold circuit transitions to a track phase in which an optical array input drives the amplifier, which drives the sample-and-hold capacitor, and then transitions to a sample phase in which the sample-and-hold capacitor is directly connected to an optical array output.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a sample-and-hold readout system and method for ramp analog-to-digital conversion, in particular to a sample-and-hold circuit and a sample-and-hold method for converting optical array samples to a digital representation. BACKGROUND

[0002] An optical sensor consists of cells or pixels that store an amount of charge determined by exposure to light. An image is formed by an array of pixels exposed to light from a scene. To read the resulting image, the charge stored on the pixel array needs to be read out. A common approach is to sample each pixel by allowing it to charge a device such as a capacitor, then convert the voltage of the capacitor using an analog-to-digital converter or ADC. A common technique for converting from analog to digital is to use a ramp ADC. A ramp ADC is an ADC that provides the voltage to be converted to the input of a comparator. The other comparator input is fed by a digital-to-analog converter that is digitally driven by a counter. The counter counts until the comparator trips. When the comparator trips, the counter stops and the value of the counter is saved as the digital equivalent of the voltage converted. A simplified representation of this system is shown in Figure 1.

[0003] Figure 1 is a prior art block diagram of optical array sensing and readout electronics. It shows the optical array output electrically coupled to a sample-and-hold circuit 120. The sample-and-hold circuit is electrically coupled to a comparator (comp). The comparator also has an input electrically coupled to a ramp buffer (ramp buf) and a buffered output of a digital-to-analog converter (not shown). When the comparator triggers (the two inputs are equal), the value of the counter driving the digital-to-analog converter is stored in a memory (ASRAM). The comparator capacitor 110 is discharged or reset by the assertion of a control called Dcomp_RST.

[0004] Figure 2 is a schematic diagram of the sample-and-hold circuit of Figure 1. Figure 2 shows two identical branch circuits so that the pixels can be read and converted in a pipelined fashion.

[0005] Figure 3 is a timing diagram for the circuit of Figure 2, useful for understanding the sample-and-hold process that occurs in the sample-and-hold circuit. Timing begins with swl closed, sw2 open (Tl), so that only the upper half of the circuit is connected to the input. At time Tl, rst2 is also asserted. Capacitor 210 is connected to Vin via switch shr 1 to sample the reset value (Rl) for row 1. The charge is held in capacitor 210 until the charge is read out and converted. Switch shr 1 is opened, and then shsl is closed (T2) to connect 212 to the input Vin to sample the signal value (Sl) for row 1. When swl is opened (T3), both capacitors 210 and 212 connected to shr 1 and shsl hold the pixel reset and signal for row 1. ADC conversion of the row 1 pixel begins with the rstl pulse (T4) to clear the sample node in the top branch. Also at T4, sw2 is closed, beginning the sampling of R(2). In the source follower configuration, shr 1 is again closed to connect capacitor 210 to the gate of FET Q220. The reset value is held and converted by counting the digital input to the DAC. When the output of the DAC equals the sample value, the pixel value is stored. For the bottom circuit connected to sw2, the situation is reversed. When sl is closed, s2 is open, and 214 and 216 are in their respective hold states, the samples taken in the previous sampling phase are converted, as shown by the decrementing count R0 and the incrementing count S0. When sl is opened, s2 is closed (T3), and the next two pixels are sampled. The same readout sequence for the pixel signal is followed, beginning with the rstl pulse (T5) to clear the sample node in the top branch. The shs2 switch is closed (T6) to connect capacitor 212 to the source follower Q220.

[0006] Both the upper and lower circuits, each driving its respective transistor 220 and 222, are configured as source followers to drive the output. Thus, the two circuits connected to swl and sw2 perform sampling and holding in such a way that one circuit samples while the other circuit holds and reads out the results. Each has its own source follower capable of driving the output.

[0007] The foregoing example shows two sample-and-hold branches, each with one sample-and-hold capacitor for the shr signal and one sample-and-hold capacitor for the shs signal. The two sample-and-hold branches operate in a pipelined mode: one branch samples the signal for one channel while the other branch outputs the signal for the other channel to the ADC for conversion. The disadvantage of this approach is that it requires a large area of chip space. Also, it is prone to mismatch between the shr and shs sample-and-hold capacitors 210 and 212 in one branch and 214 and 216 in the other branch. The samples are driven through different transistors 220 and 222, each of which is configured as a source follower amplifier. Additional electronics are needed to operate the more power. SUMMARY

[0008] In embodiments, a sample-and-hold circuit is used to sample and hold samples from an optical array in three phases. The hold phase is the phase in which the value of the charged sample-and-hold capacitor is transferred by driving the input of an amplifier with the capacitor voltage. The output of the amplifier drives the input of a ramp ADC. After the hold phase is complete, the input of the amplifier is switched to the output of the optical array to begin the track phase. The output of the amplifier is also electrically coupled to a sample-and-hold capacitor that begins charging the capacitor to the new optical array input. The track phase is followed by the sample phase in which the sample-and-hold capacitor is electrically connected to the output of the optical array and the amplifier output is connected to the input of the ADC. In embodiments, the amplifier is a field effect transistor based source follower with zero threshold voltage.

[0009] In a first aspect, embodiments of the disclosure provide a sample-and-hold circuit, comprising:

[0010] an input of the sample-and-hold circuit from an output of an optical array;

[0011] a first switch electrically coupled between the output of the optical array and a sample-and-hold capacitor;

[0012] a second switch for electrically coupling an input of an amplifier to one of:

[0013] (a) the sample-and-hold capacitor; or

[0014] (b) the input of the optical array;

[0015] a third switch for electrically coupling an output of the amplifier to the sample-and-hold capacitor; and

[0016] a fourth switch for electrically coupling the output of the amplifier to an output of the sample-and-hold circuit.

[0017] In some embodiments, the amplifier circuit comprises a field effect transistor (FET) having a zero threshold voltage.

[0018] In some embodiments, the amplifier further comprises a source follower.

[0019] In some embodiments, the output of the sample-and-hold circuit is electrically coupled to an analog-to-digital converter (ADC).

[0020] In some embodiments, the ADC comprises a comparator.

[0021] In some embodiments, the ADC further comprises a coupling capacitor having one end electrically coupled to a first input of the comparator and another end electrically coupled to the output of the sample-and-hold circuit.

[0022] In some embodiments, the ADC further comprises a fifth switch for resetting the capacitor.

[0023] In some embodiments, the ADC further comprises a ramp generator electrically coupled to a second input of the comparator.

[0024] In some embodiments, the ramp generator comprises a digital-to-analog converter (DAC).

[0025] In some embodiments, the ramp generator further comprises a counter electrically coupled to a digital input of the DAC.

[0026] In a first aspect, embodiments of the disclosure provide a sample-and-hold circuit, comprising:

[0027] an input of the sample-and-hold circuit from an output of an optical array;

[0028] a first switch having one end electrically coupled to the output of the optical array and another end electrically coupled to a common point; a second switch having one end electrically coupled to the common point and another end electrically coupled to a sample-and-hold capacitor; a third switch having one end electrically coupled to the common point and another end electrically coupled to ground;

[0029] a fourth switch configured to electrically couple an input of an amplifier to one of:

[0030] (a) the sample-and-hold capacitor

[0031] (b) the output of the optical array

[0032] a fifth switch, the fifth switch being an arrangement to electrically couple an output of the amplifier to the sample-and-hold capacitor;

[0033] a sixth switch, the sixth switch being an arrangement to electrically couple the amplifier to an output of the sample-and-hold circuit.

[0034] In a third aspect, embodiments of the disclosure provide a sample-and-hold method for converting an optical array sample to a digital representation, comprising:

[0035] In a hold phase, the first switch is configured such that the sample-and-hold capacitor is not electrically connected to an output of the optical array; the second switch is configured such that an input of the amplifier is electrically coupled to the sample-and-hold capacitor; the third switch is configured such that an output of the amplifier is not electrically coupled to the sample-and-hold capacitor; and the fourth switch is configured such that the output of the amplifier is connected to an output of the sample-and-hold circuit.

[0036] In a track phase, the first switch is configured such that the sample-and-hold capacitor is not electrically coupled to the output of the optical array; the second switch is configured such that the input of the amplifier is electrically coupled to the output of the optical array; the third switch is configured such that the output of the amplifier is electrically coupled to the sample-and-hold capacitor; and the fourth switch is configured such that the output of the amplifier is not electrically coupled to the output of the sample-and-hold circuit.

[0037] In a sample phase, the first switch is configured such that the sample-and-hold capacitor is electrically coupled to the output of the optical array; the second switch is configured such that the input of the amplifier is electrically coupled to the sample-and-hold capacitor; the third switch is configured such that the output of the amplifier is not electrically coupled to the sample-and-hold capacitor; and the fourth switch is configured such that the output of the amplifier is electrically coupled to the output of the sample-and-hold circuit.

[0038] In some embodiments, the hold phase further comprises converting the output of the sample-and-hold circuit to a digital representation.

[0039] In some embodiments, converting the output of the sample-and-hold circuit to the digital representation comprises comparing the output to an output of a digital-to-analog converter (DAC).

[0040] In some embodiments, the sample-and-hold method further comprises driving the DAC with a counter, the counter ramping the output of the DAC until the output of the DAC is equal to the output of the sample-and-hold circuit.

[0041] In some embodiments, when the output of the DAC equals the output of the sample-and-hold circuit, the value of the counter is stored in memory as a digital representation of the output of the sample-and-hold circuit. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a prior art block diagram of optical array sensing and readout electronics.

[0043] Figure 2 is a schematic diagram of the sample-and-hold circuit of Figure 1.

[0044] Figure 3 is a timing diagram for the circuit of Figure 2.

[0045] Figure 4A Timing diagram for conversion time in a sample-and-hold circuit without pipelining in an embodiment.

[0046] Figure 4B Timing diagram for conversion time in a sample-and-hold circuit using pipelining in an embodiment.

[0047] Figure 5A Embodiment of a sample-and-hold circuit.

[0048] Figure 5B Timing diagram for the circuit of Figure 5A

[0049] Model of the sample-and-hold circuit of Figure 6 Figure 5A Simulation output for the circuit model of

[0050] Figure 7 Figure 6 Simulation output for the circuit model of

[0051] Figure 8A Embodiment of a sample-and-hold circuit during the hold phase.

[0052] Figure 8B Embodiment of a sample-and-hold circuit of Figure 8A during the track phase.

[0053] Figure 8C Embodiment of a sample-and-hold circuit of Figure 8A during the sample phase.

[0054] Figure 9 Timing diagram for the circuit of Figure 8A , 8B and 8C.

[0055] Figure 10 Simulation output for the circuit of Figure 8A , 8B and 8C.

[0056] ​​Figure 11 The diagram shows the versions with and without a tracking phase. Figure 8A , 8B Simulation of circuits in 8C.

[0057] Figure 12 A sample-and-hold circuit with a "T" switch is shown. Detailed Implementation

[0058] Figure 4A This is a timing diagram of the transition time in a pipelined sample-and-hold circuit. It shows the timing for transitioning two consecutive pixels, which will be referred to as shr and shs. The timing of the pipelined sample-and-hold and transition is illustrated. The timing is expressed in duration T. RST The process begins with an RST pulse or reset. Then the shr signal is sampled, which requires a settling time T. shr_稳定 Then, by connecting the shr signal with a continuous T driven by a counter... shr_计数 The DAC is compared with the time period to perform the transformation. At the end of the counting time period, the transformation of shr is completed, and T is displayed. tx Assertions are made on the TX charge transfer pulse within a given time period. Following the TX pulse, the shs signal needs to be asserted on T. shs_稳定 The signal stabilizes within a certain time period. When the signal is completely stable, a transition occurs, where it is compared with the output of a counter-driven DAC and held for a period of T. shs_计数 The counting time period. At the end of the counting time period, the signal is converted, and the cycle starts again with a reset pulse for the new value of shr. The time required for two conversions is called the line time or T. 行 The time is:

[0059] T 行 =T rst +T shr_稳定 +T shr_计数 +T tx +T shs_稳定 +T shs_计数 .

[0060] Line time limits the speed at which pixel arrays and frame rates can be converted into digital images. Therefore, frame rate is limited by line time, and one way to increase frame rate is to reduce line time.

[0061] Figure 4B The timing diagram shows the transition times in the sample-and-hold circuit using a pipeline. It can be seen that counting is performed in parallel with the sampling and stabilization of the previous pixel. When a shr is sampled, the previous shs is transitioned or counted, in order to operate at a faster rate. The line time can be expressed as:

[0062] T 行 =TRST +T shr_稳定 +T TX +T shs_稳定 .

[0063] Figure 5A A schematic of the sample-and-hold circuit 510 is shown. It is electrically coupled to an input Vbit, which is electrically coupled to a switch swl. Vbit represents the output of the optical array. The other end of swl is electrically coupled to a capacitor 520. The capacitor is also electrically coupled to the gate of a FET Q 530, which is configured as a source follower. One side of the capacitor is connected to the switch swl and the gate, the other side of 520 is connected to ground. The source of the transistor 530 is the output Vbit_out. The source is also electrically coupled to a bias current source 540 with a drive current Isf, which is in turn electrically coupled to ground.

[0064] Figure 5B A timing diagram 560 is shown, which includes the signal tx for charge transfer, swl representing the state of the switch swl, dcomp_rst to reset the comparator as in figure 1. The state of the sample-and-hold circuit 510 is shown by the signal S / H, and also the counter from the ramp DAC (as shown in figure 1). The switch swl is closed at the beginning of the cycle (as shown by (Ta)), which connects the capacitor 520 to the switch of Vbit and allows it to charge to the value of Vbit. When it is stable, dcomp_rst is asserted (Tb), and dcomp_rst is de-asserted (Tc) at the same time as swl is opened. From Ta to Tc is the sampling time. When swl is opened, the charge transfer or charge output is completed. Vbit_out represents the voltage of the capacitor, i.e. the value of the pixel that is sampled. The time that swl is opened is the hold period. A second sampling is then performed, in which swl is closed again, and the capacitor reaches equilibrium at a new voltage. When it is opened, it is held again, in order to be transferred to Vbit_out. The first sampling is R, and the second sampling is S. Thus, the sampling of R is followed by the holding of R. The sampling of S is followed by the holding of S. In the diagram, they are labelled by sample Rl, hold Rl, sample S1, hold S1. Each sampling is followed by a respective holding. In each cycle, the counter counts down by each R sample, and then the counter counts up by each successive S. The count is the conversion of the samples to be held into a digital representation. The sampling in this example is performed consecutively. Figure 5A The sample-and-hold circuit is a pixel-by-pixel processing of the image.

[0065] Figure 6 A circuit of Figure 5A and its parasitic capacitances is shown. The optical array has an output capacitance, and is shown as C PAnd it is driven by a 605 current source with an amplitude of Ivin. The input of the ADC has an input impedance and is controlled by C. ADC The circuit features a sample-and-hold capacitor 610, a transistor 630, and a bias current source 640 driven by the amplitude of Isf. Figure 6 The circuit shown represents the circuit used for Figure 7 The model shown is a simulation.

[0066] Figure 7 It shows Figure 6 The simulation of the circuit, where C p The value is 1.5 pF, Ivin is 4 uA, Isf is 1.5 uA, C610 is 0.3 pF, C ADC The value is 0.4 pF. Initially, sw1 is off. At the end of TX 710, Vpix begins to decay. Vpix decays to a stable value until switch sw1 is closed (715) and charge is transferred from Cp to the sample-and-hold capacitor 610. This transfer causes a small transient or "bump" 720, and Vpix needs more time to stabilize again before its value is held on capacitor 610. This point marks the transition from hold to sample.

[0067] Figure 8A , 8B The 8C illustrates the sample-and-hold circuitry in three operating stages, namely... Figure 8A Maintaining Figure 8B Tracking and Figure 8C The circuit has an input from the optical array, which is selectable so that pixels can be connected to the circuit, and is represented by Vpix. The optical array input is biased by current source 850 with an amplitude of Ivin. The input Vpix is ​​switched as shown in s1 and can be electrically coupled or decoupled from the sample-and-hold capacitor 820. There is a transistor Q810, which is configured as a source follower. The drain is connected to the power supply, and the input or gate is labeled SFin, which is electrically coupled to switch 830. Switch 830 is configured to connect SFin to Vpix as shown in position s2, or switch 830 can be configured to connect SFin to Vpix_sh as shown in s4. A third switch s3 electrically couples the amplifier output to or decouples it from the sample-and-hold capacitor Vpix_sh. A fourth switch s5 electrically couples or couples the amplifier output to the output Vpix_sh of the sample-and-hold circuit. pixout .

[0068] Figure 8AThe hold phase is shown with switch s1 open, capacitor 820 is electrically coupled to input SFin via switch 830 connected to s4. SFin drives the gate of Q 810, whose drain is connected to a power supply. Transistor Q 810 is a FET configured as a source follower amplifier. The source of Q 810 is biased by a current source 840 with a magnitude of Isf. The source of Q 810 is electrically coupled to the output Vpix_out through closed switch s5. S3 is open so that capacitor 820 is isolated and holds its charge value. The source follower has a unity gain. Vpix_out will equal the input SFin, which is electrically coupled to capacitor C 820 and is the value of Vpix_sh. During the hold phase, Vpix_out will equal Vpix_sh.

[0069] During the sample phase, shown in FIG. 1, Vpix is electrically coupled to Vpix_sh through closed switch s1, and is electrically coupled to the input SFin of the amplifier input via switch 830 connected to s4. SFin is the input to the gate of Q 810, which is configured as a source follower. The drain of Q 810 is connected to a power supply, and the source is electrically coupled to a bias current source 840 with a magnitude of Isf. The source of 810 is also connected to the output Vpix_out via closed s5. Figure 8B During the track phase, shown in FIG. 2, switch s1 is open. Vpix is connected to SFin through switch 830 connected to s2, SFin is the gate where Q 810 is configured as a source follower. The gate of 810 is the amplifier input. The drain of transistor Q 810 is connected to a power supply, and the source is electrically coupled to a bias current source 840 with a magnitude of Isf. The source follower is an amplifier with a unity gain. The source is also electrically coupled to Vpix_sh through closed switch s3. The gate of Q 810, which is the amplifier input, is electrically coupled to Vpix so that capacitor C 820 charges to the value Vpix. S5 is open, thus the output Vpix_out is open. The voltage of the sample and hold capacitor 820 tracks the value of Vpix.

[0070] During the sample phase, shown in FIG. 1, Vpix is electrically coupled to Vpix_sh through closed switch s1, and is electrically coupled to the input SFin of the amplifier input via switch 830 connected to s4. SFin is the input to the gate of Q 810, which is configured as a source follower. The drain of Q 810 is connected to a power supply, and the source is electrically coupled to a bias current source 840 with a magnitude of Isf. The source of 810 is also connected to the output Vpix_out via closed s5. Figure 8C The output of the sample and hold circuit drives the input of the comparator of the ramp ADC. During the hold phase, the voltage of the sample and hold capacitor is provided to the input of the comparator through the amplifier. The other comparator input is driven by a DAC connected to a counter that increments or decrements until the two values are equal. When the two values are equal, the comparator trips and the counter stops. The value of the counter is stored in memory as the digital representation of the analog signal. When the conversion is complete, the signal dcomp_rst is asserted, as shown in FIG. 1, clearing any storage circuits within the comparator.

[0071] The output of the sample and hold circuit drives the input of the comparator of the ramp ADC. During the hold phase, the voltage of the sample and hold capacitor is provided to the input of the comparator through the amplifier. The other comparator input is driven by a DAC connected to a counter that increments or decrements until the two values are equal. When the two values are equal, the comparator trips and the counter stops. The value of the counter is stored in memory as the digital representation of the analog signal. When the conversion is complete, the signal dcomp_rst is asserted, as shown in FIG. 1, clearing any storage circuits within the comparator.

[0072] Figure 9 A timing diagram is shown for Figure 8A the three phases shown in C. We start the cycle with the closed switch sl(Tw). The closing of switch sl turns on the sampling of Rl. Dcomp_rst is asserted to clear the comparator circuit for the next readout. When dcomp_rst is de-asserted, sl is opened, and at Ty tx is asserted, the circuit enters the hold phase.

[0073] During the hold phase, the conversion sample Rl is transferred. Sl is opened, and the value is counted. The hold phase ends (Tz) with the tracking phase, i.e., sl, of the next value to be tracked and then sampled. This pattern repeats over and over until the optical array is read. For the entire optical array, each sample is tracked, sampled, and held like a game of ping pong.

[0074] Figure 10 A timing diagram is shown for Figure 8A , 8B and 8C. The simulation shows the state of switch sl, the state of switch s3, and the time that switch 830 is connected to s2 (labeled s2). It shows the time that switch 830 is connected to s4 (labeled s4), and it shows the state of s5. It also shows TX, SFin, Vpix, and Vpix_sh. The plot is divided into three phases, showing the hold phase as shown in Figure 8A , the track phase as shown in Figure 8B , and the sample phase as shown in Figure 8C . In the hold phase, switch 1 is open. Switch 830 is not connected to s2, and s3 is open. Switch s4 and switch s5 are closed. S5 is closed long enough to complete the digital conversion, then it is opened so that it is only open for a portion of the hold phase. When TX ends 1010 during the hold phase, Vpix begins to decay, and SFin remains at its value. Switch 830 is connected to s2, and s3 is closed to start the track phase. Then, SFin falls, and Vpix_sh now tracks Vpix. Vpix_sh decays to the new value of Vpix. Then sl is closed to start the sample phase. With the transition of 830 to s4 and s3 closing, Vpix is no longer transitory or greatly minimized. The "bump" is suppressed. The difference between Vpix transients can be seen in Figure 11 .

[0075] Figure 11 A timing diagram is shown for Figure 8A , 8BAnalog of the circuit in 8C. It shows when S1, S3, and 830 are connected to S2. It also shows Tx and two Vpix waveforms superimposed on each other. The signal Vpix with tracking decays smoothly and transitions from tracking to sampling without transients. This can be seen as a smooth transition. However, the Vpix signal without tracking has transients during the transition from tracking to sampling. In the tracking phase, the sample-and-hold capacitor 820 is charged to the value of Vpix. The reason it happens is that Vpix is electrically coupled to SFin, which is the input of the source follower. The gain of the source follower is 1 and is non-inverting, so the value at the source will be equal to the voltage at the gate. Because the gate is electrically coupled to Vpix and the FET has a zero threshold voltage, the source will be at the same voltage as Vpix. When s1 closes with the transition from tracking to sampling, there is no change in voltage because the voltage on capacitor C is already equal to Vpix.

[0076] Circuit selection for the design of a sample-and-hold circuit requires that the sample-and-hold capacitor be small enough to reduce Johnson-Nyquist noise (kTC noise) to a level below the quantization noise of the DAC used to ramp one side of the comparator. The sample-and-hold switch should be small enough to minimize charge injection effects.

[0077] Figure 12 A sample-and-hold circuit with a "T" switch is shown. A T switch for the sample-and-hold switch can be used as shown in Figure 12 Figure 12 A double sw1 is shown so that either side of (T) can be electrically coupled and the center post can be grounded. It has an input Vpix, a sample-and-hold capacitor 1210, a transistor Q 1220 biased with a current source 1230 at the magnitude of Isf, and the source is also connected to the output Vpix_out. The T switch can be used for the S1 switch to avoid coupling from Vpix to the signal to the S / H cap C.

[0078] The method discussed herein eliminates problems associated with any mismatch between different capacitors and amplifiers used to select R samples and S samples (SHR and SHS) because all rows are processed with the same circuit. The size of the circuit is also reduced due to the reduction in capacitor size. Because the settling time of V pix is faster, the conversion can be made.

[0079] ​The proposed embodiments reduce row time by pipelining the count period with other pixel operations (TX, reset, settling time, and horizontal blanking). These embodiments provide low power, minimal size, and no mismatch between SHR and SHS readout. These embodiments can be implemented for use with sensors that require a sample-and-hold readout scheme to accelerate frame rate.

[0080] The sample-and-hold readout system described herein can incorporate additional features without departing from the scope of the invention. It should therefore be noted that the contents of the specification contained in the above specification or shown in the accompanying drawings are to be understood as illustrative rather than limiting. The following claims are intended to cover all of the generic and specific features of the methods and systems described herein, as well as all statements of the scope of the invention method and system that, as a matter of language, might be said to be in between the two.

[0081] Changes can be made to the above methods and systems without departing from the scope of embodiments of the invention. It should therefore be noted that the contents of the specification contained in the above specification or shown in the accompanying drawings are to be understood as illustrative rather than limiting. Herein, the phrase "in an embodiment" is equivalent to the phrase "in some embodiments," unless otherwise stated, rather than referring to all embodiments. The following claims are intended to cover all of the generic and specific features of the methods and systems described herein, as well as all statements of the scope of the invention method and system that, as a matter of language, might be said to be in between the two.

Claims

1. A sample-and-hold circuit, comprising: From the output of the optical array to the input of the sample-and-hold circuit; A first switch is electrically coupled between the output terminal of the optical array and the sample-and-hold capacitor. A second switch is used to electrically couple the gate of a field-effect transistor (FET) to one of the following: (a) The sample-and-hold capacitor; and (b) The input terminal of the sample-and-hold circuit; A third switch is used to directly electrically couple the source of the FET to the sample-and-hold capacitor; and A fourth switch is used to electrically couple the source of the FET to the output of the sample-and-hold circuit.

2. The sample-and-hold circuit of claim 1, wherein the FET has a zero threshold voltage.

3. The sample-and-hold circuit according to claim 1, wherein the output terminal of the sample-and-hold circuit is electrically coupled to the analog-to-digital converter (ADC).

4. The sample-and-hold circuit of claim 3, wherein the ADC includes a comparator.

5. The sample-and-hold circuit according to claim 4, wherein the ADC further comprises a coupling capacitor, one end of the coupling capacitor being electrically coupled to a first input terminal of the comparator, and the other end of the coupling capacitor being electrically coupled to the output terminal of the sample-and-hold circuit.

6. The sample-and-hold circuit of claim 4, wherein the ADC further comprises a fifth switch for resetting the comparator.

7. The sample-and-hold circuit of claim 4, wherein the ADC further comprises a ramp generator electrically coupled to a second input terminal of the comparator.

8. The sample-and-hold circuit of claim 7, wherein the ramp generator comprises a digital-to-analog converter (DAC).

9. The sample-and-hold circuit of claim 8, wherein the ramp generator further comprises a counter electrically coupled to the digital input of the DAC.

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