Imaging Device and System with Phase Detection Auto-Focus Image Sensor

Abstract

This application relates to improved bit-line stabilization and power supply rejection ratio in a nine-cell pixel image sensor with phase detection autofocus. An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bit-lines are coupled to the pixel circuits. Clamping circuits are coupled to the bit-lines. Each of the clamping circuits includes a clamping short transistor to a power supply line and a corresponding one of the bit-lines. The clamping short transistor is configured to be switched in response to a clamping short enable signal. A first diode voltage drop device is coupled to the power supply line. A clamping idle transistor is coupled to the first diode voltage drop device such that the first diode voltage drop device and the clamping idle transistor are coupled between the power supply line and the corresponding one of the bit-lines. The clamping idle transistor is configured to be switched in response to a clamping idle enable signal.

Description

Technical Field

[0001] The present disclosure generally relates to image sensors, and more particularly but not exclusively, to improved bit line stabilization and power supply rejection ratio in image sensors that include merged pixels with phase detection autofocus. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, surveillance cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition processing. The technology for manufacturing image sensors continues to evolve at a rapid pace. For example, the demand for higher resolution and lower power consumption has encouraged further miniaturization and integration of these devices.

[0003] A typical complementary metal oxide semiconductor (CMOS) image sensor operates in response to incident image light from an external scene onto the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge when absorbing the incident image light. The image charge generated by the pixels can be measured as an analog output image signal on column bit lines that varies in accordance with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as an analog signal from the column bit lines and converted to a digital value to produce a digital image (i.e., image data) representing the external scene. Summary of the Invention

[0004] Aspects of the present disclosure provide an imaging device that includes: a pixel array including a plurality of pixel circuits arranged in rows and columns; a plurality of bit lines coupled to the plurality of pixel circuits; and a plurality of clamping circuits coupled to the plurality of bit lines, wherein each of the plurality of clamping circuits includes: a clamping short circuit transistor coupled to a power supply line and a respective one of the plurality of bit lines of the pixel array, wherein the clamping short circuit transistor is configured to be switched in response to a clamping short circuit enable signal; a first diode voltage drop device coupled to the power supply line; and a clamping idle transistor coupled to the first diode voltage drop device such that the first diode voltage drop device and the clamping idle transistor are coupled between the power supply line and the respective one of the plurality of bit lines, wherein the clamping idle transistor is configured to be switched in response to a clamping idle enable signal.

[0005] Another aspect of the present disclosure provides an imaging system, comprising: a pixel array including a plurality of pixel circuits arranged in rows and columns; a plurality of bit lines coupled to the plurality of pixel circuits; a plurality of clamping circuits coupled to the plurality of bit lines, wherein each of the plurality of clamping circuits includes: a clamping short circuit transistor coupled to a power supply line and a corresponding one of the plurality of bit lines of the pixel array, wherein the clamping short circuit transistor is configured to be switched in response to a clamping short circuit enable signal; a first diode voltage drop device coupled to the power supply line; and a clamping idle transistor coupled to the diode voltage drop device such that the first diode voltage drop device and the clamping idle device are coupled between the power supply line and the corresponding one of the plurality of bit lines, wherein the clamping idle transistor is configured to be switched in response to a clamping idle enable signal; a plurality of sample and hold switches coupled to the plurality of bit lines, wherein the corresponding one of the plurality of bit lines is further coupled to a corresponding one of the plurality of sample and hold switches; and a readout circuit coupled to the pixel array to read signals from the pixel array through the plurality of bit lines, the readout circuit including a plurality of current sources coupled to the plurality of bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, in which like reference numerals refer to like parts throughout the various views, unless otherwise specified.

[0007] Figure 1 Illustrate an example of an imaging system including a pixel array in accordance with the teachings of the present invention.

[0008] Figure 2A Illustrate an example of a schematic diagram of a 1x3 pixel circuit of a first bit line of a group of three bit lines per column of a pixel array in accordance with the teachings of the present disclosure.

[0009] Figure 2B Illustrate an example of a schematic diagram of a 1x3 pixel circuit of a second bit line of a group of three bit lines per column of a pixel array in accordance with the teachings of the present disclosure.

[0010] Figure 2C Illustrate an example of a schematic diagram of a 1x3 pixel circuit of a third bit line of a group of three bit lines per column of a pixel array in accordance with the teachings of the present disclosure.

[0011] Figure 2D Illustrate an example of a 9-cell 3x3 pixel structure including three 1x3 pixel circuits of a pixel array in accordance with the teachings of the present disclosure.

[0012] Figure 2E Illustrate an example of a group of 9-cell 3x3 pixel structures of a pixel array in accordance with the teachings of the present disclosure.

[0013] Figure 2F Describes an example of a group of 9 - cell 3x3 pixel structures including phase - detection autofocus photodiodes, where the phase - detection autofocus photodiodes are included in the central 2x2 grouping of the photodiodes included in each 6x6 pixel structure in the pixel array.

[0014] Figure 3 Describes a detailed schematic diagram of an example of a 6x6 pixel structure including 4 nine - cell 3x3 pixel structures, where the nine - cell 3x3 pixel structures include a 2x2 arrangement of phase - detection autofocus photodiodes, and the 2x2 arrangement of phase - detection autofocus photodiodes is included in the central 2x2 grouping of the photodiodes included in each 6x6 pixel structure in the pixel array.

[0015] Figure 4 Describes an example of a 6x6 pixel structure including nine - cell 3x3 pixel structures and a 2x2 grouping of phase - detection autofocus photodiodes arranged in a repeating sequence of a first group, a second group, and then a third group of pixel circuits in the pixel array along the rows of the pixel array.

[0016] Figure 5 Describes a diagram of an example of a clamping circuit coupled to a bit - line, where the bit - line is coupled to a corresponding group of pixel circuits and a read - out circuit of the pixel array.

[0017] Figure 6 Describes a schematic diagram of an example of a clamping circuit coupled to a bit - line, where the bit - line is coupled to a capacitor and a current source of the read - out circuit of the pixel array.

[0018] Figure 7 Describes a schematic diagram of an example of a sample - and - hold switch coupled to a bit - line, where the bit - line is coupled to a capacitor in the pixel array.

[0019] Figure 8A Describes an example of a coupling path for capacitively coupling a bit - line in the absence of a sample - and - hold switch in the pixel array.

[0020] Figure 8B Describes an example of isolation provided by a deactivated sample - and - hold switch coupled to a bit - line of a pixel array according to the teachings of the present invention.

[0021] Figure 9A Describes an example of a timing diagram of signals in an example clamping circuit coupled to a bit - line during a time period related to the read - out of pixel circuits in an example pixel array according to the teachings of the present invention.

[0022] Figure 9B Another example of a timing diagram of signals in an example clamping circuit coupled to bit lines during a time period related to the readout of pixel circuits in an example pixel array in accordance with the teachings of the present invention.

[0023] Figure 9C Yet another example of a timing diagram of signals in an example clamping circuit coupled to bit lines during a time period related to the readout of pixel circuits in an example pixel array in accordance with the teachings of the present invention.

[0024] Figure 10A An example of a timing diagram of signals in an example clamping circuit coupled to bit lines during a time period related to the readout of a group of pixel circuits in an example pixel array in accordance with the teachings of the present invention.

[0025] Figure 10B Another example of a timing diagram of signals in an example clamping circuit coupled to bit lines during a time period related to the readout of a group of pixel circuits in an example pixel array in accordance with the teachings of the present invention.

[0026] Figure 11 An example logic diagram for generating signals for an example clamping circuit in accordance with the teachings of the present invention.

[0027] Throughout the several views of the drawings, corresponding reference numerals indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present invention. Additionally, commonly understood elements that are useful or necessary in a commercially viable embodiment are often not depicted in order to provide a more intuitive view of these different embodiments of the present invention. Detailed Description

[0028] Examples are described herein of imaging systems related to 9-cell pixel image sensors including phase detection autofocus pixels with improved bit line stability and power supply rejection ratio. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, those skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0029] References to "an example" or "an embodiment" throughout this specification mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, appearances of the phrases "in an example" or "in an embodiment" throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0030] For ease of description, spatially relative terms, such as "below", "beneath", "above", "below", "upon", "on", "top", "bottom", "left", "right", "center", "middle", and the like, may be used herein to describe the relationship of one element or feature to another (other) element or feature, as illustrated in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is rotated or flipped, then an element described as "below" or "beneath" or "under" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both orientations of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Additionally, it will also be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements, or there can also be one or more intervening elements.

[0031] Throughout this specification, several technical terms are used. These terms are to present their ordinary meaning in the technology from which they are derived, unless explicitly defined herein or the context in which they are used otherwise clearly suggests. It should be noted that throughout this document, element names and symbols may be used interchangeably (e.g., Si for silicon); but both have the same meaning.

[0032] As will be discussed, various examples of imaging systems include pixel arrays in which a plurality of 1x3 pixel circuits are arranged in rows and columns of the pixel array. Each 1x3 pixel circuit includes 3 photodiodes arranged along a corresponding column. A plurality of bit lines are coupled to the plurality of 1x3 pixel circuits. The plurality of bit lines are divided into groups of 3 bit lines for each column of the 1x3 pixel circuits. Each column of the 1x3 pixel circuits in the pixel array includes a plurality of first groups of 1x3 pixel circuits coupled to a first bit line of the corresponding group of 3 bit lines, a plurality of second groups of 1x3 pixel circuits coupled to a second bit line of the corresponding group of 3 bit lines, and a plurality of third groups of 1x3 pixel circuits coupled to a third bit line of the corresponding group of 3 bit lines. The pixel array is further organized into a plurality of 9-cell (9C) pixel structures such that each of the 9C pixel structures includes 3 1x3 pixel structures, which form a 3x3 pixel structure.

[0033] In various examples, a color filter array is disposed above a pixel array. In one example, the color filter array includes red, green, and blue color filters arranged in a mosaic pattern (e.g., a Bayer color filter array) such that each 9C pixel structure is located below one of the color filters of the color filter array. In various examples, each 9C pixel structure is disposed below one of the color filters of the color filter array. In various examples, new 9C pixel structures are arranged in 2x2 groupings of 4 9C pixels, which form 6x6 pixel structures. Thus, the four 9C pixel structures included in each 6x6 pixel structure are disposed below the red, green, green, and blue color filters of the Bayer color filter array disposed above the pixel array. In various examples, the central 2x2 grouping of photodiodes included in each 6x6 pixel structure can be configured to provide phase detection autofocus information from the pixel array.

[0034] Thus, in various examples, the pixel array can be configured to simultaneously read out 9C merged pixels that do not have phase detection information through all 3 bitlines in each column. In another example, the pixel array can be configured to simultaneously read 9C merged pixels that have phase detection information through all 3 bitlines in each column. In yet another example, the pixel array can be configured to read out as a full resolution or full size readout. In this example, one of the 3 bitlines in each column is active, while the remaining 2 bitlines in each column of 3 bitlines are idle or unused during the full size readout.

[0035] In various examples, a clamping circuit having a sample and hold circuit is coupled to the bitlines to clamp the idle bitlines, which addresses issues that may be introduced by idle bitlines that are not clamped during full size or full resolution readouts. Specifically, the idle bitlines will capacitively couple to the active bitlines through parasitic capacitance in the 3-bitline pixel circuit because there is not enough space between the bitlines for shielding. The coupling capacitance contributes to the load of the active read bitline, which will reduce the settling time. The idle bitlines will also degrade the power supply rejection ratio performance of the image sensor because the idle bitlines will be connected to a power supply line (e.g., AVDD). The resulting fluctuations in the power supply line will appear in the idle bitlines that do not have much isolation, and the idle bitlines will thus couple back to the active bitlines through the coupling capacitance and degrade the power supply rejection ratio.

[0036] For illustration, Figure 1 FIG. 100 shows an example of an imaging system including a 1x3 pixel circuit and coupled to a readout circuit through bitlines. In one example, in accordance with the teachings of the present invention, a clamping circuit and a sample and hold circuit are coupled to the bitlines. Specifically, Figure 1The example depicted in FIG. illustrates an imaging system 100 that includes a pixel array 102, bit lines 112, control circuitry 110, a readout circuit 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array that includes a plurality of pixel circuits 104 (e.g., P1, P2, …, Pn), which are arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of a person, place, object, etc., and the image data can then be used to present an image of the person, place, object, etc.

[0037] In various examples, each pixel circuit 104 can include one or more photodiodes configured to photogenerate image charge in response to incident light. For example, in one example, the pixel circuit 104 can include 3 photodiodes such that each pixel circuit 104 is a 1x3 pixel circuit. As will be discussed, in various examples, for each column of the pixel circuit 104, there are 3 bit lines per column. The image charge generated in each photodiode is transferred to a floating diffusion included in each pixel circuit 104, and the image charge can be converted into an image signal or, in some cases, into phase detection autofocus information, and then read out from each pixel circuit 104 by the readout circuit 106 via the column bit lines 112. As will be discussed, in various examples, the readout circuit 106 can be configured to read out 9C combined image data, phase detection autofocus data, and / or full resolution image data via the column bit lines 112. In various examples, the readout circuit 106 can include a current source, routing circuitry, and a comparator, which can be included in an analog-to-digital converter or otherwise. In various examples, there is also a clamping circuit and a sample-and-hold circuit coupled to the bit lines to clamp idle bit lines to improve bit line settling time and power supply rejection ratio.

[0038] In the example, the digital image data values generated by the analog-to-digital converter in the readout circuit 106 can then be received by the functional logic 108. The functional logic 108 can simply store the digital image data or even manipulate the digital image data by applying image post-effects (e.g., cropping, rotating, removing red-eye, adjusting brightness, adjusting contrast, or others).

[0039] In one example, the control circuit 104 is coupled to the pixel array 102 to control the operation of the plurality of photodiodes in the pixel array 102. For example, the control circuit 104 can generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with an illumination effect (e.g., flash).

[0040] In one example, the imaging system 100 can be included in a digital camera, a mobile phone, a laptop computer, etc. Additionally, the imaging system 100 can be coupled to other hardware, such as a processor (general or otherwise), memory elements, outputs (USB ports, wireless transmitters, HDMI ports, etc.), lighting / flash, electrical inputs (keyboard, touch display, trackpad, mouse, microphone, etc.), and / or a display. The other hardware can deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate the image data provided by the imaging system 100.

[0041] Figure 2A An example schematic diagram of a pixel circuit 204A included in an imaging system having a photodiode array in accordance with the teachings of the present invention is illustrated. It should be understood that Figure 2A the pixel circuit 204A can be an example of one of the pixel circuits 104 included in the pixel array 102 as shown in Figure 1 and the similarly named and numbered elements described above are similarly coupled and operative hereinafter.

[0042] In Figure 2A the illustrated example, the pixel circuit 204A includes a photodiode 214-0 coupled to a transfer transistor 216-0, a photodiode 214-1 coupled to a transfer transistor 216-1, and a photodiode 214-2 coupled to a transfer transistor 216-2. Thus, each of the plurality of transfer transistors 216-0 to 216-2 is coupled to a corresponding one of the plurality of photodiodes 214-0 to 214-2. In the illustrated example, it should be understood that the three photodiodes 214-0, 214-1, and 214-2 form a 1x3 pixel circuit 204A. In other words, in various examples, the three photodiodes 214-0, 214-1, and 214-2 can be considered as a column in three rows of photodiodes, or a 1x3 pixel circuit 204A. As will be discussed below, in various examples, the readout of the three photodiodes 214-0, 214-1, and 214-2 can be combined together, or can be read out individually for full resolution readout. In another embodiment, one of the three photodiodes 214-0, 214-1, and 214-2 can be read out to provide phase detection autofocus information.

[0043] Continuing with the illustrated example, a shared floating diffusion 218 is coupled to the transfer transistor 216-0, the transfer transistor 216-1, and the transfer transistor 216-2. Thus, each of the plurality of transfer transistors 216-0 to 216-2 is coupled between a corresponding one of the plurality of photodiodes 214-0 to 214-2 and the shared floating diffusion 218. Thus, the floating diffusion 218 is a shared floating diffusion configured to receive charge transferred from the plurality of photodiodes 214-0 to 214-2.

[0044] In operation, transfer transistor 216-0 is coupled to be controlled in response to transfer control signal TX0, transfer transistor 216-1 is coupled to be controlled in response to transfer control signal TX1, and transfer transistor 216-2 is coupled to be controlled in response to transfer control signal TX2. Thus, the charge photogenerated in photodiode 214-0 in response to incident light is transferred to shared floating diffusion 218 in response to transfer control signal TX0, the charge photogenerated in photodiode 214-1 in response to incident light is transferred to shared floating diffusion 218 in response to transfer control signal TX1, and the charge photogenerated in photodiode 214-2 in response to incident light is transferred to shared floating diffusion 218 in response to transfer control signal TX2.

[0045] In the example, dual floating diffusion transistor 224 is also coupled to shared floating diffusion 218, and dual floating diffusion capacitor C DFD 228 is coupled to dual floating diffusion transistor 224, as shown. In the example, dual floating diffusion transistor 224 can be turned on and off in response to dual floating diffusion signal DFD to switch between low conversion gain or high conversion gain readout to increase the dynamic range of the image sensor. In the example, reset transistor 226 is coupled between a voltage source (e.g., AVDD) and dual floating diffusion transistor 224. In operation, reset transistor 320 is configured to reset pixel circuit 204A that includes the charge in dual floating diffusion capacitor C DFD 228 and shared floating diffusion 218.

[0046] In the illustrated example, the gate of source follower transistor 220 is coupled to shared floating diffusion 218. In the example, the drain of source follower transistor 220 is coupled to a voltage source (e.g., AVDD), and the source of source follower transistor 220 is coupled to first column bit line BL0 212-0 through row select transistor 222. Thus, in other words, source follower transistor 220 and row select transistor 222 are coupled between a voltage source (e.g., AVDD) and first column bit line 212-0. In operation, row select transistor 222 is configured to output a signal representative of the charge in shared floating diffusion 218 from source follower transistor 220 of pixel circuit 204A to first column bit line 212-0 in response to row select signal RS.

[0047] As shown in the depicted example, there are three column bit lines per column of BL0 212-0, BL1 212-1, and BL2 212-2 for each column of pixel unit 204A. As mentioned, pixel unit 204A is coupled to the first bit line BL0 212-0. Thus, since pixel unit 204A is coupled to the first of the three bit lines BL0 212-0, BL1 212-1, and BL2 212-2 per column of the pixel unit, pixel unit 204A is considered to be included in the first grouping or first group of pixel units (which is referred to as Group 0 in this disclosure). As will be shown below in Figures 2B to 2C pixel unit 204B, which is coupled to the second bit line BL1 212-1 of the three bit lines BL0 212-0, BL1 212-1, and BL2 212-2 per column of the pixel unit, is considered to be included in Group 1. Similarly, pixel unit 204C, which is coupled to the third bit line BL2 212-2 of the three bit lines BL0 212-0, BL1 212-1, and BL2 212-2 per column of the pixel unit, is considered to be included in Group 2.

[0048] For illustration, Figure 2B FIG. illustrates an example schematic diagram of pixel circuit 204B included in an imaging system having a photodiode array in accordance with the teachings of the present invention. It should be understood that Figure 2B pixel circuit 204B may be another example of one of the pixel circuits 104 included in pixel array 102 as shown in Figure 1 and similarly named and numbered elements described above are coupled and operate similarly hereinafter.

[0049] It should be further understood that Figure 2B pixel circuit 204B shares many similarities with Figure 2A pixel circuit 204. For example, there are three column bit lines BL0 212-0, BL1 212-1, and BL2 212-2 per column of pixel unit 204B. However, Figure 2B the difference between pixel circuit 204B and Figure 2A pixel circuit 204A is that in Figure 2B pixel circuit 204B, the source of source follower transistor 220 is coupled to the second column bit line BL1 212-1 through row selection transistor 222, rather than the first column bit line BL0 212-0 of the three bit lines BL0 212-0, BL1 212-2, and BL2 212-2 per column of the pixel unit in Figure 2A pixel circuit 204A. In one example, Figure 2A pixel circuit 204A and Figure 2BThe pixel circuits 204B can be located in the same column of the same pixel array. Each column of the pixel units 204B has the same three column bit lines BL0 212-0, BL1 212-1, and BL2 212-2. However, since the pixel unit 204B is coupled to the second bit line BL0 212-1, the pixel unit 204B is considered to be included in the second group or the second set of pixel units (which is referred to as Group 1 in the present disclosure).

[0050] Figure 2C An exemplary schematic diagram of a pixel circuit 204C included in an imaging system having a photodiode array in accordance with the teachings of the present invention is shown. It should be understood that Figure 2C the pixel circuit 204C can be another example of one of the pixel circuits 104 included in the pixel array 102 as shown in Figure 1 and the similarly named and numbered elements described above are similarly coupled and operative hereinafter.

[0051] It should be further understood that Figure 2C the pixel circuit 204C and Figure 2B the pixel circuit 204B and Figure 2A the pixel circuit 204A share many similarities. For example, there are three column bit lines BL0 212-0, BL1 212-1, and BL2 212-2 in each column of the pixel unit 204C. However, Figure 2C the pixel circuit 204C and Figure 2B the pixel circuit 204B and Figure 2A the pixel circuit 204A differ in that, in Figure 2C the pixel circuit 204C, the source of the source follower transistor 220 is coupled to the third column bit line BL2 212-2 through the row selection transistor 222, rather than to the second column bit line BL1 212-1 among the three bit lines BL0 212-0, BL1 212-1, and BL2 212-2 in each column of the pixel unit in the pixel circuit 204B as in Figure 2B or to the first column bit line BL0 212-0 among the three bit lines BL0 212-0, BL1 212-1, and BL2 212-2 in each column of the pixel unit in the pixel circuit 204A as in Figure 2A In one example, Figure 2A the pixel circuit 204A, Figure 2B the pixel circuit 204B, and Figure 2CThe pixel circuits 204C can be located in the same column of the same pixel array, and each column of the pixel units 204C has the same three column bit lines BL0 212-0, BL1 212-1, and BL2 212-2. However, since the pixel unit 204C is coupled to the second bit line BL0 212-0, the pixel unit 204C is considered to be included in the third group or the third set of pixel units (which is referred to as set 2 in this disclosure).

[0052] Figure 2D Illustrate an example of a 9-cell 3x3 pixel structure 230 including three 1x3 pixel circuits of a pixel array according to the teachings of this disclosure. Specifically, Figure 2D The example depicted in shows a 9-cell (9C) pixel structure 230, which can be considered a 3x3 pixel structure that includes three 1x3 pixel circuits 204 arranged side by side as shown to form a photodiode, in three columns and three rows. It should be understood that Figure 2D The three 1x3 pixel circuits 204 of can be Figure 2A The pixel circuit 204A of Figure 2B The pixel circuit 204B of or Figure 2C An example of the pixel circuit 204C of, and the similarly named and numbered elements described above are similarly coupled and operate below. Thus, it should be further understood that each of the three 1x3 pixel circuits 204 includes three bit lines per column of the 1x3 pixel circuit 204 (e.g., BL0 212-0, BL1 212-1, BL2 212-2).

[0053] Figure 2E Illustrate an example of a set N 236A of a 9-cell (9C) 3x3 pixel structure of a pixel array according to the teachings of this disclosure. In various examples, the set N 236A includes 9C pixel structures 230 arranged in rows and columns of a pixel array. It should be understood that Figure 2E The 9C pixel structure 230 depicted in can be Figure 2D An example of the 9C pixel structure 230 depicted in, and the similarly named and numbered elements described above are similarly coupled and operate below. In various examples, N = 0, 1, or 2 (e.g., set 0, set 1, set 2), such that all of the 1x3 pixel circuits included in each 9C pixel structure of the set N 236A are coupled to the first bit line BL0 212-0, the second bit line BL1 212-1, or the third bit line BL2 212-2, as discussed in detail above.

[0054] Figure 2EThe example depicted also illustrates a color filter array disposed above the pixel array. In the example, the color filter array comprises a color filter array arranged in a mosaic pattern of three colors, such as red, green, and blue color filters. In one example, the color filter array can be a Bayer color filter array such that the color filters are arranged in a repeating pattern of 2x2 squares of color filters, where the blue and green color filters are repeated in one row and the green and red color filters are repeated in adjacent rows.

[0055] As Figure 2E shown in the example illustrated in, each of the 9C pixel structures is disposed below one of the color filters in the color filter array. In the depicted example, the blue color filter is indicated by the B label, the green color filter in the same row as the blue color filter is indicated by the G B label, the red color filter is indicated by the R label, and the green color filter in the same row as the red color filter is indicated by the G R label. Thus, it should be understood that the color filters along one diagonal of the 2x2 square pattern of color filters are blue (B) and red (R), while both of the color filters along the other diagonal of the 2x2 square pattern of color filters are green (G B and G R ).

[0056] It should be understood that each 2x2 square of color filters is disposed above the corresponding 2x2 square of the 9C pixel structure 230. Thus, since each 9C pixel structure 230 comprises 3 1x3 pixel circuits 204 arranged side by side as discussed in Figure 2D , each 2x2 square of the color 9C pixel structure 230 forms a 6x6 pixel structure 232, which is formed by 4 9C pixels 230 or 12 1x3 pixel circuits 204.

[0057] Figure 2F An example of group N 236B of 9-unit 3x3 pixel structures including phase detection autofocus photodiodes in accordance with the teachings of the present disclosure is illustrated, where the phase detection autofocus photodiodes are included in a central 2x2 grouping of the photodiodes included in each 6x6 pixel structure in the pixel array. Specifically, Figure 2F group N 236B of the pixel array is illustrated, which comprises 9C pixel structures 230 arranged in rows and columns of the pixel array. It should be understood that Figure 2F group N 236B of Figure 2E shares many similarities with group N 236A of the 9C pixel structure 230 discussed above in Figure 2E . For example, similar to Figure 2FGroup N 236B also includes a 6x6 pixel structure 232 formed by four 9C pixel structures 230 or twelve 1x3 pixel circuits 204. Additionally, each of the 9C pixel structures 230 is disposed beneath one of the color filters (e.g., B, G B , G R , R) of a color filter array disposed above the pixel array.

[0058] Figure 2F The difference between group N 236B and Figure 2E group N 236A is that some of the photodiodes in group N 236B included in Figure 2F can be configured to provide phase detection information for the pixel array. For example, as shown in the example depicted in Figure 2F , the central 2x2 grouping of the photodiodes 234 of each 6x6 pixel structure 232 can be configured to provide phase detection autofocus information. It should be understood that in the depicted example, each of the central 2x2 groupings of the photodiodes 234 of each 6x6 pixel structure 232 is disposed in the respective inner corners of each of the four 9C pixel structures 230 included. Thus, in the example described herein, the four photodiodes included in each central 2x2 grouping of the photodiodes 234 are disposed beneath the respective B, G B , G R , R color filters. In other examples, it should be understood that the four photodiodes included in each central 2x2 grouping of the photodiodes 234 can all be disposed beneath a green color filter or a full-color filter, etc.

[0059] Figure 3 A detailed schematic diagram illustrating an example of a 6x6 pixel structure 332 including four 9-cell 3x3 pixel structures according to the teachings of the present disclosure, the 9-cell 3x3 pixel structure including a 2x2 arrangement of phase detection autofocus photodiodes, the 2x2 arrangement of phase detection autofocus photodiodes being included in the central 2x2 grouping of the photodiodes included in each 6x6 pixel structure 332 in the pixel array. It should be understood that Figure 3 the 6x6 pixel structure 332 can be a detailed example of one of the 6x6 pixel structures 232 illustrated in Figures 2E to 2F , and the similarly named and numbered elements described above are similarly coupled and operative hereinafter.

[0060] In Figure 3In the example depicted, the 6x6 pixel structure 332 is illustrated as including a 3x3 blue 9C pixel structure 330B, a 3x3 green 9C pixel structure 330GB in the same row as the 3x3 blue 9C pixel structure 330B, a 3x3 red 9C pixel structure 330, and a 3x3 green 9C pixel structure 330GR in the same row as the 3x3 red 9C pixel structure 330. In the example depicted, the 2x2 phase detection 334 portion is located in the central 2x2 grouping of the photodiodes to provide phase detection information for the pixel array. In the example depicted, the 4 photodiodes included in the central 2x2 grouping of the photodiodes are illustrated as being disposed below the respective B, G B , G R , R color filters. In other examples, it should be understood that the 4 photodiodes included in each central 2x2 grouping of the photodiodes 234 may all be disposed below a green color filter or a full-color filter, etc.

[0061] The example depicted also illustrates that each column of the photodiodes included in each respective 1x3 pixel circuit (e.g., 1x3 pixel circuit 204) is coupled to one of the 3 bit lines 312 per column of the 1x3 pixel circuit. In Figure 3 the example depicted, it should be understood that all 1x3 pixel circuits are coupled to a first bit line (e.g., BL0 212-0). Thus, it should be understood that Figure 3 the 6x6 pixel structure 332 in the example depicted is included in group 0. In contrast, if all 1x3 pixel circuits are coupled to a second bit line (e.g., BL1 212-1), then the example pixel 6x6 pixel structure would be included in group 1. Similarly, if all 1x3 pixel circuits are coupled to a third bit line (e.g., BL2 212-2), then the example pixel 6x6 pixel structure would be included in group 2.

[0062] Figure 3The example depicted also illustrates that the first transfer control signal TX0 316-0B is coupled to control a first transfer control transistor in a row of 1x3 pixel circuits including the 3x3 blue 9C pixel structure 330B, the second transfer control signal TX1 316-1B is coupled to control a second transfer control transistor in a row of 1x3 pixel circuits including the 3x3 blue 9C pixel structure 330B, and the third transfer control signal TX2 316-2B is coupled to control a third transfer control transistor in a row of 1x3 pixel circuits including the 3x3 blue 9C pixel structure 330B. Similarly, the first transfer control signal TX0 316-0R is coupled to control a first transfer control transistor in a row of 1x3 pixel circuits including the 3x3 red 9C pixel structure 330R, the second transfer control signal TX1 316-1R is coupled to control a second transfer control transistor in a row of 1x3 pixel circuits including the 3x3 red 9C pixel structure 330R, and the third transfer control signal TX2 316-2R is coupled to control a third transfer control transistor in a row of 1x3 pixel circuits including the 3x3 red 9C pixel structure 330R. Figure 3 The example depicted further illustrates that the phase detection transfer control signal TXPD 316-P is coupled to control a transfer control transistor coupled to a central 2x2 grouping of photodiodes included in the 6x6 pixel structure 332.

[0063] Figure 4 An example of a group 436A, 436B, 436C of 6x6 pixel structures 432 including 9-cell 3x3 pixel structures 430 and central 2x2 groupings of phase detection autofocus photodiodes 434 arranged in a repeating sequence of a first group, a second group, and then a third group of pixel circuits in the pixel array along a row of the pixel array in accordance with the teachings of the present disclosure is illustrated. In other words, Figure 4 the example depicted shows that group 0 436A, group 1 436B, and group 2 436C are arranged in a repeating sequence along a row of the pixel array. It should be understood that Figure 4 each of the groups 436A, 436B, 436C depicted Figures 2E to 2F may be an example of the groups 236A, 236B shown above, and similarly named and numbered elements described above are coupled and operate similarly below. As discussed above, each of the 1x3 pixel circuits included in group 0 436A is coupled to a first bit line BL0 (e.g., BL0 212-0), each of the 1x3 pixel circuits included in group 1 436B is coupled to a second bit line BL1 (e.g., BL1 212-1), and each of the 1x3 pixel circuits included in group 2 436C is coupled to a third bit line BL2 (e.g., BL2 212-2).

[0064] Figure 5 FIG. illustrating an example of a clamping circuit 544 coupled to bit line 512 in accordance with the teachings of the present disclosure, the bit line 512 being coupled to corresponding groups 536A, 536B, 536C of pixel circuits and a readout circuit of a pixel array. It should be understood that Figure 5 groups 536A, 536B, 536C of pixel circuits and the bit lines may be examples of the groups of pixel circuits and the bit lines discussed above in Figures 1 to 4 and elements similarly named and numbered as described above are similarly coupled and operative hereinafter.

[0065] As shown in the depicted example, clamping circuit 544 is coupled to bit line 512. In the example, bit line 512 includes a grouping of 3 bit lines (e.g., BL0, BL1, BL2). In various examples, group 0 536A pixel circuits are coupled to first bit line BL0 of bit line 512, group 2 536B pixel circuits are coupled to second bit line BL1 of bit line 512, and group 3 536C pixel circuits are coupled to third bit line BL2 of bit line 512. As shown in the example, readout circuit 506 is coupled to bit line 512 to read out groups 536A, 536B, 536C of pixel circuits. In various examples, readout circuit 506 may be configured to perform a 9C combined readout of groups 536A, 536B, 536C of pixel circuits. When performing a 9C combined readout, all 3 groups 536A, 536B, 536C of pixel circuits may be read out simultaneously via respective bit lines BL0, BL1, BL2.

[0066] In another example, a full-size or full-resolution readout of groups 536A, 536B, 536C of pixel circuits may be performed. However, for a full-size or full-resolution readout, only one group of pixel circuits is read out at a time. In other words, during a full-size readout, when group 0 536A is read out via bit line BL0, bit lines BL1 and BL2 are idle or not used. When group 1 536B is read out via bit line BL1, bit lines BL0 and BL2 are idle or not used. When group 2 536C is read out via bit line BL2, bit lines BL0 and BL1 are idle or not used. In operation, in accordance with the teachings of the present invention, clamping circuit 544 is configured to clamp idle bit lines BL0, BL1, or BL2 to improve the settling time and power supply rejection ratio.

[0067] For illustration, Figure 6 FIG. showing a schematic diagram of an example of a clamping circuit 644 coupled to bit line 612 in accordance with the teachings of the present disclosure, the bit line 612 being coupled to a capacitance and a current source of a readout circuit of a pixel array. It should be understood that Figure 6 clamping circuit 644 of Figure 5An example of one of the clamping circuits 544 described therein, and similarly named and numbered elements described above are similarly coupled and operative hereinafter.

[0068] As Figure 6 As shown in the example depicted in, the clamping circuit 644 includes a clamping shorting transistor 646 to the power supply line ADVDD and the bit line 612. In the example, the bit line 612 can be one of a group of 3 bit lines BL0, BL1, BL2, and is coupled to a current source 638 and a capacitor CAP 658. In one example, the capacitor CAP 658 can be a parasitic capacitor. In one example, the clamping shorting transistor 646 is configured to be switched in response to a clamping short enable signal 660. In the depicted example, the clamping shorting transistor 646 is implemented with a PMOS transistor.

[0069] In the example, the clamping circuit 644 further includes a first diode voltage drop device 650 coupled to the power supply line ADVDD and a clamping idle transistor 648 coupled to the first diode voltage drop device 650, such that the first diode voltage drop device and the clamping idle transistor are coupled between the power supply line ADVDD and the bit line 612. In the example, the first diode voltage drop device 650 is implemented with an NMOS transistor having a gate and a drain coupled to the power supply line ADVDD, and the clamping idle transistor 646 is implemented with an NMOS transistor. In one example, the clamping idle transistor 646 is configured to be switched in response to a clamping idle enable signal 662.

[0070] In one example, the clamping circuit 644 may also optionally include a second diode voltage drop device 656 coupled to the power supply line ADVDD, a tunable voltage level transistor 654 coupled to the second diode voltage drop device 656, and a clamping signal transistor 652 coupled to the tunable voltage level transistor 654, such that the second diode voltage drop device 656, the tunable voltage level transistor 654, and the clamping signal transistor 652 are coupled between the power supply line ADVDD and the bit line 612. In the example, the second diode voltage drop device 656 is implemented with an NMOS transistor having a gate and a drain coupled to the power supply line ADVDD, and the tunable voltage level transistor 654 and the clamping signal transistor 652 are implemented with NMOS transistors. In the example, the tunable voltage level transistor 654 is configured to be biased in response to a tunable voltage level signal 666, and the clamping signal transistor 652 is configured to be switched in response to a clamping signal enable signal 664.

[0071] In operation, it should be understood that the clamp circuit 644 can be used to clamp the unused idle bit lines 612. As will be discussed, the clamp circuit 644 can be configured to support clamping the bit line 612 to ADVDD through the clamp short transistor 646, or clamping the bit line 612 to ADVDD with a diode voltage drop through the first diode voltage drop device 650 and the clamp idle transistor 648, or optionally clamping the bit line 612 to a tunable voltage level option through the second diode voltage drop device 656, the tunable voltage level transistor 654, and the clamp signal transistor 652. As will be discussed, the clamp circuit 644 can also support a sample and hold function such that the idle bit line 612 can be clamped by a sample and hold voltage maintained by a parasitic capacitance (e.g., CAP 658).

[0072] For illustration, Figure 7 Schematic diagram illustrating an example of a sample and hold switch 768 coupled to a bit line 712 in accordance with the teachings of the present disclosure, the bit line 712 being coupled to a capacitor in a pixel array. It should be understood that Figure 7 the bit line 712 depicted in Figure 6 can be an example of the bit line 612 depicted in

[0073] As Figure 7 shown in the example depicted in each of a plurality of sample and hold switches is coupled between the power supply line ADVDD and a corresponding one of a plurality of bit lines 712. In the example, each of the plurality of sample and hold switches 768 is configured to be switched in response to a corresponding sample and hold enable signal (e.g., SH_en1, SH_en2, SH_en3, SH_en_4, SH_en5, SH_en6, SH_en7). In the illustrated example, the bit lines 712 represent the first bit BIT0, the second bit BIT1, the third bit BIT2, the fourth bit BIT3, the fifth bit BIT4, the sixth bit BIT5, and the seventh bit BIT6. In the example, the bit lines BIT0, BIT1, and BIT2 are a group of 3 bit lines of column 0 of a 1x3 pixel circuit, and the bit lines BIT3, BIT4, and BIT5 are a group of 3 bit lines of column 1 of a 1x3 pixel circuit, etc. The depicted example also illustrates the capacitances C6, C4, C2, C1, C3, C5, C7 between the respective bit lines BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6 and ground ADGND. Additionally, the depicted example also illustrates the capacitances C46, C24, C12, C13, C35, C57 between the bit lines BIT0 / BIT1, BIT1 / BIT2, BIT2 / BIT3, BIT3 / BIT4, BIT4 / BIT5, BIT5 / BIT6, respectively.

[0074] In the example, a full-size or full-resolution readout of the pixel array is being performed. Thus, only one (1) of the three bit lines per column of the 1x3 pixel circuit (e.g., BIT0, BIT3, BIT6, etc.) is active or in use at a time, and the remaining two bit lines of the three bit lines per column (e.g., BIT1 / BIT2, BIT4 / BIT5, etc.) are idle or not in use. Consequently, the sample-and-hold switches 768 coupled to the active bit lines (e.g., BIT0, BIT3, BIT6) are activated or turned on in response to the corresponding sample-and-hold enable signals (e.g., SH_en1, SH_en4, SH_en7), and the sample-and-hold switches 768 coupled to the idle bit lines (e.g., BIT1, BIT2, BIT4, BIT5) are deactivated or turned off in response to the corresponding sample-and-hold enable signals (e.g., SH_en2, SH_en3, SH_en5, SH_en6).

[0075] Figure 7 The example illustrated in shows the capacitive load of the active bit line BIT3 during readout. Specifically, with the sample-and-hold enable switches coupled to bit lines BIT1, BIT2, BIT4, BIT5 turned off, the capacitive load on bit line BIT3 is

[0076]

[0077] In Equation 1, the capacitance C2' represents the total capacitance effect of C6, C46, C4, C24, and C2, and the capacitance C3' represents the total capacitance effect of C7, C57, C5, C35, and C3.

[0078] In contrast, Figure 8A illustrates an example of a coupling path through capacitively coupled bit lines 812 in the absence of sample-and-hold switches in the pixel array. It should be understood that Figure 8A the bit lines 812 depicted in may be Figure 7 an example of the bit lines 712 depicted in, but without the sample-and-hold switches 768, and the similarly named and numbered elements described above are coupled and function similarly hereinafter.

[0079] As shown in the example depicted in FIG. 8, in the absence of the sample and hold switch 768, the bit lines BIT1, BIT2, BIT3, BIT4, BIT5, BIT6 are all kept coupled to the power supply line ADVDD, regardless of whether the corresponding bit line is active or idle. Thus, when the bit line BIT3 is active, the adjacent bit lines BIT2 and BIT4 are kept coupled to the power supply line ADVDD, thereby creating a coupling path between the power supply ADVDD and the bit line BIT3 through the adjacent bit lines BIT2 and BIT4. Thus, the capacitive load on the bit line BIT3 as illustrated in FIG. 8 is

[0080] C1 + C12 + C13 (2)

[0081] Comparing Equation 2 with Equation 1, it should be appreciated that the capacitive load on the bit line BIT3 according to Equation 1 is less than the capacitive load on the bit line BIT3 according to Equation 2. Thus, deactivation of the sample and hold switch coupled to the idle bit line reduces the capacitive load on the active bit line during full - size or full - resolution readout of the pixel array, which improves the settling time in accordance with the teachings of the present invention.

[0082] In addition, it should be further appreciated that in the absence of the isolation provided by the deactivated sample and hold switches in the idle bit lines (e.g., BIT2, BIT4), noise in the power supply line ADVDD is also coupled to the active bit line (e.g., BIT3) through the coupling capacitance between the idle bit lines and the bit lines, which reduces the power supply rejection ratio. For illustration, Figure 8B An example of the isolation provided by the deactivated sample and hold switch coupled to the bit lines of the pixel array in accordance with the teachings of the present invention is shown. It should be appreciated that Figure 8B the bit line 812 depicted in Figure 8A may be an example of the bit line 812 depicted in, but with a deactivated sample and hold switch 868, and the similarly named and numbered elements described above are similarly coupled and operative hereinafter. As shown in the example depicted, in accordance with the teachings of the present invention, isolation from the adjacent bit lines to the power supply line ADVDD is provided by the deactivated sample and hold switch. Thus, in accordance with the teachings of the present invention, the power supply rejection ratio is improved by deactivating the sample and hold switches in the idle bit lines.

[0083] Figure 9A An example of a timing diagram of a signal in a clamping circuit coupled to a bit line during a time period related to the readout of a pixel circuit in an example pixel array in accordance with the teachings of the present invention is illustrated. It should be appreciated that Figure 9A the signal depicted in Figure 6 may be an example of the signal depicted in, and the similarly named and numbered elements described above are similarly coupled and operative hereinafter.

[0084] Figure 9A The example depicted in Figure 6 controls the clamp short transistors 648 and 646 depicted in Figure 6 configured to control the clamp short transistors 648 and 646 depicted in Figure 6 Note that the clamp short enable signal 660 depicted in

[0085] In Figure 9A the depicted example, the clamp short enable signal 960 is low, which turns into a high inverted clamp_short_en_b signal 660 and turns off the clamp short transistor 646 depicted in Figure 6 throughout the first case. Continuing with the depicted example, the clamp idle enable signal 962 is initially high, which turns on the clamp idle transistor 648. Thus, the bit line 612 is clamped to the power supply line ADVDD with a diode voltage drop across the first diode voltage drop device 650. In one example, at this time the bit line 612 is clamped to a value close to the black level of the bit line to accelerate the settling time of the bit line 612.

[0086] Next, during normal readout, the clamp idle enable signal 962 transitions to a low value, which turns off or disables the clamp idle transistor 648 during normal readout through the bit line 612.

[0087] Next, after normal readout through the bit line 612, the clamp idle enable signal 962 transitions back to a high value, which turns on or enables the clamp idle transistor 648 back to the clamped value to the power supply line ADVDD with a diode voltage drop across the first diode voltage drop device 650 close to the black level of the bit line. In one example, this value will be sampled and held when the active row is switched to the idle row in response to the corresponding sample and hold enable signal. In various examples, this sampled value is held by the parasitic capacitance coupled to the bit line 612.

[0088] Figure 9B Another example of a timing diagram of signals in an example clamp circuit coupled to a bit line during a time period related to the readout of a pixel circuit in an example pixel array in accordance with the teachings of the present invention. It should be understood that Figure 9B the signals depicted in Figure 6 may be examples of the signals depicted in

[0089] Figure 9B The example depicted in Figure 9B illustrates a second case where the clamp idle enable signal 962 and the clamp short enable signal 960 are configured to control Figure 6 the clamp idle transistor 648 and the clamp short transistor 646 depicted in Figure 6 . It should be noted that Figure 6 the clamp short enable signal 660 depicted in Figure 6 is an inverted control signal (e.g., clamp_short_en_b 660) of the PMOS transistor that is coupled to control the clamp short transistor 646. Thus, it should be understood that the polarity of the clamp short enable signal 960 can be appropriately inverted to control the clamp short transistor 646 with Figure 6 the inverted clamp_short_en_b 660 signal.

[0090] In Figure 9B the example depicted in Figure 9B , the clamp idle enable signal 962 is at a low level, which turns off Figure 6 the clamp idle transistor 648 depicted in Figure 6 throughout the second case. Continuing the depicted example, the clamp short enable signal 960 is initially at a high value, which turns on the clamp short transistor 646. Thus, the bit line 612 is clamped to the power supply line ADVDD. In one example, at this time the bit line 612 is clamped to a value close to the black level of the bit line to accelerate the settling time of the bit line 612.

[0091] Next, during normal readout, the clamp short enable signal 960 transitions to a low value, which turns off or disables the clamp short transistor 646 during normal readout through the bit line 612.

[0092] Next, after normal readout through the bit line 612, the clamp short enable signal 960 transitions back to a high value, which turns on or enables the clamp short transistor 646 back to the clamped value of the power supply line ADVDD close to the black level of the bit line. In one example, this value will be sampled and held when the active row is switched to the idle row in response to the corresponding sample and hold enable signal. In various examples, this sampled value is held by the parasitic capacitance coupled to the bit line 612.

[0093] Figure 9C Another example of a timing diagram of signals in an example clamp circuit coupled to a bit line during a time period related to the readout of a pixel circuit in an example pixel array in accordance with the teachings of the present invention is illustrated. It should be understood that Figure 9C the signals depicted in Figure 9C can be Figure 6 examples of the signals depicted in Figure 6 , and the similarly named and numbered elements described above are similarly coupled and operate below.

[0094] Figure 9CThe example depicted in [FIGURE] illustrates a third scenario in which the clamp idle enable signal 962 and the clamp short enable signal 960 are configured to control Figure 6 the clamp idle transistor 648 and the clamp short transistor 646 depicted in [FIGURE]. It should be noted that Figure 6 the clamp short enable signal 660 depicted in [FIGURE] is an inverted control signal (e.g., clamp_short_en_b 660) of the PMOS transistor coupled to control the clamp short transistor 646. Thus, it should be understood that the polarity of the clamp short enable signal 960 can be appropriately inverted to control the clamp short transistor 646 with the Figure 6 inverted clamp_short_en_b 660 signal.

[0095] It should be noted that Figure 9C the third scenario depicted in [FIGURE] is a hybrid scenario in which the active row bit line is clamped by the power supply line ADVDD with a diode voltage drop (e.g., through the first diode voltage drop device 650 and the clamp idle transistor 648), while the idle row bit line is clamped to the power supply line ADVDD (e.g., through the clamp short transistor 646).

[0096] As Figure 9C shown in the example depicted in [FIGURE], the clamp idle enable signal 962 and the clamp short enable signal 960 are initially at a high value, which turns on the clamp idle transistor 648 and the clamp short transistor 646. Thus, the idle bit line is clamped to the power supply line ADVDD, and the active bit line is clamped to the power supply line ADVDD with a diode voltage drop.

[0097] Next, during normal readout, the clamp short enable signal 960 and then the clamp idle enable signal 962 transition to a low value, which turns off or disables the clamp short transistor 646 and then the clamp idle transistor 648 for normal readout through the bit line 612.

[0098] Next, after normal readout through the bit line 612, the clamp short enable signal 960 and then the clamp idle enable signal 962 transition back to a high value, which turns on or enables the clamp short transistor 646 and then the clamp idle transistor 648 back to the clamped value to the power supply line ADVDD for the idle row and the clamped value to the power supply line ADVDD with a diode voltage drop for the active bit line. In one example, when the active row is switched to the idle row in response to the corresponding sample and hold enable signal, the clamped value of the idle bit line will be sampled and held. In various examples, this sampled value is held by the parasitic capacitance coupled to the bit line 612. It should be understood that the period of initializing the bit line 612 to the clamped value, performing normal readout through the bit line 612, and then clamping the bit line 612 again to the clamped value after normal readout is 1 horizontal time step (HTP), as Figure 9Cas marked therein.

[0099] Figure 10A An example of a timing diagram illustrating signals in an example clamp circuit coupled to a bit line during a time period related to the readout of a group of pixel circuits in an example pixel array in accordance with the teachings of the present invention. It should be understood that Figure 10A the signals depicted in Figure 6 may be examples of the signals depicted in

[0100] Figure 10A The example depicted in Figure 9A illustrates group 0 1036A signals, group 1 1036B, and group 2 1036C signals. In the example, when the group 0 1036A signal is high, group 0 is read out. As shown, during a first horizontal time step (e.g., 1HTS), the group 1 1036B and group 2 1036C signals are low while the group 0 1036A signal is high. Thus, the group 0 bit line (e.g., BL0) is active while the group 1 and group 2 bit lines (e.g., BL1, BL2) are idle or not in use. During the first horizontal time step (e.g., 1HTS), the 1x3 pixel circuits included in group 0 are read out, which is indicated by the group 0 clamp idle enable signal 1062-0 (e.g., clamp_idle_en<0>662) being activated, then deactivated, and then reactivated, which enables, disables, and then enables the clamp idle transistor 648 during the first horizontal time step, as also shown in

[0101] the example of case 1 described in detail in Figure 9A as shown in the example of case 1 described in detail in

[0102] Next, during a third horizontal time step (e.g., 3HTS), when group 2 1036C is high, group 2 is read out. As shown, during the third horizontal time step (e.g., 3HTS), the group 0 1036A and group 1 1036B signals are low while the group 2 1036C signal is high. Thus, the group 2 bit line (e.g., BL2) is active while the group 0 and group 1 bit lines (e.g., BL0, BL1) are idle or not in use. During the third horizontal time step (e.g., 3HTS), the 1x3 pixel circuits included in group 2 are read out, which is indicated by the clamp idle enable signal 1062-2 for group 2 (e.g., clamp_idle_en<2> 662) being activated, then deactivated, and then reactivated, which enables, disables, and then enables the clamp idle transistor 648 during the third horizontal time step, also as Figure 9A shown in the case 1 example described in detail in

[0103] Figure 10B Another example of a timing diagram illustrating signals in an example clamp circuit coupled to a bit line during a time period related to the readout of groups of pixel circuits in an example pixel array in accordance with the teachings of the present invention. It should be understood that Figure 10B the signals depicted in Figure 6 may be examples of the signals depicted in Figure 10B and the similarly named and numbered elements described above are coupled and operate similarly below. It should also be understood that Figure 10A the example depicted in Figure 10B shares many similarities with the example depicted in Figure 10A The difference between the example depicted in Figure 10B and the example depicted in

[0104] For illustration, Figure 10BThe examples depicted therein show the Group 0 1036A signal, the Group 1 1036B, and the Group 2 1036C signal. In the example, when the Group 0 1036A signal is high, Group 0 is read out. As shown, during the first horizontal time step (e.g., 1HTS), the Group 1 1036B and Group 2 1036C signals are low while the Group 0 1036A signal is high. Thus, the Group 0 bit line (e.g., BL0) is active while the Group 1 and Group 2 bit lines (e.g., BL1, BL2) are idle or not in use. During the first horizontal time step (e.g., 1HTS), the 1x3 pixel circuits included in Group 0 are read out, which is indicated by the (active low) clamp short enable signal 1060-0B (e.g., clamp_short_en_b<0>660) of Group 0 being activated, then deactivated, and then reactivated, which enables, disables, and then enables the clamp short transistor 646 during the first horizontal time step, also as Figure 9B shown in the Case 2 example described in detail in

[0105] Next, during the second horizontal time step (e.g., 2HTS), when the Group 1 1036B is high, Group 1 is read out. As shown, during the second horizontal time step (e.g., 2HTS), the Group 0 1036A and Group 2 1036C signals are low while the Group 1 1036B signal is high. Thus, the Group 1 bit line (e.g., BL1) is active while the Group 0 and Group 2 bit lines (e.g., BL0, BL2) are idle or not in use. During the second horizontal time step (e.g., 2HTS), the 1x3 pixel circuits included in Group 1 are read out, which is indicated by the (active low) clamp short enable signal 1060-1B (e.g., clamp_short_en_b<1>660) of Group 1 being activated, then deactivated, and then reactivated, which enables, disables, and then enables the clamp short transistor 646 during the second horizontal time step, also as Figure 9B shown in the Case 2 example described in detail in

[0106] Next, during the third horizontal time step (e.g., 3HTS), when Group 2 1036C is high, Group 2 is read out. As shown, during the third horizontal time step (e.g., 3HTS), the Group 0 1036A and Group 1 1036B signals are low, while the Group 2 1036C signal is high. Thus, the Group 2 bit line (e.g., BL2) is active, while the Group 0 and Group 1 bit lines (e.g., BL0, BL1) are idle or not in use. During the third horizontal time step (e.g., 3HTS), the 1x3 pixel circuits included in Group 2 are read out, which is indicated by the (active low) clamp short enable signal 1060-2B (e.g., clamp_short_en_b<2>660) of Group 2 being activated, then deactivated, and then reactivated, which enables, disables, and then enables the clamp short transistor 646 during the third horizontal time step, also as Figure 9B shown in the Case 2 example described in detail in

[0107] Figure 11 Illustrates an example logic diagram for generating signals for an example clamp circuit in accordance with the teachings of the present invention. It should be understood that Figure 11 the signals depicted in Figures 6 to 10B may be examples of the signals depicted in

[0108] As shown in the example depicted, the Group 2, Group 1, Group 0 signals 1136 are received by inverters <2:0>1170, the outputs of which are the inverted signals bb2, bb1, bb0 1136B, which are received by inverters <2:0>1172 that output the grouped signals bl2, bl1, bl0 1136C. An inverter 1174 receives the sample and hold enable signal S&H_en1168. NAND gates <2:0>1178 are coupled to receive the inverted signals bb2, bb1, bb0 1136B and the output of inverter 1174. NAND gates <2:0>1176 are coupled to receive the clamp idle enable input signal clamp_idle_en_in1162B and the grouped signals bl2, bl1, bl0 1136C. NAND gates <2:0>1180 are coupled to receive the output of NAND gates <2:0>1176 and the output of NAND gates <2:0>1178 to generate the clamp idle enable signals clamp_idle_en<2:0>1162, which are coupled to be received by the clamp idle transistors 648 of the clamp circuit 644, as Figure 6 discussed in

[0109] Returning to the reference Figure 11In the example diagram shown, inverter 1182 is also coupled to receive the sample and hold enable signal S&H_en 1168. NAND gate <2:0> 1186 is also coupled to receive the inverted signals bb2, bb1, bb0 1136B and the output of inverter 1182. NAND gate <2:0> 1184 is coupled to receive the clamp short enable input signal clamp_short_en_in 1160B and the group signals bl2, bl1, bl0 1136C. NAND gate <2:0> 1188 is coupled to receive the output of NAND gate <2:0> 1184 and the output of NAND gate <2:0> 1186 to generate the clamp short enable signal clamp_short_en <2:0> 1160. In the example, three serially coupled inverters 1190, 1192, and 1194 are coupled to receive the clamp short enable signal clamp_short_en <2:0> 1160 to generate an inverted clamp short enable signal clamp_short_en_b <2:0> 1160B, which is coupled to be received by the clamp short transistors 648 of the clamp circuit 644, as Figure 6 discussed in

[0110] The foregoing description of the illustrated example of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. As those skilled in the relevant art will recognize, while specific examples of the invention are described herein for purposes of illustration, various modifications are possible within the scope of the invention.

[0111] These modifications to the invention are possible in light of the above detailed description. The terms used in the following claims should not be construed as limiting the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be interpreted in accordance with established doctrines of claim interpretation.

Claims

1. An imaging device, comprising: a pixel array including a plurality of pixel circuits arranged in rows and columns; a plurality of bit lines coupled to the plurality of pixel circuits; and a plurality of clamping circuits coupled to the plurality of bit lines, wherein each of the plurality of clamping circuits includes: a clamping short circuit transistor coupled to a power supply line and a respective one of the plurality of bit lines of the pixel array, wherein the clamping short circuit transistor is configured to be switched in response to a clamping short circuit enable signal; a first diode voltage drop device coupled to the power supply line; and a clamping idle transistor coupled to the first diode voltage drop device such that the first diode voltage drop device and the clamping idle transistor are coupled between the power supply line and the respective one of the plurality of bit lines, wherein the clamping idle transistor is configured to be switched in response to a clamping idle enable signal.

2. The imaging device according to claim 1, wherein each of the plurality of clamping circuits further includes: a second diode voltage drop device coupled to the power supply line; a tunable voltage level transistor coupled to the second diode voltage drop device, wherein the tunable voltage level transistor is configured to be biased in response to a tunable voltage level signal; and a clamping signal transistor coupled to the tunable voltage level transistor such that the second diode voltage drop device, the tunable voltage level transistor, and the clamping signal transistor are coupled between the power supply line and the respective one of the plurality of bit lines, wherein the clamping signal transistor is configured to be switched in response to a clamping signal enable signal.

3. The imaging device according to claim 2, further comprising a plurality of sample and hold switches coupled to the plurality of bit lines, wherein the respective one of the plurality of bit lines is further coupled to a respective one of the plurality of sample and hold switches, wherein the respective one of the plurality of sample and hold switches is configured to be switched in response to a sample and hold enable signal.

4. The imaging device according to claim 3, wherein a parasitic capacitance coupled to the respective one of the plurality of bit lines is configured to hold a sampled voltage on the respective one of the plurality of bit lines in response to the respective one of the plurality of sample and hold switches.

5. The imaging device according to claim 4, wherein the plurality of pixel circuits include a plurality of 1x3 pixel circuits arranged in the rows and columns of the pixel array, wherein each 1x3 pixel circuit includes 3 photodiodes included in a respective column of the 1x3 pixel circuits in the pixel array, and wherein the 3 photodiodes of each 1x3 pixel circuit included in the respective column of the 1x3 pixel circuits in the pixel array are included in 3 respective rows of the pixel array.

6. The imaging device according to claim 5, wherein the plurality of bit lines are divided into groups of 3 bit lines per column of the 1x3 pixel circuits in the pixel array, and each column of the 1x3 pixel circuits in the pixel array includes a plurality of first groups of the 1x3 pixel circuits coupled to a first bit line of the corresponding group of the 3 bit lines, a plurality of second groups of the 1x3 pixel circuits coupled to a second bit line of the corresponding group of the 3 bit lines, and a plurality of third groups of the 1x3 pixel circuits coupled to a third bit line of the corresponding group of the 3 bit lines.

7. The imaging device according to claim 6, wherein during full resolution readout of the pixel array, 1 bit line of each group of 3 bit lines per column of the 1x3 pixel circuits in the pixel array is configured to be active at a time, and the remaining bit lines of each group of 3 bit lines per column of the 1x3 pixel circuits in the pixel array are inactive.

8. The imaging device according to claim 7, wherein the corresponding one of the plurality of sample-and-hold switches is configured to turn on when the corresponding one of the plurality of bit lines is active, and the corresponding one of the plurality of sample-and-hold switches is configured to turn off when the corresponding one of the plurality of bit lines is idle.

9. The imaging device according to claim 8, wherein the clamp idle transistor is configured to be turned on to clamp the corresponding one of the plurality of bit lines to a black level close to the corresponding one of the plurality of bit lines, wherein the clamp idle transistor is then configured to be turned off during normal readout of the corresponding one of the plurality of bit lines, wherein the clamp idle transistor is then configured to be turned on after the normal readout of the corresponding one of the plurality of bit lines.

10. The imaging device according to claim 9, wherein when the corresponding one of the plurality of bit lines is active, the corresponding one of the plurality of sample-and-hold switches coupled to the corresponding one of the plurality of bit lines is turned on, and when the corresponding one of the plurality of bit lines becomes idle, the corresponding one of the plurality of sample-and-hold switches coupled to the corresponding one of the plurality of bit lines is turned off.

11. The imaging device according to claim 8, wherein the clamp short transistor is configured to be turned on to clamp the corresponding one of the plurality of bit lines to the power supply line coupled to the corresponding one of the plurality of bit lines, wherein the clamp short transistor is then configured to be turned off during normal readout of the corresponding one of the plurality of bit lines, wherein the clamp short transistor is then configured to be turned on after the normal readout of the corresponding one of the plurality of bit lines.

12. The imaging device according to claim 11, wherein when the corresponding one of the plurality of bit lines is active, the corresponding one of the plurality of sample-and-hold switches coupled to the corresponding one of the plurality of bit lines is turned on, and when the corresponding one of the plurality of bit lines becomes idle, the corresponding one of the plurality of sample-and-hold switches coupled to the corresponding one of the plurality of bit lines is turned off.

13. An imaging system, comprising: a pixel array including a plurality of pixel circuits arranged in rows and columns; a plurality of bit lines coupled to the plurality of pixel circuits; a plurality of clamping circuits coupled to the plurality of bit lines, wherein each of the plurality of clamping circuits includes: a clamping short-circuit transistor coupled to a power supply line and a corresponding one of the plurality of bit lines of the pixel array, wherein the clamping short-circuit transistor is configured to be switched in response to a clamping short-circuit enable signal; a first diode voltage drop device coupled to the power supply line; and a clamping idle transistor coupled to the diode voltage drop device such that the first diode voltage drop device and the clamping idle device are coupled between the power supply line and the corresponding one of the plurality of bit lines, wherein the clamping idle transistor is configured to be switched in response to a clamping idle enable signal; a plurality of sample-and-hold switches coupled to the plurality of bit lines, wherein the corresponding one of the plurality of bit lines is further coupled to the corresponding one of the plurality of sample-and-hold switches; and a readout circuit coupled to the pixel array to read signals from the pixel array through the plurality of bit lines, the readout circuit including a plurality of current sources coupled to the plurality of bit lines.

14. The imaging system according to claim 13, wherein the parasitic capacitance coupled to the corresponding one of the plurality of bit lines is configured to hold the sampled voltage on the corresponding one of the plurality of bit lines.

15. The imaging system according to claim 14, wherein the corresponding one of the plurality of sample-and-hold switches is configured to be turned on when the corresponding one of the plurality of bit lines is active, and the corresponding one of the plurality of sample-and-hold switches is configured to be turned off when the corresponding one of the plurality of bit lines is idle.

16. The imaging system according to claim 15, wherein the clamping idle transistor is configured to be turned on before normal readout of the corresponding one of the plurality of bit lines to clamp the corresponding one of the plurality of bit lines to a level close to the black level of the corresponding one of the plurality of bit lines, wherein the clamping idle transistor is then configured to be turned off during the normal readout of the corresponding one of the plurality of bit lines, wherein the clamping idle transistor is then configured to be turned on after the normal readout of the corresponding one of the plurality of bit lines.

17. The imaging system according to claim 15, The clamping short-circuit transistor is configured to be turned on before normal readout of the corresponding one of the plurality of bit lines to clamp the corresponding one of the plurality of bit lines to the power supply line coupled to the corresponding one of the plurality of bit lines. The clamping short-circuit transistor is then configured to be turned off during the normal readout of the corresponding one of the plurality of bit lines. The clamping short-circuit transistor is configured to be turned on after the normal readout of the corresponding one of the plurality of bit lines.

18. The imaging system according to claim 13, wherein each of the plurality of clamping circuits further comprises: A second diode voltage drop device coupled to the power supply line. A tunable voltage level transistor coupled to the second diode voltage drop device, wherein the tunable voltage level transistor is configured to be biased in response to a tunable voltage level signal. And A clamping signal transistor coupled to the tunable voltage level transistor such that the second diode voltage drop device, the tunable voltage level transistor, and the clamping signal transistor are coupled between the power supply line and the corresponding one of the plurality of bit lines, wherein the clamping signal transistor is configured to be switched in response to a clamping signal enable signal.

19. The imaging system according to claim 13, wherein the plurality of pixel circuits include a plurality of 1x3 pixel circuits arranged in the rows and columns of the pixel array, wherein each 1x3 pixel circuit includes 3 photodiodes included in the corresponding column of the 1x3 pixel circuits in the pixel array, and the 3 photodiodes of each 1x3 pixel circuit included in the corresponding column of the 1x3 pixel circuits in the pixel array are included in 3 corresponding rows of the pixel array.

20. The imaging system according to claim 19, wherein the plurality of bit lines are divided into groups of 3 bit lines per column of the 1x3 pixel circuits in the pixel array, and each column of the 1x3 pixel circuits in the pixel array includes a plurality of first groups of the 1x3 pixel circuits coupled to the first bit line of the corresponding group of the 3 bit lines, a plurality of second groups of the 1x3 pixel circuits coupled to the second bit line of the corresponding group of the 3 bit lines, and a plurality of third groups of the 1x3 pixel circuits coupled to the third bit line of the corresponding group of the 3 bit lines.

21. The imaging system according to claim 20, wherein during full-resolution readout of the pixel array, 1 bit line per group of 3 bit lines per column of the 1x3 pixel circuits in the pixel array is configured to be active, and the remaining bit lines of the group of 3 bit lines per column of the 1x3 pixel circuits in the pixel array are inactive.

Images