Bias control for memory devices

Abstract

Methods, systems, and devices for bias control of a memory device are described. A memory system may store an indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is incoherent, and a second value or a third value indicates that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and operate according to a host bias mode when the indication is the second value or the third value.

Description

[0001] Cross Reference

[0002] This patent application is a national phase application of international patent application No. PCT / US2021 / 073118 entitled “BIAS CONTROL FOR A MEMORY DEVICE” filed by Walker et al. on December 27, 2021, which claims priority to U.S. patent application No. 17 / 198,084 entitled “BIAS CONTROL FOR A MEMORY DEVICE” filed by Walker et al. on March 10, 2021, each of which is assigned to the present assignee and each of which is expressly incorporated herein.

[0003] The technical field relates to bias control of memory devices. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states that often correspond to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross-point), "NOR" and "NAND" memory devices, etc. Memory devices can be volatile or non-volatile. Unless periodically refreshed by an external power source, volatile memory cells (e.g., DRAM cells) may lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) may maintain their programmed state for a long time even in the absence of external power. Summary of the invention

[0006] A system is described. The system may include: a memory; and a controller coupled to the memory, wherein the controller is configured to: store a coherence state of a data set stored in the memory relative to a cache of a host device; and access the memory according to a bias state of the data set determined at least in part based on the stored coherence state of the data set based at least in part on identifying a command to perform an access operation of the data set stored in the memory, wherein the bias state is associated with control of access to the data set by the controller.

[0007] A system is described. The system may include: a memory; and a controller coupled to the memory, wherein the controller is configured to: store a coherence state of a data set stored in the memory relative to a cache of a host device; and access the memory according to a bias state of the data set determined at least in part based on the stored coherence state of the data set based at least in part on identifying a command to perform an access operation of the data set stored in the memory, wherein the bias state is associated with control of access to the data set by the host device.

[0008] A method is described. The method may include: storing a coherence state of a data set stored in a memory relative to a cache of a host device; accessing the memory according to a bias state of the data set determined based at least in part on the stored coherence state of the data set based at least in part on identifying a command to perform an access operation of the data set stored in the memory, wherein the bias state is associated with control of access to the data set by a controller associated with the memory.

[0009] A method is described. The method may include: storing a coherence state of a data set stored in a memory relative to a cache of a host device; and accessing the memory according to a bias state of the data set determined based at least in part on the stored coherence state of the data set based at least in part on identifying a command to perform an access operation of the data set stored in the memory, wherein the bias state is associated with control of access to the data set by the host device.

[0010] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: store a coherence state of a data set stored in a memory relative to a cache of a host device; and access the memory based at least in part on identifying a command to perform an access operation of the data set stored in the memory according to a bias state of the data set determined at least in part based on the stored coherence state of the data set, wherein the bias state is associated with control of access to the data set by a controller associated with the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system supporting bias control of a memory device according to examples as disclosed herein is shown.

[0012] Figure 2 An example of a system supporting bias control of a memory device according to examples as disclosed herein is shown.

[0013] Figure 3 An example of a system supporting bias control of a memory device according to examples as disclosed herein is shown.

[0014] Figure 4 An example of a process flow diagram is shown to support bias control of a memory device according to examples as disclosed herein.

[0015] Figure 5 An example of a process flow diagram is shown to support bias control of a memory device according to examples as disclosed herein.

[0016] Figure 6 A block diagram of a memory controller supporting bias control of a memory device according to examples as disclosed herein is shown.

[0017] Figure 7 and 8 A flow chart is shown illustrating one or more methods of supporting bias control of a memory device according to examples as disclosed herein. DETAILED DESCRIPTION

[0018] Some interfaces, such as the Compute Express Link (CXL) interface, may provide a mechanism for a bias-based coherence model. Specifically, the CXL specification provides that a device-attached memory may track a bias state to determine whether the device needs to send a request to a host device to resolve coherence when the device (e.g., a processing unit of the device) accesses the memory. The two bias states are host bias, where the device needs to send a request to resolve coherence to the host device; and device bias, where the memory device may access the memory independently of the host device.

[0019] The CXL specification indicates that the device shall maintain a bias table for blocks (e.g., pages) of memory and a transition agent for managing bias transitions. Bias transitions are typically managed by software using commands between the memory device and the host device and are managed on a per-block basis. However, managing bias transitions on a per-block basis may result in inefficiencies when portions of a block may have different coherence states.

[0020] Methods and systems for managing bias transitions at a relatively finer granularity are described herein. The CXL specification describes metadata that can be maintained for each row of data. One of the metadata fields described is a Meta0-state, which can hold one of three values: Invalid, Any, or Shared. The Invalid state indicates that the host does not have a cacheable copy of the row, the Any state indicates that the host may have a shared, exclusive, or modified copy of the row, and the Shared state indicates that the host may have at most a shared copy of the row. The CXL specification therefore indicates that the bias state used to synchronize control for coherence is maintained separately from the Meta0-state that indicates the cache or coherence state. The Meta0-state for each row can be stored, and the Meta0-state can be stored with the row data.

[0021] As described herein, the Meta0-state field may be used to track the current bias state. Specifically, according to various aspects, the Meta0-state Invalid may be equivalent to the device bias, and both Any and Shared may be equivalent to the host bias. Tracking the device-attached media bias at a granularity corresponding to the cache line size of the host device may allow the device to transform the bias of the medium on any component that has access to the medium. This allows full hardware control of the bias, and does not require software to perform the complex task of transforming the device-attached media bias to achieve optimal device performance. In some instances, the Meta0-state may be stored in the memory medium along with the data row, or may be stored only in the device cache (e.g., maintained in the cache only for the row). If it is stored only in the cache, the device will present the Any state on a cache miss. In either example, utilizing the Meta0-state of the CXL specification to track the bias state on a per-cache line basis may improve the overall performance of the memory device while maintaining a relatively simple programming model.

[0022] First, in the reference Figures 1 to 3 Features of the present disclosure are described in the context of the described system. Figure 4 and 5 Features of the present disclosure are described in the context of a process flow diagram. Figure 6-8These and other features of the present disclosure are further illustrated and described with reference to the described apparatus diagrams and flow charts relating to bias control of memory devices.

[0023] Figure 1 An example of a system 100 that supports bias control of a memory device according to examples as disclosed herein is shown. The system 100 includes a host system 105 coupled to a memory system 110.

[0024] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0025] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device that includes a memory and a processing device.

[0026] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and read data from the memory system 110. Although in Figure 1One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0027] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 are configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DIMM socket interface supporting DDR), an Open NAND Flash Interface (ONFI), a Low Power Double Data Rate (LPDDR) interface, and a CXL interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110 or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0028] Memory system 110 may include a memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0029] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface), and may be an example of a control component configured to cause the memory system 110 to perform various operations according to examples as described herein. The memory system controller 115 may also be coupled and communicate with the memory devices 130 to perform operations that may generally be referred to as access operations at the memory devices 130, such as reading data, writing data, erasing data, or refreshing data, as well as other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to perform such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0030] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0031] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0032] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating codes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for internal storage or computations related to the functions attributed herein to the memory system controller 115, for example. Additionally or alternatively, the local memory 120 may act as a cache for the memory system controller 115. For example, in the case of a read from or write to the memory device 130, the data may be stored in the local memory 120, and the data may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 in accordance with a cache policy (e.g., with reduced latency relative to the memory device 130).

[0033] although Figure 1 The example of the memory system 110 in FIG. 1 has been shown as including a memory system controller 115, but in some cases the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 that may be internal to the memory device 130 to perform the functions attributed herein to the memory system controller 115, respectively. In general, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof in some cases. In some cases, the memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device, but other types of managed memory devices are also supported. For example, a managed memory device may include any type or number of volatile or non-volatile memory devices.

[0034] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0035] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115, or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As shown in , memory device 130 - a may include a local controller 135 - a and memory device 130 - b may include a local controller 135 - b.

[0036] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0037] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as a multi-level cell (MLC) if configured to store two bits of information each, a triple-level cell (TLC) if configured to store three bits of information each, a quad-level cell (QLC) if configured to store four bits of information each, or more generally, a multi-level memory cell. A multi-level memory cell may provide greater storage density relative to an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0038] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 having the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0039] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0040] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0041] The system 100 may include any number of non-transitory computer-readable media that support bias control of a memory device. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0042] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0043] In some examples, the host system 105 may include a cache that includes one or more pages (e.g., one or more pages for storing data). Each page may include one or more rows, each associated with a certain amount of data. As described herein, the memory system controller 115 may be configured to track the coherence of data shared between the host system 105 and the memory system 110. For example, the memory system controller 115 may track the coherence of data shared between the memory device 130-a or the memory device 130-b and the host system 105. The coherence of the data may involve one of three states indicating whether there is no coherent copy of the data at the host system 105 and the memory system 110 or whether there is a shared, exclusive, or modified copy of the data.

[0044] The memory system 110 may be an example of a CXL device, and the memory system controller 115 may be an example of a processing unit configured to access the memory device 130-a and the memory device 130-b. For example, the memory system controller 115 may be configured to access the memory device 130-a and the memory device 130-b according to a host bias mode or a device bias mode. When operating according to the device bias mode, the memory system controller 115 may access the memory device 130-a or the memory device 130-b independently of the host system 105 (e.g., after receiving an access request or an access command). Conversely, when operating according to the host bias mode, the memory system controller 115 may access the memory device 130-a or the memory device 130-b via the host system 105. In addition, when one or more pages are associated with the host bias mode, the host may modify the version of the one or more pages maintained by the host without notifying the memory system controller 115.

[0045] In some examples, each row of data stored to memory device 130-a or memory device 130-b may be associated with an optional 2-bit Meta0 field. As described herein, the 2-bit Meta0 field may be used to indicate the bias state of the associated data based on the three coherent states. For example, when the data is associated with a first coherent state (e.g., an "invalid" state; when there is no coherent copy of the data), the Meta0 field may indicate operation according to a device bias mode. Additionally or alternatively, when the data is associated with a second coherent state (e.g., an "any" state; when there is a coherent copy of the data) or a third coherent state (e.g., a "shared" state; when there is a coherent copy of the data), the Meta0 field may indicate operation according to a host bias mode. Therefore, tracking device bias using the Meta0-state may allow bias states to be tracked at a greater granularity.

[0046] Figure 2 An example of a system 200 for supporting bias control of a memory device according to an example disclosed herein is shown. The system 200 may be a reference Figure 1 The system 200 may include a memory system 210 configured to store data received from a host system 205 and to send data to the host system 205 if requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 may be implemented as described in reference Figure 1 Aspects of the described system 100. For example, memory system 210 and host system 205 can be instances of memory system 110 and host system 105, respectively.

[0047] As described herein, the memory system 210 may include a memory device 240 to store data transferred between the memory system 210 and the host system 205, for example, in response to receiving an access command from the host system 205. The memory device 240 may include a reference Figure 1 For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0048] The memory system 210 may include a storage controller 230 for controlling the transfer of data directly into and out of the memory devices 240, for example, for storing data, retrieving data, and determining memory locations in which data is to be stored and from which data is to be retrieved. The storage controller 230 may communicate with the memory devices 240 directly or via a bus (not shown) using a protocol specific to each type of memory device 240. In some cases, a single storage controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, the memory system 210 may include multiple storage controllers 230, for example, a different storage controller 230 for each type of memory device 240. In some cases, the storage controller 230 may implement a reference Figure 1 Aspects of the local controller 135 are described.

[0049] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data being transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may be used to translate data between the host system 205 and the memory device 240, such as shown by the data path 250, and may be collectively referred to as data path components.

[0050] Using buffer 225 to temporarily store data during transfer can allow data to be buffered while commands are being processed, thereby reducing latency between commands and allowing arbitrary data sizes associated with commands. This can also allow bursts of commands to be processed, and once the burst stops, the buffered data can be stored or transmitted (or both). Buffer 225 can include relatively fast memory (e.g., some type of volatile memory, such as SRAM or DRAM) or a hardware accelerator or both to allow fast storage and retrieval of data in and out of buffer 225. Buffer 225 can include a data path switching component for bidirectional data transfer between buffer 225 and other components.

[0051] Temporary storage of data within buffer 225 may refer to storage of data in buffer 225 during execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., may be overwritten with data from additional access commands). In addition, buffer 225 may be a non-cacheable buffer. That is, the host system 205 may not read data directly from buffer 225. For example, a read command may be added to a queue without requiring an operation to match an address with an address already in buffer 225 (e.g., without requiring a cache address match or lookup operation).

[0052] The memory system 210 may further include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be as described in reference Figure 1 An example of a memory system controller 115 is depicted. Bus 235 may be used to communicate between system components.

[0053] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. For example, this may be beneficial if the memory system 210 processes more than one access command from the host system 205 in parallel. As an example of a possible implementation, the command queue 260, buffer queue 265, and storage queue 270 are depicted at the interface 220, the memory system controller 215, and the storage controller 230, respectively. However, if used, the queues may be located anywhere within the memory system 210.

[0054] Data transferred between the host system 205 and the memory device 240 may take a different path than non-data information (e.g., commands, status information) in the memory system 210. For example, system components in the memory system 210 may communicate with each other using the bus 235, while data may use the data path 250 that passes through data path components instead of the bus 235. The memory system controller 215 may control how and whether data is transferred between the host system 205 and the memory device 240 by communicating with the data path components over the bus 235 (e.g., using a protocol specific to the memory system 210).

[0055] If the host system 205 transmits an access command to the memory system 210, the interface 220 may receive the command, for example, according to a protocol (e.g., UFS protocol, eMMC protocol, CXL protocol). Therefore, the interface 220 may be considered as the front end of the memory system 210. After receiving each access command, the interface 220 may transmit the command to the memory system controller 215, for example, via the bus 235. In some cases, each command may be added to the command queue 260 by the interface 220 to transmit the command to the memory system controller 215.

[0056] The memory system controller 215 may determine that an access command has been received based on a communication from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving a command from the command queue 260. The command may be removed from the command queue after, for example, the command has been retrieved from the command queue by the memory system controller 215. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260, for example, via the bus 235.

[0057] Upon determining that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transmitting the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0058] In either case, the memory system controller 215 may use the buffer 225 for, among other things, temporary storage of data received from or sent to the host system 205. The buffer 225 may be considered the middle of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0059] To process a write command received from the host system 205, the memory system controller 215 may first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, e.g., via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the write command.

[0060] In some cases, the buffer queue 265 may be used to control a command stream associated with data stored in the buffer 225, including write commands. The buffer queue 265 may include access commands associated with data currently stored in the buffer 225. In some cases, commands in the command queue 260 may be moved to the buffer queue 265 by the memory system controller 215 and may remain in the buffer queue 265 while the associated data is stored in the buffer 225. In some cases, each command in the buffer queue 265 may be associated with an address at the buffer 225. That is, a pointer indicating the location in the buffer 225 where the data associated with each command is stored may be maintained. Using the buffer queue 265, multiple access commands may be received sequentially from the host system 205 and at least portions of the access commands may be processed in parallel.

[0061] If the buffer 225 has sufficient space to store the write data, the memory system controller 215 may cause the interface 220 to transmit an indication of availability to the host system 205 (e.g., a "ready to transfer" indication), for example, according to a protocol (e.g., a UFS protocol or an eMMC protocol). When the interface 220 subsequently receives data associated with a write command from the host system 205, the interface 220 may transfer the data to the buffer 225 using the data path 250 for temporary storage. In some cases, the interface 220 may obtain the location of the stored data within the buffer 225 from the buffer 225 or the buffer queue 265. The interface 220 may indicate to the memory system controller 215, for example, via the bus 235, whether the data transfer to the buffer 225 has been completed.

[0062] Once the write data has been stored in the buffer 225 by the interface 220, the data may be transferred out of the buffer 225 and stored in the memory device 240. This may be done using the storage controller 230. For example, the memory system controller 215 may cause the storage controller 230 to retrieve the data from the buffer 225 and transfer the data to the memory device 240 using the data path 250. The storage controller 230 may be considered the back end of the memory system 210. The storage controller 230 may indicate to the memory system controller 215, for example, via the bus 235, that the data transfer to the memory device in the memory device 240 has been completed.

[0063] In some cases, the storage queue 270 may be used to assist in the delivery of write data. For example, the memory system controller 215 may push (e.g., via the bus 235) a write command from the buffer queue 265 to the storage queue 270 for processing. The storage queue 270 may include an entry for each access command. In some examples, the storage queue 270 may additionally include: a buffer pointer (e.g., an address) that may indicate where in the buffer 225 the data associated with the command is stored; and a storage pointer (e.g., an address) that may indicate a location in the memory device 240 associated with the data. In some cases, the storage controller 230 may obtain the location within the buffer 225 from which the data is to be obtained from the buffer 225, the buffer queue 265, or the storage queue 270. The storage controller 230 may manage the location within the memory device 240 where the data is to be stored (e.g., perform wear leveling, garbage collection, etc.). Entries may be added to the storage queue 270, for example, by the memory system controller 215. After the transfer of data is complete, the entry may be removed from the storage queue 270 , for example, by the storage controller 230 or the memory system controller 215 .

[0064] To process a read command received from the host system 205, the memory system controller 215 may also first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, for example, via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the read command.

[0065] In some cases, the buffer queue 265 may be used to assist in buffer storage of data associated with a read command in a manner similar to that discussed above with respect to a write command. For example, if the buffer 225 has sufficient space to store the read data, the memory system controller 215 may cause the memory controller 230 to retrieve the data associated with the read command from the memory device 240 and store the data in the buffer 225 for temporary storage using the data path 250. The memory controller 230 may indicate to the memory system controller 215, for example, via the bus 235, whether the data transfer to the buffer 225 has been completed.

[0066] In some cases, the storage queue 270 may be used to assist in the delivery of read data. For example, the memory system controller 215 may push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 may obtain a location within the memory device 240 from which data is to be retrieved from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 may obtain a location within the buffer 225 from which data is to be stored from the buffer queue 265. In some cases, the storage controller 230 may obtain a location within the buffer 225 from which data is to be stored from the storage queue 270. In some cases, the memory system controller 215 may move the command processed by the storage queue 270 back to the command queue 260.

[0067] Once the data has been stored in the buffer 225 by the storage controller 230, the data may be transferred out of the buffer 225 and sent to the host system 205. For example, the memory system controller 215 may cause the interface 220 to retrieve the data from the buffer 225 using the data path 250 and transmit the data to the host system 205, e.g., according to a protocol (e.g., UFS protocol, eMMC protocol, CXL protocol). For example, the interface 220 may process commands from the command queue 260 and may indicate to the memory system controller 215, e.g., via the bus 235, that the transmission of data to the host system 205 has been completed.

[0068] The memory system controller 215 may execute the received commands according to an order (e.g., a first-in, first-out order according to the order of the command queue 260). For each command, the memory system controller 215 may cause data corresponding to the command to be moved into and out of the buffer 225, as discussed above. The command may remain in the buffer queue 265 while the data is moved into and stored within the buffer 225. If processing of the command has been completed (e.g., if data corresponding to an access command has been transferred from the buffer 225), the command may be removed from the buffer queue 265, such as by the memory system controller 215. If a command is removed from the buffer queue 265, the address that previously stored data associated with the command may be used to store data associated with a new command.

[0069] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue a command indicating one or more LBAs, and the memory system controller 215 may identify the one or more physical block addresses indicated by the LBAs. In some cases, one or more contiguous LBAs may correspond to non-contiguous physical block addresses. In some cases, the storage controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the storage controller 230, and the storage controller 230 may be omitted.

[0070] In some examples, the host system 205 may include a cache that includes one or more pages (e.g., one or more pages for storing data). Each page may include one or more rows, each associated with a certain amount of data. As described herein, the memory system controller 215 may be configured to track the coherence of data shared between the host system 205 and the memory system 210. For example, the memory system controller 215 may track the coherence of data shared between the device memory (not shown) and the host system 205 (not shown). For example, one or more of the memory devices 240 may be CXL devices configured to access data stored in various device-accessible memories (e.g., device memories). The memory system controller 215 may track the coherence of the data, which may involve one of three states indicating whether there is no coherent copy of the data at the host system 205 and the memory system 210 or whether there is a shared, exclusive, or modified copy of the data.

[0071] The memory system 210 may be an example of a CXL device that may be configured to access a device memory (memory device 240). For example, the CXL device may include a processing device (not shown) configured to access the device memory according to a host bias mode or a device bias mode. When operating according to the device bias mode, the memory system controller 215 may access the device memory independently of the host system 205 (e.g., after receiving an access request or access command). Conversely, when operating according to the host bias mode, the memory system controller 215 may access the device memory via the host system 205. Thus, when operating according to the host bias mode, the host system 205 may be configured to access the device memory for the corresponding CXL device.

[0072] In some examples, each row of data stored to the device memory may be associated with an optional 2-bit Meta0 field. As described herein, the 2-bit Meta0 field may be used to indicate the bias state of the associated data based on the three coherent states. For example, when the data is associated with a first coherent state (e.g., an "invalid" state; when there is no coherent copy of the data), the Meta0 field may indicate operation according to a device bias mode. Additionally or alternatively, when the data is associated with a second coherent state (e.g., an "any" state; when there is a coherent copy of the data) or a third coherent state (e.g., a "shared" state; when there is a coherent copy of the data), the Meta0 field may indicate operation according to a host bias mode. Therefore, tracking device bias using the Meta0-state can allow bias states to be tracked with greater granularity.

[0073] Figure 3 An example of a system 300 that supports bias control of a memory device according to examples as disclosed herein is shown. The system 300 may include a memory system 305 and a host device 310. The memory system 305 may be coupled to the host device 310 via an interface 315, which may be a CXL interface. The memory system 305 may include a device memory 320, a cache 325, a controller 330, and a processing unit 335, and the host device 310 may include a cache 340. In some examples, the system 300 may be configured to track the coherence state of the data using one or more metadata fields (e.g., Meta0-state). Furthermore, utilizing the Meta0-state to track the bias state on a per-cache line basis may improve the overall performance of the memory system 305 while maintaining a relatively simple programming model.

[0074] Memory system 305 may be a CXL device. Device memory 320 may be accessed by one or more accelerators that include or may be associated with processing unit 335 . Figure 3330 may be a single logic component formed on the same field programmable gate array (FPGA) or application specific integrated circuit (ASIC). However, in some examples, the controller 330 and the processing unit 335 may be separate components. For example, the processing unit 335 may be associated with a graphics processing unit (GPU) or a general purpose graphics processing unit (GPGPU) of the memory system 305. The processing unit 335 may be configured to transmit signaling and / or commands for accessing the device memory 320 to the controller 330. As described herein, the controller 330 may access the device memory 320 independently of the host device 310 in the device bias state, and the controller 330 may access the device memory 320 via the host device 310 in the host bias state.

[0075] In some examples, the host device 310 may include a cache 340. The cache 340 may include a collection of pages, each of which may include 4kB of data. In addition, each page may include one or more blocks, which may be referred to as cache lines, and each cache line may include 64B of data. Although the size of each page and cache line is intended for exemplary purposes only, and each page and cache line may be configured to store different amounts of data, the memory system 305 may be configured to track the bias state using a Meta0-state on a per-cache line basis rather than a bias table maintained on a page basis. That is, tracking device bias using a Meta0-state may allow tracking bias states at a greater granularity.

[0076] Device memory 320 may be configured to store data that is accessible by processing unit 335 (e.g., via controller 330) and host device 310. Because data is accessible by both processing unit 335 and host device 310 (e.g., data is shared), it is desirable to track the coherence of the data. That is, it is desirable for both processing unit 335 and host device 310 to know whether data in cache 340 is coherent with corresponding data (for the same address) in device memory 320. In order to track cache coherence, three states of cache coherence may be maintained and tracked using metadata. For example, a first state may be associated with an "invalid" state - e.g., cache 340 of host device 310 does not have a cacheable copy of the data. A second state may be associated with an "any" state - e.g., cache 340 of host device 310 may have a shared, exclusive, or modified copy of the data. A third state may be associated with a "shared" state - e.g., cache 340 of host device 310 may have at most a shared copy of the data. As the coherence state of the data changes, updated metadata associated with the coherence state may be stored to the device memory 320 .

[0077] In some examples, data stored to the device memory 320 may be accessed according to a device bias mode or a host bias mode. The host bias mode may prioritize coherent accesses from the host device 310 to the device memory 320. The host bias mode may be used during work submission (when data is being written to the device memory 320 from the host device 310) and during work completion (when data is being read from the device memory 320 by the host device 310). In the host bias mode, the device memory 320 may appear to the memory system (or to the processing unit 335) as if it were a memory attached to the host device 310. If the processing unit 335 needs to access the device memory 320 while operating in the host bias mode, the access operation is handled by the controller 330 first transmitting a request (e.g., command; signaling) to the host device 310.

[0078] In contrast, in the device bias mode, the processing unit 335 may directly access the device memory 320. That is, the processing unit 335 may access the device memory 320 without any interaction of the host device 310. Thus, if the processing unit 335 needs to access the device memory 320 while operating in the device bias mode, the access operation may be handled by the controller 330 directly accessing the device memory 320.

[0079] The CXL specification provides an optional 2-bit Meta0 field that can be associated with a device-attached medium. According to various aspects described herein, the 2-bit Meta0 field can be used to deliver a coherence state of data (e.g., data associated with the size of a cache line of cache 340), and the coherence state can be used to determine a bias state of the associated data. In some instances, the Meta0 field can be configured to store a first value (e.g., a first bit value) associated with an "invalid" coherence state. When the Meta0 field contains the first value, the data associated with the Meta0 field can be accessed according to a device bias mode. Additionally or alternatively, the Meta0 field can be configured to store a second value (e.g., a second bit value) and a third value (e.g., a third bit value) associated with "shared" and "any" states. When the Meta0 field contains the second value or the third value, the data associated with the Meta0 field can be accessed according to a host bias mode.

[0080] In some examples, a corresponding Meta0 field may be associated with each row of data stored to device memory 320, and thus may be determined when processing unit 335 needs to access device memory 320. For example, processing unit 335 may transmit an access request (e.g., command; signaling) to controller 330, and the controller may determine the Meta0 value of the associated data. Depending on the Meta0 value (e.g., coherence state), controller 330 may be able to directly access the row of data (e.g., according to the device bias mode), or may transmit a request (e.g., command; signaling) to host device 310 for resolving the coherence associated with the data (e.g., according to the host bias mode).

[0081] The host device 310 may periodically update the coherence state of the data and / or the Meta0 field associated with the data. For example, if the host device 310 performs any operation that affects the coherence of the data, the host device 310 may communicate the changes to the memory system 305. In some examples, the host device 310 may communicate the updated coherence state to the memory system 305 (e.g., explicitly or implicitly from an access command), and the controller 330 may use the updated coherence state to update the Meta0 field of the associated data stored to the device memory 320 or cache 325. In other examples, the host device 310 may communicate the updated Meta0 field to the memory system 305, and the controller 330 may update the Meta0 field of the associated data stored to the device memory 320 or cache 325.

[0082] Additionally or alternatively, the cache 325 may be used to determine whether to access data based on a device bias state or a host bias state. For example, data and an associated Meta0 field may be stored in the cache 325. That is, in some instances, the Meta0 field may be stored only with cached data, not data stored in the device memory 320. When the processing unit 335 needs to access data (e.g., when the processing unit 335 transmits a command for data to the controller 330), the controller 330 may determine whether the data is stored in the cache 325. If the data is stored in the cache (e.g., when there is a cache "hit"), the data may be accessed based on the coherence state indicated by the Meta0 field (e.g., by associating the coherence state with the bias state). In other instances, if the data is not stored in the cache (e.g., when there is a cache "miss"), the controller 330 may consider the data to be associated with the host bias state. Accordingly, when there is a cache "miss," the processing unit 335 may access the device memory 320 via the host device 310. Regardless of whether the Meta0 field is stored to the device memory 320 or to the cache 325, utilizing the Meta0-state to track the bias state on a per-cache line basis may improve the overall performance of the memory system 305 while maintaining a relatively simple programming model.

[0083] Figure 4 An example of a process flow diagram 400 is shown to support bias control of a memory device according to examples as disclosed herein. The process flow diagram 400 may illustrate the operation of a processing unit 405, a controller 410, a device memory 415, and a cache 420. In some examples, the processing unit 405, the controller 410, the device memory 415, and the cache 420 may be respectively Figure 3 An example of a processing unit 335, a controller 330, a device memory 320, and a cache 325 of a memory system 305 is depicted. Process flow diagram 400 may illustrate utilizing Meta0-state to track bias states on a per-cache line basis, which may improve overall performance of the memory system 305 while maintaining a relatively simple programming model.

[0084] At 425, the coherence state of the data row may be stored at the device memory 415. In some instances, the coherence state of multiple data rows may be stored. For example, the coherence state of each data row may be stored to the device memory 415. As described herein, the coherence state may correspond to an "invalid," "any," or "shared" state, and may be stored in a Meta0 field associated with the corresponding data row. In other instances, at 425, the coherence state of the data may be updated. That is, the coherence state of one or more data rows may have been previously stored to the device memory 415, but due to a change in the coherence state, the stored state may be updated. In either example, the coherence state stored at 425 may be used to determine a bias state associated with the data. Although shown as being stored at the device memory 415, the coherence state may be stored additionally or alternatively at the cache 420, as described below.

[0085] At 430, processing unit 405 may determine to access the row of data. For example, processing unit 405 may determine to read the row of data from device memory 415, or may determine to write the row of data to device memory 415. For exemplary purposes, the row of data may be stored at device memory 415. However, in some examples, the row of data may be stored to cache 420 (e.g., the data may be cached), and processing unit 405 or controller 410 may determine whether the data is stored to cache 420 or device memory 415.

[0086] At 435, the processing unit 405 may transmit signaling to the controller 410. The signaling may be in response to determining to access the row of data (e.g., at 425), and the signaling may include a command (e.g., a read command, a write command), a request, or another type of communication. The signaling may indicate to the controller 410 the type of access operation and the address of the device memory 415 for the row of data (e.g., a memory address).

[0087] At 440, the controller 410 may transmit signaling to the cache 420. The signaling may indicate the type of access operation and the address of the device memory 415 (e.g., at 435) in response to the signaling, and the signaling may include a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on the cache 420 to determine whether the associated line of data is stored to the cache 420.

[0088] At 445, controller 410 may receive signaling from cache 420. The signaling may be in response to the signaling transmitted at 440 and may indicate whether the line of data is stored to the cache (e.g., a cache "hit" or a cache "miss"). For exemplary purposes only, the signaling may indicate a cache "miss".

[0089] At 450, the controller 410 may transmit signaling to the device memory 415. The signaling may indicate a cache "miss" in response to the signaling, and the signaling may include a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on the device memory 415.

[0090] At 455, the controller 410 may receive signaling from the device memory 415. The signaling may be in response to the signaling transmitted at 450, and may include a row of data read from the device memory 415. In addition, the signaling may include a Meta0 state associated with the row of data. As described herein, the Meta0 state may indicate a first value corresponding to an "invalid" coherence state, a second value corresponding to a "shared" coherence state, or a third value corresponding to an "any" state. Alternatively, the Meta0 state may not be stored in the device memory 415, and the controller 410 may present a Meta0 state of "any" or "shared" after a cache miss occurs.

[0091] At 460, the controller 410 may determine the bias state of the row of data read from the device memory 415. The controller 410 may determine the bias state of the row of data in response to signaling received by the controller 410 (e.g., at 455). For example, the signaling may have indicated that the Meta0 field includes a first value corresponding to an "invalid" coherence state. Thus, the controller 410 may determine the device bias state of the row of data stored to the first memory address, and may complete processing of the access operation without any interaction from the host device.

[0092] In other examples, signaling (e.g., at 435) may indicate a write command at a second memory address of the device memory 415. In such examples, the controller 410 may determine a bias state for writing data to the second memory address based on the Meta0 field associated with the data row. For example, the controller 410 may transmit signaling to the device memory 415 to read the data row corresponding to the second memory address from the device memory 415. In response, the controller 410 may receive signaling indicating the Meta0 state of the data row. If the Meta0 state corresponds to an "invalid" coherent state, the controller 410 may operate according to the device bias. In this example, the controller 410 may write data to the second memory address of the device memory 415 without any interaction from the host device.

[0093] In other examples, the controller 410 may not transmit signaling to the cache 420 and / or the device memory 415, but may instead maintain a table for tracking the Meta0 status of one or more rows of data. For example, for both read operations or write operations, the controller 410 may track the Meta0 value on a per-row basis, so that when the processing unit determines to access data (e.g., at 430), the controller may determine the Meta0 status based on the table. Accordingly, based on the Meta0 status, the controller 410 may operate in a device bias mode or a host bias mode.

[0094] At 465, the data may be transmitted to the processing unit 405. In some examples, the data may be transmitted in response to determining the bias state of the data (e.g., at 450). In some examples, the data may be transmitted directly to the processing unit 405, while in other examples, the data may be transmitted to the controller 410, and the controller 410 may transmit the data to the processing unit 405.

[0095] At 470, the processing unit 405 may determine to access a row of data (e.g., another row of data). For example, the processing unit 405 may determine to read a row of data stored to the cache 420 (e.g., a cached row of data). For exemplary purposes, the row of data may be stored at the cache 420. However, in some instances, the row of data may not be stored to the cache 420 (e.g., the data may not be cached), thereby generating a cache "miss". When a cache "miss" occurs, the controller 410 may determine to access the data according to the host bias mode.

[0096] At 475, the processing unit 405 may transmit signaling to the controller 410. The signaling may be in response to determining to access the row of data (e.g., at 465), and the signaling may include a command (e.g., a read command, a write command), a request, or another type of communication. The signaling may indicate to the controller 410 the type of access operation and the address of the device memory 415 (e.g., a memory address).

[0097] At 480, the controller 410 may transmit signaling to the cache 420. The signaling may indicate the type of access operation and the address of the device memory 415 (e.g., at 475) in response to the signaling, and the signaling may include a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on the cache 420 to determine whether the associated line of data is stored to the cache 420.

[0098] At 485, the controller 410 may receive signaling from the cache 420. The signaling may be in response to the signaling transmitted at 440 and may indicate whether the line of data is stored to the cache (e.g., a cache "hit" or a cache "miss"). For exemplary purposes only, the signaling may indicate a cache "hit". Accordingly, the signaling may include the line of data and an associated Meta0 state, which may indicate a first value corresponding to an "invalid" coherence state, a second value corresponding to a "shared" coherence state, or a third value corresponding to an "any" state.

[0099] At 490, the controller 410 may determine a bias state for the row of data read from the cache 420. The controller 410 may determine the bias state for the row of data in response to signaling (e.g., at 485) received by the controller 410. For example, the signaling may have indicated that the Meta0 field includes a first value corresponding to an "invalid" coherence state. Thus, the controller 410 may determine the device bias state for the row of data stored to the cache, and may complete processing of the access operation without any interaction from the host device.

[0100] At 495, the data may be transferred to the processing unit 405. In some examples, the data may be transferred in response to signaling (e.g., at 475) transmitted from the controller 410 to the processing unit. In some examples, the data may be transferred directly to the processing unit 405, while in other examples, the data may be transferred to the controller 410 and the controller 410 may transfer the data to the processing unit 405. Whether the Meta0 field is stored to the device memory 415, stored to the cache 420, or tracked by the controller 410, utilizing the Meta0-state to track the bias state on a per-cache line basis may improve the overall performance of the memory system while maintaining a relatively simple programming model.

[0101] Figure 5 An example of a process flow diagram 500 for supporting bias control of a memory device according to an example disclosed herein is shown. The process flow diagram 500 may be shown as shown in FIG. Figure 3 Operation of memory system 501 and host device 525 of the example of memory system 305 and host device 310 described. Memory system 501 may include processing unit 505, controller 510, device memory 515, and cache 520. Process flow diagram 500 may illustrate utilizing Meta0-state to track bias states on a per-cache line basis, which may improve overall performance of memory system 501 while maintaining a relatively simple programming model.

[0102] At 530, the coherence state of the data row may be stored at the device memory 515. In some instances, the coherence state of multiple data may be stored. For example, the coherence state of each data row may be stored to the device memory 515. As described herein, the coherence state may correspond to an "invalid," "any," or "shared" state, and may be stored in the Meta0 field associated with the corresponding data row. In other instances, at 530, the coherence state of the data may be updated. That is, the coherence state of one or more data rows may have been previously stored to the device memory 415, but due to a change in the coherence state, the stored state may be updated. In either example, the coherence state stored at 530 may be used to determine a bias state associated with the data.

[0103] At 535, processing unit 505 may determine to access the row of data. For example, processing unit 505 may determine to read the row of data from device memory 515, or may determine to write the row of data to device memory 515. For exemplary purposes, the row of data may be stored at device memory 515. However, in some examples, the row of data may be stored to cache 520 (e.g., the data may be cached), and processing unit 505 or controller 510 may determine whether the data is stored to cache 520 or device memory 515.

[0104] At 540, the processing unit 505 may transmit signaling to the controller 510. The signaling may be in response to determining to access the row of data (e.g., at 535), and the signaling may include a command (e.g., a read command, a write command), a request, or another type of communication. The signaling may indicate to the controller 510 the type of access operation and the address of the device memory 515 (e.g., a memory address).

[0105] After 540, controller 510 may transmit signaling to cache 520, which is not Figure 5 540. The signaling may indicate the type of access operation and the address of the device memory 515 (e.g., at 540) in response to the signaling, and the signaling may include a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on the cache 520 to determine whether the associated data line is stored to the cache 520.

[0106] After transmitting the signaling to the cache 520, the controller 510 may receive the signaling from the cache 520, which is not in Figure 5 . The signaling may indicate whether the line of data is stored to the cache (e.g., a cache "hit" or a cache "miss"). For exemplary purposes only, this signaling indicates a cache "miss". In some examples, after a cache "miss", the controller 510 may then be presented as operating in the host bias mode.

[0107] After the controller 510 receives the signaling, the controller 510 may transmit the signaling to the device memory 515, which is not in Figure 5 The signaling may indicate a cache "miss" in response to the signaling, and the signaling may include a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on the device memory 515.

[0108] After transmitting the signaling to the device memory 515, the controller 510 may receive the signaling from the device memory 515, which is not in Figure 5 . The signaling may include a data row read from the device memory 515. In addition, the signaling may include a Meta0 state associated with the data row. As described herein, the Meta0 state may indicate a first value corresponding to an "invalid" coherence state, a second value corresponding to a "shared" coherence state, or a third value corresponding to an "any" state.

[0109] At 545, the controller 510 may determine a bias state for a row of data stored to the device memory 515 in response to receiving the row of data and the associated Meta0 state. The controller 510 may determine the bias state based on the Meta0 state. For example, the Meta0 field may indicate a first value corresponding to an "invalid" coherence state and generate a device bias for the row of data. Additionally or alternatively, the Meta0 field may indicate a second value corresponding to a "shared" state or a third value corresponding to an "any" state, both of which generate a host bias for the row of data. For exemplary purposes only, the controller 510 may determine a host bias state for a row of data stored to a first memory address.

[0110] At 550, the controller 510 may transmit signaling to the host device 525. The signaling may be in response to determining to access the device memory 415 according to the host bias mode (e.g., at 545), and the signaling may include a command (e.g., a read command), a request, or another type of communication. For example, the signaling may include a request for the host device 525 to resolve the coherency of a row of data, or may include a request for the host device 525 to grant access to the row of data to the controller 510.

[0111] At 555, the host device 525 may transmit signaling to the controller 510 (or to another component of the memory system 501). The signaling may be in response to the signaling transmitted to the host device 525 (e.g., at 550), and the signaling may include a command (e.g., a second command, a read command), a request, or another type of communication. For example, the second command may resolve the coherency of the data by granting the controller 510 direct access to the row of data.

[0112] In other examples, signaling (e.g., at 540) may indicate a write command at a second memory address of the device memory 515. In such examples, the controller 510 may determine a bias state for writing data to the second memory address based on the Meta0 field associated with the data row. For example, the controller 510 may transmit signaling to the device memory 515 to read the data row corresponding to the second memory address from the device memory 515. In response, the controller 510 may receive signaling indicating the Meta0 state of the data row. If the Meta0 state corresponds to an "invalid" coherent state, the controller 510 may operate according to the device bias. In this example, the controller 510 may write data to the second memory address of the device memory 515 without any interaction from the host device.

[0113] In other examples, the controller 510 may not transmit signaling to the cache 520 and / or the device memory 515, but may instead maintain a table for tracking the Meta0 status of one or more rows of data. For example, for both read operations or write operations, the controller 510 may track the Meta0 value on a per-row basis, so that when the processing unit determines to access data (e.g., at 530), the controller may determine the Meta0 status based on the table. Accordingly, based on the Meta0 status, the controller 410 may operate in a device bias mode or a host bias mode.

[0114] At 560, the data may be transferred to the processing unit 505. In some examples, the data may be transferred in response to signaling (e.g., at 555) transmitted from the host device 525 to the controller 510. In some examples, the data may be transferred directly to the processing unit 505, while in other examples, the data may be transferred to the controller 510, and the controller 510 may transfer the data to the processing unit 505.

[0115] At 565, the processing unit 505 may determine to access a row of data (e.g., another row of data). For example, the processing unit 505 may determine to read a row of data that may be stored in the cache 520 (e.g., a cached row of data). For exemplary purposes, the row of data may not be stored at the cache 520. However, in some examples, the row of data may be stored in the cache 520 (e.g., the data may be cached), thereby generating a cache "hit". When a cache "hit" occurs, the controller 510 may determine to access the data based on a coherent state (e.g., Meta0 field) associated with the row of data.

[0116] At 570, the processing unit 505 may transmit signaling to the controller 510. The signaling may be in response to determining to access the row of data (e.g., at 565), and the signaling may include a command (e.g., a read command, a write command), a request, or another type of communication. The signaling may indicate to the controller 510 the type of access operation and the address of the device memory 515 (e.g., a memory address).

[0117] After 570, controller 510 may transmit signaling to cache 520, which is not Figure 5 540. The signaling may indicate the type of access operation and the address of the device memory 515 (e.g., at 540) in response to the signaling, and the signaling may include a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on the cache 520 to determine whether the associated data line is stored to the cache 520.

[0118] After transmitting the signaling to the cache 520, the controller 510 may receive the signaling from the cache 520, which is not in Figure 5 520 . The signaling may indicate whether the data line is stored to the cache (e.g., a cache "hit" or a cache "miss"). For exemplary purposes only, this signaling indicates a cache "hit". In addition, the signaling may include the data line read from the cache 520, and may include a Meta0 state associated with the data line. As described herein, the Meta0 state may indicate a first value corresponding to an "invalid" coherence state, a second value corresponding to a "shared" coherence state, or a third value corresponding to an "any" state.

[0119] At 575, the controller 510 may determine a bias state for a row of data stored in the device memory 520 in response to receiving the row of data and the associated Meta0 state. The controller 510 may determine the bias state based on the Meta0 state. For example, the Meta0 field may indicate a first value corresponding to an "invalid" coherence state and generate a device bias for the row of data. Additionally or alternatively, the Meta0 field may indicate a second value corresponding to a "shared" state or a third value corresponding to an "any" state, both of which generate a host bias for the row of data. For exemplary purposes only, the controller 510 may determine a host bias state for a row of data stored in the cache 520.

[0120] At 580, the controller 510 may transmit signaling to the host device 525. The signaling may be in response to determining to access the cache 520 according to the host bias mode (e.g., at 575), and the signaling may include a command (e.g., a read command), a request, or another type of communication. For example, the signaling may include a request for the host device 525 to resolve the coherency of a row of data, or may include a request for the host device 525 to grant access to the row of data to the controller 510.

[0121] At 585, the host device 525 may transmit signaling to the controller 510 (or to another component of the memory system 501). The signaling may be in response to the signaling transmitted to the host device 525 (e.g., at 580), and the signaling may include a command (e.g., a second command, a read command), a request, or another type of communication. For example, the second command may resolve the coherency of the data by granting the controller 510 direct access to the row of data.

[0122] At 590, the data may be transferred to the processing unit 505. In some examples, the data may be transferred directly to the processing unit 505, while in other examples, the data may be transferred to the controller 510, and the controller 510 may transfer the data to the processing unit 505. Whether the Meta0 field is stored to the device memory 515, stored to the cache 520, or tracked by the controller 510, utilizing the Meta0-state to track the bias state on a per-cache line basis may improve the overall performance of the memory system while maintaining a relatively simple programming model.

[0123] Figure 6 A block diagram 600 is shown of a memory controller 620 that supports bias control of a memory device according to examples as disclosed herein. The memory controller 620 may be as described in reference Figures 1 to 5 6. The memory controller 620 or its various components may be examples of means for performing various aspects of bias control of a memory device as described herein. For example, the memory controller 620 may include a coherence component 625, a memory access component 630, a transmission component 635, a reception component 640, a determination component 645, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0124] Coherence component 625 may be configured as or otherwise support means for storing a coherence state of a data set stored in memory relative to a cache of a host device. In some examples, coherence component 625 may be configured as or otherwise support means for storing a coherence state of a data set stored in memory relative to a cache of a host device.

[0125] The memory access component 630 may be configured as or otherwise support a component for accessing a memory based at least in part on identifying a command to perform an access operation on a data set stored in the memory according to a bias state of a data set determined at least in part based on a stored coherence state of the data set, wherein the bias state is associated with control of access to the data set by a controller associated with the memory.

[0126] In some examples, the memory access component 630 can be configured or otherwise support means for accessing the memory independently of the host device based at least in part on the bias state. In some examples, the command includes a read command, and the memory access component 630 can be configured or otherwise support means for accessing a data set stored in a cache based at least in part on determining that the data set is stored in a cache associated with the memory.

[0127] In some examples, the memory access component 630 can be configured to or otherwise support means for accessing the memory according to a bias state of the data set determined at least in part based on a stored coherence state of the data set based at least in part on identifying a command to perform an access operation of the data set stored in the memory, wherein the bias state is associated with control of access to the data set by the host device. In some examples, the command includes a read command, and the memory access component 630 can be configured to or otherwise support means for accessing the memory for the data set based at least in part on receiving a second command from the host device.

[0128] In some examples, the coherence state of the data set is stored independently of the command, and the transmitting component 635 can be configured as or otherwise support means for transmitting to the host device an indication of an access operation to be performed on the data set based at least in part on determining to process the command according to the bias state. In some examples, the transmitting component 635 can be configured as or otherwise support means for transmitting to the memory a data set received from the host device based at least in part on receiving the data set from the host device.

[0129] In some examples, the coherence state of the data set is stored independently of the command, and the receiving component 640 can be configured to or otherwise support means for receiving a second command from the host device indicating direct access to the data set for the access operation based at least in part on transmitting an indication of the access operation.

[0130] In some examples, the command includes a read command, and the determining component 645 can be configured as or otherwise support means for determining that the data set is stored to a cache associated with the memory.

[0131] In some instances, the memory is configured to store a first value associated with a first coherence state of the data set, a second value associated with a second coherence state of the data set, or a third value associated with a third coherence state of the data set. In some instances, the first value indicates that the data set is incoherent. In some instances, the second value and the third value indicate that the data set is coherent, wherein the controller is configured to process the command according to the bias state based at least in part on the memory storing the first value of the data set.

[0132] In some instances, the data set is associated with a first quantity of data. In some instances, a cache line of a host device coupled to the memory is configured to store the first quantity of data. In some instances, the bias state corresponds to the first bias state. In some instances, the second bias state is associated with control of access to the data set by the host device. In some instances, the memory is configured to store a first value associated with a first coherence state of the data set, a second value associated with a second coherence state of the data set, or a third value associated with a third coherence state of the data set.

[0133] In some instances, the first value indicates that an invalid version of the data set is stored in a cache of the host device. In some instances, the second value indicates that a shared version or an exclusive version of the data set is stored in a cache of the host device. In some instances, the third value indicates that a shared version of the data set is stored in a cache of the host device. In some instances, the second value and the third value indicate that the data set is coherent. In some instances, the command is processed according to a bias state based at least in part on the second value or the third value of the memory storing the data set.

[0134] In some instances, the data set is associated with a first amount of data. In some instances, a cache line of a host device coupled to the memory is configured to store the first amount of data. In some instances, the first bias state is associated with control of access to the data set by the controller. In some instances, the bias state corresponds to a second bias state.

[0135] Figure 7 A flow chart is shown illustrating a method 700 for supporting bias control of a memory device according to examples as disclosed herein. The operations of the method 700 may be implemented by a memory controller or components thereof as described herein. For example, the operations of the method 700 may be implemented by a memory controller or components thereof as described herein. Figures 1 to 5 The memory controller described in and 6 performs. In some examples, the memory controller may execute instruction sets to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory controller may use dedicated hardware to perform aspects of the described functions.

[0136] At 705, the method may include storing a coherence state of a data set stored in memory relative to a cache of a host device. The operations of 705 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 705 may be described with reference to Figure 6 The described coherent components 625 execute.

[0137] At 710, the method may include accessing the memory based at least in part on identifying a command to perform an access operation of the data set stored in the memory according to a bias state of the data set determined at least in part based on a stored coherence state of the data set, wherein the bias state is associated with control of access to the data set by a controller associated with the memory. The operations of 710 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 710 may be performed as described in reference to Figure 6 The memory access component 630 is described as performing.

[0138] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for storing a coherence state of a data set stored in a memory relative to a cache of a host device, and accessing the memory according to a bias state of the data set determined based at least in part on the stored coherence state of the data set based at least in part on identifying a command to perform an access operation of the data set stored in the memory, wherein the bias state is associated with control of access to the data set by a controller associated with the memory.

[0139] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for accessing a memory independent of a host device based at least in part on a bias state.

[0140] In some instances of the method 700 and apparatus described herein, the command includes a read command, and the method, apparatus, and non-transitory computer-readable medium may include additional operations, features, circuit systems, logic, components, or instructions for determining that a data set can be stored in a cache associated with a memory, and accessing a data set stored in a cache based at least in part on determining that the data set can be stored in a cache associated with the memory.

[0141] In some instances of the method 700 and devices described herein, the memory may be configured to store a first value associated with a first coherence state of a data set, a second value associated with a second coherence state of the data set, or a third value associated with a third coherence state of the data set.

[0142] In some examples of the method 700 and apparatus described herein, the first value indicates that the data set may be incoherent and the second and third values ​​indicate that the data set may be coherent, wherein the controller may be configured to process the command according to a bias state based at least in part on the first value of the memory storing the data set.

[0143] In some examples of the methods 700 and apparatus described herein, a data set may be associated with a first amount of data, and a cache line of a host device coupled to the memory may be configured to store the first amount of data.

[0144] In some examples of the methods 700 and apparatus described herein, the bias state corresponds to a first bias state, and the second bias state may be associated with control of access to the data set by the host device.

[0145] Figure 8 A flow chart is shown illustrating a method 800 for supporting bias control of a memory device according to examples as disclosed herein. The operations of the method 800 may be implemented by a memory controller or components thereof as described herein. For example, the operations of the method 800 may be implemented by a memory controller or components thereof as described herein. Figures 1 to 5 The memory controller described in and 6 performs. In some examples, the memory controller may execute instruction sets to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory controller may use dedicated hardware to perform aspects of the described functions.

[0146] At 805, the method may include storing a coherence state of a data set stored in memory relative to a cache of a host device. The operations of 805 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 805 may be described with reference to Figure 6 The described coherent components 625 execute.

[0147] At 810, the method may include accessing the memory based at least in part on identifying a command to perform an access operation of the data set stored in the memory according to a bias state of the data set determined at least in part based on a stored coherence state of the data set, wherein the bias state is associated with control of access to the data set by a host device. The operations of 810 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 810 may be performed as described in reference to Figure 6 The memory access component 630 is described as performing.

[0148] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for storing a coherence state of a data set stored in a memory relative to a cache of a host device, and accessing the memory according to a bias state of the data set determined based at least in part on the stored coherence state of the data set based at least in part on identifying a command to perform an access operation of the data set stored in the memory, wherein the bias state is associated with control of access to the data set by the host device.

[0149] In some examples of the method 800 and apparatus described herein, a coherence state of a data set may be stored independently of a command, and the method, apparatus, and non-transitory computer-readable medium may include additional operations, features, circuit systems, logic, components, or instructions for transmitting to a host device an indication of an access operation to be performed on the data set based at least in part on determining to process the command according to a bias state, and receiving from the host device a second command indicating direct access to the data set for the access operation based at least in part on transmitting the indication of the access operation.

[0150] In some examples of the method 800 and apparatus described herein, the command includes a read command, and the method, apparatus, and non-transitory computer-readable medium may include additional operations, features, circuit systems, logic, components, or instructions for accessing memory for a data set based at least in part on receiving a second command from a host device.

[0151] Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for transmitting a data set received from a host device to a memory based at least in part on receiving the data set from the host device.

[0152] In some instances of the method 800 and devices described herein, the memory may be configured to store a first value associated with a first coherence state of a data set, a second value associated with a second coherence state of the data set, or a third value associated with a third coherence state of the data set.

[0153] In some instances of the method 800 and apparatus described herein, a first value indicates that an invalid version of a data set may be stored in a cache of a host device, a second value indicates that a shared version or an exclusive version of a data set may be stored in a cache of a host device, and a third value indicates that a shared version of a data set may be stored in a cache of a host device.

[0154] In some examples of the method 800 and apparatus described herein, the second and third values ​​indicate that the data sets may be coherent, and the command may be processed according to the bias state based at least in part on the second or third value of the memory storage data set.

[0155] In some examples of the method 800 and apparatus described herein, a data set may be associated with a first amount of data, and a cache line of a host device coupled to the memory may be configured to store the first amount of data.

[0156] In some examples of the methods 800 and apparatus described herein, a first bias state may be associated with controlling access to a data set by a controller and the bias state corresponds to a second bias state.

[0157] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. In addition, two or more parts from the methods described may be combined.

[0158] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths.

[0159] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device that includes the connected components, the conductive path between the components that are in electronic communication (or conductive contact or connected or coupled) with each other may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0160] The term "coupled" refers to a condition of moving from an open circuit relationship between components, in which signals are currently unable to be transmitted between components via conductive paths, to a closed circuit relationship between components, in which signals are able to be transmitted between components via conductive paths. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0161] The term "isolation" refers to a relationship between components where a signal is currently unable to flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. If a controller isolates two components, the controller implements a change that blocks a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0162] The terms "if", "when", "based on", or "based at least in part on" are used interchangeably. In some instances, the terms "if", "when", "based on", or "based at least in part on" are interchangeable if they are used to describe a conditional action, a conditional process, or a connection between parts of a process.

[0163] The term "responsive to" may refer to one condition or action occurring at least in part (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least in part as a result of the prior condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occur after the first condition or action).

[0164] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, such that no other intermediate conditions or actions occur between an earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between an earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on", "at least partially based on" or "in response to" some other step, action, event or condition execution may be performed additionally or alternatively (e.g., in an alternative instance) "directly in response to" or "directly in response to" this other condition or action.

[0165] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some instances, the substrate is a semiconductor wafer. In some other instances, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping means.

[0166] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components via conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may make the channel conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "disabled".

[0167] The descriptions set forth herein in conjunction with the accompanying drawings describe example configurations and do not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to" other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0168] In the drawings, similar components or features may have the same reference label. In addition, components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0169] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features implementing the functions may also be physically located at various locations, including being distributed so that the various parts of the functions are implemented at different physical locations.

[0170] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0171] As used herein, including in the claims, "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0172] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media may be any available media that can be accessed by a general or special purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage, or any other non-transitory media that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general or special purpose computer or a general or special purpose processor.

[0173] Also, any connection is properly referred to as a computer-readable medium. For example, if the software is transmitted from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio and microwave are included in the definition of medium. As used herein, disk and optical disc include CD, laser disc, optical disc, digital video disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while optical discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0174] The description herein is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to a person skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: Memory; as well as a controller coupled to the memory, wherein the controller is configured to: storing a coherence status of a data set stored in the memory relative to a cache of a host device; and Accessing the memory based at least in part on identifying a command to perform an access operation on the data set stored in the memory according to a first bias state of the data set determined at least in part based on the coherence state of the stored data set, wherein the first bias state is associated with control of access to the data set by the controller, and wherein a second bias state is associated with control of access to the data set by the host device. 2 . The system of claim 1 , wherein the controller is configured to access the memory independently of the host device based at least in part on the first bias state.

3. The system of claim 2, further comprising: a cache associated with the memory, wherein the command comprises a read command, and wherein the controller is configured to: determining storage of the data set to the cache associated with the memory based at least in part on identifying the command; as well as The data set stored to the cache is accessed based at least in part on determining that the data set is stored to the cache.

4. The system of claim 3, wherein the controller is configured to: determining that the second data set is not to be stored to the cache based at least in part on identifying a command to perform an access operation on the second data set; and The memory is accessed according to the second bias state of the second data set based at least in part on a determination that the second data set is not to be stored in the cache.

5. A system according to claim 1, wherein the memory is configured to store a first value associated with a first coherence state of the data set, a second value associated with a second coherence state of the data set, or a third value associated with a third coherence state of the data set.

6. The system of claim 5, wherein: The first value indicates that the data set is irrelevant; and The second value and the third value indicate that the data set is coherent, wherein the controller is configured to process the command according to the first bias state based at least in part on the memory storing the first value of the data set. 7 . The system of claim 1 , wherein the data set is associated with a first amount of data, and wherein a cache line of the host device coupled to the memory is configured to store the first amount of data.

8. A system comprising: Memory; as well as a controller coupled to the memory, wherein the controller is configured to: storing a coherence status of a data set stored in the memory relative to a cache of a host device; and Accessing the memory based at least in part on identifying a command to perform an access operation on the data set stored in the memory according to a second bias state of the data set determined at least in part based on the coherence state of the stored data set, wherein the second bias state is associated with control of access to the data set by the host device, and wherein the first bias state is associated with control of access to the data set by the controller.

9. The system of claim 8, wherein the controller is configured to store the coherence state of the data set independently of the command, wherein the controller is configured to: transmitting to the host device an indication of the access operation to be performed on the data set based at least in part on determining to process the command according to the second bias state; and A second command is received from the host device indicating direct access to the data set for the access operation based at least in part on transmitting the indication of the access operation.

10. The system of claim 9, wherein the controller is configured to: The memory is accessed for the data set based at least in part on receiving the second command from the host device.

11. The system of claim 8, wherein the memory is configured to store a first value associated with a first coherence state of the data set, a second value associated with a second coherence state of the data set, or a third value associated with a third coherence state of the data set.

12. The system of claim 11, wherein: the first value indicating that an invalid version of the data set is stored to the cache of the host device; the second value indicates whether a shared version or an exclusive version of the data set is stored in the cache of the host device; and The third value indicates that the shared version of the data set is stored to the cache of the host device.

13. The system of claim 11, wherein the second value and the third value indicate that the data set is coherent, and wherein the controller is configured to process the command according to the second bias state based at least in part on the memory storing the second value or the third value of the data set.

14. The system of claim 8, wherein the data set is associated with a first amount of data, and wherein a cache line of the host device coupled to the memory is configured to store the first amount of data.

15. A method comprising: storing a coherence status of a data set stored in the memory relative to a cache memory of the host device; as well as Accessing the memory based at least in part on identifying a command to perform an access operation on the data set stored in the memory according to a first bias state of the data set determined at least in part based on the coherence state of the stored data set, wherein the first bias state is associated with control of access to the data set by a controller associated with the memory, and wherein a second bias state is associated with control of access to the data set by the host device.

16. The method according to claim 15, further comprising: The memory is accessed independent of the host device based at least in part on the first bias state.

17. The method of claim 16, wherein the command comprises a read command, the method further comprising: determining that the data set is stored in a cache associated with the memory; as well as The data set stored to the cache is accessed based at least in part on a determination that the data set is stored to the cache associated with the memory.

18. The method of claim 15, wherein the memory is configured to store a first value associated with a first coherence state of the data set, a second value associated with a second coherence state of the data set, or a third value associated with a third coherence state of the data set.

19. The method according to claim 18, wherein: The first value indicates that the data set is irrelevant; and The second value and the third value indicate that the data set is coherent, wherein the controller is configured to process the command according to the first bias state based at least in part on the memory storing the first value of the data set.

20. The method of claim 15, wherein the data set is associated with a first amount of data, and wherein a cache line of the host device coupled to the memory is configured to store the first amount of data.

21. A method comprising: storing a coherence status of a data set stored in the memory relative to a cache memory of the host device; as well as Accessing the memory based at least in part on identifying a command to perform an access operation on the data set stored in the memory according to a second bias state of the data set determined at least in part based on the coherence state of the stored data set, wherein the second bias state is associated with control of access to the data set by the host device, and wherein the first bias state is associated with control of access to the data set by a controller associated with the memory.

22. The method of claim 21 , wherein the coherence state of the data set is stored independently of the command, the method further comprising: transmitting, to the host device, an indication of the access operation to be performed on the data set based at least in part on determining that the command is to be processed according to the second bias state; as well as A second command is received from the host device indicating direct access to the data set for the access operation based at least in part on transmitting the indication of the access operation.

23. The method of claim 22, wherein the command comprises a read command, the method further comprising: The memory is accessed for the data set based at least in part on receiving the second command from the host device.

24. The method of claim 23, further comprising: The data set received from the host device is transmitted to the memory based at least in part on receiving the data set from the host device.

25. The method of claim 21, wherein the memory is configured to store a first value associated with a first coherence state of the data set, a second value associated with a second coherence state of the data set, or a third value associated with a third coherence state of the data set.

26. The method of claim 25, wherein: the first value indicating that an invalid version of the data set is stored to the cache of the host device; the second value indicates whether a shared version or an exclusive version of the data set is stored in the cache of the host device; and The third value indicates that the shared version of the data set is stored to the cache of the host device.

27. The method of claim 25, wherein the second value and the third value indicate that the data set is coherent, and wherein the command is processed according to the second bias state based at least in part on the memory storing the second value or the third value of the data set.

28. The method of claim 21, wherein the data set is associated with a first amount of data, and wherein a cache line of the host device coupled to the memory is configured to store the first amount of data.

29. A non-transitory computer-readable medium storing code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: storing a coherence status of a data set stored in the memory relative to a cache of the host device; and Accessing the memory based at least in part on identifying a command to perform an access operation on the data set stored in the memory according to a first bias state of the data set determined at least in part based on the coherence state of the stored data set, wherein the first bias state is associated with control of access to the data set by a controller associated with the memory, and wherein a second bias state is associated with control of access to the data set by the host device.

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