Silicon carbide semiconductor device and silicon carbide semiconductor substrate

Abstract

In n + On the type starting substrate (21), the first buffer (11), the second buffer (12), and n are sequentially arranged. ‑ Epitaxial growth in the drift region (2). The impurity concentration in the first buffer zone (11) is higher than that in n. ‑ The impurity concentration in the type drift region (2) is high and higher than that in n + The impurity concentration of the initial substrate (21) is low. The impurity concentration of the second buffer (12) is higher than that of the first buffer (11), and it is higher than that of the n-type initial substrate (21). ‑ The gradient change point (41a) on the drift region (2) side increases continuously with a first impurity concentration gradient (41) towards the gradient change point (41b) on the first buffer zone (11) side; decreases continuously with a second impurity concentration gradient (42) from the gradient change point (41a) towards the first interface (27); and decreases continuously with a third impurity concentration gradient (43) from the gradient change point (41b) towards the second interface (26). The second impurity concentration gradient (42) is smaller than the third impurity concentration gradient (43). This improves reliability.

Description

Technical Field

[0001] This invention relates to silicon carbide semiconductor devices and silicon carbide semiconductor substrates. Background Technology

[0002] Previously, in SiC-MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field effect transistors with an insulated gate consisting of a metal-oxide-semiconductor three-layer structure) using silicon carbide (SiC) as the semiconductor material, n-type field effect transistors made of silicon carbide were used. + On the starting substrate of type n - A semiconductor chip is formed by the sequential epitaxial growth of epitaxial layers of the p-type drift region and the p-type base region. Inside the epitaxial layers of the semiconductor chip, basal plane dislocations (BPDs) are generated from the starting substrate during the epitaxial growth process due to transport and / or process damage.

[0003] If the p-type base region formed in the epitaxial layer and the n - When the parasitic diode (body diode) formed by the pn junction in the pn-type drift region turns on, stacking faults grow (expand) in the epitaxial layer, forming a high-resistivity layer that makes it difficult for current to flow, thus increasing the MOSFET's on-state voltage. It is speculated that the stacking faults are caused by the bipolar action of the body diode, which allows current to be injected into the n-type drift region. - Minority carriers (holes) in the type-type drift region recombine with electrons near the BPD, which becomes the starting point of stacking faults. Therefore, by starting the substrate and n - An n-type buffer (epitaxy layer) is configured between the pn-type drift regions to reduce holes reaching the BPD from the pn junction and suppress the growth of stacking faults.

[0004] As with conventional SiC-MOSFETs, devices have been proposed that use a double-layer structure with different impurity concentrations and thicknesses for the buffer layer (see, for example, Patent Documents 1-3 below). In Patent Documents 1-3 below, the n-type buffer layer is configured with a double-layer structure with different impurity concentrations and thicknesses. - Compared to the n-type drift region side + The bilayer structure, with lower impurity concentration and thinner thickness on the initiation substrate side, enables n - n on the drift region side + The impurity concentration of the type buffer (second buffer) and n + The impurity concentration of the type-initiated substrate is approximately the same, which improves the effect of suppressing the growth of stacking faults, and the second buffer and n +The reflected infrared light at the interface between the n-type buffers (first buffers) on the starting substrate side can be used to measure the thickness of the second buffer based on Fourier transform.

[0005] Furthermore, the following patent documents 1 to 3 disclose: n + The impurity concentration of the type-initiated substrate is 1×10 18 / cm 3 Above and 2×10 19 / cm 3 The impurity concentration in the first buffer is n. + The impurity concentration of the initial substrate or the second buffer is less than 1 / 3, preferably 1×10⁻⁶. 17 / cm 3 Above and 1×10 18 / cm 3 The thickness of the first buffer is 0.1 μm or more and 5 μm or less, preferably 1 μm or more, and the impurity concentration of the second buffer is 3 times or more the impurity concentration of the first buffer and is equal to n. + The impurity concentration of the initial substrate is the same, and the thickness of the second buffer is greater than 3 μm. - The impurity concentration in the drift region is lower than that in the first and second buffer zones.

[0006] In addition, as with other conventional silicon carbide semiconductor devices, devices have been proposed that use a stacked structure of two or more layers with different impurity concentrations for the buffer (for example, see Patent Documents 4 and 5 below). In Patent Document 4 below, by making n + The impurity concentration ratio of the first buffer zone on the type-starting substrate side to n + The low impurity concentration of the type-initiating substrate allows for the transfer of impurities from n... + The probability of a BPD propagating from the type-initiated substrate being converted into a threading edge dislocation (TED) in the first buffer is relatively increased. This is achieved by increasing the impurity concentration in the second buffer compared to n. + Type-initiated substrate, first buffer zone and n - The impurity concentration in the n-type drift region is high, thus preventing it from... - New crystal defects are generated within the drift region.

[0007] The following patent document 4 discloses: n + The impurity concentration of the type-initiated substrate is 5×10 17 / cm 3 Above and 1×10 19 / cm 3 Below, the impurity concentration in the first buffer is compared to n. + The impurity concentration of the type-initiated substrate is low and is 5×10.16 / cm 3 Above and 1×10 19 / cm 3 Below, the thickness of the first buffer is 500 nm, and the impurity concentration of the second buffer is greater than n. + The impurity concentration of the type-initiated substrate is high and is 5×10. 18 / cm 3 Above and 2×10 19 / cm 3 The thickness of the second buffer is 1 μm, n - The impurity concentration in the drift region is lower than that in the first buffer zone and is 1×10⁻⁶. 14 / cm 3 Above and 5×10 16 / cm 3 Below, n - The thickness of the drift region is 10 μm.

[0008] Furthermore, in the following patent document 4, by means of n + Between the type starting substrate and the first buffer, between the first buffer and the second buffer, and between the second buffer and n - Buffer zones with continuously varying impurity concentrations along the depth direction are configured between the drift regions to prevent abrupt changes in impurity concentration at each interface, thereby further suppressing the generation of crystal defects. A method is disclosed to... - The configuration between the type drift regions is from the interface between the second buffer and n. - For every 1 μm thickness of the interface between the drift regions, the impurity concentration increases by 2 × 10⁻⁶. 18 / cm 3 The buffer zone is reduced in thickness by approximately 10 μm, thereby adjusting the impurity concentration within the buffer zone to match n. - The interface between the drift regions will not become abrupt.

[0009] In the following patent document 5, by making n + The impurity concentration ratio of the first buffer zone on the type-starting substrate side to n + The low impurity concentration of the type-initiating substrate allows for the transfer of impurities from n... + The probability of BPD propagating from the p-type base region to TED within the first buffer is relatively increased. By making the impurity concentration in the second buffer higher than that in the first buffer, the probability of BPD propagating from the p-type base region to TED is increased. - The depletion layer of the pn junction expansion in the type drift region stops in the second buffer. Additionally, in n... + Between the type-starting substrate and the first buffer zone, an impurity concentration is configured from n +The interface between the type starting substrates is directed toward the interface between the first buffer and the continuous increase of the buffer, at which the BPD is easily converted to TED.

[0010] The following patent document 5 discloses: n + The impurity concentration of the type-initiated substrate is greater than 1×10 18 / cm 3 And it is 1×10 19 / cm 3 Below, the impurity concentration in the first buffer zone is greater than 1×10⁻⁶. 16 / cm 3 And it is 1×10 17 / cm 3 The thickness of the first buffer is several hundred nm, and the impurity concentration of the second buffer is 1 × 10⁻⁶. 17 / cm 3 Above and less than 1×10 19 / cm 3 The thickness of the second buffer zone is 0.5μm to 8μm, n - The impurity concentration in the drift region is 1×10 14 / cm 3 Above and less than 5×10 16 / cm 3 n - The thickness of the drift region is 3μm to 80μm, and the impurity concentration in the first buffer zone is always higher than that in the n-type drift region. + Both the type-initiating substrate and the second buffer have low impurity concentrations, and are lower than n. - The impurity concentration is high in the drift region.

[0011] Existing technical documents

[0012] Patent documents

[0013] Patent Document 1: International Publication No. 2017 / 104751

[0014] Patent Document 2: Japanese Patent No. 6627938

[0015] Patent Document 3: Japanese Patent No. 6729757

[0016] Patent Document 4: Japanese Patent No. 6351874

[0017] Patent Document 5: Japanese Patent No. 6791274 Summary of the Invention

[0018] Technical issues

[0019] However, in conventional silicon carbide semiconductor substrates, by making the second buffer (n - The impurity concentration in the buffer zone on the drift region side is relatively high, thus making the second buffer zone and n - The impurity concentration difference in the drift region increases, therefore, in the second buffer zone and n - Lattice defects are easily generated near the interface between the drift regions, reducing the reliability of the silicon carbide semiconductor substrate. In addition, the higher the impurity concentration in the second buffer, the worse the control over the impurity concentration during epitaxial growth in the second buffer, and the greater the deviation of the impurity concentration in the depth direction in the second buffer. Therefore, the on-state voltage of the silicon carbide semiconductor substrate fluctuates, reducing reliability.

[0020] The purpose of this invention is to eliminate the problems of the prior art described above and to provide a silicon carbide semiconductor device and a silicon carbide semiconductor substrate that can improve reliability.

[0021] Technical solution

[0022] To address the aforementioned issues and achieve the objectives of this invention, the silicon carbide semiconductor device of this invention provides a silicon carbide semiconductor device in which current flows in a direction perpendicular to the main surface of a semiconductor substrate epitaxially grown from a starting substrate made of silicon carbide, and has the following characteristics: A first semiconductor region of a first conductivity type is disposed within the epitaxial layer. A second semiconductor region of the first conductivity type is disposed between the first semiconductor region and the starting substrate within the epitaxial layer, in contact with the starting substrate. The impurity concentration of the second semiconductor region is higher than that of the first semiconductor region and lower than that of the starting substrate. A third semiconductor region of the first conductivity type is disposed between the first semiconductor region and the second semiconductor region within the epitaxial layer, in contact with both the first and second semiconductor regions.

[0023] The impurity concentration in the third semiconductor region is higher than that in the second semiconductor region. The impurity concentration in the third semiconductor region increases continuously with a first impurity concentration gradient from a predetermined first depth position relatively close to the first interface between the third and first semiconductor regions towards a predetermined second depth position relatively close to the second interface between the second and third semiconductor regions, reaching a maximum impurity concentration at the second depth position. The impurity concentration in the third semiconductor region decreases continuously with a second impurity concentration gradient from the first depth position towards the first interface. The impurity concentration in the third semiconductor region decreases continuously with a third impurity concentration gradient from the second depth position towards the second interface. The second impurity concentration gradient is smaller than the third impurity concentration gradient.

[0024] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the absolute value of the first impurity concentration gradient is smaller than the absolute values ​​of the second impurity concentration gradient and the third impurity concentration gradient.

[0025] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the impurity concentration of the third semiconductor region is less than 1 / 2 of the impurity concentration of the starting substrate.

[0026] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-described invention, the impurity concentration of the third semiconductor region is 1.0 × 10⁻⁶. 18 / cm 3 Above and 5.0×10 18 / cm 3 Within the following range.

[0027] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-described invention, the impurity concentration of the third semiconductor region is 3.0 × 10⁻⁶. 18 / cm 3 Within the above range.

[0028] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-described invention, the impurity concentration of the starting substrate is 1.0 × 10⁻⁶. 18 / cm 3 Above and 1.0×10 19 / cm 3 Within the following range.

[0029] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-described invention, the impurity concentration of the second semiconductor region is 0.5 × 10⁻⁶. 18 / cm 3 Above and 1.5×10 18 / cm 3 Within the following range.

[0030] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the thickness of the third semiconductor region is in the range of being thicker than 1 μm and less than 7 μm.

[0031] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the thickness of the second semiconductor region is in the range of more than 1 μm and less than 4 μm.

[0032] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the thickness of the second semiconductor region is 1 μm or less.

[0033] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the thickness of the third semiconductor region is less than 1 μm.

[0034] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the total thickness of the second semiconductor region and the third semiconductor region is in the range of 2 μm or more and 8 μm or less.

[0035] Furthermore, the silicon carbide semiconductor device of the present invention, as described above, includes a fourth semiconductor region of a second conductivity type, a fifth semiconductor region of a first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. The fourth semiconductor region is disposed within the epitaxial layer between a first main surface of the semiconductor substrate and the first semiconductor region. The fifth semiconductor region is selectively disposed within the epitaxial layer between the first main surface of the semiconductor substrate and the fourth semiconductor region. The gate insulating film is configured to contact the region of the fourth semiconductor region between the first semiconductor region and the fifth semiconductor region. The gate electrode is disposed on the opposite side of the fourth semiconductor region, across the gate insulating film. The first electrode is disposed on the first main surface of the semiconductor substrate formed by the epitaxial layer and is electrically connected to the fourth and fifth semiconductor regions. The second electrode is disposed on the second main surface of the semiconductor substrate formed by the starting substrate and is electrically connected to the starting substrate.

[0036] Furthermore, in order to solve the above-mentioned problems and achieve the objective of the present invention, the silicon carbide semiconductor substrate of the present invention is a silicon carbide semiconductor substrate epitaxially grown from a starting substrate made of silicon carbide, and has the following characteristics: A first semiconductor region of a first conductivity type is disposed inside the epitaxial layer. A second semiconductor region of the first conductivity type is disposed between the first semiconductor region and the starting substrate, in contact with the starting substrate, inside the epitaxial layer. The impurity concentration of the second semiconductor region is higher than that of the first semiconductor region, and lower than that of the starting substrate. A third semiconductor region of the first conductivity type is disposed between the first semiconductor region and the second semiconductor region, in contact with both the first semiconductor region and the second semiconductor region, inside the epitaxial layer.

[0037] The impurity concentration in the third semiconductor region is higher than that in the second semiconductor region. The impurity concentration in the third semiconductor region increases continuously with a first impurity concentration gradient from a predetermined first depth position relatively close to the first interface between the third and first semiconductor regions towards a predetermined second depth position relatively close to the second interface between the second and third semiconductor regions, reaching a maximum impurity concentration at the second depth position. The impurity concentration in the third semiconductor region decreases continuously with a second impurity concentration gradient from the first depth position towards the first interface. The impurity concentration in the third semiconductor region decreases continuously with a third impurity concentration gradient from the second depth position towards the second interface. The second impurity concentration gradient is smaller than the third impurity concentration gradient.

[0038] According to the invention described above, by providing a third semiconductor region, the generation of stacking faults over time can be suppressed. By forming a first impurity concentration gradient to a third impurity concentration gradient in the impurity concentration distribution of the third semiconductor region, the rate of decrease in impurity concentration on the first semiconductor region side of the third semiconductor region (the second impurity concentration gradient) becomes gradual, thereby reducing the stress generated in the semiconductor substrate due to the impurity concentration difference between the third and first semiconductor regions. Therefore, the generation of lattice defects near the first interface between the third and first semiconductor regions can be suppressed.

[0039] Technical effect

[0040] The silicon carbide semiconductor device and silicon carbide semiconductor substrate according to the present invention have the effect of improving reliability. Attached Figure Description

[0041] Figure 1 This is a cross-sectional view showing the structure of the silicon carbide semiconductor substrate according to Embodiment 1.

[0042] Figure 2 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 1.

[0043] Figure 3 It is shown Figure 1 Characteristic diagrams of impurity concentration distribution in the first and second buffers.

[0044] Figure 4 This is a graph showing the relationship between the impurity concentration and thickness of the first and second buffers in the experimental example and the on-state voltage Von.

[0045] Symbol Explanation

[0046] 1:n + Leakage area

[0047] 2:n- Type Drift Zone

[0048] 3: n-type current diffusion region

[0049] 4: p-type base region

[0050] 5:n + Source area

[0051] 6:p ++ Type contact area

[0052] 7: Trench

[0053] 8: Gate insulating film

[0054] 9: Gate electrode

[0055] 10: Silicon carbide semiconductor devices

[0056] 11: First Buffer (n-type Buffer)

[0057] 12: Second Buffer (n + Type buffer)

[0058] 13, 14: p + Type area

[0059] 15: Interlayer insulating film

[0060] 16: Source electrode

[0061] 17: Drain electrode

[0062] 20: Silicon carbide semiconductor substrate

[0063] 21:n + Type of starting substrate

[0064] 22–24, 31, 32: Epitaxial layers

[0065] 25:n + Interface between the type starting substrate and the first buffer zone

[0066] 26: Interface between the first buffer and the second buffer

[0067] 27: Second buffer and n - Interface between drift regions

[0068] 30: Semiconductor substrate

[0069] 33: pn junction

[0070] 41–44: Impurity concentration gradient

[0071] 41a, 41b, 42a, 43a, 44a: Gradient change points in impurity concentration distribution

[0072] t1: Thickness of the first buffer zone

[0073] t2: Thickness of the second buffer zone

[0074] t3:n - Thickness of the drift region

[0075] t10: Total thickness of the first and second buffers Detailed Implementation

[0076] Hereinafter, preferred embodiments of the silicon carbide semiconductor device and silicon carbide semiconductor substrate of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers or regions prefixed with n or p respectively indicate that electrons or holes are the majority carriers. Furthermore, the + and - symbols marked with n or p respectively indicate that the doping concentration is higher and lower than that of layers or regions not marked with + and -. It should be noted that in the following description of the embodiments and the accompanying drawings, the same symbols are used to refer to the same structures, and repeated descriptions are omitted.

[0077] (Implementation Method)

[0078] The structure of the silicon carbide semiconductor device according to the embodiment will be described. Figure 1 , 2 These are cross-sectional views illustrating the structures of the silicon carbide semiconductor substrate and the silicon carbide semiconductor device according to the embodiments. Figure 3 It is shown Figure 1 Characteristic diagrams of impurity concentration distribution in the first and second buffer zones. Figure 3 The diagram shows the case where the target thickness t1 of the first buffer 11 is set to 1 μm and the target thickness t2 of the second buffer 12 is set to 7 μm. Additionally, in... Figure 3 The diagram showing the impurity concentration distribution near the two main surfaces of the silicon carbide semiconductor substrate 20 is omitted. + Type-starting substrate 21 and n - The drift region 2 is shown in only a portion (near the interface 25 between the first buffer zone 11 and the interface 27 between the second buffer zone 12).

[0079] Figure 1 The silicon carbide semiconductor substrate 20 of the illustrated embodiment is based on an n-type semiconductor material using silicon carbide (SiC). + An epitaxial substrate is formed by sequentially stacking multiple n-type epitaxial layers 22-24 with different impurity concentrations, such as nitrogen (N), on the front side of the type-starting substrate 21, and is suitable for applications such as SiC-MOSFETs. Figure 2Fabrication (manufacturing) of vertically oriented silicon carbide semiconductor devices, such as p-intrinsic-n diodes (not shown), where current flows in a direction perpendicular to the main surface of the semiconductor substrate (semiconductor chip). In the case of fabricating a SiC-MOSFET using a silicon carbide semiconductor substrate 20, n + Type-starting substrate 21 becomes n + Type Drain Region 1. When fabricating a pin diode using a silicon carbide semiconductor substrate 20, n + Type-starting substrate 21 becomes n + Type of cathode region.

[0080] n + The impurity concentration of the type-initiating substrate 21 is, for example, 1.0 × 10⁻⁶. 18 / cm 3 Above and 1.0×10 19 / cm 3 Within the range to the left and right below, epitaxial layers 22-24 respectively become the first buffer (n-type buffer: second semiconductor region) 11 and the second buffer (n-type buffer: second semiconductor region) 11. + Type buffer: third semiconductor region) 12 and n - 2. The impurity concentration of the n-type drift region (first semiconductor region) 22 (first buffer layer 11) is higher than that of the n-type epitaxial layer 22. + Type-starting substrate 21 and n + The impurity concentration in the type epitaxial layer 23 (second buffer 12) is low, and it is lower than that in n - Type epitaxial layer 24(n) - The impurity concentration in drift region 2) is high. The impurity concentration in the first buffer zone 11 is, for example, 0.5 × 10⁻⁶. 18 / cm 3 Above and 1.5×10 18 / cm 3 Within the range to the left and right below.

[0081] The thickness t1 of the first buffer zone 11 is preferably, for example, thicker than 1 μm and about 4 μm or less. If the thickness t2 of the second buffer zone 12 exceeds 1 μm, the thickness t1 of the first buffer zone 11 can be set to about 1 μm or less. The first buffer zone 11 has epitaxial layers 22-24 and epitaxial layers 31 and 32 (described later) (see reference). Figure 2 During the epitaxial growth of n) + The BPD propagated from the type-starting substrate 21 is converted into TED. In addition, the thickness of the second buffer 12 can be measured based on Fourier transform using the reflected light of infrared rays reflected from the surface (interfaces 25, 26) of the first buffer 11 (see the above-mentioned Patent Documents 1 to 3).

[0082] The second buffer 12 has the following function: capturing the pn node that becomes the main node (e.g., p-type base region 4 and p-type base region 4, described later). + Type regions 13 and 14 and n-type current diffusion regions 3 and n - pn junction 33 of type drift region 2: Figure 2 When a current flows in the forward direction in the pn junction, the minority carriers (holes) generated at the interface of the pn junction are eliminated through recombination with the majority carriers (electrons), reducing the number of carriers that can reach the n-th junction located further from the second buffer zone 12. + Holes in the BPD on the side of the type-starting substrate 21. Therefore, through n - Type Drift Region 2 and n + A second buffer zone 12 is provided between the type-starting substrates 21, thereby suppressing the growth of stacking faults over time caused by the use of SiC-MOSFETs.

[0083] The impurity concentration ratio of the second buffer zone 12 to n + The impurity concentration of the type-initiating substrate 21 is low and is n + The impurity concentration of the initial substrate 21 is approximately half or less. Specifically, the impurity concentration of the second buffer 12 is, for example, 1.0 × 10⁻⁶. 18 / cm 3 Above and 5.0×10 18 / cm 3 Within the range of the following left and right, 3.0 × 10 is preferred. 18 / cm 3 Within the range of approximately ±10%, by setting the impurity concentration of the second buffer 12 within the aforementioned range, the impurity concentration of the second buffer 12 can be controlled to be approximately ±10% relative to the target impurity concentration. Therefore, compared to conventional structures where the impurity concentration of the second buffer exceeds the upper limit of the aforementioned range, the controllability of the impurity concentration during epitaxial growth of the second buffer 12 is improved.

[0084] Furthermore, regarding the impurity concentration of the second buffer 12, in the first portion 23a of the predetermined depth range occupying a large portion of the thickness t2 of the second buffer 12, the concentration is higher than that of the second buffer 12 at n. - The second part 23b and n on both sides of the drift zone 2 + The third portion 23c is higher on the side of the type starting substrate 21 (the side of the first buffer 11). The first portion 23a, which is a predetermined depth range with a relatively high impurity concentration approximately in the center of the second buffer 12, is from the side relatively close to the second buffer 12 and n. -The portion of the depth range from the predetermined depth position (hereinafter, designated as the gradient change point: first depth position) 41a of the interface (first interface) 27 between the drift zones 2 to the predetermined depth position (gradient change point: second depth position) 41b of the interface (second interface) 26 between the first buffer zone 11 and the second buffer zone 12. Figure 3 ).

[0085] The impurity concentration distribution along the depth direction of the second buffer zone 12 is mountain-shaped. This mountain shape has a apex in the first part 23a (the part between gradient change points 41a and 41b) of a predetermined depth range with relatively high impurity concentration at approximately the center. The impurity concentration increases with increasing concentration from this apex towards n. - Type drift region 2 sides and n + The shape decreases continuously from the starting substrate 21 side. In the impurity concentration distribution in the depth direction of the second buffer 12, different first impurity concentration gradients 41 to third impurity concentration gradients 43 are formed in the first part 23a, the second part 23b, and the third part 23c. The first part 23a starts from n - The gradient change point 41a on both sides of the drift region n + The second portion 23b extends from the gradient change point 41b on the side of the initial substrate 21 to n. - The gradient change point 41a on the second side of the drift region 2 acts as a second buffer zone 12 and n - Up to interface 27 between drift regions 2, the third part 23c extends from n. + The gradient change point 41b on the side of the initial substrate 21 extends to the interface 26 between the first buffer 11 and the second buffer 12.

[0086] Specifically, by setting the impurity concentration of the second buffer 12 within the aforementioned range, the impurity concentration of the second buffer 12 is adjusted from n... - The gradient change point 41a on the two sides of the drift region is oriented towards n. + The gradient change point 41b on the side of the initial substrate 21 continuously increases, reaching its maximum impurity concentration at gradient change point 41b. In the impurity concentration distribution along the depth direction of the second buffer zone 12, the impurity concentration increases with increasing density from n... - The gradient change point 41a on the two sides of the drift region is oriented towards n. + The gradient change point 41b on the starting substrate 21 side continuously increases the first impurity concentration gradient 41 (increase rate: in Figure 3 The absolute value of the slope of the approximate straight line (represented by the thinnest dashed line) is very small compared to the absolute values ​​of the second impurity concentration gradient 42 (reduction rate) and the third impurity concentration gradient 43 (reduction rate). This second impurity concentration gradient 42 is the rate at which the impurity concentration decreases as it moves from gradient change point 41a towards n. -The third impurity concentration gradient 43 is a concentration gradient in which the impurity concentration decreases continuously from the gradient change point 41b toward the first buffer zone 11.

[0087] The inventors have confirmed the following situation: assuming that the impurity concentration in the second buffer 12 is reduced to n... - When the impurity concentration in drift region 2 is below a certain level, the impurity concentration in the second buffer zone 12 becomes uniform in the depth direction. When the impurity concentration in the second buffer zone 12 is raised to a level exceeding the upper limit of the aforementioned range, the impurity concentration in the second buffer zone 12 increases with increasing impurity concentration from n... - Type drift zone 2 sides facing n + The impurity concentration on the starting substrate 21 side decreases continuously at a predetermined impurity concentration gradient. Furthermore, the inventors confirmed that if the impurity concentration in the second buffer 12 exceeds the upper limit of the aforementioned range, then the second buffer 12 and n... - The impurity concentration difference in the drift region 2 increases, thereby generating stress and other crystal defects (such as lattice defects) in the semiconductor substrate 30, in addition to stacking faults.

[0088] In this embodiment, by setting the impurity concentration of the second buffer 12 within the aforementioned range, a first impurity concentration gradient 41 is formed in the depth direction of the second buffer 12, wherein the impurity concentration distribution changes with the depth of the buffer. - The gradient change point 41a on the two sides of the drift region is oriented towards n. + The concentration gradient increases continuously from the gradient change point 41b on the side of the initial substrate 21. A first impurity concentration gradient 41 is formed by the impurity concentration distribution in the depth direction of the second buffer 12, thereby making n... - The second impurity concentration gradient 42 on the side of the drift region 2 is compared to n. + The third impurity concentration gradient 43 on the side of the type-starting substrate 21 is small. Therefore, due to the second buffer zone 12 and n - The stress caused by the impurity concentration difference in drift region 2 is reduced, and the lattice readily interacts with each other in the second buffer zone 12 and n. - The interface 27 between the drift regions 2 is bonded, thus making it difficult for lattice defects to occur.

[0089] Furthermore, in the impurity concentration distribution along the depth direction of the second buffer zone 12, n - The second impurity concentration gradient 42 on the side of the drift region 2 is within the second buffer zone 12. - Near the gradient change point 41a on the second side of the drift region, the impurity concentration decreases in a parabolic pattern, bulging upwards towards the side with higher impurity concentration. +The third impurity concentration gradient 43 on the side of the type-starting substrate 21 within the second buffer 12 + Near the gradient change point 41b on the side of the initial substrate 21, the impurity concentration decreases in a parabolic pattern, bulging towards the high impurity concentration side. In the impurity concentration distribution along the depth direction of the second buffer zone 12, it is related to n... + Compared to the parabolic impurity concentration distribution near the gradient change point 41b of the third impurity concentration gradient 43 on the side of the type-starting substrate 21, n - The parabolic impurity concentration distribution near the gradient change point 41a of the second impurity concentration gradient 42 on the side of the drift region 2 has a small curvature and the decrease in impurity concentration is gradual.

[0090] The second impurity concentration gradient 42 of the impurity concentration distribution in the second buffer 12 starts at n within the second buffer 12. - The gradient change point 41a on the two sides of the drift region is n. - The predetermined depth position (gradient change point) 42a within the drift region 2. Therefore, n - The impurity concentration distribution in drift region 2 follows the same impurity concentration gradient as the second impurity concentration gradient 42 in the second buffer 12, from the second buffer 12 and n - The interface 27 between the drift regions 2 and n - The gradient change point 42a within the drift region 2 decreases continuously, and at this gradient change point 42a becomes n. - Minimum impurity concentration in drift region 2. - The impurity concentration in drift region 2 becomes uniformly n along the depth direction in the part far from the second buffer zone 12 (the part further to the left of the gradient change point 42a). - Minimum impurity concentration in drift region 2.

[0091] The starting point of the third impurity concentration gradient 43 in the impurity concentration distribution of the second buffer 12 is n within the second buffer 12. + The gradient change point 41b on the side of the initial substrate 21 is one starting point, and the other starting point is a predetermined depth position (gradient change point) 43a within the first buffer 11. Therefore, the impurity concentration distribution in the first buffer 11 decreases continuously from the interface 26 between the first buffer 11 and the second buffer 12 toward the gradient change point 43a within the first buffer 11, with the same impurity concentration gradient 43 as the third impurity concentration gradient 43 of the impurity concentration distribution in the second buffer 12. At this gradient change point 43a, the minimum impurity concentration in the first buffer 11 is reached, and from this gradient change point 43a, the impurity concentration decreases toward n... + The type-starting substrate 21 is continuously increased at a predetermined fourth impurity concentration gradient 44.

[0092] The fourth impurity concentration gradient 44 of the impurity concentration distribution in the first buffer 11 has one starting point at the gradient change point 43a within the first buffer 11, and another starting point at n. + The predetermined depth position (gradient change point) 44a within the type starting substrate 21. Therefore, n + The impurity concentration distribution of the type-starting substrate 21 follows the same impurity concentration gradient 44 as the impurity concentration distribution of the first buffer 11, from n + The interface 25 between the initial substrate 21 and the first buffer zone 11 continuously increases toward the gradient change point 44a, and becomes n at the gradient change point 44a. + The maximum impurity concentration of the type-initiating substrate 21. + The impurity concentration of the type-starting substrate 21 is uniformly n along the depth direction in the portion far from the first buffer zone 11 (the portion further to the right of the gradient change point 44a). + The maximum impurity concentration of the type-initiating substrate 21.

[0093] Second buffer 12 and n - The interface 27 between the type drift regions 2 is n within the second buffer 12. - Gradient change points 41a and n on both sides of the drift region 2 - The depth position of the gradient change point 42a (the middle of the second impurity concentration gradient 42) within the drift region 2. The interface 26 between the first buffer zone 11 and the second buffer zone 12 is the n-th boundary within the second buffer zone 12. + The depth position between the gradient change point 41b on the side of the initial substrate 21 and the gradient change point 43a in the first buffer zone 11 (the middle of the third impurity concentration gradient 43). + The interface 25 between the type starting substrate 21 and the first buffer 11 is a depth position that is line-symmetrical with respect to the interface 26 between the first buffer 11 and the second buffer 12, with the gradient change point 43a in the first buffer 11 as a reference.

[0094] The thickness t2 of the second buffer 12 is preferably in the range of, for example, thicker than 1 μm and less than about 7 μm. If the thickness t1 of the first buffer 11 exceeds 1 μm, the thickness t2 of the second buffer 12 can be set to about 1 μm or less. The total thickness t10 (=t1+t2) of the first buffer 11 and the second buffer 12 is preferably as thin as possible, for example, in the range of about 2 μm or more and about 8 μm or less. The thinner the total thickness t10 of the first buffer 11 and the second buffer 12 (especially the thinner the thickness t2 of the second buffer 12 with a relatively high impurity concentration), the lower the material cost and the lower the warpage of the silicon carbide semiconductor substrate 20 (and subsequently the semiconductor substrate 30). If the total thickness t10 of the first buffer 11 and the second buffer 12 exceeds the upper limit of the above range, the surface roughness (unevenness) of the silicon carbide semiconductor substrate 20 increases and the coverage of the insulating film deteriorates, or, for example, the leakage current between the gate and source of the SiC-MOSFET increases, which is therefore undesirable.

[0095] n - The impurity concentration in drift region 2 is, for example, 1.0 × 10⁻⁶. 15 / cm 3 Above and 2.0×10 16 / cm 3 Within the range to the left and right below. n - The thickness t3 of the drift region 2 is, for example, in the range of approximately 5 μm to 35 μm. (This is achieved through n...) - Type drift region 2 (n of silicon carbide semiconductor substrate 20) - The epitaxial layer 24) is made into a p-type base region 4 (refer to the epitaxial layer 24). Figure 2 The p-type epitaxial layer is epitaxially grown in the p-type anode region and / or via an n-type epitaxial layer, thereby forming a SiC-MOSFET. Figure 2 The pn junction of the main junction of a ) and / or pin diode (not shown) (e.g., in Figure 2 In SiC-MOSFETs, this is equivalent to a pn junction (33).

[0096] Reference Figure 2 The SiC-MOSFET fabricated using silicon carbide semiconductor substrate 20 will be described. Figure 2 The silicon carbide semiconductor device 10 of the illustrated embodiment is a vertically oriented SiC-MOSFET with a trench gate structure on the front side of a semiconductor substrate (semiconductor chip) 30 using SiC as the semiconductor material. The semiconductor substrate 30 is based on the aforementioned... Figure 1 The silicon carbide semiconductor substrate 20 n -An epitaxial substrate is formed by further stacking epitaxial layers 31 and 32 sequentially on the p-type epitaxial layer 24. For the semiconductor substrate 30, the main surface on the side of the p-type epitaxial layer 32 is designated as the front side (first main surface), and the n-type epitaxial layer 32 is designated as the front side. + The main surface of the type starting substrate 21 is set as the back side. + Type-starting substrate 21 becomes n + Type 1 leak area.

[0097] As described above, epitaxial layers 22-24 respectively serve as the first buffer 11, the second buffer 12, and n. - Type 2 drift region. First buffer 11 and second buffer 12 are set in n - Type Drift Region 2 and n + Between the type-starting substrate 21. The first buffer zone 11 and n + The type-starting substrate 21 is adjacent. The second buffer zone 12 is adjacent to n. - Type drift region 2 adjacent. - The epitaxial layer 31 selectively forms n-type current diffusion regions 3 and p-type current diffusion regions 3 and 3 respectively inside it. + Type 13, 14 ( Figure 2 ), or become n - P-type drift region 2 (not shown). The p-type epitaxial layer 32 becomes the p-type base region 4. The p-type base region 4 is disposed on the front side of the semiconductor substrate 30 and adjacent to the n-type base region 4. - Between type drift region 2.

[0098] The trench gate structure consists of a p-type base region (fourth semiconductor region) and n-type base region. + Source region (fifth semiconductor region) 5, p ++ The p-type base region 4 is composed of a contact region 6, a trench 7, a gate insulating film 8, and a gate electrode 9. This is formed between the p-type base region 4 and the n-type base region 9. - Between drift zones 2, closer to n than the bottom surface of trench 7. + At a depth on the side of the drain region 1, n-type current diffusion regions 3 and p-type current diffusion regions 3 and 4 are selectively provided respectively. + Type regions 13 and 14. n-type current diffusion regions 3 and p. + Type regions 13 and 14 were formed in n through ion implantation. - The diffusion region inside the epitaxial layer 31. - In addition to the n-type current diffusion region 3 and p-type epitaxial layer 31 + The parts other than type regions 13 and 14 and n - The epitaxial layer 24 together become n - Type 2 drift zone.

[0099] The n-type current spreading region 3 is a so-called current spreading layer (CSL) that reduces the spreading resistance of charge carriers. The n-type current spreading region 3 is located between adjacent trenches 7 in the depth direction, adjacent to the p-type base region 4 and the n-type current spreading region 5. - The n-type drift region 2 contacts and extends along a direction parallel to the front side of the semiconductor substrate 30 to the trench 7, thereby contacting the gate insulating film 8. Alternatively, the n-type current diffusion region 3 may not be provided. Without the n-type current diffusion region 3, the n... - Type 2 drift region replaces n-type current diffusion region 3 and from n + The drain region 1 reaches the p-type base region 4 and extends to the trench 7 in a direction parallel to the front side of the semiconductor substrate 30, thus contacting the gate insulating film 8.

[0100] p + Type regions 13 and 14 are fixed at the potential of the source electrode (first electrode) 16, as described later, and are depleted when the SiC-MOSFET (silicon carbide semiconductor device 10) is turned off (or the n-type current diffusion region 3 is depleted, or the p-type current diffusion region 16 is depleted). + The depletion of both n-type regions 13 and 14 and n-type current diffusion region 3 mitigates the electric field applied to the bottom surface of the gate insulating film 8 of the trench 7. + Type 13 is arranged separately from p-type base region 4 and faces the bottom surface of trench 7 in the depth direction. + Type 13 is connected to p through the part of the diagram that is omitted. + P-type region 14 is partially connected or connected to other p-type regions, thereby electrically connecting to source electrode 16. + Region 13 can be in contact with the gate insulating film 8 on the bottom surface of the trench 7, or it can be separated from the bottom surface of the trench 7.

[0101] p + Type 14 with groove 7 and p + The type zone 13 is separated between adjacent trenches 7. + Type 14 in n + The surface of the source region 5 contacts the p-type base region 4, and is electrically connected to the source electrode 16 via the p-type base region 4. The trench 7 extends along the depth direction from the front side of the semiconductor substrate 30 through the p-type epitaxial layer 32 to reach the n-type current diffusion region 3 (or n-type if the n-type current diffusion region 3 is not provided). - Type drift region 2). Between adjacent trenches 7, n-type base regions are selectively disposed between the front side of the semiconductor substrate 30 and the p-type base region 4. + Source region 5 and p ++ Type 6 contact area.

[0102] n + Source region 5 and p ++The n-type contact region 6 is a diffusion region formed inside the p-type epitaxial layer 32 by ion implantation. Besides the n-type contact region, the p-type epitaxial layer 32 also contains other features. + Source region 5 and p ++ The portion outside the type contact region 6 is the p-type base region 4. + Source region 5 and p ++ The contact area 6 reaches the front side of the semiconductor substrate 30. + Source area 5 is set at p ++ The contact area 6 is located closer to the trench 7 and contacts the gate insulating film 8 on the sidewall of the trench 7. Alternatively, the p-type contact area may not be provided. ++ Type contact area 6. Without setting p ++ In the case of contact region 6, p-type base region 4 replaces p. ++ The contact area 6 reaches the front side of the semiconductor substrate 30.

[0103] Inside the trench 7, a gate electrode 9 is disposed on the gate insulating film 8 in a manner embedded in the trench 7. The gate insulating film 8 is located on the inner wall of the trench 7 and is flush with n + Source region 5, p-type base region 4, and n-type current diffusion region 3 (or n-type current diffusion region 4 if n-type current diffusion region 3 is not provided) - Type drift region 2) contact. Inside the trench 7, a gate electrode 9 is disposed with respect to the gate insulating film 8. Figure 2 In the illustration, only one unit cell (the constituent unit of an element) of a MOSFET is shown, but multiple unit cells with the same trench gate structure are arranged adjacent to each other on the semiconductor substrate 30. An interlayer insulating film 15 is disposed on the front side of the semiconductor substrate 30 and covers the gate electrode 9.

[0104] n is exposed at the contact holes of the interlayer insulating film 15. + Source region 5 and p ++ Type contact area 6 (without setting p) ++ In the case of p-type contact region 6, it is p-type base region 4). The source electrode 16 makes ohmic contact with the front side of the semiconductor substrate 30 in the contact hole of the interlayer insulating film 15, and makes contact with the n-type base region 4. + Source region 5, p ++ The n-type contact region 6 and the p-type base region 4 are electrically connected. On the back side of the semiconductor substrate 30 (n... + A drain electrode (second electrode) 17 is provided on the entire back surface of the type starting substrate 21. The drain electrode 17 and n + Type 1 (n) + The type starting substrate 21) contacts and is in contact with n + Type 1 leakage area electrical connection.

[0105] The operation of the silicon carbide semiconductor device 10 according to the embodiment will be explained. If a voltage greater than or equal to the gate threshold voltage is applied to the gate electrode 9 while a positive voltage (forward voltage) is applied to the drain electrode 17 relative to the source electrode 16, a channel (an inversion layer of the n-type) is formed in the p-type base region 4 along the sidewall of the trench 7. As a result, current flows from the n-type base region 10 to the gate electrode 9. + Type 1 leak area flows to n through the channel + Source region 5, SiC-MOSFET (silicon carbide semiconductor device 10) is turned on.

[0106] On the other hand, when a positive voltage is applied between the source and drain, and a voltage less than the gate threshold voltage is applied to the gate electrode 9, by making p + Type regions 13 and 14, as well as p-type base region 4 and n-type current diffusion regions 3 and n - The pn junction (main junction) 33 of the drift region 2 is reverse biased, thereby preventing current flow and keeping the SiC-MOSFET in the off state. Additionally, current flows from this pn junction 33 to the pn junction through the depletion layer. + The expansion of regions 13 and 14 mitigates the electric field applied to the bottom surface of the gate insulating film 8 in the trench 7.

[0107] Furthermore, when the SiC-MOSFET is off, by applying a negative voltage relative to the source electrode 16 to the drain electrode 17, current can be directed in the positive direction through the p-type base region 4 and p-type source region 16. + Type regions 13 and 14 and n-type current diffusion regions 3 and n - The current flows through the parasitic diode (body diode) formed by the pn junction 33 of the drift region 2. For example, a parasitic diode built into the semiconductor substrate 30 can be used as a freewheeling diode to protect the SiC-MOSFET itself.

[0108] Injected into n through the bipolar action of the body diode - The minority carriers (holes) in type drift region 2 are configured in n - Type Drift Region 2 and n + The electrons recombine and disappear within the second buffer zone 12 between the type-initiating substrates 21. Therefore, it is possible to reduce the number of electrons reaching electrons located further away from the second buffer zone 12. + The holes in the BPD on the side of the type-start substrate 21 can suppress the growth of stacking faults in the epitaxial layers 22-24, 31, and 32. Therefore, the rise of the turn-on voltage Von of the SiC-MOSFET can be suppressed.

[0109] Next, the manufacturing method of the silicon carbide semiconductor device 10 according to the embodiment will be described. First, prepare n using silicon carbide as the semiconductor material. + Type-based starter substrate (starter wafer) 21. Next, in n +The front side of the type-starting substrate 21 is configured as a first buffer zone 11, a second buffer zone 12, and an n-type buffer zone. - The epitaxial layers 22-24 and 31 of the drift region 2 are sequentially epitaxially grown. Using n + The substrate 21 and epitaxial layers 22-24 are used to fabricate the structure. Figure 1 The silicon carbide semiconductor substrate (semiconductor wafer) 20. First buffer 11, second buffer 12, and n - The conditions for drift region 2 (impurity concentration and thickness t1 to t3) are as described above. - The impurity concentration of the epitaxial layer 31 is, for example, related to n. - The impurity concentration is the same in drift region 2.

[0110] In n + There are 500 per cm² in the type starting substrate 21. 2 ~1000 pieces / cm 2 The BPD is around the left and right, but during epitaxial growth from n + The BPD propagating from the initial substrate 21 to the epitaxial layers 22-24, 31 is easily grown on the n-type epitaxial layer in the initial epitaxial growth. + The first buffer zone 11 (n-type epitaxial layer 22) on the n-type starting substrate 21 is converted to TED. This reduces the amount of material transferred from the n-type epitaxial layer 22 to the first buffer zone 11. + The number of BPDs that the n-type starting substrate 21 passes over the n-type epitaxial layer 22 to reach the epitaxial layers 23, 24, and 31 is reduced. Therefore, it is possible to suppress the injection of BPDs into the n-type MOSFET (silicon carbide semiconductor device 10) when the body diode is turned on. - The recombination of minority carriers (holes) in the drift region 2 leads to the growth of stacking faults in epitaxial layers 22-24, 31, and 32, starting from the BPD.

[0111] Next, through photolithography and ion implantation of p-type impurities, in n - The surface regions of the epitaxial layer 31 are selectively formed with p in a manner that is separated from each other and alternately repeated. + Type 13 and p + The lower part (n) of type 14 + (The portion on the 1st side of the n-type drain region). Additionally, through photolithography and ion implantation of n-type impurities, in the n... - The surface region of the epitaxial layer 31, in the adjacent p + Type 13 and p + The lower part of the n-type current diffusion region 3 is formed between the n-type regions 14. - The ratio of p in the epitaxial layer 31 + Type regions 13 and 14 and n-type current diffusion region 3 are closer to n + The portion on the side of the type starting substrate 21 becomes n - Type 2 drift zone.

[0112] Next, further epitaxial growth will be performed to increase n - The p-type epitaxial layer 31 is thickened to a predetermined thickness. Next, through photolithography and ion implantation of p-type impurities, the n-type epitaxial layer is further thickened. - The increased thickness of the epitaxial layer 31 selectively forms p-type epitaxial layer. + The upper part of type 14 (n) + (The portion on the 5th side of the source region). Additionally, through photolithography and ion implantation of n-type impurities, in the n... - The increased thickness of the epitaxial layer 31 forms the upper part of the n-type current diffusion region 3. + The upper part of the n-type region 14 and the upper part of the n-type current diffusion region 3 are respectively formed in the depth direction with respect to the p-type region. + The lower part of the n-type region 14 and the lower part of the n-type current diffusion region 3 are positioned opposite each other, and are respectively with p + The lower part of the n-type region 14 is connected to the lower part of the n-type current diffusion region 3.

[0113] Next, in n - On the p-type epitaxial layer 31, a p-type epitaxial layer 32, which serves as the p-type base region 4, is epitaxially grown (stacking). Through the processes up to this point, a p-type epitaxial layer 32 is fabricated. + A semiconductor substrate (semiconductor wafer) 30, on the front side of the p-type starting substrate 21, has epitaxial layers 22-24, 31, and 32 sequentially stacked. Next, photolithography and ion implantation are repeatedly performed under different conditions to selectively form n-type epitaxial layers 32 on their surface regions. + Source region 5 and p ++ Type contact region 6. The ratio of n to p-type epitaxial layer 32. + Source region 5 and p ++ Type 6 contact area is closer to n - The portion on the side of the epitaxial layer 31 becomes the p-type base region 4.

[0114] Next, for all diffusion regions (p) formed by ion implantation + Type regions 13, 14, n-type current diffusion region 3, n + Source region 5 and p ++ The contact region 6) undergoes heat treatment for impurity activation. This heat treatment can also be performed each time a diffusion region is formed via ion implantation. Next, photolithography and etching are used to form a through-n region. + The trench 7 extends from the p-type source region 5 and the p-type base region 4 to the n-type current diffusion region 3. Next, using conventional methods, the gate insulating film 8, gate electrode 9, interlayer insulating film 15, source electrode 16, and drain electrode 17 are formed. Subsequently, the semiconductor wafer (semiconductor substrate 30) is cut (slit) to monolithically form individual chips, thereby completing the process. Figure 2 10. Silicon carbide semiconductor device.

[0115] As described above, according to the embodiment, the silicon carbide semiconductor substrate is in n + The type-starting substrate is used to form a first buffer, a second buffer, and n. - A substrate formed by sequentially epitaxially growing the epitaxial layers in the drift region. The impurity concentration of the first buffer zone is higher than that of n. - The impurity concentration in the type-drift region is high and higher than that in the n-type drift region. + The impurity concentration of the initial substrate is low. The impurity concentration of the second buffer is higher than that of the first buffer. This is achieved through n... + The n-type epitaxial layer, initially forming a first buffer zone, is epitaxially grown on the n-type starting substrate, thereby improving the epitaxial growth from n... + The ratio of BPD propagation from the substrate to the epitaxial layer to TED can suppress the growth of stacking faults originating from BPD.

[0116] The impurity concentration in the second buffer increases as it decreases from a level relatively close to that of the second buffer with respect to n. - The impurity concentration at a predetermined first depth position of the first interface between the drift regions increases continuously with a first impurity concentration gradient toward a predetermined second depth position of the second interface relatively close to the first buffer and the second buffer, reaching a maximum at the second depth position. The concentration then decreases continuously with a second impurity concentration gradient from the first depth position toward the first interface, and further decreases continuously with a third impurity concentration gradient from the second depth position toward the second interface. In the impurity concentration distribution of the second buffer, n - The rate of reduction in impurity concentration on the drift region side (second impurity concentration gradient) is greater than that on the first buffer side (n + The rate of reduction of impurity concentration on the starting substrate side (third impurity concentration gradient) is small.

[0117] Through n - Type drift region and n + A second buffer is provided between the starting substrates to suppress the generation of stacking faults over time caused by the use of silicon carbide semiconductor devices. By providing the second buffer, even in n... - Type drift region and n + The concentration of n-type impurities is relatively higher between the initial substrates, and the first to third impurity concentration gradients mentioned above are formed in the impurity concentration distribution of the second buffer, thereby increasing the concentration of n-type impurities in the second buffer. - The rate of decrease in impurity concentration on the drift region side (the second impurity concentration gradient) becomes gradual, which can reduce the impact of the second buffer zone on n. - The stress generated within the semiconductor substrate due to the impurity concentration difference between the drift regions is thus mitigated. Therefore, it is possible to suppress the stress generated in the second buffer zone and the n-type drift region. - Lattice defects are generated near the first interface between the drift regions.

[0118] The first to third impurity concentration gradients of the impurity concentration distribution in the second buffer are used to reduce the impurity concentration in the second buffer to as low as 1.0 × 10⁻⁶. 18 / cm 3 Above and 5.0×10 18 / cm 3 It is formed within the range of the following left and right. Furthermore, by keeping the impurity concentration of the second buffer within this range, the controllability of the impurity concentration during epitaxial growth of the second buffer is improved, and deviations in the depth direction of the impurity concentration in the second buffer are suppressed, thus suppressing fluctuations in the conduction voltage. Therefore, by setting the second buffer, the generation of stacking faults over time can be suppressed, and by setting the impurity concentration of the second buffer within the aforementioned range, the generation of lattice defects and / or Von fluctuations caused by setting a relatively high impurity concentration in the second buffer can be suppressed, thus improving reliability.

[0119] (Experimental Example)

[0120] The relationship between the impurity concentration and thicknesses t1 and t2 of the first buffer 11 and the second buffer 12 and the conduction voltage Von was verified. Figure 4 This is a graph showing the relationship between the impurity concentration and thickness of the first and second buffers in the experimental example and the on-state voltage Von. According to the silicon carbide semiconductor device 10 of the above embodiment, a predetermined number of samples (SiC-MOSFETs) (hereinafter referred to as experimental examples) were fabricated, each with different design conditions (16 conditions: hereinafter referred to as sample No. 1 to No. 16) for the impurity concentration and thickness t1 and t2 of the first and second buffers 11 and 12. The body diodes of all these samples were tested under the same conditions (1000 A / cm²). 2 After the forward current is applied, the on-state voltage Von of the SiC-MOSFET is measured.

[0121] For each specimen under these multiple conditions, the results verifying the fluctuation rate (hereinafter referred to as Von fluctuation rate) of the turn-on voltage Von relative to the design value (the turn-on voltage Von that can be expected under the respective design conditions of the specimen) are shown in [the table]. Figure 4 .exist Figure 4In this study, samples with a Von volatility of less than 1% under the same conditions are defined as having a high (○) effect in suppressing the conduction voltage Von volatility (hereinafter referred to as Von volatility suppression effect). Samples with a Von volatility of less than 5% under the same conditions are defined as having a conduction voltage volatility suppression effect (△). Samples with a Von volatility of 5% or more are defined as having a low (×) Von volatility suppression effect even if only one of them exists under the design conditions. Under the design conditions of samples with Von volatility suppression effects marked as ○ and △, Von volatility can be suppressed within a practically usable range.

[0122] according to Figure 4 The results show that the Von fluctuation suppression effect is lower in sample No. 1 (where the second buffer 12 is not provided, and the thickness t2 of the second buffer 12 is 0 μm) and in samples No. 6, No. 10, No. 13, and No. 16 (where the impurity concentration and thickness t1, t2 ranges of the first buffer 11 and second buffer 12 do not meet the above-described embodiment). On the other hand, samples No. 2 to No. 5, No. 7 to No. 9, No. 11, No. 12, No. 14, and No. 15 (where the impurity concentration and thickness t1, t2 ranges of the first buffer 11 and second buffer 12 meet the above-described embodiment), which can suppress Von fluctuations within a practically usable range.

[0123] Thus, it was confirmed that by satisfying the ranges of impurity concentration and thicknesses t1 and t2 of the first buffer 11 and the second buffer 12 described in the above embodiment, Von fluctuations can be suppressed. In particular, by satisfying the range of impurity concentration of the second buffer 12 described in the above embodiment, the controllability of the impurity concentration during epitaxial growth of the second buffer 12 is improved, and the deviation of the impurity concentration in the depth direction of the second buffer 12 is reduced, thereby increasing the Von fluctuation suppression effect. Therefore, by satisfying the range of impurity concentration of the second buffer 12 described in the above embodiment, the n of the second buffer 12 can be made more stable. - The reduction rate of impurity concentration on both sides of the drift region (second impurity concentration gradient 42: reference) Figure 3 It can smooth out and suppress the generation of lattice defects, and can also suppress Von fluctuations.

[0124] The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the invention. For example, the present invention can also be applied to Schottky barrier diodes (SBDs) and IGBTs (Insulated Gate Bipolar Transistors). When applying the present invention to SBDs, as long as the structure is formed with... Figure 1 n of silicon carbide semiconductor substrate - Electrodes with Schottky contacts in the epitaxial layer are acceptable. When applying this invention to IGBTs, p... + Type-starting substrate to replace n + A type-based starting substrate is sufficient. Alternatively, a planar gate structure can be used instead of a trench gate structure. Furthermore, this invention describes the first conductivity type as n-type and the second conductivity type as p-type, but the conductivity types are not limited to these; reversing the conductivity types (n-type and p-type) also applies.

[0125] Industrial availability

[0126] As described above, the silicon carbide semiconductor device and silicon carbide semiconductor substrate of the present invention are useful for power semiconductor devices used in power conversion devices, power supply devices for various industrial machinery, etc., and are particularly suitable for SiC-MOSFETs and pin diodes.

Claims

1. A silicon carbide semiconductor device, characterized by, A current flows in a direction perpendicular to the main surface of a semiconductor substrate, said semiconductor substrate being a substrate epitaxially grown from a starting substrate made of silicon carbide, said silicon carbide semiconductor device comprising: A first semiconductor region of a first conductivity type is disposed inside the epitaxial layer; A second semiconductor region of a first conductivity type is disposed inside the epitaxial layer between the first semiconductor region and the starting substrate in such a way that it contacts the starting substrate. The impurity concentration of the second semiconductor region is higher than that of the first semiconductor region and lower than that of the starting substrate. as well as A third semiconductor region of a first conductivity type is disposed inside the epitaxial layer, between the first semiconductor region and the second semiconductor region, in contact with both the first and second semiconductor regions, and has a higher impurity concentration than the second semiconductor region. The impurity concentration of the third semiconductor region is configured as follows: As the impurity concentration continuously increases from a first depth position toward a second depth position with a first impurity concentration gradient, reaching its maximum at the second depth position, the first depth position is a predetermined depth position relatively close to the first interface between the third semiconductor region and the first semiconductor region, and the second depth position is a predetermined depth position relatively close to the second interface between the second semiconductor region and the third semiconductor region. As the concentration decreases continuously from the first depth position toward the first interface with a second impurity concentration gradient, As the concentration decreases continuously from the second depth position toward the second interface with a third impurity concentration gradient, The impurity concentration in the third semiconductor region is lower than the impurity concentration in the starting substrate. The second impurity concentration gradient is smaller than the third impurity concentration gradient.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, The absolute value of the first impurity concentration gradient is smaller than the absolute values ​​of the second impurity concentration gradient and the third impurity concentration gradient.

3. The silicon carbide semiconductor device according to claim 1, characterized in that, The impurity concentration of the third semiconductor region is less than half of the impurity concentration of the starting substrate.

4. The silicon carbide semiconductor device according to claim 1, characterized in that, The impurity concentration of the third semiconductor region is 1.0 x 10 18 / cm 3 above and 5.0 x 10 18 / cm 3 below.

5. The silicon carbide semiconductor device according to claim 4, characterized in that, The impurity concentration of the third semiconductor region is 3.0 x 10 18 / cm 3 within the above range.

6. The silicon carbide semiconductor device according to claim 1, characterized in that, The impurity concentration of the starting substrate is 1.0 x 1010 18 / cm 3 The above and 1.0 x 1010 19 / cm 3 The below range.

7. The silicon carbide semiconductor device according to claim 1, characterized in that, The impurity concentration of the second semiconductor region is in the range of 0.5 x 10 18 / cm 3 above and 1.5 x 10 18 / cm 3 below.

8. The silicon carbide semiconductor device according to claim 1, characterized in that, The thickness of the third semiconductor region is within the range of more than 1 μm and less than 7 μm.

9. The silicon carbide semiconductor device according to claim 8, characterized in that, The thickness of the second semiconductor region is in the range of more than 1 μm and less than 4 μm.

10. The silicon carbide semiconductor device according to claim 8, characterized in that, The thickness of the second semiconductor region is less than 1 μm.

11. The silicon carbide semiconductor device according to claim 1, characterized in that, The thickness of the second semiconductor region is in the range of more than 1 μm and less than 4 μm.

12. The silicon carbide semiconductor device according to claim 11, characterized in that, The thickness of the third semiconductor region is less than 1 μm.

13. The silicon carbide semiconductor device according to claim 1, characterized in that, The total thickness of the second semiconductor region and the third semiconductor region is in the range of 2 μm or more and 8 μm or less.

14. The silicon carbide semiconductor device of any one of Claims 1-13, further comprising: have: The fourth semiconductor region of the second conductivity type is disposed inside the epitaxial layer between the first main surface of the semiconductor substrate and the first semiconductor region. A fifth semiconductor region of a first conductivity type is selectively disposed within the epitaxial layer between the first main surface of the semiconductor substrate and the fourth semiconductor region; A gate insulating film is configured to contact the region of the fourth semiconductor region, between the first semiconductor region and the fifth semiconductor region; A gate electrode is disposed on the opposite side of the fourth semiconductor region, separated by the gate insulating film; A first electrode is disposed on a first main surface of the semiconductor substrate formed by the epitaxial layer and is electrically connected to the fourth semiconductor region and the fifth semiconductor region; as well as The second electrode is disposed on the second main surface of the semiconductor substrate formed by the starting substrate and is electrically connected to the starting substrate.

15. A silicon carbide semiconductor substrate, characterized by, An epitaxial layer is epitaxially grown on a starting substrate made of silicon carbide, and has the following characteristics: A first semiconductor region of a first conductivity type is disposed inside the epitaxial layer; A second semiconductor region of a first conductivity type is disposed inside the epitaxial layer between the first semiconductor region and the starting substrate in such a way that it contacts the starting substrate. The impurity concentration of the second semiconductor region is higher than that of the first semiconductor region and lower than that of the starting substrate. as well as A third semiconductor region of a first conductivity type is disposed inside the epitaxial layer, between the first semiconductor region and the second semiconductor region, in contact with both the first and second semiconductor regions, and has a higher impurity concentration than the second semiconductor region. The impurity concentration of the third semiconductor region is configured as follows: As the impurity concentration continuously increases from a first depth position toward a second depth position with a first impurity concentration gradient, reaching its maximum at the second depth position, the first depth position is a predetermined depth position relatively close to the first interface between the third semiconductor region and the first semiconductor region, and the second depth position is a predetermined depth position relatively close to the second interface between the second semiconductor region and the third semiconductor region. As the concentration decreases continuously from the first depth position toward the first interface with a second impurity concentration gradient, As the concentration decreases continuously from the second depth position toward the second interface with a third impurity concentration gradient, The impurity concentration in the third semiconductor region is lower than the impurity concentration in the starting substrate. The second impurity concentration gradient is smaller than the third impurity concentration gradient.

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