Metal oxide thin film transistor, manufacturing method thereof, display panel and display device

Abstract

The present disclosure relates to a metal oxide thin film transistor and a manufacturing method thereof, a display panel and a display device, and belongs to the technical field of display. The metal oxide thin film transistor comprises a gate, a gate insulating layer, a metal oxide semiconductor layer, a source and a drain, and a passivation layer, which are sequentially arranged on a substrate. The source and the drain are both of a laminated structure. The laminated structure of the source or the drain comprises at least a main metal layer and an electrode protection layer. The electrode protection layer comprises a metal or a metal alloy. The electrode protection layer is arranged between the metal oxide semiconductor layer and the main metal layer. A metal oxide layer is arranged between the electrode protection layer and the main metal layer. The metal elements of the metal oxide layer comprise at least one of the metal elements of the main metal layer and the metal elements of the electrode protection layer. The thickness of the metal oxide layer is not more than 2% of the thickness of any one of the source and the drain. The thickness of the metal oxide layer is not more than 10% of the thickness of the electrode protection layer.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a metal oxide thin-film transistor and its fabrication method, a display panel, and a display device. Background Technology

[0002] Thin-film transistors (TFTs) are the core components of display devices. Each pixel in a display device relies on a TFT for switching and driving. Metal-oxide-slim TFTs have high mobility, which can improve the resolution of display devices, and their application in display devices is becoming increasingly widespread. Summary of the Invention

[0003] This disclosure provides a metal oxide thin-film transistor and its fabrication method, a display panel, and a display device. The technical solution is as follows:

[0004] On one hand, this disclosure provides a metal-oxide-semiconductor thin-film transistor (MOSFET), comprising, sequentially on a substrate, a gate, a gate insulating layer, a metal-oxide-semiconductor layer, a source, a drain, and a passivation layer; the source and the drain are both stacked structures, the stacked structure of the source or drain includes at least a host metal layer and an electrode protection layer, the electrode protection layer is located on at least one side of the host metal layer, and the electrode protection layer comprises a metal or a metal alloy; the electrode protection layer of the source or drain is at least disposed between the metal-oxide-semiconductor layer and the host metal layer; a metal oxide layer is present between the electrode protection layer of the source or drain and the host metal layer of the source or drain, the metal element of the metal oxide layer including at least one of the metal elements of the host metal layer and the metal element of the electrode protection layer; the thickness of the metal oxide layer of the source or drain does not exceed 2% of the thickness of either the source or the drain electrode; the thickness of the metal oxide layer of the source or drain does not exceed 10% of the thickness of the electrode protection layer.

[0005] In one implementation of this disclosure, the thickness of the metal oxide layer of the source or drain electrode does not exceed 0.5% of the thickness of either the source or drain electrode; and the thickness of the metal oxide layer of the source or drain electrode does not exceed 8% of the thickness of the electrode protective layer.

[0006] In one implementation of this disclosure, the thickness of the metal oxide layer of the source or drain electrode does not exceed 3 nanometers.

[0007] In one implementation of this disclosure, the oxygen element distribution in the metal oxide layer of the source or drain electrode is located between the electrode protective layer and the main metal layer. The oxygen element distribution has a set thickness, which is the thickness of the metal oxide layer. The metal oxide layer of the source electrode is a film layer of metal oxides distributed from near the drain electrode to away from the drain electrode, and the thickness of the metal oxides decreases as it moves further away from the drain electrode. And / or the metal oxide layer of the drain electrode is a film layer of metal oxides distributed from near the source electrode to away from the source electrode, and the thickness of the metal oxides decreases as it moves further away from the source electrode.

[0008] In one implementation of this disclosure, the distance between the metal oxide extending from the side of the source or drain electrode to the top of the electrode protection layer and the bottom of the main metal layer does not exceed the edge of the electrode protection layer.

[0009] In one implementation of this disclosure, the metal oxide extends inward between the top of the electrode protective layer and the bottom of the main metal layer in the channel length direction by a distance not exceeding the edge of the electrode protective layer.

[0010] In one implementation of this disclosure, the electrode protection layer of the source or drain includes a first part and a second part connected together. The first part and the second part are both located on the side of the metal oxide semiconductor layer. In a direction perpendicular to the surface of the substrate, the second part is located above the first part, and the slope angle of the first part is greater than that of the second part.

[0011] In one implementation of this disclosure, the slope angle of the first part ranges from 80 degrees to 100 degrees, and the slope angle of the second part ranges from 30 degrees to 60 degrees.

[0012] In one implementation of this disclosure, the thickness of the first portion is less than the thickness of the second portion.

[0013] In one implementation of this disclosure, the metal oxide semiconductor layer includes a first sub-metal oxide semiconductor layer and a second sub-metal oxide semiconductor layer stacked together, the first sub-metal oxide semiconductor layer being located between the substrate and the second sub-metal oxide semiconductor layer; the crystallinity of the first sub-metal oxide semiconductor layer is less than that of the second sub-metal oxide semiconductor layer; the first portion is attached to the side of the first sub-metal oxide semiconductor layer, and the second portion is attached to the side of the second sub-metal oxide semiconductor layer.

[0014] In one implementation of the present disclosure, the side surface of the first sub-metal oxide semiconductor layer is a plane; or the side surface of the first sub-metal oxide semiconductor layer is a curved surface.

[0015] In one implementation of the present disclosure, the first sub-metal oxide semiconductor layer comprises an amorphous or nanocrystalline metal oxide, and the second sub-metal oxide semiconductor layer comprises a C-axis crystalline metal oxide.

[0016] In one implementation of this disclosure, the atomic content of oxygen in the metal oxide semiconductor layer ranges from 50% to 70%.

[0017] In one implementation of this disclosure, the passivation layer includes a first sub-passivation layer and a second sub-passivation layer stacked together, the first sub-passivation layer being located between the metal oxide semiconductor layer and the second sub-passivation layer; the atomic content of hydrogen in the first sub-passivation layer ranges from 2.5% to 3%, the oxygen-silicon bond content in the second sub-passivation layer is less than 7%, and the peak bond energy of the oxygen-silicon bonds in the first sub-passivation layer is greater than 1060 cm⁻¹. -1 And not exceeding 1080cm -1 .

[0018] In one implementation of this disclosure, the stacked structure includes two electrode protective layers, which are located on opposite sides of the main metal layer; the electrode protective layers are molybdenum-niobium layers, and the main metal layer is a copper layer.

[0019] In one implementation of this disclosure, the thickness of the electrode protective layer ranges from 20 nanometers to 30 nanometers, and the thickness of the main metal layer ranges from 400 nanometers to 600 nanometers.

[0020] In one implementation of this disclosure, the metal oxide in the metal oxide semiconductor layer includes at least one of indium, gallium, zinc, tin, and praseodymium.

[0021] In one implementation of this disclosure, the metal oxide includes indium gallium zinc oxide; the ratio of indium atoms, gallium atoms and zinc atoms in the indium gallium zinc oxide is 4:2:3, or 1:3:6, or 1:1:1.

[0022] On the other hand, this disclosure provides a method for fabricating a metal-oxide-semiconductor thin-film transistor, characterized in that the method includes: providing a substrate; sequentially forming a gate, a gate insulating layer, a metal-oxide-semiconductor layer, a source and a drain, and a passivation layer on the substrate; the source and the drain are both stacked structures, the stacked structure of the source or drain includes at least a host metal layer and an electrode protection layer, the electrode protection layer is located on at least one side of the host metal layer, and the electrode protection layer comprises a metal or a metal alloy; the electrode protection layer of the source or drain is at least disposed between the metal-oxide-semiconductor layer and the host metal layer; a metal oxide layer is present between the electrode protection layer of the source or drain and the host metal layer of the source or drain, the metal element of the metal oxide layer including at least one of the metal elements of the host metal layer and the metal element of the electrode protection layer; the thickness of the metal oxide layer of the source or drain does not exceed 2% of the total thickness of the source or drain; the thickness of the metal oxide layer of the source or drain does not exceed 10% of the thickness of the electrode protection layer.

[0023] In one implementation of this disclosure, forming a metal oxide semiconductor layer includes: depositing a first metal oxide semiconductor film on the side of the gate insulating layer away from the substrate, the first metal oxide semiconductor film comprising amorphous or nanocrystalline metal oxide, the temperature range for depositing the first metal oxide semiconductor film being 100°C to 200°C, the oxygen content of the deposition gas being 1% to 30%, and the deposition power being 10 kW to 40 kW; depositing a second metal oxide semiconductor film on the side of the first metal oxide semiconductor film away from the substrate, the second sub-metal oxide semiconductor film comprising C-axis crystalline metal oxide, the temperature range for depositing the second sub-metal oxide semiconductor film being 100°C to 300°C, the oxygen content of the deposition gas being 80% to 100%, and the deposition power being 10 kW to 40 kW; and patterning the first metal oxide semiconductor film and the second sub-metal oxide semiconductor film to form the metal oxide semiconductor layer.

[0024] In one implementation of this disclosure, forming the source and drain includes: forming a first electrode protection film on the side of the metal oxide semiconductor layer away from the substrate, the thickness of the first electrode protection film being less than 25 nanometers; forming a body metal film on the side of the first electrode protection film away from the substrate; forming a second electrode protection film on the side of the body metal film away from the substrate; and patterning the first electrode protection film, the body metal film, and the second electrode protection film using wet etching to form the source and drain.

[0025] In one implementation of this disclosure, forming a passivation layer includes: introducing nitrous oxide and silicon tetrahydrode into a reaction chamber, and forming a first insulating film on the substrate using a chemical vapor deposition (CVD) apparatus. The thickness of the first insulating film ranges from 50 nanometers to 200 nanometers. During the formation of the first insulating film, the deposition power of the CVD apparatus ranges from 6 kilowatts to 10 kilowatts, the deposition pressure of the CVD apparatus is less than 1000 millitriles, the temperature of the substrate is less than 230°C, and the ratio of the nitrous oxide content to the silicon tetrahydrode content is greater than 80. The first insulating film forms a first sub-passivation layer; silicon tetrahydrode and ammonia gas are introduced into the reaction chamber, and a second insulating film is formed on the first insulating film using a chemical vapor deposition (CVD) device. The thickness of the second insulating film is less than 100 nanometers. When forming the second insulating film, the deposition power of the CVD device is in the range of 6 kW to 10 kW, the deposition pressure of the CVD device is less than 1000 mT, and the temperature of the substrate is greater than 280°C. The second insulating film forms a second sub-passivation layer, and the first sub-passivation layer and the second sub-passivation layer form the passivation layer.

[0026] On the other hand, this disclosure provides a display panel, the display panel including a substrate and a plurality of metal oxide thin film transistors disposed on the substrate.

[0027] On the other hand, this disclosure provides a display device, characterized in that the display device includes a power supply component and a display panel, wherein the power supply component is used to supply power to the display panel.

[0028] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0029] In this embodiment, the thickness of the metal oxide layer between the electrode protective layer and the main metal layer is limited to no more than 2% of the thickness of either the source or drain electrode, and no more than 10% of the thickness of the electrode protective layer. Reducing the total amount of metal oxide in the metal oxide thin-film transistor (MTBT) results in fewer hydrogen bonds reacting with the metal oxide, less loss of hydrogen bonds in the passivation layer, and a reduced impact on the passivation layer's resistance to water and oxygen. This improves the passivation layer's resistance to water and oxygen, reducing corrosion and oxidation of the MTBT; furthermore, impurities such as water vapor and hydrogen are less likely to penetrate the passivation layer into the metal oxide semiconductor layer, reducing the number of charge carriers in the metal oxide semiconductor layer and thus improving the stability of the MTBT. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a metal oxide thin-film transistor provided in an embodiment of this disclosure;

[0032] Figure 2 yes Figure 1 An enlarged view of a possible structure at point A in the middle;

[0033] Figure 3 This is provided by the embodiments of this disclosure. Figure 1 A schematic diagram of the actual structure at point A in the middle;

[0034] Figure 4 yes Figure 1 An enlarged view of another possible structure at point A;

[0035] Figure 5 This is a partial structural schematic diagram of a metal oxide thin-film transistor provided in an embodiment of this disclosure;

[0036] Figure 6 This is a schematic diagram of the bonding between an electrode protective layer and a metal oxide semiconductor layer according to an embodiment of this disclosure;

[0037] Figure 7 This is a schematic diagram of the actual structure of an electrode protective layer provided in an embodiment of this disclosure;

[0038] Figure 8 This is a graph showing the proportion of oxygen in a metal oxide semiconductor layer provided in this embodiment of the present disclosure;

[0039] Figure 9 This is a schematic diagram of the structure of a metal oxide thin-film transistor provided in an embodiment of this disclosure;

[0040] Figure 10 This is a test schematic diagram of a first insulating film formed on a large-size substrate according to an embodiment of this disclosure;

[0041] Figure 11 This is a schematic diagram of the bond energy curve of a silicon-oxygen bond provided in an embodiment of this disclosure;

[0042] Figure 12 yes Figure 11 A partial schematic diagram of region B;

[0043] Figure 13This is a schematic diagram of the structure of a metal oxide thin-film transistor provided in an embodiment of this disclosure;

[0044] Figure 14 This is a flowchart illustrating a method for fabricating a metal oxide thin-film transistor according to an embodiment of this disclosure;

[0045] Figure 15 This is a flowchart illustrating a method for fabricating a metal oxide thin-film transistor according to an embodiment of this disclosure;

[0046] Figure 16 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0048] In related technologies, oxide thin-film transistors include a gate, a gate insulating layer, a metal oxide semiconductor layer, a source, a drain, and a passivation layer stacked on a substrate, wherein the source and drain are on the same layer. Both the source and drain are stacked structures, and the stacked structure includes a host metal layer and an electrode protection layer, with the electrode protection layer located between the metal oxide semiconductor layer and the host metal layer.

[0049] However, during the fabrication of oxide thin-film transistors (TFTs), the electrode protective layer and the main metal layer are oxidized, forming a metal oxide layer between them. During the subsequent fabrication of the passivation layer, hydrogen bonds in the passivation layer can enter the metal oxide layer and react with the metal oxide, reducing the number of hydrogen bonds in the passivation layer and consequently decreasing its water and oxygen resistance. Water vapor, hydrogen, and other impurities can more easily penetrate the passivation layer into the metal oxide semiconductor layer. The metal oxide semiconductor in the metal oxide semiconductor layer reacts with these impurities, creating oxygen vacancies and affecting the stability of the metal oxide thin-film transistor.

[0050] In metal-oxide-semiconductor (MOS) thin-film transistors (TFTs), controlling the stability is crucial. Factors affecting this characteristic include controlling the target material and process conditions used to fabricate the MOS semiconductor, as well as the layers in contact with it, such as the MOS layer and passivation layer. Controlling the quality of these layers is relatively important.

[0051] In addition to ensuring the stability of metal oxide thin-film transistors meets requirements, it is also necessary to consider mass production capacity and the impact of mass production on stability to improve yield. For example, the electrode protective layer in contact with the metal oxide semiconductor layer must not crack during annealing, and there are certain requirements for the deposition rate and film quality of this electrode protective layer.

[0052] The aforementioned technical problems, in part and in part, can be optimized through the limited embodiments described below.

[0053] The metal oxide thin-film transistors provided in this disclosure are used in display areas or array substrate row driving (Gate on Array, GOA) areas.

[0054] The metal oxide thin-film transistors provided in this disclosure can be used in small-sized mobile devices, notebook computers, tablet computers, small-to-medium-sized monitors, or medium-to-large-sized televisions, displays, and other products.

[0055] The metal oxide thin film transistors provided in this disclosure can be used in the display field or the chip field. In the display field, they can be used in the fields of liquid crystal display (LCD), organic light-emitting diode (OLED), quantum dot light-emitting diode (QLED) display, micro light-emitting diode (Micro LED) display, sensing, etc., as TFTs in pixel switch TFTs, GOAs, or pixel driving circuits.

[0056] The thin-film transistors provided in this disclosure are more effective in solving the problems of products with back channel etched (BCE) structures, but are not limited to products with this structure.

[0057] This disclosure primarily uses the bottom-gate BCE structure as an example for illustration.

[0058] Figure 1 This is a schematic diagram of the structure of a metal-oxide-slim thin-film transistor provided in an embodiment of this disclosure. See also... Figure 1 The metal-oxide-semiconductor thin-film transistor 10 includes a gate 101, a gate insulator (GI) 102, a metal-oxide-semiconductor layer 103, a source 104, a drain 105, and a passivation layer (PVX) 106, sequentially disposed on a substrate 20. The source 104 and drain 105 are on the same layer and are both connected to the metal-oxide-semiconductor layer 103.

[0059] In embodiments of this disclosure, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. When source 104 and drain 105 are formed by performing one or more steps of the same patterning process in the same layer material, they are in the same layer. In another example, source 104 and drain 105 can be formed in the same layer by simultaneously performing the steps of forming source 104 and forming drain 105. The term "same layer" does not always mean that the thickness of the layer or the layers in a cross-sectional view are the same.

[0060] In this embodiment, both the source 104 and the drain 105 are stacked structures. Figure 2 yes Figure 1 An enlarged view of one possible structure at point A. See also Figure 2 The stacked structure includes at least a main metal layer 107 and an electrode protective layer 108. The electrode protective layer 108 is located on at least one side of the main metal layer 107 and comprises a metal or a metal alloy. The electrode protective layer 108 is disposed at least between the metal oxide semiconductor layer 103 and the main metal layer 107. A metal oxide layer 109 is provided between the electrode protective layer 108 and the main metal layer 107. The metal element of the metal oxide layer 109 includes at least one of the metal elements in the main metal layer 107 and the metal elements in the electrode protective layer 108.

[0061] In this embodiment of the disclosure, the metal oxide layer 109 is for either the source electrode 104 or the drain electrode 105.

[0062] For example, the main metal is copper or aluminum, and the electrode protective layer is titanium or an alloy.

[0063] The electrode protective layer is located on one or both sides of the copper or aluminum metal to protect the copper or aluminum metal from severe oxidation that would affect its electrical properties as a conductor.

[0064] Since both the electrode protective layer 108 and the main metal layer 107 contain metal elements, these metal elements will inevitably be oxidized during the manufacturing process to form an oxide layer 109. Therefore, the metal elements in the metal oxide layer 109 naturally include at least one of the metal elements in the main metal layer 107 and the metal elements in the electrode protective layer 108. While the electrode protective layer 108 and the main metal layer 107 have a certain degree of adhesion, there are still microscopic channels or gaps between them. Oxygen can easily enter between the electrode protective layer 108 and the main metal layer 107, and the chemical reaction between oxygen and metals or alloys more readily forms metal oxides, i.e., the metal oxide layer 109.

[0065] In this embodiment, the thickness D1 of the metal oxide layer 109 does not exceed 2% of the thickness D2 of either the source electrode 104 or the drain electrode 105. For example, if the thickness of the source electrode 104 is A and the thickness of the drain electrode 105 is B, and A ≤ B, then the thickness D1 of the metal oxide layer 109 ≤ A * 2%. Furthermore, the thickness D1 of the metal oxide layer 109 does not exceed 10% of the thickness D3 of the electrode protective layer 108.

[0066] The control of the aforementioned thinner metal oxide layer 109 has the following advantages:

[0067] (1) Taking IGZO as an example of a metal oxide semiconductor, due to the strong intrinsic electron migration ability inside the IGZO film, the quantity of oxygen vacancies directly determines the overall characteristic level and its stability. Therefore, the control of oxygen vacancies inside IGZO is extremely important. At the same time, IGZO is also easily affected by external water vapor or hydrogen ions, which capture H and generate oxygen vacancies, leading to an increase in charge carriers. Ultimately, this can easily cause negative bias in the characteristics, resulting in shiny sand-like defects on the panel. Therefore, controlling the injection of H and O is crucial. Generally, some H will overflow after annealing, and O will also overflow. Oxygen replenishment is usually required after the fabricated metal oxide semiconductor layer.

[0068] Most of the oxygen (O) in the metal oxide layer 109 enters during passivation layer annealing or oxygen replenishment of the metal oxide semiconductor. A portion or most of this O is transported downwards into the metal oxide semiconductor. A portion remains near the electrode protective layer and enters that layer. The entry of some oxygen absorbs nearby H, and the O and H form a small amount of H2O, preventing or inhibiting H from diffusing downwards into the metal oxide semiconductor, thus allowing more O to enter the metal oxide semiconductor, achieving sufficient oxygen replenishment. However, if too much O enters the electrode protective layer, resulting in a large amount of H2O, the electrode protective layer or the main metal layer may be corroded by H2O, which is counterproductive. Viewing the electrode from above can cause TFT failure at that location, resulting in pinhole defects in the product.

[0069] (2) In this embodiment of the present disclosure, the thickness D1 of the metal oxide layer 109 is limited to no more than 2% of the thickness D2 of either the source electrode 104 or the drain electrode 105, and the thickness D1 of the metal oxide layer 109 is limited to no more than 10% of the thickness D3 of the electrode protection layer 108. The total amount of metal oxide layer 109 in the metal oxide thin film transistor is relatively small. Within this thickness range, the amount of metal oxide that is oxidized or reduced during the formation of the passivation layer 106 is controlled, and consequently, the amount of hydrogen participating in the redox reaction is also reduced. The loss of hydrogen bonds in the passivation layer 106 is reduced, thereby reducing the impact on the water and oxygen resistance of the passivation layer 106.

[0070] In the embodiments of this disclosure, the decrease in stability of a metal oxide thin film transistor refers to the negative bias of the characteristics of the metal oxide thin film transistor, including increased threshold voltage (Vth) drift and increased leakage current.

[0071] In one implementation of the present disclosure, the thickness D1 of the metal oxide layer 109 does not exceed 0.5% of the thickness D2 of either the source electrode 104 or the drain electrode 105, and the thickness D1 of the metal oxide layer 109 does not exceed 8% of the thickness D3 of the electrode protective layer 108.

[0072] By further limiting the thickness D1 of the metal oxide layer 109, the metal oxide layer 109 is made thinner, which further reduces the total amount of metal oxide participating in the redox reaction in the metal oxide thin film transistor, which is beneficial to further improve the stability of the metal oxide thin film transistor.

[0073] For example, the thickness D1 of the metal oxide layer 109 is 0.3% of the thickness D2 of either the source electrode 104 or the drain electrode 105, and the thickness D1 of the metal oxide layer 109 is 6% of the thickness D3 of the electrode protective layer 108.

[0074] In this embodiment, the thickness of the metal oxide layer 109 is no more than 3 nanometers (nm). Experiments have shown that when the thickness of the metal oxide layer 109 is no more than 3 nanometers, both the fabrication process requirements and performance requirements of the metal oxide thin-film transistor can be simultaneously met.

[0075] For example, the thickness of the metal oxide layer 109 is 1.5 nanometers.

[0076] In the above embodiments of this disclosure, the thickness D1 of the metal oxide layer 109 is the average thickness or maximum thickness of the metal oxide layer.

[0077] It should be noted that, in this embodiment of the disclosure, the thickness of the metal oxide layer 109 refers to the thickness of the metal oxide in the 80% area, excluding the thickness of the abrupt portion, or excluding the thickness of the exposed metal oxide that is not covered by the main metal.

[0078] from Figure 2 and Figure 3 It can be seen that a small area of ​​the metal oxide layer 109 has a tip 191 extending into the interior of the main metal layer 107. At this time, the thickness of the metal oxide layer 109 does not include the thickness of the tip 191.

[0079] One embodiment of this disclosure is as follows: Figure 2 and Figure 3The structure shown does not have the tip 191 extending into the interior of the main metal layer 107, as... Figure 4 . Figure 4 It can be obtained using a transmission electron microscope (TEM).

[0080] In this embodiment, the oxygen element in the metal oxide layer 109 is distributed between the electrode protective layer 108 and the main metal layer 107, and the oxygen element distribution has a set thickness, which is the thickness of the metal oxide layer 109. That is, the oxygen element is distributed in the metal oxide layer 109.

[0081] The metal oxide layer 109 of the source electrode 104 is a film of metal oxide distributed from near the drain electrode 105 to away from the drain electrode 105, with the thickness of the metal oxide decreasing the further away from the drain electrode 105. Figure 2 It can be seen that the thickness of the metal oxide layer 109 in the source electrode 104 is variable. The closer to the drain electrode 105, the thicker the metal oxide layer 109 is, and the further away from the drain electrode 105, the thinner the metal oxide layer 109 is.

[0082] The above embodiment can also be described as extending from the region between the drain and the source towards the drain, and in this extension direction, the thickness of the metal oxide layer 109 becomes thinner and thinner.

[0083] Because there is a gap between the electrode protective layer 108 and the main metal layer 107, oxygen elements enter the interior from the edge of the gap, resulting in more metal oxide at the edge of the gap. Furthermore, the source electrode 104 and drain electrode 105 are fabricated in the same layer, and then patterning processes such as etching are used to form mutually separated source and drain electrodes 104 and 105, creating grooves between the source electrode 104, drain electrode 105, and the metal oxide semiconductor layer. During the etching process, this may affect the gap between the electrode protective layer 108 and the main metal layer 107, causing the gap to widen. This results in more oxygen elements entering the gap closer to the groove, leading to variations in the thickness of the formed metal oxide layer 109. Consequently, the further away the source electrode 104 is from the drain electrode 105, the thinner the metal oxide layer 109 becomes.

[0084] Similarly, the metal oxide layer 109 of the drain 105 is a film of metal oxide distributed from near the source 104 to away from the source 104, with the thickness of the metal oxide decreasing the further away from the source 104. The shape of the metal oxide layer 109 of the drain 105 is similar to that of the metal oxide layer 109 of the source 104, and a detailed description is omitted here.

[0085] In this embodiment of the disclosure, the metal oxide layer 109 of the source 104 and / or drain 105 presents Figure 2 The configuration shown is acceptable. "And / or" indicates at least one of the source 104 and drain 105 electrodes.

[0086] In this embodiment, the distance between the top of the electrode protection layer 108 and the bottom of the main metal layer 107, extending from the source 104 or drain 105, does not exceed the edge of the electrode protection layer 108. That is, the orthographic projection of the metal oxide layer 109 onto the surface of the substrate 10 lies within the orthographic projection of the electrode protection layer 10 onto the surface of the substrate 10. Figure 2 As shown, the portion of the metal oxide layer 109 extending to the left is still located inside the edge of the electrode protective layer 108.

[0087] Because metal oxides have low conductivity, if the distance between the top of the electrode protection layer 108 and the bottom of the main metal layer 107 is too large, it will affect the conductivity of the source 104 or the drain 105. Therefore, in this embodiment, the distance between the top of the electrode protection layer 108 and the bottom of the main metal layer 107 is limited to no more than the edge of the electrode protection layer 108. This ensures that the electrode protection layer 108 and the main metal layer 107 are not completely separated by the metal oxide layer 109, thereby guaranteeing that the source 104 and the drain 105 can conduct when the metal oxide thin film transistor is working.

[0088] For example, in the channel length direction, the metal oxide extends inward between the top of the electrode protective layer 108 and the bottom of the body metal layer 107 by a distance not exceeding the edge of the electrode protective layer 108.

[0089] When the metal oxide thin film transistor is turned on, the current between the source 104 and the drain 105 flows along the channel length direction. The metal oxide extends inward to a distance not exceeding the edge of the electrode protection layer 108, which ensures smoother current flow in the channel length direction.

[0090] In this embodiment, the orthographic projection of the source 104 onto the surface of the substrate 20 overlaps with the orthographic projection of the metal oxide semiconductor layer 103 onto the surface of the substrate 20. The width L of the overlapping portion in the channel length direction a does not exceed 3.5 micrometers (μm).

[0091] For example, the width L of the overlapping portion is 3 micrometers.

[0092] Similarly, the orthographic projection of the drain 105 onto the surface of the substrate 20 overlaps with the orthographic projection of the metal oxide semiconductor layer 103 onto the surface of the substrate 20. The width of the overlapping portion in the channel length direction a does not exceed 3.5 micrometers.

[0093] Figure 5 This is a partial structural schematic diagram of a metal-oxide-slim thin-film transistor provided in an embodiment of this disclosure. See also... Figure 5 The stacked structure includes two electrode protective layers 108, which are located on opposite sides of the main metal layer 107.

[0094] When the metal oxide thin film transistor is working, the main metal layer 107 is the main conductive layer of the source 104 and the drain 105. Electrode protection layers 108 are arranged on both sides of the main metal layer 107 to protect the main metal layer 107 and prevent damage to the main metal layer 107 during the etching process.

[0095] When the stacked structure includes two electrode protective layers 108, it is made in the manner of stacking electrode protective layer 108, main metal layer 107 and electrode protective layer 108, so there is a metal oxide layer 109 between the main metal layer 107 and the two main metal layers 107.

[0096] In this embodiment, the thickness and width of the metal oxide layer 109 are defined for a metal oxide layer 109 between a main metal layer 107 and an electrode protection layer 108 of one of the electrodes, a source electrode 104 and a drain electrode 105.

[0097] In one implementation of this embodiment, the electrode protective layer 108 is a molybdenum-niobium (MoNb) layer, and the main metal layer 107 is a copper (Cu) layer. Molybdenum-niobium has good corrosion resistance and can provide good protection, while copper has good conductivity and can ensure the conductivity of the source electrode 104 and the drain electrode 105.

[0098] At this time, the metal oxide layer 109 between the bottom electrode protective layer 108 and the main metal layer 107 includes at least one of copper oxide, molybdenum oxide and niobium oxide.

[0099] In this embodiment, the thickness of the electrode protective layer 108 ranges from 20 nanometers to 30 nanometers. This ensures the protective function of the electrode protective layer 108 while preventing it from being too thick, which could affect the yield and production cost of the display panel.

[0100] In this embodiment, the thickness of the main metal layer 107 ranges from 400 nanometers to 600 nanometers. This avoids the main metal layer 107 being too thin, which would result in too low resistance and increased power consumption, while also avoiding the main metal layer 107 being too thick, which would affect the yield rate and production cost of the display panel.

[0101] For example, the electrode protective layer 108 has a thickness of 25 nanometers and the main metal layer 107 has a thickness of 500 nanometers.

[0102] Figure 4 This is a schematic diagram illustrating the bonding of an electrode protective layer and a metal oxide semiconductor layer according to an embodiment of this disclosure. See also... Figure 4 The electrode protective layer 108 includes a first portion 181 and a second portion 182 connected together. Both the first portion 181 and the second portion 182 are located on the side surface of the metal oxide semiconductor layer 103. In a direction perpendicular to the surface of the substrate, the second portion 182 is located above the first portion 181. The slope angle α1 of the first portion 181 is greater than the slope angle α2 of the second portion 182. In this embodiment, the bottom surface of the metal oxide semiconductor layer 103 is the surface where the metal oxide semiconductor layer 103 and the gate insulating layer 102 are attached, and the top surface of the metal oxide semiconductor layer 103 is the surface opposite to the bottom surface. The side surface of the metal oxide semiconductor layer 103 connects the top surface and the bottom surface of the metal oxide semiconductor layer 103.

[0103] In this embodiment, during the fabrication of the metal oxide semiconductor layer 103, a metal oxide semiconductor thin film is first fabricated, and then the metal oxide semiconductor thin film is etched to form the metal oxide semiconductor layer 103. In some cases, the etching amount varies at different locations of the metal oxide semiconductor layer 103. For example, the bottom of the side surface of the metal oxide semiconductor layer 103 may have a larger etching amount, causing the bottom of the side surface of the metal oxide semiconductor layer 103 to be recessed inward. Since the electrode protective layer 108 covers the side surface of the metal oxide semiconductor layer 103, the inward recess of the bottom of the side surface of the metal oxide semiconductor layer 103 will cause the tilt angle of the electrode protective layer 108 to vary at different locations. In this embodiment, the second portion 182 is located above the first portion 181. The first portion 181 is attached to the bottom of the side surface of the metal oxide semiconductor layer 103, and the second portion 182 is attached to the top of the side surface of the metal oxide semiconductor layer 103. Therefore, the slope angle of the first portion 181 is greater than the slope angle of the second portion 182. The inward indentation of the side surface of the metal oxide semiconductor 103 indicates that the side surface of the metal oxide semiconductor 103 has an inward tilting tendency.

[0104] In this embodiment of the disclosure, the slope angle of the first part 181 ranges from 80 degrees (°) to 100 degrees, and the slope angle of the second part 182 ranges from 30 degrees to 60 degrees.

[0105] By limiting the slope angle of the first part 181 and the slope angle of the second part 182 to the above range, it can be ensured that the first part 181 and the second part 182 can wrap the side of the metal oxide semiconductor layer 103 without breaking it and affecting the performance of the electrode.

[0106] For example, the slope angle of the first part 181 and the slope angle of the second part 182 can be obtained by transmission electron microscopy.

[0107] In this embodiment of the disclosure, the thickness of the first portion 181 is less than the thickness of the second portion 182. The thickness of the first portion 181 is the thickness of the first portion 181 in the direction perpendicular to the slope of the first portion 181; the thickness of the second portion 182 is the thickness of the second portion 182 in the direction perpendicular to the slope of the second portion 182.

[0108] Since the bottom of the side of the metal oxide semiconductor layer 103 is recessed inward, when the electrode protection layer 108 is fabricated, the material of the source and drain electrode protection layer 108 at the position corresponding to the recessed portion will also be recessed inward, resulting in less material at the position opposite to the recessed portion, and thus a smaller thickness of the first portion 181 corresponding to the recessed portion.

[0109] See again in some examples Figure 4 The metal oxide semiconductor layer 103 includes a first sub-metal oxide semiconductor layer 131 and a second sub-metal oxide semiconductor layer 132 stacked together, with the first sub-metal oxide semiconductor layer 131 located between the substrate 20 and the second sub-metal oxide semiconductor layer 132.

[0110] Two sub-metal oxide semiconductor layers are arranged, wherein the second sub-metal oxide semiconductor layer 132 is located on the side of the first sub-metal oxide semiconductor layer 131 away from the substrate 20. In this way, the second sub-metal oxide semiconductor layer 132 can protect the first sub-metal oxide semiconductor layer 131 and prevent subsequent etching from affecting the first sub-metal oxide semiconductor layer 131.

[0111] The crystallinity of the first sub-metal oxide semiconductor layer 131 is less than that of the second sub-metal oxide semiconductor layer 132. Thus, under the same etching conditions, the etching rate of the first sub-metal oxide semiconductor layer 131 is greater than that of the second sub-metal oxide semiconductor layer 132. The first portion 181 is bonded to the side surface of the first sub-metal oxide semiconductor layer 131, and the second portion 182 is bonded to the side surface of the second sub-metal oxide semiconductor layer 132.

[0112] Because the etching rates of the first sub-metal oxide semiconductor layer 131 and the second sub-metal oxide semiconductor layer 132 are different during fabrication, and the etching rate of the first sub-metal oxide semiconductor layer 131 is faster, under the same conditions, the first sub-metal oxide semiconductor layer 131 is etched more, causing the side surface of the first sub-metal oxide semiconductor layer 131 to be recessed inward, thereby forming... Figure 4 The shape shown.

[0113] In other implementations, the metal oxide semiconductor layer 103 may also include a third sub-metal oxide semiconductor layer, wherein the first sub-metal oxide semiconductor layer 131, the second sub-metal oxide semiconductor layer 132 and the third sub-metal oxide semiconductor layer are sequentially stacked on the gate insulating layer 102.

[0114] The side surface shape of the first sub-metal oxide semiconductor layer 131 is related to the etching conditions. In one implementation of this disclosure, the side surface of the first sub-metal oxide semiconductor layer 131 is planar, such as... Figure 4 As shown.

[0115] In other implementations, the side surface 131 of the first sub-metal oxide semiconductor layer is curved.

[0116] In one implementation of this disclosure, the metal oxide in the metal oxide semiconductor layer 103 includes at least one of indium, gallium, zinc, tin, and praseodymium. Oxides of elements such as indium, gallium, zinc, tin, and praseodymium are excellent semiconductor materials, which can ensure the properties of the metal oxide semiconductor layer 103.

[0117] For example, metal oxides include indium gallium zinc oxide (IGZO).

[0118] In the embodiments disclosed herein, the ratio of indium atoms, gallium atoms, and zinc atoms in indium gallium zinc oxide is 4:2:3, or 1:3:6, or 1:1:1.

[0119] Optionally, the ratio of indium, gallium, and zinc atoms in the indium gallium zinc oxide is 4:2:3. That is, the ratio of indium atoms to gallium atoms to zinc atoms in the indium gallium zinc oxide is 4:2:3. For example, the material of the metal oxide semiconductor layer 103 can be In4Ga2Zn3O. x .

[0120] In one implementation of the present disclosure, the first sub-metal oxide semiconductor layer 131 comprises amorphous or nanocrystalline metal oxide, and the second sub-metal oxide semiconductor layer 132 comprises C-axis crystalline metal oxide.

[0121] Optionally, the material of the first sub-metal oxide semiconductor layer 131 can be amorphous or nanocrystalline In4Ga2Zn3O xThe material of the second sub-metal oxide semiconductor layer 132 can be C-axis crystalline In4Ga2Zn3O x .

[0122] In this embodiment of the disclosure, the thickness of the first sub-metal oxide semiconductor layer 131 ranges from 10 angstroms. The thickness of the second sub-metal oxide semiconductor layer 132 ranges from 10 angstroms to 400 angstroms.

[0123] In this embodiment of the disclosure, the atomic content of oxygen in the metal oxide semiconductor layer 103 ranges from 50% to 70%.

[0124] In related technologies, the oxygen atomic content in the metal oxide semiconductor layer is typically less than 50%, resulting in a large number of oxygen vacancies in the metal oxide semiconductor layer 103. These numerous oxygen vacancies increase the number of charge carriers in the metal oxide semiconductor layer 103, reducing the stability of the metal oxide thin-film transistor. In this embodiment, increasing the oxygen atomic content in the metal oxide semiconductor layer to more than 50% can reduce oxygen vacancies and improve the stability of the metal oxide thin-film transistor. Simultaneously, the oxygen atomic content in the metal oxide semiconductor layer 101 is limited to no more than 70%, thereby avoiding oxygen enrichment.

[0125] The atomic content of oxygen in the metal oxide semiconductor layer 103 can be obtained using a secondary ion mass spectrometry (SIMS) analyzer. The atomic content of oxygen in the metal oxide semiconductor layer 103 is based on actual test data.

[0126] Because metal oxide semiconductors (MOS) have strong electron mobility, the abundance or scarcity of oxygen vacancies directly determines the performance and stability of MOS thin-film transistors (TFTs). Therefore, controlling the number of oxygen vacancies within MOS materials is extremely important. In related technologies, a high number of oxygen vacancies in the MOS layer leads to lower stability in MOS thin-film transistors, resulting in display defects such as bright spots and product imperfections (mura) on the display surface of the display device. The MOS thin-film transistor provided in this disclosure effectively solves this problem.

[0127] Figure 8 This is a graph showing the proportion of each element in a passivation layer, a metal oxide semiconductor layer, and a gate insulating layer provided in an embodiment of this disclosure. Figure 8 The percentage of various elements in the passivation layer, metal oxide semiconductor layer, and gate insulating layer of the metal oxide thin film transistor in the pixel of the sand-free area is shown.

[0128] exist Figure 8 In the diagram, the vertical axis represents the elemental percentage (%), and the horizontal axis represents the film thickness (micrometers). The passivation layer surface is designated as 0, where 0–A represents the passivation layer, A–B represents the metal-oxide-semiconductor layer, and B–C represents the gate insulating layer. From… Figure 8 As can be seen, in the sand-free region, the atomic content of oxygen in the metal oxides is greater than 50%.

[0129] In this embodiment of the disclosure, when testing the elemental composition of the metal oxide semiconductor layers (A-B), the test location can be a position of the metal oxide semiconductor layer 109 in the thickness direction. Two adjacent test locations can be adjacent positions of the metal oxide semiconductor layer 109 in the thickness direction. Figure 8 It can be seen that the percentage curve of oxygen atoms at each test location in the thickness direction of the metal oxide semiconductor layer 109 can be a continuous curve. Therefore, the test locations in the thickness direction of the metal oxide semiconductor layer 109 can also be continuous test locations.

[0130] Furthermore, when testing the oxygen content at various test locations along the thickness direction of the metal oxide semiconductor layer 109, the outer sidewalls of the metal oxide semiconductor layer 109 can be tested directly after its formation. Alternatively, the metal oxide semiconductor layer 109 can be cut along its thickness direction, and the sidewalls of the cut metal oxide semiconductor layer 109 can then be tested. This disclosure does not limit the scope of the test.

[0131] Figure 9 This is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure. See also... Figure 9 The passivation layer 106 includes a first sub-passivation layer 161 and a second sub-passivation layer 162 stacked together, with the first sub-passivation layer 161 located between the metal oxide semiconductor layer 103 and the second sub-passivation layer 162.

[0132] Arranging the passivation layer 106 as two sub-passivation layers can improve the water and oxygen resistance of the passivation layer 106, reduce the entry of impurities such as water, oxygen, and hydrogen into the metal oxide semiconductor layer 103, reduce the number of charge carriers in the metal oxide semiconductor layer 103, improve the stability of the metal oxide thin film transistor, and improve the display failure phenomenon of the display device.

[0133] The first sub-passivation layer 161 is an inorganic insulating film containing at least silicon (Si) and oxygen. In actual testing, the first sub-passivation layer 161 also contains a small amount of nitrogen (N), but the atomic percentage of nitrogen is very small; therefore, the first sub-passivation layer 161 can be simply referred to as silicon oxide (SiO2). x )layer.

[0134] In this embodiment, the atomic content (H%) of hydrogen in the first sub-passivation layer 161 ranges from 2.5% to 3%. Limiting the range of hydrogen atomic content in the first sub-passivation layer 161 results in less hydrogen in the first sub-passivation layer 161. Consequently, less hydrogen enters the metal oxide semiconductor layer 103 during fabrication, occupying less oxygen in the semiconductor material. Therefore, there are fewer oxygen vacancies in the semiconductor material, fewer charge carriers in the metal oxide semiconductor layer 101, and a reduced impact on the stability of the metal oxide thin-film transistor.

[0135] Table 1 shows the relationship between the atomic content of hydrogen in the first sub-passivation layer 161 and the display defects.

[0136] Table 1

[0137]

[0138] from Figure 1 As can be seen from the embodiments of this disclosure, when the metal oxide thin-film transistor is applied to a display device, although the thickness uniformity is reduced, the number of driving bright spots and speckle-like inclusions is reduced to 0.0%, which greatly improves display defects such as driving bright spots and speckle-like inclusions. The reduced hydrogen (H2) content at the edge of the first sub-passivation layer indicates that the atomic content of hydrogen in the first sub-passivation layer is reduced, ensuring that the atomic content of hydrogen in the first sub-passivation layer is between 2.5% and 3%.

[0139] In this embodiment of the disclosure, the peak bond energy of the silicon-oxygen bond (Si-O) in the first sub-passivation layer 161 is greater than 1060 cm⁻¹. -1 And not exceeding 1080cm -1 The higher the bond energy peak of the oxygen-silicon bond in the first sub-passivation layer 161, the more oxygen and silicon are present in the first sub-passivation layer 161, and the less hydrogen atoms are present in the first sub-passivation layer 161. The hydrogen atom content in the first sub-passivation layer 161 can be controlled by controlling the bond energy peak of the oxygen-silicon bond in the first sub-passivation layer 161.

[0140] In the embodiments of this disclosure, when preparing a display panel, it can be prepared on a large-size substrate and multiple display panels can be obtained by cutting. Figure 10 This is a test schematic diagram of a first insulating film formed on a large-size substrate according to an embodiment of this disclosure. Figure 10 This is used to represent the percentage of hydrogen atoms in the center and edge regions of the first sub-passivation layer formed on the large-size substrate, which can be used to test the bond energy peak of the silicon-oxygen bonds in the center and edge regions of the first sub-passivation layer formed on the large-size substrate.

[0141] Table 2 shows the relationship between the peak bond energy of the oxygen-silicon bond in the first sub-passivation layer 161 and the atomic content of hydrogen.

[0142] Table 2

[0143] Test location peak bond energy of silicon-oxygen bond Hydrogen atom content (H%) Middle area 1060.7 2.9％ Edge area 1053.0 4.1％

[0144] As shown in Table 2, the Si-O bond energy peak value in the central region is larger than that in the edge region. Therefore, the H% in the central region is lower than that in the edge region, resulting in less hydrogen available for reaction with metal oxides in the central region. A higher oxygen-silicon bond energy peak value corresponds to a lower hydrogen atomic content. To ensure that the hydrogen atomic content in the first sub-passivation layer 161 is less than 3.0%, the oxygen-silicon bond energy peak value in the first sub-passivation layer 161 needs to be greater than 1060 cm⁻¹. -1 .

[0145] Figure 11 This is a schematic diagram of the bond energy curve of a silicon-oxygen bond provided in an embodiment of this disclosure. Refer to Table 2 above and... Figure 11 It can be seen that the peak bond energy of the silicon-oxygen bonds in the central region of the first sub-passivation layer formed on the large-size substrate is 1060.7 cm⁻¹. -1 The first sub-passivation layer formed on the large-size substrate has a silicon-oxygen bond energy peak of 1053.7 cm⁻¹ in the edge region of the large-size substrate. -1 .

[0146] The test results of the silicon-oxygen bond bond energy peak and hydrogen atom content show that the silicon-oxygen bond energy peak in the central region is greater than that in the edge region, and the hydrogen atom percentage in the central region is lower than that in the edge region (the hydrogen atom percentage in the central region is less than 3%, while the hydrogen atom percentage in the edge region is greater than 3%). This indicates that when forming the first sub-passivation layer on a large-size substrate, the film quality of the first sub-passivation layer located in the central region is better than that in the edge region. In other words, the smaller the size of the large-size substrate during fabrication, the higher the quality of the first sub-passivation layer can be obtained. Therefore, a smaller substrate size can be used to fabricate a smaller number of display panels at a time, while ensuring production capacity.

[0147] In this embodiment of the disclosure, when the silicon-oxygen bonds (Si-O) in the first sub-passivation layer 161 are tested using a fourier transform infrared spectroscopy (FTIR) instrument, the bond energy peak value of the silicon-oxygen bonds can be in the range of 1060 cm⁻¹. -1 Up to 1080cm -1 . Figure 12 yes Figure 11 A partial schematic diagram of region B. See also... Figure 12 When the silicon-oxygen bonds (Si-O) in the first sub-passivation layer 161 were tested using an infrared absorption spectrometer, the peak bond energy of the silicon-oxygen bonds could reach a range of 1063 cm⁻¹. -1 Up to 1067cm -1 Among them, cm -1 Used to indicate the number of waves contained in 1 cm. The bond energy peak of the silicon-oxygen bond is used to indicate the bond energy value at which the absorbance is maximum.

[0148] In this embodiment, the thickness of the first sub-passivation layer 161 is less than 2000 angstroms. Because the thickness of the first sub-passivation layer 161 is small, on the one hand, the production capacity of the first sub-passivation layer 161 is high, reducing costs and improving mass production. On the other hand, it avoids the formation of cracks in the area overlapping with the source electrode 104 or drain electrode 105 during high-temperature annealing after the formation of the first sub-passivation layer 161, as the thicker the first sub-passivation layer 161 has higher internal stress. Since these cracks may expose the source electrode 104 or drain electrode 105, their appearance may directly lead to the oxidation of the source electrode 104 or drain electrode 105, resulting in an increase in the metal oxide layer 109 in the source electrode 104 or drain electrode 105. Furthermore, hydrogen elements in the film layer located above the source 104 or drain may enter the surface of the metal oxide semiconductor layer 103 that is in contact with the source 104 or drain 105 through the source 104 or drain 105, causing the characteristics of the metal oxide thin film transistor to deteriorate, and in severe cases, causing sand spots to appear on the display panel.

[0149] In this embodiment, the first sub-passivation layer 161 can be formed on the substrate 20 using a chemical vapor deposition (CVD) apparatus. Furthermore, the gas used to prepare the first sub-passivation layer 161 may include N₂O (nitrous oxide) and SiH₄ (silicon tetrahydroxide). The N₂O and SiH₄ react to deposit silicon oxide, meaning the first sub-passivation layer 161 can be a single-layer silicon oxide film. This single-layer silicon oxide film can be a film with the same film quality (referred to as film mass) prepared using the same process conditions.

[0150] In some embodiments, the second sub-passivation layer 162 may consist only of a silicon oxide film, or only of a silicon nitride (SiNx) film, or may include a silicon oxide film and a silicon nitride film sequentially stacked on one side of the first sub-passivation layer 161, or may include a silicon oxide film, a silicon oxynitride film and a silicon nitride film sequentially stacked on one side of the first sub-passivation layer 161.

[0151] Optionally, an organic resin (Resin) may be present between the first sub-passivation layer 161 and the second sub-passivation layer 162. Of course, the organic resin may not be present between the first sub-passivation layer 161 and the second sub-passivation layer 162.

[0152] As an alternative implementation, if the second sub-passivation layer 162 consists only of a silicon nitride film, then the first sub-passivation layer 161 and the second sub-passivation layer 162 can be distinguished based on the material of the film. Furthermore, the second sub-passivation layer 162 can remove hydrogen from the silicon nitride film during high-temperature annealing.

[0153] For example, if the characteristics of the metal oxide thin film transistor can meet the basic requirements, then in order to increase production capacity and reduce costs, a silicon nitride film can be formed directly on the first sub-passivation layer 161 (which is a single-layer silicon oxide film).

[0154] As an alternative implementation, given the high performance requirements of metal-oxide-slim transistors, a second silicon oxide film with a different composition than the first silicon oxide film can be deposited on the first sub-passivation layer 161 (the first sub-passivation layer 161 is a single-layer silicon oxide film, referred to as the first silicon oxide film layer). Furthermore, a silicon nitride film layer is present on the side of the second silicon oxide film layer away from the first sub-passivation layer 161. The second silicon oxide film layer and the silicon nitride film layer can both belong to the second sub-passivation layer 162.

[0155] It should be noted that the difference in film quality between the first silicon oxide film and the second silicon oxide film can be used to represent at least one of the following differences: the percentage of oxygen atoms in the first silicon oxide film is significantly different from the percentage of oxygen atoms in the second silicon oxide film; the deposition rate when forming the first silicon oxide film is significantly different from the deposition rate when forming the second silicon oxide film; the density of the first silicon oxide film is significantly different from the density of the second silicon oxide film.

[0156] Optionally, the thickness of the silicon oxide film in the second sub-passivation layer 162 can be greater than the thickness of the first sub-passivation layer 161, for example, the thickness of the silicon oxide film in the second sub-passivation layer 162 can be 3000 angstroms. The thickness of the silicon nitride film in the second sub-passivation layer 162 can be 1000 angstroms.

[0157] As another alternative implementation, the second sub-passivation layer 162 may include a silicon oxide film, a silicon oxynitride film, and a silicon nitride film stacked on one side of the first sub-passivation layer 161.

[0158] In this implementation, the silicon oxide film in the second sub-passivation layer 162 can function the same as the second silicon oxide film in the previous implementation. Furthermore, during the high-temperature annealing process, the second sub-passivation layer 162 can remove hydrogen elements from its silicon oxynitride and silicon nitride films, and replenish oxygen elements from the first sub-passivation layer 161 into the metal oxide semiconductor layer 103.

[0159] In this embodiment, the primary film layer preventing external hydrogen from entering the critical film layer is the second sub-passivation layer 162. The structure of this second sub-passivation layer 162 can be as described in the above embodiments. That is, the first sub-passivation layer 161 (a single-layer silicon oxide film with a thickness of less than 2000 angstroms) in this embodiment is not equivalent to the first passivation layer of the prior art (a silicon oxide film with a thickness ranging from 3000 angstroms to 5000 angstroms).

[0160] In this embodiment, the content of oxygen-silicon bonds (Si-H) in the second sub-passivation layer 162 is less than 7%. The less oxygen-silicon bonds in the second sub-passivation layer 162, the less hydrogen is present in the second sub-passivation layer 162. The atomic content of hydrogen in the second sub-passivation layer 162 is controlled by controlling the content of oxygen-silicon bonds in the second sub-passivation layer 162.

[0161] In this embodiment of the disclosure, the substrate 20 may be a glass substrate or a polyimide (PI) substrate.

[0162] In this embodiment of the disclosure, the material of the gate 101 includes at least one of nickel, nickel-manganese alloy, nickel-chromium alloy, and nickel-molybdenum-iron alloy.

[0163] Figure 13 This is a schematic diagram of the structure of a metal-oxide-slim thin-film transistor provided in an embodiment of this disclosure. See also... Figure 13 The gate metal insulating layer may include a first sub-gate insulating layer 121 and a second sub-gate insulating layer 120, wherein the first sub-gate insulating layer 121 is attached to the gate 101 and the second sub-gate insulating layer 120 is attached to the metal oxide semiconductor layer 103.

[0164] For example, the first sub-gate insulating layer 121 is a silicon nitride layer, and the second sub-gate insulating layer 120 is a silicon oxide layer.

[0165] Figure 14 This is a flowchart illustrating a method for fabricating a metal-oxide-slim thin-film transistor according to an embodiment of this disclosure. This method can be used to fabricate the metal-oxide-slim thin-film transistor provided in the above embodiments, for example, for preparing... Figure 1 The metal-oxide-slim thin-film transistor shown. (Reference) Figure 14 The method may include:

[0166] In step 301, a substrate is provided.

[0167] For example, the substrate can be a glass substrate or a polyimide substrate.

[0168] In step 302, a gate electrode, a gate insulating layer, a metal oxide semiconductor layer, a source electrode, a drain electrode, and a passivation layer are sequentially formed on the substrate. Both the source and drain electrodes are stacked structures, each including at least a host metal layer and an electrode protection layer. The electrode protection layer is located on at least one side of the host metal layer and comprises a metal or metal alloy. The electrode protection layer is at least disposed between the metal oxide semiconductor layer and the host metal layer. A metal oxide layer is present between the electrode protection layer and the host metal layer, and the metal element in the metal oxide layer includes at least one of the metal elements in the host metal layer and the metal element in the electrode protection layer. The thickness of the metal oxide layer does not exceed 2% of the total thickness of the source or drain electrode, and the thickness of the metal oxide layer does not exceed 8% of the thickness of the electrode protection layer.

[0169] Figure 15 This is a flowchart illustrating a method for fabricating a metal-oxide-slim thin-film transistor according to an embodiment of this disclosure. See also... Figure 15 The method includes:

[0170] In step 401, a substrate is provided.

[0171] In step 402, a gate is formed on the substrate.

[0172] For example, a gate film can be formed on one side of a substrate first, and then the gate film can be patterned to obtain the gate.

[0173] In step 403, a gate insulating layer is formed on the side of the gate away from the substrate.

[0174] For example, after the gate is formed, a gate insulating layer may be formed on the side of the gate away from the substrate to insulate the gate from the subsequently formed source and drain.

[0175] Optionally, the gate insulating layer may include a first sub-gate insulating layer and a second sub-gate insulating layer sequentially stacked along a direction away from the substrate. The first sub-gate insulating layer may be made of silicon nitride, and the second sub-gate insulating layer may be made of silicon oxide.

[0176] In step 404, a first metal oxide semiconductor thin film is deposited on the side of the gate insulating layer away from the substrate.

[0177] After forming the gate insulating layer, a first metal oxide semiconductor thin film can be deposited on the side of the gate insulating layer away from the substrate, and the first metal oxide semiconductor thin film can cover the entire substrate.

[0178] Optionally, a first metal oxide semiconductor thin film can be formed on the side of the gate insulating layer away from the substrate using a magnetron sputtering apparatus. This first metal oxide semiconductor thin film can be prepared using a material with high mobility; for example, the material of the first metal oxide semiconductor thin film is an amorphous or nanocrystalline metal oxide.

[0179] Optionally, the material of the first metal oxide semiconductor thin film can be amorphous or nanocrystalline In4Ga2Zn3O x ,

[0180] In this embodiment of the disclosure, when forming the first metal oxide semiconductor thin film, the temperature of the substrate can range from 100°C to 200°C, the oxygen content of the sputtering gas of the magnetron sputtering apparatus can range from 1% to 30%, and the power of the magnetron sputtering apparatus can range from 10 kilowatts (KW) to 40 kilowatts (KW). The thickness of the first metal oxide semiconductor thin film ranges from 10 angstroms to 300 angstroms.

[0181] In step 405, a second metal oxide semiconductor film is deposited on the side of the first metal oxide semiconductor film away from the substrate.

[0182] Optionally, a second metal oxide semiconductor film can be formed on the side of the first metal oxide semiconductor film away from the substrate using a magnetron sputtering apparatus. The material of the first metal oxide semiconductor film is a c-axis crystalline metal oxide.

[0183] Optionally, the material of the second metal oxide semiconductor thin film can be c-axis crystalline In4Ga2Zn3O x .

[0184] In this embodiment of the disclosure, when forming the second metal oxide semiconductor thin film, the temperature of the substrate can be in the range of 100°C to 300°C, the oxygen content of the sputtering gas of the magnetron sputtering equipment can be in the range of 80% to 100%, and the power of the magnetron sputtering equipment can be in the range of 10KW to 40KW. The thickness of the second metal oxide semiconductor thin film ranges from 10 angstroms to 400 angstroms.

[0185] In step 406, the first metal oxide semiconductor film and the second sub-metal oxide semiconductor film are patterned to form a metal oxide semiconductor layer.

[0186] In this embodiment of the disclosure, after forming a metal oxide semiconductor thin film, the metal oxide semiconductor thin film can be patterned using a photolithography process to obtain a metal oxide semiconductor layer. The orthogonal projection of the metal oxide semiconductor layer onto the substrate at least partially overlaps with the orthogonal projection of the gate onto the substrate. This photolithography process may include processes such as photoresist (PR) coating, exposure, development, etching, and photoresist stripping. This photolithography process can also be referred to as a mask process.

[0187] Optionally, the metal oxide semiconductor thin film in steps 404 and 405 above includes a first metal oxide semiconductor thin film and a second sub-metal oxide semiconductor thin film. Therefore, the patterning process of the metal oxide semiconductor thin film in step 406 can refer to patterning the first metal oxide semiconductor thin film and the second sub-metal oxide semiconductor thin film interchangeably. Specifically, patterning the first metal oxide semiconductor thin film yields a first metal oxide semiconductor layer, and patterning the second metal oxide semiconductor thin film yields a second metal oxide semiconductor layer.

[0188] In this embodiment of the disclosure, when fabricating the metal oxide semiconductor layer, the oxygen addition amount of the overall metal oxide semiconductor layer must be controlled to be greater than 55% in order to ensure that the atomic content of oxygen element in the final metal oxide semiconductor layer is greater than 50%.

[0189] In step 407, a first electrode protective film is formed on the side of the metal oxide semiconductor layer away from the substrate.

[0190] The thickness of the protective film for the first electrode is less than 25 nanometers.

[0191] In this embodiment of the disclosure, after the metal oxide semiconductor layer is prepared, a first electrode protection film can be formed on the side of the metal oxide semiconductor layer away from the substrate. The material of the first electrode protection film can be molybdenum or niobium.

[0192] In step 408, a main metal film is formed on the side of the first electrode protective film away from the substrate.

[0193] For example, the material of the main metal film can be copper.

[0194] In step 409, a second electrode protective film is formed on the side of the main metal film away from the substrate.

[0195] For example, the material of the second electrode protective film can be molybdenum-niobium.

[0196] In step 410, wet etching is used to pattern the first electrode protective film, the main metal film, and the second electrode protective film to form the source and drain.

[0197] In this embodiment, after forming the first electrode protection film, the main metal film, and the second electrode protection film, the source and drain films can be patterned using photolithography to obtain the source and drain. Specifically, when etching the source and drain films, a wet etching rate (WER) can be used to obtain the source and drain. In this implementation, the source and drain are fabricated using the same patterning process.

[0198] In this embodiment of the disclosure, the wet etching over-etching amount is controlled to be less than 50% to ensure the formation of a more perfect source and drain morphology. At the same time, the first electrode protective film and the main metal film will not produce undercut phenomenon, reducing the formation of metal oxide layer.

[0199] In this embodiment, the orthographic projection of the source electrode on the substrate overlaps with the orthographic projection of the metal oxide semiconductor layer on the substrate. Similarly, the orthographic projection of the drain electrode on the substrate overlaps with the orthographic projection of the metal oxide semiconductor layer on the substrate.

[0200] Furthermore, the thickness of the fabricated source and drain electrodes can be greater than 3000 angstroms and less than 6000 angstroms. Also, the slope angles of both the fabricated source and drain electrodes are less than 60°. Designing both the source and drain slope angles to be small avoids cracking of the first insulating film formed on the side of the source and drain electrodes away from the substrate at the slope points of the source and drain electrodes, thus ensuring the yield of the metal-oxide-slim thin-film transistor.

[0201] In step 411, nitrous oxide (N2O) and silicon tetrahydrogen (SiH4) are introduced into the reaction chamber, and a first insulating film is formed on the substrate using a chemical vapor deposition apparatus.

[0202] In this embodiment of the disclosure, the various film layers of the metal oxide thin-film transistor can be fabricated within a reaction chamber. During the formation of the first insulating film, N₂O and SiH₄ can be introduced into the reaction chamber. Optionally, the ratio of N₂O content to SiH₄ content can be greater than 78. For example, the ratio of N₂O content to SiH₄ content can be 80.

[0203] By designing a relatively large ratio of N2O content to SiH4 content, the peak value of silicon-oxygen bonds in the prepared first insulating film can reach 1060 cm⁻¹ in infrared absorption spectroscopy. -1 Up to 1080cm -1Within the range. Typically, the Si-O peak value reaches 1060 cm⁻¹. -1 The above measures can prevent the high content of impurities (such as H (hydrogen) in the first insulating film from causing instability in the characteristics of metal oxide thin film transistors.

[0204] In this embodiment of the disclosure, the deposition rate of the first insulating film is related to the deposition power of the chemical vapor deposition equipment, the deposition pressure, and the temperature of the substrate during the preparation of the first insulating film.

[0205] Optionally, the deposition power and deposition pressure of the chemical vapor deposition (CVD) apparatus can be relatively low when forming the first insulating film. For example, the deposition power of the CVD apparatus ranges from 6 kW to 10 kW, and the deposition pressure is less than 1000 mT (millot). The substrate temperature ranges from 200°C to 250°C, for example, 230°C, when forming the first insulating film.

[0206] For example, the material of the first insulating film is silicon oxide.

[0207] In step 412, silicon tetrahydrode and ammonia are introduced into the reaction chamber, and a second insulating film is formed on the first insulating film using a chemical vapor deposition device.

[0208] In this embodiment, a second insulating film can be formed on the side of the first insulating film away from the substrate using a chemical vapor deposition (CVD) apparatus. Furthermore, the preparation conditions for the second insulating film differ from those for the first insulating film. The second insulating film is a nitrogen-containing inorganic insulating film. For example, the second insulating film is a silicon nitride layer.

[0209] This disclosure also provides a display panel, which may include: a substrate, and a plurality of metal oxide thin-film transistors as provided in the above embodiments disposed on the substrate, wherein the metal oxide thin-film transistors may be... Figures 1 to 7 as well as Figure 9 and Figure 10 Any of the metal oxide thin-film transistors shown.

[0210] Optionally, the display panel may further include pixel units located on the side of the second insulating film of the metal oxide thin-film transistor away from the substrate. The pixel unit may include at least a pixel electrode, which may be made of indium tin oxide (ITO).

[0211] Figure 16 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. (Reference) Figure 16The display device may include a power supply component 2 and a display panel 1 as provided in the above embodiments. The power supply component 2 is used to supply power to the display panel 1.

[0212] Optionally, the display device can be any product or component with display and fingerprint recognition functions, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame or navigator.

[0213] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A metal oxide thin-film transistor, characterized in that, The metal oxide thin film transistor includes a gate, a gate insulating layer, a metal oxide semiconductor layer, a source and a drain, and a passivation layer, which are sequentially located on a substrate. Both the source and the drain are stacked structures. The stacked structure of the source or drain includes at least a main metal layer and an electrode protective layer. The electrode protective layer is located on at least one side of the main metal layer and contains metal or metal alloy. The source or drain electrode protective layer is disposed at least between the metal oxide semiconductor layer and the main metal layer; A metal oxide layer is provided between the electrode protection layer of the source or drain and the main metal layer of the source or drain, wherein the metal element of the metal oxide layer includes at least one of the metal elements of the main metal layer and the metal elements in the electrode protection layer; The thickness of the metal oxide layer of the source or drain electrode does not exceed 2% of the thickness of either the source or the drain electrode. The thickness of the metal oxide layer of the source or drain electrode does not exceed 10% of the thickness of the electrode protective layer.

2. The metal oxide thin-film transistor according to claim 1, characterized in that, The thickness of the metal oxide layer of the source or drain electrode does not exceed 0.5% of the thickness of either the source or the drain electrode. The thickness of the metal oxide layer of the source or drain electrode does not exceed 8% of the thickness of the electrode protective layer.

3. The metal oxide thin-film transistor according to claim 1 or 2, characterized in that, The thickness of the metal oxide layer of the source or drain electrode does not exceed 3 nanometers.

4. The metal-oxide-slim thin-film transistor according to any one of claims 1 to 3, characterized in that, The oxygen element distribution in the metal oxide layer of the source or drain electrode is located between the electrode protective layer and the main metal layer, and the oxygen element distribution has a set thickness, which is the thickness of the metal oxide layer; The metal oxide layer of the source electrode is a film of metal oxide distributed from near the drain electrode to away from the drain electrode, and the thickness of the metal oxide is smaller the farther away from the drain electrode; and / or The metal oxide layer of the drain electrode is a film of metal oxide distributed from near the source electrode to away from the source electrode, and the thickness of the metal oxide layer is smaller the farther away from the source electrode.

5. The metal oxide thin-film transistor according to claim 4, characterized in that, The metal oxide extends from the side of the source or drain electrode into the electrode protection layer and the main metal layer at a distance not exceeding the edge of the electrode protection layer.

6. The metal oxide thin-film transistor according to claim 4, characterized in that, Along the length of the channel, the metal oxide extends inward between the top of the electrode protective layer and the bottom of the main metal layer by a distance not exceeding the edge of the electrode protective layer.

7. The metal-oxide thin-film transistor according to any one of claims 1 to 6, characterized in that, The source or drain electrode protection layer includes a first part and a second part connected together. The first part and the second part are both located on the side of the metal oxide semiconductor layer. In a direction perpendicular to the surface of the substrate, the second part is located above the first part, and the slope angle of the first part is greater than that of the second part.

8. The metal oxide thin-film transistor according to claim 7, characterized in that, The slope angle of the first part ranges from 80 degrees to 100 degrees, and the slope angle of the second part ranges from 30 degrees to 60 degrees.

9. The metal oxide thin-film transistor according to claim 7, characterized in that, The thickness of the first part is less than the thickness of the second part.

10. The metal oxide thin-film transistor according to claim 7, characterized in that, The metal oxide semiconductor layer includes a first sub-metal oxide semiconductor layer and a second sub-metal oxide semiconductor layer stacked together, wherein the first sub-metal oxide semiconductor layer is located between the substrate and the second sub-metal oxide semiconductor layer. The crystallinity of the first sub-metal oxide semiconductor layer is less than that of the second sub-metal oxide semiconductor layer; The first portion is attached to the side of the first sub-metal oxide semiconductor layer, and the second portion is attached to the side of the second sub-metal oxide semiconductor layer.

11. The metal-oxide thin-film transistor according to claim 10, characterized in that, The side surface of the first sub-metal oxide semiconductor layer is planar; or, the side surface of the first sub-metal oxide semiconductor layer is curved.

12. The metal oxide thin-film transistor according to claim 10, characterized in that, The first sub-metal oxide semiconductor layer comprises amorphous or nanocrystalline metal oxide, and the second sub-metal oxide semiconductor layer comprises C-axis crystalline metal oxide.

13. The metal-oxide thin-film transistor according to any one of claims 1 to 12, characterized in that, The atomic content of oxygen in the metal oxide semiconductor layer ranges from 50% to 70%.

14. The metal-oxide thin-film transistor according to any one of claims 1 to 13, characterized in that, The passivation layer includes a first sub-passivation layer and a second sub-passivation layer stacked together, wherein the first sub-passivation layer is located between the metal oxide semiconductor layer and the second sub-passivation layer; The atomic content of hydrogen in the first sub-passivation layer ranges from 2.5% to 3%, the oxygen-silicon bond content in the second sub-passivation layer is less than 7%, and the peak bond energy of the oxygen-silicon bonds in the first sub-passivation layer is greater than 1060 cm⁻¹. -1 And not exceeding 1080cm -1 .

15. The metal-oxide-slim thin-film transistor according to any one of claims 1 to 14, characterized in that, The stacked structure includes two electrode protective layers, which are located on opposite sides of the main metal layer. The electrode protective layer is a molybdenum-niobium layer, and the main metal layer is a copper layer.

16. The metal-oxide-slim thin-film transistor according to any one of claims 1 to 15, characterized in that, The thickness of the electrode protective layer ranges from 20 nanometers to 30 nanometers, and the thickness of the main metal layer ranges from 400 nanometers to 600 nanometers.

17. The metal-oxide-slim thin-film transistor according to any one of claims 1 to 16, characterized in that, The metal oxide in the metal oxide semiconductor layer includes at least one of indium, gallium, zinc, tin, and praseodymium.

18. The metal-oxide thin-film transistor according to claim 17, characterized in that, The metal oxide includes indium gallium zinc oxide; The ratio of indium atoms, gallium atoms, and zinc atoms in the indium gallium zinc oxide is 4:2:3, or 1:3:6, or 1:1:

1.

19. A method for fabricating a metal oxide thin-film transistor, characterized in that, The method includes: Provide a substrate; A gate electrode, a gate insulating layer, a metal-oxide-semiconductor layer, a source electrode, a drain electrode, and a passivation layer are sequentially formed on the substrate. Both the source and drain electrodes are stacked structures, each including at least a host metal layer and an electrode protection layer. The electrode protection layer is located on at least one side of the host metal layer and comprises a metal or metal alloy. The electrode protection layer is at least disposed between the metal-oxide-semiconductor layer and the host metal layer. A metal oxide layer is located between the electrode protection layer and the host metal layer, and the metal element in the metal oxide layer includes at least one of the metal elements in the host metal layer and the metal element in the electrode protection layer. The thickness of the metal oxide layer of the source or drain electrode does not exceed 2% of the total thickness of the source or drain electrode, and the thickness of the metal oxide layer of the source or drain electrode does not exceed 10% of the thickness of the electrode protection layer.

20. The manufacturing method according to claim 19, characterized in that, Forming a metal-oxide-semiconductor layer includes: A first metal oxide semiconductor film is deposited on the side of the gate insulating layer away from the substrate. The first metal oxide semiconductor film includes amorphous or nanocrystalline metal oxide. The temperature range for depositing the first metal oxide semiconductor film is 100 degrees Celsius to 200 degrees Celsius, the oxygen content of the deposition gas ranges from 1% to 30%, and the deposition power ranges from 10 kilowatts to 40 kilowatts. A second metal oxide semiconductor film is deposited on the side of the first metal oxide semiconductor film away from the substrate. The second metal oxide semiconductor film includes a C-axis crystalline metal oxide. The temperature range for depositing the second metal oxide semiconductor film is 100 degrees Celsius to 300 degrees Celsius, the oxygen content of the deposition gas ranges from 80% to 100%, and the deposition power ranges from 10 kW to 40 kW. The first metal oxide semiconductor film and the second metal oxide semiconductor film are patterned to form the metal oxide semiconductor layer.

21. The manufacturing method according to claim 19, characterized in that, The formation of the source and drain includes: A first electrode protection film is formed on the side of the metal oxide semiconductor layer away from the substrate, and the thickness of the first electrode protection film is less than 25 nanometers. A main metal film is formed on the side of the first electrode protective film away from the substrate. A second electrode protective film is formed on the side of the main metal film away from the substrate. The first electrode protection film, the main metal film, and the second electrode protection film are patterned using wet etching to form the source and the drain.

22. The manufacturing method according to claim 19, characterized in that, Forming a passivation layer includes: Nitrous oxide and silicon tetrahydrogen are introduced into a reaction chamber, and a first insulating film is formed on the substrate using a chemical vapor deposition (CVD) apparatus. The thickness of the first insulating film ranges from 50 nanometers to 200 nanometers. During the formation of the first insulating film, the deposition power of the CVD apparatus ranges from 6 kilowatts to 10 kilowatts, the deposition pressure of the CVD apparatus is less than 1000 millitrile, the temperature of the substrate is less than 230°C, and the ratio of the nitrous oxide content to the silicon tetrahydrogen content is greater than 80. The first insulating film forms a first sub-passivation layer. Silicon tetrahydrode and ammonia gas are introduced into the reaction chamber, and a second insulating film is formed on the first insulating film using a chemical vapor deposition (CVD) device. The thickness of the second insulating film is less than 100 nanometers. When forming the second insulating film, the deposition power of the CVD device is in the range of 6 kW to 10 kW, the deposition pressure of the CVD device is less than 1000 mT, and the temperature of the substrate is greater than 280°C. The second insulating film forms a second sub-passivation layer, and the first sub-passivation layer and the second sub-passivation layer form the passivation layer.

23. A display panel, characterized in that, The display panel includes a substrate and a plurality of metal oxide thin-film transistors as described in any one of claims 1 to 18 disposed on the substrate.

24. A display device, characterized in that, The display device includes a power supply component and a display panel as described in claim 23, wherein the power supply component is used to supply power to the display panel.

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