Method and related equipment for calibrating timing errors of control signals of multiple quantum bits

Abstract

This application belongs to the field of quantum information technology and specifically discloses a method and related equipment for calibrating the timing error of control signals of multiple quantum bits. The method is applied to a quantum chip with at least two quantum bits. The calibration method is to obtain the relative delay between the control signals of each quantum bit, wherein the relative delay is the time difference between the timing start moments of the control signals of each quantum bit; the relative delay is used to calibrate the timing start moments of the control signals of each quantum bit so that the control signals of each quantum bit can arrive at the quantum chip at the same time, wherein the control signals are quantum state control signals or frequency control signals. The application can effectively calibrate the timing error of the control signals of the quantum bits caused by line transmission delay, so that the timing start points of the control signals arriving at multiple quantum bits in the quantum chip are strictly aligned, meeting the timing logic requirements.

Description

Technical Field

[0001] The present application relates to the field of quantum information, and in particular to a method for calibrating timing errors of control signals of multiple quantum bits and related equipment. Background Art

[0002] A quantum computer is a physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store, and process quantum information. The quantum chip, the core component of a quantum computer, integrates multiple qubits. To ensure the proper functioning of these qubits, a quantum control system must be established. Within this control system, multiple signaling devices provide various control signals, such as frequency control signals and quantum state control signals, to each qubit. When executing a quantum computing task on a quantum chip, frequency control and quantum state control signals must first be applied to the qubit to execute the calculation. To obtain the result, a read signal must also be applied to read the result. During the control and readout of the qubits, the various signals applied have corresponding timing sequences. The timing of the various signals reaching the qubits in the quantum chip must strictly conform to timing logic requirements to ensure the smooth operation of the quantum computing task.

[0003] In the related art, each qubit in a quantum chip is equipped with an XY control terminal and a Z control terminal. Correspondingly, a quantum control system is equipped with multiple XY and Z circuits, connecting the XY and Z control terminals of each qubit, respectively. Quantum state control signals and frequency control signals are applied to each qubit via the XY and Z circuits, respectively. However, due to the varying cable lengths of different circuits and the addition of different filters and microwave components, the transmission delays of the qubit control signals along these circuits vary. This results in errors in the timing of the signals reaching the qubits in the quantum chip due to transmission delays. Furthermore, it is difficult for the control signals for multiple qubits used to execute the same quantum computing task to arrive simultaneously and in the prescribed sequence at the corresponding qubits in the quantum chip.

[0004] Therefore, how to calibrate the timing error of the quantum bit control signal to ensure that the timing of the signal reaching the quantum bit in the quantum chip meets the timing logic requirements has become a technical problem that needs to be solved urgently in this field. Summary of the Invention

[0005] The purpose of this application is to provide a method and related equipment for calibrating the timing error of the control signal of multiple quantum bits to address the shortcomings of the existing technology. It can effectively calibrate the timing error of the control signal of the quantum bits caused by line transmission delay, so that the timing starting points of the control signals reaching multiple quantum bits in the quantum chip are strictly aligned to meet the timing logic requirements.

[0006] To achieve the above objectives, a first embodiment of the present application provides a method for calibrating timing errors of control signals for multiple qubits, which is applied to a quantum chip having at least two qubits. The calibration method includes:

[0007] Obtaining a relative delay between control signals of each qubit, wherein the relative delay is a time difference between the timing start times of the control signals of each qubit;

[0008] The relative delay is used to calibrate the timing start time of the control signal of each quantum bit, so that the control signal of each quantum bit can reach the quantum chip at the same time, wherein the control signal is a quantum state control signal or a frequency control signal.

[0009] Preferably, obtaining the relative delay between control signals of each qubit includes:

[0010] Determine a reference qubit, obtain a start time of a control signal for the reference qubit as a reference zero time of a timing sequence of control signals of all qubits in the same quantum chip, and obtain an absolute delay of the control signal of each qubit based on the reference zero time, wherein the absolute delay is a time difference between a timing start time of the control signal of each qubit and the reference zero time;

[0011] The difference in the absolute delays corresponding to the control signals of the respective qubits is obtained as the relative delay between the control signals of the respective qubits.

[0012] Preferably, if the control signal is a quantum state control signal, the determination of a reference quantum bit and the starting time of obtaining the control signal of the reference quantum bit are the reference zero time of the timing of the control signals of all quantum bits in the same quantum chip, and the absolute delay of the control signal of each quantum bit is obtained based on the reference zero time, wherein the absolute delay is the time difference between the timing start time of the control signal of each quantum bit and the reference zero time, including:

[0013] Obtaining a first delay between frequency control signals of any two coupled quantum bits, wherein the two frequency control signals can arrive at the quantum chip at the same time, and the first delay is the difference between the timing start times of the two frequency control signals;

[0014] Arbitrarily select a quantum bit as a reference quantum bit, obtain the starting time of the control signal of the reference quantum bit, and use this time as the reference zero time of the quantum state control signal timing of all quantum bits;

[0015] The absolute delay of the quantum state control signal of each quantum bit is determined based on the reference zero time and the first delay.

[0016] Preferably, determining the absolute delay of the quantum state control signal of each quantum bit based on the reference zero time and the first delay includes:

[0017] Determining a quantum bit as a quantum bit to be measured, and determining a coupling connection link including the quantum bit to be measured and the reference quantum bit according to the coupling topology of the quantum bits in the quantum chip;

[0018] Obtaining a first delay between frequency control signals of all two coupled quantum bits on the coupled link, and adding the obtained first delays to obtain a first delay sum;

[0019] The absolute delay of the quantum state control signal of the subbit to be measured is determined based on the reference zero time and the first delay sum.

[0020] Preferably, if the qubit control signal is a frequency control signal, the determination of a reference qubit and the starting time of obtaining the control signal of the reference qubit are the reference zero time of the control signal timing of all qubits in the same quantum chip, and the absolute delay of each qubit control signal is obtained based on the reference zero time, wherein the absolute delay is the time difference between the timing start time of the control signal of each qubit and the reference zero time, including:

[0021] Obtaining a second delay between a quantum state control signal and a frequency control signal of each qubit, wherein the quantum state control signal and the frequency control signal of each qubit can arrive at the quantum chip at the same time, and the second delay is a difference between the timing start times of the quantum state control signal and the frequency control signal;

[0022] Arbitrarily select a quantum bit as a reference quantum bit, obtain the starting time of the control signal of the reference quantum bit, and use this time as the reference zero time of the frequency control signal timing of all quantum bits;

[0023] An absolute delay of a frequency control signal of each quantum bit is determined based on the reference zero time, the first delay, and the second delay.

[0024] Preferably, determining the absolute delay of the frequency control signal of each quantum bit based on the reference zero time, the first delay, and the second delay includes:

[0025] Determining a quantum bit as a quantum bit to be measured, and obtaining an absolute delay of a quantum state control signal of the quantum bit to be measured, wherein the absolute delay of the quantum state control signal of the quantum bit to be measured is determined by the reference zero time and the first delay;

[0026] adding the absolute delay of the quantum state control signal of the subbit to be measured and the second delay between the quantum state control signal of the subbit to be measured and the frequency control signal to obtain a second delay sum;

[0027] The absolute delay of the frequency control signal of the sub-bit to be measured is determined based on the reference zero time and the second delay sum.

[0028] Preferably, the step of using the relative delay to calibrate the timing start time of each qubit control signal so that each qubit control signal can reach the quantum chip at the same time includes:

[0029] The sum of the timing start time of obtaining the control signal of each quantum bit and its corresponding relative delay is the final timing start time of the control signal reaching each quantum bit in the quantum chip, so that the control signal of each quantum bit can reach the quantum chip at the same time.

[0030] A second aspect of the present application provides a timing error calibration device for a multi-qubit control signal, the calibration device comprising:

[0031] A delay acquisition module, configured to acquire the relative delay between the control signals of each qubit, wherein the relative delay is the time difference between the timing start moments of the control signals of each qubit;

[0032] A timing calibration module is used to use the relative delay to calibrate the timing start time of the control signal of each quantum bit so that the control signal of each quantum bit can reach the quantum chip at the same time, wherein the control signal is a quantum state control signal or a frequency control signal.

[0033] A third aspect of the present application provides a quantum computer, comprising a quantum chip and a device for calibrating the timing error of control signals for multiple quantum bits as described above; wherein the quantum chip is provided with a plurality of mutually coupled quantum bits, each of the quantum bits being connected to an XY circuit and a Z circuit, and the device for calibrating the timing error of control signals for multiple quantum bits is connected to the ZY circuit and the Z circuit, and is used to implement the method for calibrating the timing error of control signals for multiple quantum bits as described above.

[0034] The fourth aspect of the present application provides a readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it can implement the method for calibrating the timing error of the control signal of multiple quantum bits as described in any one of the above items.

[0035] Compared with the prior art, this application has the following beneficial effects:

[0036] The embodiments of the present application obtain the relative delay between the control signals of each quantum bit, which is the time difference between the timing start times of the control signals of each quantum bit, and use the relative delay to calibrate the timing start time of the control signal of each quantum bit to eliminate the signal transmission delay on different XY lines and Z lines, so that the timing start times of different quantum state control signals and / or different frequency control signals arriving at the corresponding quantum bits in the quantum chip are strictly aligned, so that the timing of the control signals of multiple quantum bits meets the set timing logic requirements, and can then reach the corresponding quantum bits in the quantum chip at the same time according to the set timing, and the corresponding quantum bits can be controlled simultaneously, thereby effectively improving the control accuracy of the quantum bits.

[0037] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application and should not be regarded as limiting the scope. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 It is a schematic diagram of the structure of a quantum computer in related technology;

[0040] Figure 2 This is a diagram of the coupling topology between quantum bits of a quantum chip in related technology;

[0041] Figure 3 This is a workflow diagram of a method for calibrating timing errors of control signals of multiple quantum bits provided in one embodiment of the present application;

[0042] Figure 4 This is a flowchart of a process for obtaining the relative delay between control signals of each quantum bit provided by an embodiment of the present application;

[0043] Figure 5 This is a flowchart of a process for obtaining the absolute delay of the quantum state control signal of each quantum bit provided by an embodiment of the present application;

[0044] Figure 6 2 is a graph showing test results of a first delay between frequency control signals of two coupled qubits provided in one embodiment of the present application;

[0045] Figure 7This is a timing diagram of the simultaneous arrival of multi-qubit control signals at a quantum chip according to an embodiment of the present application;

[0046] Figure 8 This is a flowchart of a process for obtaining the absolute delay of the frequency control signal of each quantum bit provided by an embodiment of the present application;

[0047] Figure 9 1 is a graph showing test results of a second delay between a quantum state control signal and a frequency control signal for obtaining a quantum bit according to an embodiment of the present application;

[0048] Figure 10 This is a structural block diagram of a device for calibrating timing errors of control signals of multiple quantum bits provided in one embodiment of the present application. DETAILED DESCRIPTION

[0049] The following is a more detailed description of the specific embodiments of the present application, with reference to schematic diagrams. The advantages and features of the present application will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present application.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0051] The timing error calibration method for multi-qubit control signals provided in the embodiments of the present application can be applied to computer terminals, or so-called quantum computers.

[0052] See also Figure 1In a quantum computer, the quantum chip is the processor that performs quantum computations. It integrates multiple interconnected qubits, each coupled to an XY control terminal for receiving a quantum state control signal and a Z control terminal for receiving a frequency control signal. The quantum state control signal is used to manipulate the quantum state of the corresponding qubit to the quantum state required to complete the quantum computation, while the frequency control signal is used to control the frequency of the corresponding qubit. Only when the frequency control signal is used in related technologies does the quantum computer also include a quantum control system that provides the operating environment for the quantum chip. The quantum control system primarily consists of hardware devices located in the room temperature layer, as well as cryogenic devices and signal transmission lines within the dilution refrigerator. After packaging, the quantum chip is secured to the lowest, ultra-cold layer of the dilution refrigerator and ultimately connected to the room temperature hardware via coaxial cables between layers. In the quantum control system, two main types of circuits are used to manipulate the quantum state of the qubit: the XY circuit for manipulating the quantum state of the qubit, and the Z circuit for manipulating the frequency of the qubit.

[0053] See also Figure 1 and Figure 2 The coupling between multiple qubits on a quantum chip is achieved through neighbor-to-neighbor coupling via a coupled topology. When conducting a multi-qubit experiment, a frequency control signal must first be applied to the Z circuit to adjust the frequencies of the relevant qubits to and maintain the operating point frequency. The operating point frequency is specifically the energy level transition frequency between the qubit's ground state (i.e., the |0> state) and excited state (i.e., the |1> state). Then, a quantum state control signal is applied to the XY circuit to adjust the quantum state of the relevant qubits to the quantum state required by the quantum logic gate implemented by the sequential logic requirements of the quantum computing task. The signal sources for the quantum state control signal and the frequency control signal are both provided by room-temperature hardware devices. However, because the XY and Z circuits from the room-temperature hardware devices to the XY and Z control terminals of the qubits are equipped with different filters and microwave devices, and the lengths of the different XY and Z circuits cannot be guaranteed to be completely equal, the transmission delays of the control signals on the different XY and Z circuits vary. As a result, different control signals cannot reach their corresponding qubits simultaneously according to the designed timing, significantly reducing the precision of quantum state control of multiple qubits.

[0054] To do this, see Figure 3 The present invention provides a method for calibrating the timing error of a multi-qubit control signal, which is applied to a quantum chip having at least two qubits. The method includes:

[0055] S1: Obtaining the relative delay between the control signals of each quantum bit, wherein the relative delay is the time difference between the timing start moments of the control signals of each quantum bit.

[0056] S2: Using the relative delay, calibrate the timing start time of the control signal for each qubit so that the control signal for each qubit arrives at the quantum chip simultaneously, i.e., the timing start time of the control signal arriving at each qubit in the quantum chip is strictly aligned; wherein the control signal is a quantum state control signal or a frequency control signal. The timing start time of the control signal for each qubit can be obtained from a parameter list of the quantum computing task or a timing diagram of each control signal.

[0057] Specifically, the sum of the timing start time of obtaining the control signal of each quantum bit and its corresponding relative delay is the final timing start time of the control signal reaching each quantum bit in the quantum chip, so that the control signal of each quantum bit can reach the quantum chip at the same time.

[0058] For example, in practical applications, a period of empty signal with a duration equal to the absolute value of the relative delay is spliced before the start moment of the control signal timing of the corresponding quantum bit, thereby eliminating the signal transmission delay on the transmission line of each quantum bit and ensuring that the control signal of each quantum bit can reach the corresponding quantum bit in the quantum chip at the same time.

[0059] Therefore, the embodiment of the present application obtains the relative delay between the control signals of each quantum bit, which is the time difference between the timing start times of the control signals of each quantum bit, and uses the relative delay to calibrate the timing start time of the control signal of each quantum bit to eliminate the signal transmission delay on different XY lines and Z lines, so that the timing start times of different quantum state control signals and / or different frequency control signals arriving at the corresponding quantum bits in the quantum chip are strictly aligned, so that the timing of the control signals of multiple quantum bits meets the set timing logic requirements, and can then reach the corresponding quantum bits in the quantum chip at the same time according to the set timing, and control the corresponding quantum bits at the same time, effectively improving the control accuracy of the quantum bits.

[0060] As a specific implementation of the embodiment of this application, please refer to Figure 4 , the relative delay between the control signals of each quantum bit is obtained in step S1, specifically including:

[0061] S11: Determine a reference quantum bit, and obtain the starting time of the control signal of the reference quantum bit as the reference zero time of the timing of the control signals of all quantum bits in the same quantum chip, and obtain the absolute delay of the control signal of each quantum bit based on the reference zero time, wherein the absolute delay is the time difference between the timing start time of the control signal of each quantum bit and the reference zero time.

[0062] S12: Obtain the difference in the absolute delays corresponding to the control signals of the respective qubits as the relative delays between the control signals of the respective qubits.

[0063] It should be noted that since the XY line and Z line connected to each quantum bit transmit quantum state control signals and frequency control signals respectively, the two signals are processed differently, which leads to differences in the filters and microwave devices set on the XY line and the Z line. Therefore, the signal transmission delays on the two lines need to be treated differently.

[0064] As a specific implementation of the embodiment of this application, please refer to Figure 5 If the control signal is a quantum state control signal, it is manifested as a signal transmission delay on the XY line connected to each quantum bit. Then step S11 specifically includes:

[0065] S1110: Obtain a first delay between frequency control signals of any two coupled quantum bits, wherein the two frequency control signals can arrive at the quantum chip at the same time, and the first delay is the difference between the timing start times of the two frequency control signals.

[0066] S1111: Randomly select a quantum bit as a reference quantum bit, obtain the starting time of the control signal of the reference quantum bit, and use this time as the reference zero time of the quantum state control signal timing of all quantum bits.

[0067] S1112: Determine the absolute delay of the quantum state control signal of each quantum bit based on the reference zero time and the first delay.

[0068] Specifically, obtaining the first delay between the frequency control signals of any two coupled qubits in step S1110 includes the following steps:

[0069] First, a first qubit and a second qubit that are coupled to each other are determined, the quantum states of the first qubit and the second qubit are preset to a |1> state and a |0> state, respectively, and a first amplitude and a second amplitude of a frequency control signal applied to the first qubit and the second qubit, respectively, are obtained based on a resonance test of the first qubit and the second qubit; wherein the resonance test is an experiment for measuring the coupling strength between the first qubit and the second qubit as the amplitude of the frequency control signal changes.

[0070] It should be noted that the two mutually coupled first qubits and second qubits specifically refer to two qubits that have a direct connection relationship in the coupling topology of the quantum chip, for example Figure 1 and Figure 2 In the example, qubit Q2 is connected to qubit Q3, qubit Q4 is connected to qubit Q5, and so on. For example, qubit Q2 can be used as the first qubit, and qubit Q3 can be used as the second qubit, and vice versa. In a specific implementation, a π pulse signal is applied to the first qubit to control the quantum state of the first qubit to the |1> state. A 0 pulse signal is applied to the second qubit to control the quantum state of the second qubit to the |0> state. Based on this, a resonance experiment is performed on the first qubit and the second qubit to obtain the first amplitude of the frequency control signal applied to the Z line connected to the first qubit and the second amplitude of the frequency control signal applied to the Z line connected to the second qubit when the first qubit and the second qubit resonate and the coupling strength is maximum (the operating point frequencies of the two qubits are equal).

[0071] In addition, because the first qubit and the second qubit are coupled to each other, adjustments to their operating point frequencies will affect each other, and thus their quantum states. When the operating point frequencies of the first and second qubits are adjusted to be equal, the coupling strength between the first and second qubits is maximized, and the quantum states of the first and second qubits exchange, i.e., the first qubit decays from the |1> state to the |0> state, while the second qubit is excited from the |0> state to the |1> state. Thus, the coupling strength between the first and second qubits affects their quantum states. The resonance test described in this embodiment specifically involves an experiment in which the probability that the quantum states of the first and second qubits are eigenstates (including the |0> state and the |1> state) varies with the amplitude of the frequency control signal.

[0072] Secondly, a frequency control signal having a first amplitude is applied to the first qubit, and a frequency control signal having a second amplitude is applied to the second qubit, so that the first qubit and the second qubit resonate and have the maximum coupling strength (the operating point frequencies of the two qubits are equal). Based on this, a quantum state oscillation experiment is performed on the first qubit and the second qubit to obtain the first width of the frequency control signal applied to the first qubit and the second qubit when the probability of the quantum state of the first qubit and the second qubit being an eigenstate during the exchange process is most sensitive to the change in the width of the frequency control signal. The quantum state oscillation experiment is an experiment to measure the change in the quantum state of the first qubit and the second qubit as a function of the width of the frequency control signal.

[0073] It should be noted that the width of the frequency control signal applied to the first quantum bit and the second quantum bit is equal from beginning to end and changes synchronously, that is, the duration of the frequency control signal applied to the first quantum bit and the second quantum bit is equal and changes synchronously.

[0074] Then, a first frequency control signal having the first amplitude and the first width is applied to the first quantum bit, and the first preset delay is updated sequentially within a first preset range. A second frequency control signal having the second amplitude and the first width after the first preset delay is updated is applied to the second quantum bit, and a first curve is obtained in which the probabilities of the quantum states of the first quantum bit and the second quantum bit being the |1> state and the |0> state respectively vary with the first preset delay.

[0075] In this step, a first frequency control signal having the first amplitude and the first width is applied to the first quantum bit, and the first preset delay is updated sequentially within a first preset range, and a second frequency control signal having the second amplitude and the first width after the first preset delay is updated is applied to the second quantum bit, the first quantum bit and the second quantum bit resonate, the coupling strength is maximized, and the probability change of the quantum state of the first quantum bit and the second quantum bit being an eigenstate is most sensitive to the change in the duration of the frequency control signal.

[0076] Among them, the first preset range is set according to the length of the Z line connected to the first quantum bit and the second quantum bit respectively, so as to ensure that the first preset delay takes a value within the first preset range, and all valid data information can be obtained, so that the first curve is complete. The first preset delay is updated in a fixed step-by-step increasing or decreasing manner within the first preset range. For example, each time the first preset delay is increased by one step, a frequency control signal with the second amplitude and the first width after the first preset delay is updated is applied to the second quantum bit, and the probability of the quantum states of the first quantum bit and the second quantum bit being |1> state and |0> state respectively is measured once as the data information changes with the first preset delay, and then all the data information is expressed with the first preset delay Delay1 (ns) as the horizontal axis and the probability P of the quantum states of the first quantum bit and the second quantum bit being |1> state and |0> state respectively. 10 The vertical axis is a first curve showing the probability of the quantum states of the first quantum bit and the second quantum bit being |1> and |0> respectively as the first preset delay changes, such as Figure 6 shown.

[0077] Finally, it is determined whether the first curve has a minimum value. If so, the first delay is determined based on a first preset delay corresponding to the minimum value of the first curve.

[0078] In this step, you can Figure 6 It is intuitive to see whether the first curve has a minimum value. The actual situation presented at the minimum value is that after the Z line connecting the first quantum bit and the second quantum bit is delay calibrated based on the first preset delay corresponding to this point, when the two frequency control signals are respectively transmitted to the first quantum bit and the second quantum bit through their respective corresponding Z lines, the widths of the waveforms of the two frequency control signals are aligned (that is, the starting point and end point of the waveforms of the two frequency control signals are aligned).

[0079] From the foregoing description, it can be seen that when the waveforms of the frequency control signals of the first qubit and the second qubit are aligned (that is, the widths of the frequency control signals of the first qubit and the second qubit are equal), the mutual influence between the first qubit and the second qubit is the greatest, and the probability change of the quantum state of the first qubit and the second qubit being the eigenstate is most sensitive to the duration of the frequency control signal, showing that the probability of the quantum state of the first qubit and the second qubit being the |1> state and the |0> state, respectively, is the lowest and equal, specifically both around 0.5.

[0080] In addition, when the first curve does not have a minimum value, that is, a changing curve with a minimum value cannot be obtained by delaying the second frequency control signal, indicating that the signal transmission speed on the Z line connected to the second quantum bit is less than the signal transmission speed on the Z line connected to the first quantum bit. At this time, the first frequency control signal needs to be delayed for a first fixed time length of a certain length, so as to ensure the feasibility of subsequent solutions.

[0081] As a specific implementation of the embodiment of the present application, in step S1112, determining the absolute delay of the quantum state control signal of each quantum bit based on the reference zero time and the first delay includes the following steps:

[0082] First, a quantum bit is determined as the quantum bit to be measured, and a coupling connection link including the quantum bit to be measured and the reference quantum bit is determined according to the coupling topology structure of the quantum bits in the quantum chip.

[0083] Then, obtaining a first delay between frequency control signals of all two coupled quantum bits on the coupled link, and adding the obtained first delays to obtain a first delay sum;

[0084] Finally, the absolute delay of the quantum state control signal of the subbit to be measured is determined based on the reference zero time and the first delay sum.

[0085] It should be noted that different quantum chips can adopt different quantum bit coupling topologies, for example Figure 1 and Figure 2 The coupling topology of two quantum bits is shown in Figure 2 In the coupling topology of the qubits shown in FIG, after a qubit is selected as the reference qubit, a portion of the qubits is selected as the subbits to be measured, and there are multiple coupling connection links between the coupling connection links of the subbit to be measured and the reference qubit.

[0086] In addition, since the relative delay between the control signals of any two quantum bits in the quantum chip is determined by the signal transmission delay of the corresponding XY line or Z line, when the signal transmission delay of the XY line or Z line is determined, the relative delay is basically fixed, that is, the difference in the absolute delays of the quantum state control signals of the two quantum bits obtained based on the reference zero time is fixed.

[0087] Therefore, the absolute delay of the quantum state control signal of the subbit to be measured obtained through each of the coupling connection links is the same, so one of the coupling connection links can be arbitrarily selected to obtain the first delay sum.

[0088] For example, if you choose Figure 1 and Figure 2 The qubit Q2 in the example is used as the reference qubit. Specifically, the timing start time of the quantum state signal transmitted on the XY line XY2 of qubit Q2 is selected as the reference zero time. When qubit Q5 is selected as the qubit to be measured, Figure 1 In the example, there is only one coupling connection link between qubit Q2 and qubit Q5, which includes qubit Q2, qubit Q3, qubit Q4 and qubit Q5. The coupling connection link can be expressed as Q2-Q3-Q4-Q5. Figure 2 In the figure, there are four coupling connection links between quantum bit Q2 and quantum bit Q5, which are represented as Q2-Q3-Q4-Q5, Q2-Q9-Q8-Q7-Q6-Q5, Q2-Q9-Q8-Q3-Q4-Q5, and Q2-Q9-Q8-Q7-Q4-Q5.

[0089] For example, the coupling connection link Q2-Q3-Q4-Q5 is selected to calculate the absolute delay of the quantum state control signal of the subbit Q5 to be measured. The specific process is:

[0090] See also Figure 7 , sequentially obtaining the first delay zz23 between the frequency control signals of qubits Q3 and Q2, the first delay zz34 between the frequency control signals of qubits Q4 and Q3, and the first delay zz45 between the frequency control signals of qubits Q4 and Q5. The sum of the first delays on this coupled connection link is then obtained as zz23 + zz34 + zz45. Based on the reference zero time determined by qubit Q2, the absolute delay of the quantum state control signal of qubit Q5 is obtained as zz23 + zz34 + zz45.

[0091] Since the timing start time of the quantum state signal output on XY2 connected to the quantum bit Q2 is the reference zero time, in order to make the quantum state signal output on XY2 connected to the quantum bit Q2 and the quantum state signal output on XY5 connected to the quantum bit Q5 reach the quantum bit Q2 and the quantum bit Q5 at the same time, it can be achieved by splicing a blank signal with an absolute value of zz23+zz34+zz45 before the timing start time of the quantum state signal output on XY5 connected to the quantum bit Q5.

[0092] Selecting other coupled connection links to calculate the absolute delay of the quantum state control signal of the sub-bit Q5 to be measured is consistent with the above process and will not be described in detail here.

[0093] As a specific implementation of the embodiment of this application, please refer to Figure 8If the qubit control signal is a frequency control signal, it is manifested as a signal transmission delay on the Z line connected to each qubit. Then step S11 specifically includes:

[0094] S1120: Obtain a second delay between the quantum state control signal and the frequency control signal of each quantum bit, wherein the quantum state control signal and the frequency control signal of each quantum bit can reach the quantum chip at the same time, and the second delay is the difference between the timing start times of the quantum state control signal and the frequency control signal.

[0095] S1121: Randomly select a quantum bit as a reference quantum bit, obtain the starting time of the control signal of the reference quantum bit, and use this time as the reference zero time of the frequency control signal timing of all quantum bits.

[0096] S1122: Determine the absolute delay of the frequency control signal of each quantum bit based on the reference zero time, the first delay, and the second delay.

[0097] As a specific implementation of the embodiment of the present application, in step S1120, obtaining the second delay between the quantum state control signal and the frequency control signal of each quantum bit includes:

[0098] A target qubit is identified, a first control signal is applied to the target qubit via an XY circuit connected to the target qubit, and a second control signal with a second preset delay is applied to the target qubit via a Z circuit connected to the target qubit. The first control signal is used to control the quantum state of the target qubit to a |1> state, and the second control signal is used to control the frequency of the target qubit. Changes in the frequency of the target qubit affect the probability that its quantum state is in the |1> state.

[0099] In a specific implementation, each qubit on a quantum chip can be used as a target qubit to measure the second delay between the quantum state control signal and the frequency control signal for each qubit. The first control signal can be a π pulse signal, where the probability that the target qubit's quantum state is in the |1> state is 1 or a probability value close to 1.

[0100] A second control signal having a second preset delay is applied to the target qubit via the Z circuit connected to the target qubit to control the frequency of the target qubit. The frequency of the target qubit is the energy level transition frequency between the ground state (i.e., |0> state) and the excited state (i.e., |1> state) of the target qubit.

[0101] It should be noted that only when the frequency of the first control signal is equal to or close to the frequency of the target qubit will the target qubit resonate with the first control signal, thereby achieving the goal of applying the first control signal through the XY circuit connected to the target qubit to control the quantum state of the target qubit. However, when the frequency of the target qubit differs significantly from the frequency of the first control signal, the quantum state of the target qubit will not respond to the first control signal. Therefore, in this embodiment, the second control signal applied to the target qubit will control the frequency of the qubit, which in turn affects the effect of the first control signal on the control of the quantum state of the target qubit. That is, as the frequency of the target qubit changes, the probability of the quantum state being the |1> state will also change.

[0102] The second preset delay is updated sequentially within a second preset range, and the second control signal after the updated second preset delay is applied to the target quantum bit to obtain a second curve showing the probability of the quantum state of the target quantum bit being the |1> state as the second preset delay changes; wherein the second preset range is set according to the lengths of the XY line and the Z line connected to the target quantum bit.

[0103] During specific implementation, the second preset range is set according to the length of the XY line and the Z line connected to the target quantum bit, which can ensure that the second preset delay takes a value within the second preset range, and all valid data information can be obtained, so that the second curve is complete. The second preset delay is updated in a fixed step-by-step manner within the second preset range. For example, each time the second preset delay is increased by one step, the second control signal after the updated second preset delay is applied to the target quantum bit, and the probability of the quantum state of the target quantum bit being the |1> state is measured once as the data information changes with the second preset delay. Then, all the data information is plotted with the second preset delay Zdelay (ns) as the horizontal axis and the probability P1 of the quantum state of the target quantum bit as the vertical axis to form a second curve showing the probability of the quantum state of the target quantum bit being the |1> state as the second preset delay changes, such as Figure 9 shown.

[0104] Determine whether the second curve has a minimum value; if so, determine the second delay based on a second preset delay corresponding to the minimum value of the second curve.

[0105] Specifically, you can Figure 9It is intuitive to see whether the second curve has a minimum value. The actual situation presented at the minimum value is that when the second control signal after the preset delay corresponding to this point is applied to the Z line connected to the target quantum bit, the first control signal and the second control signal are respectively transmitted to the target quantum bit via the XY line and the Z line connected to the target quantum bit, and the waveform of the first control signal is aligned with the center of the waveform of the second control signal.

[0106] As mentioned above, when the frequency of the target quantum bit changes, the quantum state of the target quantum bit will also change accordingly. When the waveform of the first control signal is aligned with the center of the waveform of the second control signal, that is, the second control signal applied to the Z line connected to the target quantum bit will adjust the frequency of the target quantum bit to deviate from the maximum value of the operating point frequency. Correspondingly, at this time, the first control signal applied to the XY line connected to the target quantum bit has the worst effect on regulating the quantum state of the target quantum bit, and the probability that the quantum state of the target quantum bit is the |1> state is the lowest.

[0107] Furthermore, if the second curve does not have a minimum value, meaning that a curve with a minimum value cannot be obtained by delaying the second control signal, this indicates that the transmission speed of the Z line connected to the target qubit is slower than the transmission speed of the XY line connected to it. In this case, the timing start of the first control signal can be delayed by a second fixed duration to ensure the feasibility of subsequent solutions.

[0108] As a specific implementation of an embodiment of the present application, in step S1122, determining the absolute delay of the frequency control signal of each quantum bit based on the reference zero time, the first delay, and the second delay includes the following steps:

[0109] First, a quantum bit is determined as a quantum bit to be measured, and an absolute delay of a quantum state control signal of the quantum bit to be measured is obtained, wherein the absolute delay of the quantum state control signal of the quantum bit to be measured is determined by the reference zero time and the first delay.

[0110] Secondly, the absolute delay of the quantum state control signal of the subbit to be measured and the second delay between the quantum state control signal of the subbit to be measured and the frequency control signal are added to obtain a second delay sum.

[0111] Finally, the absolute delay of the frequency control signal of the sub-bit to be measured is determined based on the reference zero time and the second delay sum.

[0112] Please continue reading Figure 7 , continue to select Figure 1 or Figure 2The quantum bit Q2 in the equation is used as the reference quantum bit. Specifically, the timing start time of the quantum state signal transmitted on the XY line XY2 of the quantum bit Q2 is selected as the reference zero time, and the quantum bit Q5 is selected as the quantum bit to be measured. From the above description, it can be seen that the absolute delay of the quantum state control signal of the quantum bit Q5 is zz23+zz34+zz45. The second delay between the quantum state control signal and the frequency control signal of the quantum bit Q5 obtained is d4, and the second delay sum is zz23+zz34+zz45+d4. The absolute delay of the frequency control signal of the quantum bit Q5 determined based on the reference zero time and the second delay sum is zz23+zz34+zz45+d4. When the remaining quantum bits are used as the quantum bits to be measured, the method of obtaining the absolute delay of the frequency control signal of the quantum bit to be measured is similar and will not be described in detail here.

[0113] Based on the same inventive concept, please refer to Figure 10 , the embodiment of the present application further proposes a device for calibrating timing errors of control signals of multiple quantum bits, comprising:

[0114] The delay acquisition module 210 is used to obtain the relative delay between the control signals of each quantum bit, wherein the relative delay is the time difference between the timing start moments of the control signals of each quantum bit.

[0115] The timing calibration module 220 is used to use the relative delay to calibrate the timing start time of the control signal of each quantum bit so that the control signal of each quantum bit can reach the quantum chip at the same time, wherein the control signal is a quantum state control signal or a frequency control signal.

[0116] It is understandable that the delay acquisition module 210 and the timing calibration module 220 can be combined into one device for implementation, or any one of the modules can be split into multiple sub-modules, or at least part of the functions of one or more modules in the delay acquisition module 210 and the timing calibration module 220 can be combined with at least part of the functions of other modules and implemented in one functional module. According to an embodiment of the present application, at least one of the delay acquisition module 210 and the timing calibration module 220 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or can be implemented in hardware or firmware in any other reasonable way of integrating or packaging the circuit, or in an appropriate combination of software, hardware, and firmware. Alternatively, at least one of the delay acquisition module 210 and the timing calibration module 220 can be at least partially implemented as a computer program module, which can execute the functions of the corresponding module when the program is run by a computer.

[0117] Based on the same inventive concept, an embodiment of the present application also proposes a quantum computer, including the method for calibrating the timing error of the control signal of multiple quantum bits as described above, or using the method for calibrating the timing error of the control signal of multiple quantum bits as described in any of the above items to calibrate the timing of the quantum bit control signal.

[0118] Based on the same inventive concept, an embodiment of the present application also proposes a readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it can implement the method for calibrating the timing error of the control signal of multiple quantum bits as described in any of the above items.

[0119] The readable storage medium can be a tangible device that can keep and store the instruction used by the instruction execution device, such as, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device or any suitable combination thereof. The more specific example (non-exhaustive list) of readable storage medium includes: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a convex structure in a groove having instructions stored thereon, and any suitable combination thereof. The computer program described herein can be downloaded to each computing / processing device from the readable storage medium, or downloaded to an external computer or external storage device by a network, such as the Internet, a local area network, a wide area network and / or a wireless network. The network can include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer program from the network and forwards the computer program for storage in a readable storage medium in each computing / processing device. The computer program for performing the operations of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as "C" or similar programming languages. The computer program can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, various aspects of the present invention are implemented by utilizing state information of a computer program to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), which can execute computer-readable program instructions.

[0120] Various aspects of the present invention are described herein with reference to the flowcharts and / or block diagrams of the methods, systems, and computer program products according to embodiments of the present invention. It should be understood that each block of the flowcharts and / or block diagrams, as well as the combination of blocks in the flowcharts and / or block diagrams, can be implemented by computer programs. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine such that when these programs are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowcharts and / or block diagrams. These computer programs can also be stored in a readable storage medium, which causes the computer, programmable data processing device, and / or other device to operate in a specific manner, so that the readable storage medium storing the computer program comprises an article of manufacture comprising instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowcharts and / or block diagrams.

[0121] The computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0122] In the description of this specification, reference to the terms "one embodiment," "some embodiments," "example," or "specific example" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0123] The above is only a preferred embodiment of the present application and does not limit the present application in any way. Any person skilled in the art who, without departing from the scope of the technical solution of the present application, makes any equivalent substitution or modification to the technical solution and technical content disclosed in the present application shall be deemed to have not departed from the content of the technical solution of the present application and shall still fall within the scope of protection of the present application.

Claims

1. A method for calibrating timing errors of control signals of multiple quantum bits, characterized in that: Applied to a quantum chip having at least two qubits, the calibration method comprises: Determine a reference qubit, and obtain the starting time of the control signal of the reference qubit as the reference zero time of the control signal timing of all qubits in the same quantum chip; wherein the control signal is a quantum state control signal or a frequency control signal; Obtaining a first delay between frequency control signals of any two coupled qubits and a second delay between a quantum state control signal and a frequency control signal of each qubit; wherein the first delay is a difference between the timing start times of the two frequency control signals, and the second delay is a difference between the timing start times of the quantum state control signal and the frequency control signal; Determine the difference between the absolute delays of the control signals of each quantum bit as the relative delay based on the reference zero time, the first delay, and the second delay; The sum of the timing start time of obtaining the control signal of each quantum bit and its corresponding relative delay is the final timing start time of the control signal reaching each quantum bit in the quantum chip, so that the control signal of each quantum bit can reach the quantum chip at the same time.

2. The calibration method according to claim 1, wherein: If the control signal is a quantum state control signal, obtaining a first delay between frequency control signals of any two coupled quantum bits, and obtaining a control delay between control signals of any two coupled quantum bits include: Obtaining a first delay between frequency control signals of any two coupled quantum bits, wherein the two frequency control signals can arrive at the quantum chip at the same time, and the first delay is the difference between the timing start times of the two frequency control signals; Determining the difference between the absolute delays of the control signals of each quantum bit as the relative delay based on the reference zero time, the first delay, and the second delay includes: Determining the absolute delay of the quantum state control signal of each quantum bit based on the reference zero time of the quantum state control signal timing, the first delay and / or the second delay; The difference in the absolute delay corresponding to the quantum state control signal of each quantum bit is obtained as the relative delay between the quantum state control signals of each quantum bit.

3. The calibration method according to claim 2, wherein: Determining the absolute delay of the quantum state control signal of each quantum bit based on the reference zero time of the quantum state control signal, the first delay, and the second delay includes: Determining a quantum bit as a quantum bit to be measured, and determining a coupling connection link including the quantum bit to be measured and the reference quantum bit according to the coupling topology of the quantum bits in the quantum chip; Obtaining a first delay between frequency control signals of all two coupled quantum bits on the coupled link, and adding the obtained first delays to obtain a first delay sum; The absolute delay of the quantum state control signal of the subbit to be measured is determined based on the reference zero time and the first delay sum.

4. The calibration method according to claim 2, wherein: If the qubit control signal is a frequency control signal, obtaining a second delay between the quantum state control signal and the frequency control signal of each qubit includes: Obtaining a second delay between a quantum state control signal and a frequency control signal of each qubit, wherein the quantum state control signal and the frequency control signal of each qubit can arrive at the quantum chip at the same time, and the second delay is a difference between the timing start times of the quantum state control signal and the frequency control signal; Determining the difference between the absolute delays of the control signals of each quantum bit as the relative delay based on the reference zero time and the control delay includes: Determine the absolute delay of the frequency control signal of each quantum bit based on the reference zero time of the frequency control signal timing, the first delay, and the second delay; The difference in the absolute delays corresponding to the frequency control signals of the respective qubits is obtained as the relative delay between the frequency control signals of the respective qubits.

5. The calibration method according to claim 4, wherein: Determining the absolute delay of the frequency control signal of each quantum bit based on the reference zero time of the frequency control signal timing, the first delay, and the second delay includes: Determining a quantum bit as a quantum bit to be measured, and obtaining an absolute delay of a quantum state control signal of the quantum bit to be measured, wherein the absolute delay of the quantum state control signal of the quantum bit to be measured is determined by the reference zero time and the first delay; adding the absolute delay of the quantum state control signal of the subbit to be measured and the second delay between the quantum state control signal of the subbit to be measured and the frequency control signal to obtain a second delay sum; The absolute delay of the frequency control signal of the sub-bit to be measured is determined based on the reference zero time and the second delay sum.

6. A timing error calibration device for a multi-qubit control signal, characterized in that: The calibration setup consists of: A delay acquisition module is used to determine a reference quantum bit, and the starting time of obtaining the control signal of the reference quantum bit is the reference zero time of the control signal timing of all quantum bits in the same quantum chip; wherein, wherein, the control signal is a quantum state control signal or a frequency control signal; obtain a first delay between the frequency control signals of any two coupled quantum bits and a second delay between the quantum state control signal and the frequency control signal of each quantum bit; wherein, the first delay is the difference between the timing start times of the two frequency control signals, and the second delay is the difference between the timing start times of the quantum state control signal and the frequency control signal; based on the reference zero time, the first delay, and the second delay, the difference in the absolute delay of the control signal of each quantum bit is determined as a relative delay; The timing calibration module is used to obtain the sum of the timing start time of the control signal of each quantum bit and its corresponding relative delay as the final timing start time of the control signal arriving at each quantum bit in the quantum chip, so that the control signal of each quantum bit can reach the quantum chip at the same time.

7. A quantum computer, characterized in that The quantum computer includes a quantum chip and a device for calibrating the timing error of control signals of multiple quantum bits as described in claim 6; wherein, a plurality of mutually coupled quantum bits are provided on the quantum chip, each of the quantum bits is connected to an XY circuit and a Z circuit, and the device for calibrating the timing error of control signals of multiple quantum bits is connected to the XY circuit and the Z circuit, and is used to implement the method for calibrating the timing error of control signals of multiple quantum bits as described in any one of claims 1 to 5.

8. A readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it can implement the method for calibrating the timing error of the control signal of multiple quantum bits according to any one of claims 1 to 5.

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