Graphics processor core, system, device, equipment, main core configuration unit, and method

Abstract

The present disclosure provides a graphics processing system, device, electronic device, GPU core, main core configuration unit, and method based on a multi-core GPU architecture. The system includes multiple GPU cores, each GPU core includes a main core configuration interface and a first communication interface, and each GPU core is configured to: obtain main core configuration information through the main core configuration interface, enable the first communication interface when the main core configuration information indicates that the GPU core is the main core, and the first communication interface is used to communicate with the CPU. The technical solution of the present disclosure can be used to reconstruct the main core of the multi-core GPU architecture, avoiding the situation where the chip is scrapped due to damage to the main core.

Description

Technical Field

[0001] The present disclosure relates to the technical field of multi-core GPU (Graphics Processing Unit), and in particular to a graphics processing system, device, electronic device, GPU core and main core configuration unit, and method. Background Art

[0002] Multi-core GPU architecture refers to integrating multiple GPU cores into one system, and multiple GPU cores perform tasks as a whole. Multi-core GPU architecture facilitates performance expansion and can flexibly adjust the number of GPU cores in the system according to the performance requirements of actual products, so that a multi-core GPU architecture can meet the performance requirements of multiple products.

[0003] In a multi-core GPU architecture, there is usually a fixed GPU core as the master core that is responsible for interacting with the CPU (Central Processing Unit) and managing and scheduling other GPU cores. Other GPU cores are slave cores that receive management and scheduling commands from the master core. Usually, the master core is fixed during the chip design stage.

[0004] For chips using multi-core GPU architecture, if a defective slave core is found during the production test phase, the chip can be shipped as a low-end product by shutting down the defective slave core (down core). Once the master core is damaged, even if the slave core functions intact, the multi-core GPU architecture as a whole will not work properly and the chip will have to be scrapped. Summary of the invention

[0005] The purpose of the present disclosure is to provide a graphics processing system, device, electronic device, GPU core and main core configuration unit, and method to avoid the situation in which the main core is fixed during the chip design stage, resulting in damage to the main core and chip scrapping.

[0006] According to one aspect of the present disclosure, a graphics processing system is provided. The graphics processing system is based on a multi-core GPU architecture, and the graphics processing system includes:

[0007] Multiple GPU cores, each GPU core includes a main core configuration interface and a first communication interface, each GPU core is configured to: obtain main core configuration information through the main core configuration interface, enable the first communication interface when the main core configuration information indicates that the GPU core is the main core, and the first communication interface is used to communicate with the CPU.

[0008] In the present disclosure, there are multiple communication modes between the first communication interface and the CPU. As an example and not limitation, the first communication interface can be connected to a bus network and communicate with the CPU through the bus network. In practice, the bus network used by the first communication interface and the bus network used between GPU cores can be two independent bus networks. In order to reduce the bus connection relationship and simplify the chip connection, the communication between GPU cores and the communication between the main core and the CPU can use the same bus network, that is, the bus network used by the first communication interface and the bus network used between GPU cores are the same bus network.

[0009] In a feasible implementation of the present disclosure, each GPU may further include a second communication interface, and each GPU core is configured to: send operating status information through the second communication interface, wherein the operating status information of the main core is sent to the status information receiving module. In another feasible implementation, the operating status information of the main core may be sent to the status information receiving module through the first communication interface.

[0010] If each GPU core includes a second communication interface, in order to ensure that only the running status information of the main core is sent to the status information receiving module, a feasible implementation method is: the system also includes a state selector, the state selector is connected to the second communication interface of each GPU core, and the state selector is configured to: identify the running status information sent by the main core according to the main core configuration information obtained by the selection end, and send it to the status information receiving module. Another feasible implementation method is: each GPU core is configured to: enable the second communication interface when the main core configuration information indicates that the GPU core is the main core.

[0011] Based on any of the above embodiments, there are multiple ways to connect the main core configuration interface. Based on a feasible connection method, the system provided by the present disclosure may further include a main core configuration register, which is connected to the main core configuration interface of each GPU core and is used to temporarily store the main core configuration information sent by the CPU. Based on another feasible connection method, the main core configuration interface is directly connected to the CPU.

[0012] Based on any of the above embodiments, the main core is selected from the available GPU cores, and the information of the available GPU cores can be stored on the above system. Accordingly, the above system can also include a storage module, and the storage module is used to store the information of the available GPU cores; the CPU is configured to: select the main core according to the information of the available GPU cores, and send the main core configuration information. Of course, the information of the available GPU cores can also be stored outside the above system.

[0013] Based on any of the above embodiments, the main core configuration information includes at least one of the following: a main core identifier, a main core base address, and main core startup indication information.

[0014] According to another aspect of the present disclosure, an electronic device is also provided, which includes a graphics processing system based on a multi-core GPU architecture as described in any of the above embodiments. In some usage scenarios, the product form of the electronic device is embodied as a graphics card; in other usage scenarios, the product form of the electronic device is embodied as a CPU motherboard.

[0015] According to another aspect of the present disclosure, an electronic device is also provided, which includes the above-mentioned electronic device. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, etc.

[0016] According to another aspect of the present disclosure, a main core configuration unit is further provided, which is applied to a graphics processing system based on a multi-core GPU architecture, wherein the main core configuration unit includes:

[0017] A state selector, the state selector is connected to the second communication interface of the multiple GPU cores, and the state selector is configured to: identify the running state information sent by the main core according to the main core configuration information obtained by the selection end, and send it to the state information receiving module; the main core configuration information is used to instruct the main core among the multiple GPU cores to enable the first communication interface, and the first communication interface is used to communicate with the CPU.

[0018] The main core configuration unit may further include a main core configuration register, which is connected to the main core configuration interface of each GPU core and is used to temporarily store the main core configuration information sent by the CPU.

[0019] According to another aspect of the present disclosure, a graphics processor core is also provided, which is applied to a graphics processing system in a multi-core GPU architecture, wherein the graphics processor core includes a main core configuration interface and a first communication interface; the graphics processor core is configured to: obtain main core configuration information through the main core configuration interface, enable the first communication interface when the main core configuration information indicates that the GPU core is the main core, and the first communication interface is used to communicate with the CPU.

[0020] In the present disclosure, there are multiple communication modes between the first communication interface and the CPU. As an example and not limitation, the first communication interface can be connected to a bus network and communicate with the CPU through the bus network. In practice, the bus network used by the first communication interface and the bus network used between GPU cores can be two independent bus networks. In order to reduce the bus connection relationship and simplify the chip connection, the communication between GPU cores and the communication between the main core and the CPU can use the same bus network, that is, the bus network used by the first communication interface and the bus network used between GPU cores are the same bus network.

[0021] In a feasible implementation of the present disclosure, the GPU core may further include a second communication interface, and the GPU core is configured to: send operating status information through the second communication interface, wherein the operating status information of the main core is sent to the status information receiving module. In another feasible implementation, the operating status information of the main core may be sent to the CPU through the first communication interface.

[0022] According to another aspect of the present disclosure, a main core configuration method is also provided, which is applied to a graphics processing system based on a multi-core GPU architecture, wherein the method includes:

[0023] The CPU selects a master core from the available GPU cores and sends the master core configuration information;

[0024] Each GPU core obtains the main core configuration information, and enables a first communication interface when the main core configuration information indicates that the GPU core is the main core, where the first communication interface is used to communicate with the CPU.

[0025] Among them, a feasible implementation method for sending the main core configuration information includes: the CPU saves the main core configuration information to the main core configuration register; accordingly, each GPU core obtains the main core configuration information, and its implementation method includes: each GPU core obtains the main core configuration information from the main core configuration register through the main core configuration interface.

[0026] Another feasible implementation of sending the main core configuration information includes: the CPU directly sends the main core configuration information to each GPU core. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the connection relationship of a GPU core according to an embodiment of the present disclosure;

[0028] Figure 2 A schematic diagram of the structure of a graphics processing system based on a multi-core GPU architecture according to an embodiment of the present disclosure;

[0029] Figure 3 This is a schematic diagram of the structure of a graphics processing system based on a multi-core GPU architecture according to another embodiment of the present disclosure;

[0030] Figure 4 This is a schematic diagram of the structure of a main core configuration unit according to an embodiment of the present disclosure;

[0031] Figure 5 The figure is a flowchart of a method for configuring a main core according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Before introducing the embodiments of the present disclosure, it should be noted that:

[0033] Some embodiments of the present disclosure are described as processing flows. Although the various operation steps of the flow may be given sequential step numbers, the operation steps therein may be implemented in parallel, concurrently or simultaneously.

[0034] In the embodiments of the present disclosure, the terms "first", "second", etc. may be used to describe various features, but these features should not be limited by these terms. These terms are used only to distinguish one feature from another.

[0035] The term “and / or” may be used in embodiments of the present disclosure. “And / or” includes any and all combinations of one or more of the associated features listed.

[0036] It should be understood that when describing the connection or communication relationship between two components, unless it is explicitly stated that the two components are directly connected or directly communicating, the connection or communication between the two components can be understood as direct connection or communication, or as indirect connection or communication through an intermediate component.

[0037] In order to make the technical solutions and advantages of the embodiments of the present disclosure more clearly understood, the exemplary embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0038] The purpose of the present disclosure is to provide a reconfigurable master-slave core design solution under a multi-core GPU architecture. The GPU core refers to a processor with computing functions implemented by hardware, which includes components such as a computing unit and a cache, and can be a GPGPU (general-purpose graphics processing unit) or a GPU.

[0039] One embodiment of the present disclosure provides a graphics processing system based on a multi-core GPU architecture, the system comprising at least: a plurality of GPU cores, each GPU core comprising a main core configuration interface and a first communication interface, each GPU core being configured to: obtain main core configuration information through the main core configuration interface, enable the first communication interface when the main core configuration information indicates that the GPU core is the main core, and the first communication interface is used to communicate with the CPU.

[0040] In the present disclosure, enabling the first communication interface specifically refers to enabling the function of the first communication interface to communicate with the CPU.

[0041] The connections of multiple GPU cores in the system are in equal positions, and each GPU core can communicate with the CPU through the first communication interface. Therefore, in the system provided by the embodiment of the present disclosure, any GPU core can be used as the main core, which provides a feasibility guarantee for the reconstruction of the main core of the multi-core GPU architecture from the perspective of physical connection relationship. On this basis, the GPU core can receive the main core configuration information through the main core configuration interface, and determine whether the GPU core is the main core based on the main core configuration information. If the GPU core is the main core, then the first communication interface of the GPU core is enabled, and the connection relationship of the GPU core is changed in this way, so that only the main core can communicate with the CPU. It can be seen that, using the graphics processing system provided by the present disclosure, the configuration of the main core is not fixed in the chip design stage, but the master and slave cores can be reconstructed according to the actual situation, thereby avoiding the situation where the fixed main core is damaged and the chip is scrapped, which can effectively improve the chip yield and reduce product costs.

[0042] like Figure 1 As shown, in the disclosed embodiment, the interfaces for the GPU core to communicate with the outside world may include the following categories: a main core configuration interface, a first communication interface (also called a CPU communication interface in this embodiment), a memory communication interface, and a second communication interface (also called a status interface in this embodiment).

[0043] The GPU core can obtain the following information through the main core configuration interface, but is not limited to:

[0044] The main core identification (ID) is used by each GPU core (such as Core 0, Core 1...Core n) to identify the main core; the main core communication base address is used by the slave core to address the main core in order to communicate with the main core; the boot selection (Boot select) is used to notify the GPU core to load the boot code from the memory.

[0045] In the embodiment of the present disclosure, the Boot select corresponding to the main core is transmitted through the main core configuration interface to notify the main core to load the boot code from the memory. The Boot select corresponding to the main core is also called the main core boot indication information.

[0046] Optionally, the Boot select corresponding to the slave core may also be transmitted through the master core configuration interface, so that the slave core loads the boot code from the memory according to the information.

[0047] The above-mentioned main core configuration information serving as a basis for enabling the first communication interface at least includes a main core identifier.

[0048] Among them, the CPU communication interface is used to receive commands from the CPU or return status to the CPU. Only the main core has the ability to communicate with the CPU, so the CPU only sends commands to the main core. When the communication between GPU cores and the communication between the GPU core and the CPU use the same bus protocol, the CPU communication interface and the communication interface between each GPU core can be connected to a bus network, thereby reducing the connection relationship of the bus. It should be pointed out that in practice, the bus network connected to the first communication interface and the bus network connected between the GPU cores can also be two independent bus networks.

[0049] Among them, the memory communication interface is used for the GPU core to read and write memory. Usually, multiple GPU cores need to exchange data with the memory. The memory communication interface of each GPU core can be uniformly connected to the data communication network.

[0050] The status interface is used for the GPU core to send operating status information. The specific contents of the operating status information transmitted by the status interface depend on the design of the GPU itself, and the embodiments of the present disclosure do not limit this. As an example and not a limitation, the operating status information may include: GPU interruption, GPU power status and other pin status, and may also include other types of status information.

[0051] In the disclosed embodiment, the running status information of the main core is sent to the status information receiving module, while the running status information of the slave core does not need to be sent to the status information receiving module. In order to ensure that only the running status information of the main core is sent to the status information receiving module, a feasible implementation method is: the system also includes a state selector, the state selector is connected to the state interface of each GPU core, and the state selector is configured to: identify the running status information sent by the main core according to the main core configuration information obtained by the selection end, and send it to the status information receiving module, and the status information receiving module can be a CPU or other processing module that needs to obtain the running status of the main core. Another feasible implementation method is: each GPU core is configured to: enable the status interface when the main core configuration information indicates that the GPU core is the main core, and close the status interface when the main core configuration information indicates that the GPU core is not the main core. In practical applications, the selection of the running status information of the main core through the state selector can reduce hardware wiring and simplify the hardware connection structure.

[0052] In another embodiment of the present disclosure, if the running status information includes information that can be transmitted through an interface, correspondingly, such running status information of the GPU core can be transmitted by the CPU communication interface. Since only the CPU communication interface of the main core is enabled, transmitting the running status information through the CPU communication interface can ensure that only the running status information of the main core is sent to the CPU.

[0053] Based on any of the above embodiments, there are multiple ways to connect the main core configuration interface. Based on a feasible connection method, the system provided by the present disclosure may also include a main core configuration register, which is connected to the main core configuration interface of each GPU core and is used to temporarily store the main core configuration information. Correspondingly, the main core configuration interface reads the main core configuration information from the main core configuration register. In addition, the selection end of the state selector can also be connected to the main core configuration register to obtain the main core configuration information. Based on another feasible connection method, the main core configuration interface is directly connected to the CPU.

[0054] In the disclosed embodiment, the main core configuration register can receive the configuration from the CPU through the configuration bus, and then each GPU core reads the CPU configuration from the main core configuration register and reconstructs the connection of the GPU core accordingly (enable / disable the corresponding interface).

[0055] Based on any of the above embodiments, the main core is selected from the available GPU cores, and the information of the available GPU cores can be stored on the above system. Accordingly, the above system can also include a storage module, and the storage module is used to store the information of the available GPU cores; the CPU is configured to: select the main core according to the information of the available GPU cores, and send the main core configuration information. Of course, the information of the available GPU cores can also be stored outside the above system.

[0056] The graphics processing system based on the multi-core GPU architecture provided by the present disclosure can be a die (tube core), or a SOC (System on Chip) with multiple dies interconnected, or other organizational forms. The connections of multiple GPU cores in the system are in equal positions. In terms of hardware wiring, the connections of multiple GPU cores are all connected to the system, so that any core can be used as the main core.

[0057] The following uses a die as an example to illustrate the architecture and working principle of the graphics processing system provided by the present disclosure.

[0058] exist Figure 2 In one embodiment shown, a single-die graphics processing system includes multiple GPU cores, and a main core configuration interface and a status interface of the GPU core are connected to the outside world through a main core configuration unit.

[0059] Each GPU core is used to process drawing commands, and according to the drawing commands, execute the image rendering pipeline, and can also be used to execute other calculation commands; multiple GPU cores complete the execution of drawing or other computing tasks as a whole. Each GPU core further includes: a computing unit, which is used to execute instructions compiled by the shader, and is a programmable module composed of a large number of ALUs; a cache (Cache), which is used to cache GPU core data to reduce memory access; a rasterization module, a fixed stage of the 3D rendering pipeline; a slicing (Tilling) module, which performs slicing processing on a frame in the TBR and TBDR GPU architectures; a cropping module, a fixed stage of the 3D rendering pipeline, which crops out the primitives outside the observation range or that are not displayed on the back; a post-processing module, which is used to scale, crop, rotate, and other operations on the drawn image; a micro core (Micro core), which is used for scheduling between various pipeline hardware modules on the GPU core, or for task scheduling of multiple GPU cores.

[0060] The master core configuration interface, CPU communication interface, memory interface and status interface of each GPU core are connected to the on-chip network. The on-chip network is used for data exchange between masters and slaves on the graphics processing system. In this embodiment, the on-chip network includes a configuration bus, a data communication network, a communication bus, etc.

[0061] The ID of the available GPU core is stored on the fuse (not shown in the figure) of the graphics processing system. The application processor (i.e., CPU) accesses the fuse through the PCIe interface to obtain the ID of the available GPU core; the application processor selects a GPU core from the available GPU cores as the main core, and stores the ID, Boot select, and main core base address of the main core to the main core configuration register of the main core configuration unit via the configuration bus of the on-chip network; the microcore of each GPU core reads the main core ID from the main core configuration register via the on-chip network through the main core configuration interface, and compares the main core ID with the ID of the GPU core. If the main core ID is the ID of the GPU core, the CPU communication interface of the GPU core is enabled; the application processor controls the reset of the GPU core via the on-chip network; the main core reads the Boot select from the main core configuration register via the on-chip network through the main core configuration interface, and reads the startup code from the memory via the on-chip network through the memory interface, to complete the startup; and then schedules and configures the slave core. During the operation of the main core, the operation status information is sent through the status interface via the on-chip network. The selection end of the state selector of the main core configuration unit is connected to the main core configuration register. According to the main core ID in the main core configuration register, the operation status information of the main core is identified from the operation status information, so that the operation status information of the main core is sent to the application processor or other modules that need to receive the main core operation status information through the on-chip network.

[0062] like Figure 2 As shown, the graphics processing system may also include:

[0063] General DMA (Direct Memory Access) is used to perform data transfer between host memory and graphics processing system memory (such as graphics card memory). For example, DMA is used to move vertex data of 3D drawings from host memory to graphics processing system memory.

[0064] PCIe controller, an interface for communicating with the host, implements the PCIe protocol, and enables the graphics processing system to be connected to the host through the PCIe interface. The host runs programs such as the graphics API and graphics card driver;

[0065] The application processor is used to schedule tasks of various modules on the graphics processing system. For example, after the GPU renders a frame of image, it notifies the application processor, and the application processor then starts the display controller to display the image drawn by the GPU on the screen.

[0066] Memory controller, used to connect memory devices and save data on SOC;

[0067] Display controller, which controls the output of the frame buffer in the memory to the display via the display interface (HDMI, DP, etc.);

[0068] Video decoding, which can decode the encoded video on the host hard disk into a displayable picture;

[0069] Video encoding can encode the original video code stream on the host hard disk into a specified format and return it to the host.

[0070] exist Figure 3 In another embodiment shown, a single-die graphics processing system includes multiple GPU cores, the status interface of the GPU core is connected to the outside world through a main core configuration unit, and the main core configuration interface of the GPU core is directly connected to the application processor in a GPIO manner.

[0071] The disclosed embodiment also provides an electronic device, which includes a graphics processing system based on a multi-core GPU architecture as described in any of the above embodiments. In some usage scenarios, the product form of the electronic device is a graphics card; in other usage scenarios, the product form of the electronic device is a CPU motherboard.

[0072] The disclosed embodiments also provide an electronic device, which includes the above-mentioned electronic device. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, a workstation, a server, etc.

[0073] The disclosed embodiment also provides a main core configuration unit based on a multi-core GPU architecture, such as Figure 4 As shown, the main core configuration unit includes:

[0074] A state selector, the state selector is connected to the second communication interface of the multiple GPU cores, and the state selector is configured to: identify the running state information sent by the main core according to the main core configuration information obtained by the selection end, and send it to the state information receiving module; the main core configuration information is used to instruct the main core among the multiple GPU cores to enable the first communication interface, and the first communication interface is used to communicate with the CPU.

[0075] like Figure 4 As shown, the main core configuration unit may further include a main core configuration register, which is connected to the main core configuration interface of each GPU core and is used to temporarily store the main core configuration information sent by the CPU.

[0076] Optionally, the main core configuration register is also connected to the selection end of the state selector so as to output the main core configuration information to the selection end of the state selector.

[0077] The disclosed embodiment also provides a graphics processor core in a multi-core GPU architecture, wherein the graphics processor core includes a main core configuration interface and a first communication interface; the graphics processor is configured to: obtain main core configuration information through the main core configuration interface, enable the first communication interface when the main core configuration information indicates that the GPU core is the main core, and the first communication interface is used to communicate with the CPU.

[0078] In the present disclosure, there are multiple communication modes between the first communication interface and the CPU. As an example and not limitation, the first communication interface can be connected to a bus network and communicate with the CPU through the bus network. In practice, the bus network used by the first communication interface and the bus network used between GPU cores can be two independent bus networks. In order to reduce the bus connection relationship and simplify the chip connection, the communication between GPU cores and the communication between the main core and the CPU can use the same bus network, that is, the bus network used by the first communication interface and the bus network used between GPU cores are the same bus network.

[0079] In a feasible implementation of the present disclosure, the GPU core may further include a second communication interface, and the GPU core is configured to: send operating status information through the second communication interface, wherein the operating status information of the main core is sent to the status information receiving module. In another feasible implementation, the operating status information of the main core may be sent to the CPU through the first communication interface.

[0080] The present disclosure also provides a method for configuring a main core based on a multi-core GPU architecture. Figure 5 As shown, the method includes the following operations:

[0081] Step 501: The CPU selects a main core from available GPU cores and sends main core configuration information;

[0082] Step 502: Each GPU core obtains the main core configuration information, and enables a first communication interface when the main core configuration information indicates that the GPU core is the main core, where the first communication interface is used to communicate with the CPU.

[0083] Among them, a feasible implementation method for sending the main core configuration information includes: the CPU saves the main core configuration information to the main core configuration register; accordingly, each GPU core obtains the main core configuration information, and its implementation method includes: each GPU core obtains the main core configuration information from the main core configuration register through the main core configuration interface.

[0084] Another feasible implementation of sending the main core configuration information includes: the CPU directly sends the main core configuration information to each GPU core.

[0085] In another embodiment of the present disclosure, the main core configuration process of a multi-core GPU is as follows: first, a fully functional GPU core is tested, and relevant information of the usable GPU core (such as GPU ID) is stored in the fuse of the chip or other unchangeable memory; when the chip is powered on, the CPU selects the main core from the fully functional GPU cores, and then stores the main core ID, BOOTSELECT and main core base address in the main core configuration register through the configuration bus, each GPU core reads the main core ID from the main core configuration register, and determines whether the GPU core is the main core. If so, the CPU communication interface of the GPU core is enabled, thereby completing the main core configuration; after the configuration is completed, the CPU releases the reset of the GPU core; the process of enabling the main core to load the startup code is enabled, and the main core reads BOOT SELECT from the main core configuration register, thereby loading the startup code from the memory; after the main core startup is completed, the slave core can be configured or scheduled and other related work.

[0086] When the CPU writes the configuration information into the main core configuration register, the configuration is considered complete.

[0087] Based on the above solution, in a multi-GPU core system, flexible configuration of the main core is achieved, so that as long as there are cores with complete functions in the system, the system can be considered available, thereby improving the utilization rate of the chip.

[0088] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0089] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A graphics processing system based on a multi-core GPU architecture, the graphics processing system comprising: A plurality of GPU cores, each GPU core comprising a main core configuration interface and a first communication interface, wherein each GPU core is configured to: obtain main core configuration information through the main core configuration interface, and enable the first communication interface when the main core configuration information indicates that the GPU core is the main core, wherein the first communication interface is used to communicate with the CPU; Each GPU core further includes a second communication interface, and each GPU core is configured to: send running status information through the second communication interface, wherein the running status information of the main core is sent to the status information receiving module; The system also includes a state selector, which is connected to the second communication interface of each GPU core. The state selector is configured to: identify the running status information sent by the main core according to the main core configuration information obtained by the selection end, and send it to the status information receiving module. 2 . The system according to claim 1 , wherein the first communication interface is connected to a bus network, and the bus network is used for communication between GPU cores and communication between the main core and the CPU.

3. The system according to any one of claims 1-2, further comprising a main core configuration register, wherein the main core configuration register is connected to the main core configuration interface of each GPU core and is used to temporarily store the main core configuration information sent by the CPU.

4. The system according to any one of claims 1-2, further comprising a storage module, wherein the storage module is used to store information of available GPU cores; The CPU is configured to: select a main core according to the information of the available GPU cores, and send main core configuration information.

5. According to the system according to any one of claims 1-2, the main core configuration information includes at least one of the following: a main core identifier, a main core base address, and a main core startup indication information.

6. An electronic device comprising the system according to any one of claims 1 to 5.

7. An electronic device comprising the electronic device according to claim 6.

8. A main core configuration unit, applied to a graphics processing system based on a multi-core GPU architecture, comprising: A state selector, wherein the state selector is connected to the second communication interface of the plurality of GPU cores, and the state selector is configured to: identify the operation state information sent by the main core according to the main core configuration information obtained by the selection end, and send the operation state information to the state information receiving module; the main core configuration information is used to instruct the main core among the plurality of GPU cores to enable the first communication interface, and the first communication interface is used to communicate with the CPU.

9. The main core configuration unit according to claim 8 further comprises a main core configuration register, which is connected to the main core configuration interface of each GPU core and is used to temporarily store the main core configuration information sent by the CPU so that the main core configuration interface can obtain it.

10. A graphics processor core, applied to a graphics processing system in a multi-core GPU architecture, comprising a main core configuration interface and a first communication interface; the graphics processor core is configured to: obtain main core configuration information through the main core configuration interface, enable the first communication interface when the main core configuration information indicates that the GPU core is the main core, and the first communication interface is used to communicate with the CPU; It also includes a second communication interface, and the graphics processor core is configured to: send running status information through the second communication interface, wherein: The running status information of the main core is sent to the status information receiving module; the second communication interface is connected to the status selector so that the status selector identifies the running status information sent by the main core according to the main core configuration information obtained by the selection end, and sends it to the status information receiving module. 11 . The graphics processor core according to claim 10 , wherein the first communication interface is connected to a bus network, and the bus network is used for communication between GPU cores and communication between the main core and the CPU.

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