Test method, device and equipment for memory capacitor stability
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-01
- Publication Date
- 2026-06-26
Smart Images
Figure CN116935941B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method, apparatus and device for testing the stability of memory capacitance. Background Technology
[0002] In the current semiconductor technology field, the testing of Dynamic Random Access Memory (DRAM) products requires testing the stability of the capacitor dielectric. Existing technologies primarily employ high-temperature operating life (HTOL) testing to assess the reliability of DRAM products. This involves collecting and comparing leakage current data of the capacitor dielectric before and after the high-temperature process to determine whether the capacitance is stable.
[0003] However, this method in the existing technology has a complex testing process and requires a long testing time, resulting in extremely low testing efficiency. Summary of the Invention
[0004] This disclosure provides a method, apparatus, and device for testing the stability of memory capacitors, which addresses the problems of complex testing processes, long testing times, and low testing efficiency in the prior art.
[0005] According to some embodiments, a first aspect of this disclosure provides a method for testing the stability of memory capacitance, comprising:
[0006] Write logic levels into all the capacitors of the memory to be tested, the memory comprising multiple capacitors arranged in an array;
[0007] Read the logic level from all the capacitors in the memory;
[0008] Repeat the above write-to-read steps to obtain multiple sets of logic levels written into the capacitors of the memory and logic levels read out;
[0009] The logic levels written into the capacitors of the memory and the logic levels read out are transmitted to a computer device; wherein the logic levels written into the capacitors of the memory and the logic levels read out are used to determine the stability of the memory capacitors.
[0010] In an optional embodiment of this disclosure, after writing logic levels to all capacitors of the memory to be tested and before reading logic levels from all capacitors of the memory, the method further includes:
[0011] Leave the memory idle.
[0012] In one alternative embodiment of this disclosure, the idle time of the memory is any duration between 2 ms and 1024 ms.
[0013] In an optional embodiment of this disclosure, before writing logic levels to all capacitors of the memory to be tested, the method further includes:
[0014] During the circuit testing phase, the voltage of the lower plate of each capacitor and the voltage of the bit line pairs of the memory during pre-charging are set in test mode using DFT.
[0015] In an optional embodiment of this disclosure, setting the voltage of the lower plate of the capacitor and the voltage of the bit line pair during pre-charging via DFT in test mode includes:
[0016] In test mode, the voltage difference between the upper and lower plates of all capacitors in the memory is adjusted to be greater than a first preset voltage difference using DFT.
[0017] And / or,
[0018] In test mode, the voltage difference between the voltage read from one bit line and the pre-charge voltage of the other bit line in the bit line pair of the memory is adjusted to be less than a second preset voltage difference by using DFT.
[0019] In an optional embodiment of this disclosure, the first preset voltage difference is Vcc / 2, and the second preset voltage difference is (Ccell / (Ccell+Cbl))*(Vcc / 2);
[0020] Wherein, Ccell is the capacitance value on the capacitor, Cbl is the parasitic capacitance value on the bit line, and Vcc is the operating voltage value.
[0021] In an optional embodiment of this disclosure, setting the voltage of each capacitor's lower plate and the voltage of the memory's bit line pairs during pre-charge via DFT in test mode includes:
[0022] Write logic "0" into all capacitors of the memory;
[0023] The voltage of the lower plate of each capacitor is raised to 1V, and / or the voltage of the bit line pair during pre-charging is applied to be 0.42V to 0.46V.
[0024] In an optional embodiment of this disclosure, setting the voltage of each capacitor's lower plate and the voltage of the memory's bit line pairs during pre-charge via DFT in test mode includes:
[0025] Write logic "1" into all capacitors of the memory.
[0026] The voltage of the lower plate of each capacitor is pulled down to 0V, and / or the voltage of the bit line pair during pre-charging is applied to be 0.56V to 0.59V.
[0027] In an optional embodiment of this disclosure, repeating the above-described write-to-read steps to obtain multiple sets of logic levels written into the capacitors of the memory and read out the logic levels includes:
[0028] Repeat the above write-to-read steps N times to obtain N sets of logic levels written to the capacitors of the memory and the logic levels read out, where N is a positive integer greater than or equal to 20.
[0029] According to some embodiments, a second aspect of this disclosure provides a method for testing the stability of memory capacitance, comprising:
[0030] Receive multiple sets of logic levels written into the capacitors of the memory under test and logic levels read out, transmitted by the test device;
[0031] Based on the logic levels written into and read from the multiple sets of capacitors in the memory to be tested, the number of capacitor failures in the memory is determined each time, thus obtaining the number of capacitor failures in multiple sets.
[0032] The stability of the memory capacitors is determined based on the changes in the number of failures of the multiple sets of capacitors.
[0033] In an optional embodiment of this disclosure, determining the number of capacitor failures in the memory for each test based on the logic levels in the multiple sets of capacitors written to the memory under test and the logic levels read out, to obtain multiple sets of capacitor failure counts, includes:
[0034] For each group of capacitors written to the memory and the corresponding logic level read from the memory, if the logic level during writing and the logic level during reading are consistent, then the data in the capacitor is determined to be reliable.
[0035] If there is no consistency, the capacitor is determined to be faulty;
[0036] The number of capacitor failures for each group is obtained by determining the number of capacitor failures based on the logic level written into and read from each group of capacitors in the memory.
[0037] In an optional embodiment of this disclosure, determining the stability of the memory capacitor based on the change in the number of failures of the multiple sets of capacitors includes:
[0038] Based on the dynamic changes among the number of capacitor failures in the multiple groups, a stability evaluation curve for the memory capacitor is obtained. The stability evaluation curve is used to represent the relationship between the number of tests and the number of capacitor failures in each group corresponding to each test.
[0039] The stability of the memory capacitor is determined based on the stability evaluation curve.
[0040] According to some embodiments, a third aspect of this disclosure provides a testing apparatus for memory capacitance stability, comprising:
[0041] A read / write module is used to write logic levels to all the capacitors of the memory under test, the memory comprising multiple capacitors arranged in an array;
[0042] The read / write module is also used to read logic levels from all the capacitors of the memory;
[0043] The processing module is used to repeat the above-described write-to-read steps to obtain multiple sets of logic levels written into the capacitors of the memory and the logic levels read out.
[0044] An output module is used to transmit the logic levels written into the capacitors of the memory and the logic levels read out to a computer device; wherein the logic levels written into the capacitors of the memory and the logic levels read out are used to determine the stability of the memory capacitors.
[0045] According to some embodiments, a fourth aspect of this disclosure provides a testing apparatus for memory capacitance stability, comprising:
[0046] The receiving module is used to receive multiple sets of logic levels written into the capacitors of the memory under test and logic levels read out from the test device.
[0047] The processing module is used to determine the number of capacitor failures in the memory each time based on the logic levels written to the capacitors in the multiple sets of capacitors to be tested and the logic levels read out, thereby obtaining the number of capacitor failures in multiple sets.
[0048] The processing module is also used to determine the stability of the memory capacitor based on the changes in the number of failures of the multiple sets of capacitors.
[0049] According to some embodiments, a fifth aspect of this disclosure provides a testing apparatus for memory capacitance stability, comprising:
[0050] Test circuitry, storage unit, at least one processor, and transmission interface;
[0051] The storage unit stores instructions executable by the at least one processor, which, when executed by the at least one processor, enable the testing device to perform the memory capacitance stability testing method described in any of the first aspects.
[0052] According to some embodiments, a sixth aspect of this disclosure provides a computer device, including:
[0053] At least one processor, a storage unit communicatively connected to the at least one processor, a display, and a transmission interface;
[0054] The storage unit stores instructions executable by the at least one processor, which, when executed by the at least one processor, enable the computer device to perform the memory capacitance stability test method according to any one of the second aspects.
[0055] According to some embodiments, a seventh aspect of this disclosure provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, enable the processor to perform the memory capacitance stability test method according to any one of the first or second aspects.
[0056] According to some embodiments, the eighth aspect of this disclosure provides a computer program product, including a computer program that, when executed by a processor, implements the method for testing the stability of memory capacitance as described in either the first or second aspect.
[0057] This disclosure provides a method, apparatus, and device for testing the stability of memory capacitors. In this method, the testing apparatus writes logic levels to all capacitors of the memory under test and reads logic levels from all capacitors of the memory. The write-to-read steps are repeated to obtain multiple sets of logic levels written to the capacitors and read logic levels, which are then transmitted to a computer device. The computer device determines the number of capacitor failures in the memory in each test based on the multiple sets of logic levels written to the capacitors and read logic levels. Finally, based on the changes in the number of capacitor failures in the multiple sets of capacitor failures, the stability of the memory capacitor medium is determined. By comparing the written and read levels, the capacitor medium can be tested during the circuit testing stage without waiting for a long time, quickly verifying the stability of the capacitors. The testing process is simple and the testing time is short, effectively improving the testing efficiency of memory capacitors. Attached Figure Description
[0058] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0059] Figure 1 This is a schematic diagram of a high-temperature service life testing scheme in the prior art;
[0060] Figure 2 A schematic flowchart of Embodiment 1 of the method for testing the stability of memory capacitors provided in this disclosure;
[0061] Figure 3 A schematic flowchart of Embodiment 2 of the method for testing the stability of memory capacitors provided in this disclosure;
[0062] Figure 4 A schematic flowchart of Embodiment 3 of the method for testing the stability of memory capacitors provided in this disclosure;
[0063] Figure 5 A schematic flowchart of Embodiment 4 of the method for testing the stability of memory capacitors provided in this disclosure;
[0064] Figure 6 A schematic diagram showing the connection of writing logic "0" into a capacitor according to an embodiment of this disclosure;
[0065] Figure 7 A schematic diagram showing the connection of writing a logic "1" into a capacitor according to an embodiment of this disclosure;
[0066] Figure 8 A schematic diagram of a test circuit provided in an embodiment of this disclosure;
[0067] Figure 9 A schematic diagram illustrating the stability testing process of a capacitor provided in an embodiment of this disclosure;
[0068] Figure 10 A schematic diagram of a stability evaluation curve provided for an example of this disclosure;
[0069] Figure 11 Another schematic diagram of stability evaluation curves provided for this disclosure example;
[0070] Figure 12 A schematic diagram of the structure of a test apparatus for memory capacitance stability provided in this disclosure, according to embodiment one;
[0071] Figure 13A schematic diagram of the structure of a second embodiment of the memory capacitance stability testing apparatus provided in this disclosure;
[0072] Figure 14 A schematic diagram of the physical structure of the memory capacitance stability testing device provided in the embodiments of this disclosure;
[0073] Figure 15 This is a schematic diagram of the structure of a computer device entity provided in an embodiment of this disclosure. Detailed Implementation
[0074] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.
[0075] The terms "first," "second," etc., used in this disclosure, claims, and accompanying drawings are for distinguishing similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such use of terms can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein.
[0076] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion, such that a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.
[0077] In the field of semiconductor technology, the stability testing of the capacitors in the memory array is an essential part of the production and design process of memory (such as Dynamic Random Access Memory, or DRAM). It is generally characterized by product reliability testing. Therefore, the existing technology generally uses the high temperature operating life test (HTOL) to test the memory array. Figure 1 This is a schematic diagram of a high-temperature service life testing scheme in the prior art, such as... Figure 1As shown, during the test, the product is placed in a temperature chamber for heating (i.e., the failure rate acceleration process). A certain high temperature is set, and the product is left to stand for a period of time to obtain the final failure rate. This failure rate varies depending on the product and performance test. In specific tests, the product needs to stand for more than 500 hours before being removed and subjected to performance characterization tests at a set voltage. The stability of the capacitor dielectric is generally tested by collecting leakage current data for comparison to ultimately determine whether the capacitor dielectric in the memory is stable. However, current testing methods are time-consuming, costly, and inefficient.
[0078] To address the problems existing in the prior art, this disclosure provides a method for testing the stability of memory capacitors. The stability of the capacitor dielectric is determined by the change in the level of repeated writing. Based on this, the test of the capacitor dielectric stability is implemented in the circuit testing stage. Specifically, in a specific test mode, a fixed logic level is written into the memory array, and after a period of rest, the data is read. This process is repeated multiple times to compare multiple sets of input logic levels and output logic levels. This method has a simple test process, the data is relatively clear and easy to analyze, the overall test time is controllable, and the test efficiency can be improved.
[0079] The following describes in detail the test method for memory capacitor stability provided in this disclosure through some specific implementation methods.
[0080] The specific implementation of the memory capacitance stability testing method provided in this disclosure requires the cooperation of a testing device and a computer. The testing device needs to include a testing circuit that writes logic levels into the memory array (i.e., multiple capacitors arranged in an array) of the memory under test, and then reads the logic levels from all the capacitors of the memory. Therefore, the testing circuit also needs to have the functions of writing and reading logic levels. In addition, the testing device needs to control the execution of the corresponding steps and output the multiple sets of written logic levels and the corresponding read logic levels obtained from the test to the computer for analysis. Therefore, the testing device also needs to include components such as memory, processor, and transmission interface.
[0081] The computer device can be a computer, personal computer, or other similar device, as long as it has data analysis and processing capabilities and can output analysis results. This solution does not restrict the specific form of the device. The computer device is directly connected to the testing device through a transmission interface. After reading the logic level, the testing device can transmit the written logic level and the corresponding read logic level to the computer device through the transmission interface for subsequent analysis and processing.
[0082] Figure 2A schematic flowchart of Embodiment 1 of the method for testing the stability of memory capacitance provided in this disclosure is shown below. Figure 2 As shown, this memory capacitance stability test method is a scheme applied in a test device, and specifically includes the following steps:
[0083] S101: Write logic levels to all capacitors of the memory to be tested, the memory comprising multiple capacitors arranged in an array.
[0084] In this step, when it is necessary to perform a capacitance stability test on the memory, the memory to be tested is connected to the test device. The test device controls the magnitude of the write voltage to write logic levels to all the capacitors of the memory. The logic level can be high or low, and this solution does not restrict it.
[0085] S102: Read logic levels from all capacitors in the memory.
[0086] In this step, after writing logic levels to all the capacitors of the memory, logic levels are then read out from all the capacitors of the memory, thus obtaining a set of written logic levels and corresponding read logic levels.
[0087] S103: Repeat the above write to read steps to obtain the logic levels in the capacitors written to the memory and the logic levels read out.
[0088] In the above steps, in order to effectively analyze the stability of the memory capacitors, i.e., the stability of the capacitor dielectric, through repeated tests, multiple tests are required. This means that all capacitors in the memory need to be written to and read from logic levels multiple times. In other words, steps S101 and S102 need to be repeated multiple times to obtain multiple sets of logic levels written to and read from the capacitors in the memory, which can be used to analyze the stability of the memory capacitors.
[0089] Optionally, in one specific implementation of this scheme, after each logic level is written to all capacitors of the memory to be tested, and before the logic level is read from all capacitors of the memory, the memory to which the logic level has been written can be left idle, that is, the memory can be left idle.
[0090] In this scheme, after writing logic levels to all capacitors in the memory, the memory is left idle for a preset duration, which can be selected according to the actual situation. In specific implementations, it can be any duration between 2ms and 1024ms, such as 48ms, 64ms, 144ms, etc., or it can be greater than 1024ms; this scheme does not impose any restrictions on this.
[0091] After each preset rest period, the logic level of each capacitor in the memory is read during the test to obtain a set of written logic levels and read logic levels. Since the capacitor medium in the memory may be unstable, the read logic level may not be exactly the same as the written one. Therefore, the computer device can determine the stability of the capacitor in the memory, that is, the stability of the capacitor medium, based on these written and read logic levels.
[0092] To improve the accuracy of the test, it is necessary to repeatedly write the logic level, let it stand, and then read the logic level. Generally, this process is repeated multiple times.
[0093] In one possible implementation, the above write-to-read steps can be repeated N times to obtain N sets of logic levels written to the capacitors of the memory and the logic levels read out, where N is a positive integer greater than or equal to 20. The specific number of repetitions can be selected according to the actual situation. This solution does not limit the specific number of repetitions, as long as it can test whether the capacitors of the memory are stable.
[0094] S104: Transmit the logic levels written to and read from the capacitors in the memory to the computer device; wherein the logic levels written to and read from the capacitors in the memory are used to determine the stability of the memory capacitors.
[0095] In this step, the capacitance of the memory is tested in the testing device. This involves writing logic levels to all capacitors and reading out the logic levels. After repeating the aforementioned write and read process multiple times, multiple sets of logic levels written to the capacitors of the memory and logic levels read out are obtained. These results need to be output to a computer device for analysis to ultimately determine the stability of the capacitance of the memory under test.
[0096] In practice, a transmission channel is established between the testing device and the computer equipment via a preset interface. After each test, the testing device can output a set of logic levels for the written capacitors and the read logic levels to the computer equipment through this preset interface. For example, if the testing device and the computer equipment are directly connected via a data cable, the logic levels for the written capacitors and the read logic levels can be directly transmitted to the computer equipment via the data cable. Alternatively, the analysis software installed on the computer equipment can directly read these logic levels for the written capacitors and the read logic levels via the data cable. This solution does not impose any restrictions on this approach.
[0097] In this scheme, it should be understood that the preset interface refers to the reserved interface between the test device and the computer equipment, which is used for data interaction between the test device and the computer equipment.
[0098] Each set of logic levels for writing to and reading from the capacitor is transmitted repeatedly until the end of the cycle. All sets of logic levels for writing to and reading from the capacitor are then transmitted to the computer device. Based on these levels, the computer device determines the number of capacitor failures in the memory during each test, thereby ultimately determining the stability of the memory capacitors.
[0099] The memory capacitor stability testing method provided in this embodiment involves writing logic levels to all capacitors during the circuit testing phase, then reading the logic levels from all capacitors. This writing and reading process is repeated multiple times to obtain multiple sets of logic levels written to and read from the memory capacitors. These multiple sets of logic levels are used to determine the stability of the memory capacitors. The process is simple, the testing time is short, and the data is simple and easy to analyze, effectively improving testing efficiency.
[0100] Figure 3 A schematic flowchart of Embodiment 2 of the method for testing the stability of memory capacitance provided in this disclosure is shown below. Figure 3 As shown, the method for testing the stability of memory capacitance is applied in a computer device connected to the testing apparatus, and specifically includes the following steps:
[0101] S201: Receives multiple sets of logic levels written into the capacitors of the memory under test and logic levels read out, transmitted by the test device.
[0102] In this step, the computer device acquires multiple sets of data from the testing device to test the memory under test, specifically multiple sets of logic levels for writing to the memory capacitors and logic levels for reading. In one specific implementation, the computer device can receive the multiple sets of logic levels for writing to the memory capacitors and the logic levels for reading transmitted by the testing device through a preset interface. Each time the testing device repeats the write, rest, and read process, it acquires a set of logic levels for that write and the logic levels for that read, and then transmits these acquired values to the computer device through the interface connected to the computer device.
[0103] That is, the computer equipment receives the logic levels of all capacitors written to the memory and the logic levels read out each time from the test device through a preset interface.
[0104] Optionally, in one specific embodiment, the testing device repeats the test N times, where N is a positive integer greater than or equal to 20. That is, the testing device can repeat the test 20 times or more. Thus, for the computer device, it can receive 20 or more sets of logic levels written to all levels and logic levels read from all levels.
[0105] S202: Based on the logic levels written to the capacitors in the memory under test and the logic levels read out, determine the number of capacitor failures in the memory for each test, and obtain the number of capacitor failures in multiple sets.
[0106] In this step, after the computer device obtains the logic level of each test write to the memory capacitor and the logic level read, it needs to analyze and process the data to determine whether the capacitor in the memory is stable, that is, whether the capacitor medium is stable.
[0107] In one specific implementation, the computer device determines the data in the capacitor to be reliable if the logic level during writing and the logic level during reading are consistent for each capacitor in each group written to the memory and the corresponding logic level read from the memory; otherwise, the capacitor is determined to be faulty. Based on the number of capacitor failures determined by the logic levels in each group of capacitors written to the memory and the logic levels read from the memory, the number of capacitor failures in multiple groups is obtained.
[0108] The meaning of this scheme is that the computer equipment can compare and analyze the logic levels written to and read from a set of memory capacitors. For each capacitor, based on the comparison of the written and read logic levels, it can determine whether the capacitor is a failed capacitor, thereby determining the number of failed capacitors in the memory during each test. By analyzing the data from each test in this way, multiple sets of capacitor failure data can be obtained.
[0109] S203: Determine the stability of the memory capacitors based on the changes in the number of capacitor failures across multiple groups.
[0110] In this step, after determining the number of capacitor failures in each test, the computer device can determine the stability of the memory capacitors, i.e., the stability of the capacitor dielectric, based on the proportion of capacitor failures or the changes in the number of capacitor failures.
[0111] Specifically, in analyzing the logic levels written to and read from memory capacitors, it should be understood that for memory with poor stability, the number of failed data points in the test data may increase with each repetition of the above test. In other words, the memory experiences attenuation with each repeated test, especially with a large number of repetitions, resulting in more and more capacitor failures in each cycle. For memory with stable capacitors, the number of failed capacitors in the test data tends to stabilize after multiple repetitions, and the number of failed capacitors does not increase with each test. Therefore, in analyzing multiple sets of write and read logic levels for memory capacitors, the stability of the memory capacitors can be determined by observing the change in the number of failed capacitors after each repetition.
[0112] Optionally, in another implementation, if the number of capacitor failures is greater than a preset number based on the logic levels read after multiple logic levels are written to the capacitor, the capacitor of the memory can also be determined to be unstable; otherwise, the capacitor of the memory is determined to be stable. These preset numbers can be set according to the actual situation of the memory.
[0113] In this scheme, taking a repetition of twenty times as an example, if after several tests, the number of capacitor failures detected in subsequent tests exceeds a preset threshold, then the capacitors in the memory are determined to be unstable. If the number of capacitor failures detected each time is less than the preset threshold, and the number is relatively stable with little change, then the capacitors in the memory are determined to be stable.
[0114] Alternatively, taking a repeat of twenty times as an example, if the percentage of capacitor failures determined after multiple tests is greater than a preset threshold for the percentage of capacitor failures, then the capacitors in the memory are determined to be unstable. If the percentage of capacitor failures obtained each time is less than the preset threshold for the percentage of capacitor failures, then the capacitors in the memory are determined to be stable.
[0115] In general, the analysis of the capacitance stability of a memory under test in computer equipment is mainly based on the change in the number of capacitor failures. If the number of capacitor failures stabilizes after several tests and no more capacitor failures occur, then it can be basically determined that the capacitance of the memory is stable. Otherwise, if the number of capacitor failures changes in each test, then the capacitance of the memory is determined to be unstable.
[0116] The memory capacitor stability testing method provided in this embodiment allows a computer device to analyze and process the logic levels written and read from the memory under test for each test by the testing device. Based on the change in the number of capacitor failures, it can quickly determine whether the capacitors in the memory are stable. This testing scheme has a simple process, short testing time, and easy data analysis, effectively improving the efficiency and accuracy of testing the stability of the capacitor medium in the memory.
[0117] Figure 4 A flowchart illustrating Embodiment 3 of the method for testing the stability of memory capacitance provided in this disclosure is shown below. Figure 4 As shown above, in the above Figure 2 Based on the illustrated embodiment, in the specific implementation of this memory capacitance stability test scheme, before writing logic levels to all capacitors of the memory under test, the following steps are also included:
[0118] S301: During the circuit testing phase, the voltage of the lower plate of each capacitor and the voltage of the memory bit line pair during pre-charging are set in test mode via DFT.
[0119] In this scheme, when testing the memory, the voltage of the lower plate of the capacitor in the memory is set in the corresponding test mode using Digital Circuit Testability (DFT) during the circuit testing phase, and the voltage of the memory bit line pairs during pre-charging also needs to be set.
[0120] The specific implementation of this step includes at least the following methods:
[0121] In the first implementation method, the voltage difference between the upper and lower plates of all capacitors in the memory is adjusted to be greater than a first preset voltage difference in test mode by using DFT.
[0122] The second implementation involves adjusting the voltage difference between the voltage read from one bit line and the pre-charge voltage of the other bit line in the memory bit line pair to be less than a second preset voltage difference using DFT in test mode.
[0123] The third implementation involves adjusting the voltage difference between the upper and lower plates of all capacitors in the memory to be greater than a first preset voltage difference in test mode via DFT, while simultaneously adjusting the voltage difference between the voltage read from one bit line and the pre-charge voltage of the other bit line in the bit line pair of the memory to be less than a second preset voltage difference.
[0124] Optionally, in the aforementioned implementations, the first preset voltage difference is Vcc / 2, and the second preset voltage difference is (Ccell / (Ccell+Cbl))*(Vcc / 2); where Ccell refers to the capacitance value on the capacitor, Cbl is the parasitic capacitance value on the bit line, and Vcc is the operating voltage value.
[0125] For example, in a specific implementation, the working voltage Vcc is 1V and Vcc / 2 is 0.5V. By controlling the magnitude of the write voltage, logic "0" is written to all the capacitors in the memory, and the capacitance value Cell on the capacitor is 0V. This pulls the voltage of the lower plate of each capacitor up to 1V. At this time, the voltage difference between the upper and lower plates of the capacitor is 1V, which is greater than Vcc / 2. This makes it easier for these capacitors with unstable dielectrics to leak current, exposing the true failure situation. Applying a voltage of 0.42V to 0.46V, such as 0.42V, 0.425V, 0.43V, or 0.46V, to the bit line pairs of the memory during pre-charge reduces the voltage difference between the read voltage of one bit line and the pre-charge voltage of the other bit line, making it less than the potential of the bit line returning during pre-charge under normal operation. In other words, it reduces the sensing margin of the sensing amplifier when reading the memory capacitor. The voltage difference between the read voltage of one bit line and the pre-charge voltage of the other bit line is less than (Ccell / (Ccell+Cbl))*(Vcc / 2), making it more difficult to read the logic level written to these capacitors with unstable capacitor dielectrics, thereby exposing the true failure condition.
[0126] Alternatively, in another implementation, a logic "1" is written to all capacitors in the memory by controlling the magnitude of the write voltage, pulling the voltage of the lower plate of each capacitor down to 0V. The bit line pairs are precharged with voltages such as 0.56V to 0.59V, 0.56V, 0.575V, 0.58V, 0.585V, and 0.59V. During this test, to ensure accuracy, the same logic level is written to each capacitor in the memory, and the relevant voltage is set, thus providing a worse read environment and making it easier to expose capacitors with poor dielectric stability.
[0127] Optionally, in a specific implementation, between writing logic levels to each capacitor in the memory and reading out logic levels, the following steps are also included:
[0128] S302: Static storage.
[0129] In this step, similar to the previous embodiments, between each time logic levels are written to all capacitors of the memory under test and each time logic levels are read from all capacitors of the memory, the memory with the written logic levels can be left idle. In the specific implementation, the idle time can be selected according to the actual situation. For example, any time between 2ms and 1024ms, or a time greater than 1024ms, can be selected. This solution does not limit this.
[0130] The memory capacitor stability testing method provided in this embodiment uses a simple testing method to quickly verify the stability of the capacitor medium in the memory during the circuit testing stage. This advances the testing time of the capacitor medium, allows for early screening, exposes problems as early as possible, and improves testing efficiency.
[0131] Figure 5 A schematic flowchart of Embodiment 4 of the method for testing the stability of memory capacitance provided in this disclosure is shown below. Figure 5 As shown, based on the above embodiments, step S203 can be specifically implemented as follows:
[0132] S2031: Based on the dynamic changes among the number of capacitor failures in multiple groups, obtain the stability evaluation curve for the memory capacitors. The stability evaluation curve is used to represent the relationship between the number of tests and the number of capacitor failures in each group corresponding to each test.
[0133] S2032: Determine the stability of the memory capacitor based on the stability evaluation curve.
[0134] In the aforementioned steps, after determining the number of capacitor failures in each test, the computer equipment can directly analyze the changes in the number of capacitor failures to determine whether the capacitors in the memory are stable and output the determined results. It can also further analyze and display the data, generate a stability evaluation curve for output, and more intuitively show the stability of the capacitor medium.
[0135] The stability evaluation curve can more intuitively show the relationship between the number of tests and the number of capacitor failures corresponding to each test.
[0136] Based on the above embodiments, the following is an example of a DRAM memory to illustrate the test method for memory capacitance stability provided in this disclosure.
[0137] In the capacitor stability test scheme provided in this example, during the circuit test phase, the voltage of the lower plate of the capacitor is adjusted in test mode using DFT. Then, by controlling the write voltage of the bit line connected to the capacitor, logic "0" is written to all capacitors in the memory, so that all capacitors in the entire DRAM chip store "0", thereby creating a certain voltage difference between the upper and lower plates of each capacitor in the memory. After waiting for a period of time, such as 144ms, the value of all capacitors is read. This process is repeated N (N>=20) times.
[0138] Figure 6 This is a schematic diagram showing the connection of a capacitor with logic "0" written in it, provided in an embodiment of this disclosure. Figure 7 This is a schematic diagram showing the connection of writing a logic "1" into a capacitor according to an embodiment of this disclosure. Figure 8 A schematic diagram of a test circuit provided in an embodiment of this disclosure, with reference to... Figure 8 The storage cell 51 includes a first switching element M1 and a capacitor Cell. The first switching element M1 can be, for example, an N-type transistor. The source of M1 is connected to the capacitor C, the drain is connected to the bit line BL, and the gate is connected to the word line WL. A column select unit 52, a balancing unit 53, and a sense amplifier 54 are sequentially arranged on the bit line BL.
[0139] The column selection unit 52 includes a second switching element M2, which is an N-type transistor. Its source is connected to the local input / output signal line (LIO), its drain is connected to the bit line BL, and its gate is connected to the column selection signal line YS (Y Select).
[0140] The balancing unit 53 includes a third switching element M3, a fourth switching element M4, and a fifth switching element M5. All three switching elements are N-type transistors, and their gates are connected to the voltage of the equalizer (VEQ). Specifically, the source of the third switching element M3 and the drain of the fourth switching element M4 are connected to the voltage of the bit line precharge (VBLP). The drain of the third switching element M3 is connected to the bit line BL, and the source of the fourth switching element M4 is connected to the complementary bit line / BL.
[0141] The sense amplifier (SA) 54 is a differential amplifier with two input terminals connected to a bit line pair, namely bit line BL and complementary bit line / BL, to amplify the voltage difference between bit line BL and complementary bit line / BL. The sense amplifier 54 includes a sixth switching element M6, a seventh switching element M7, an eighth switching element M8, and a ninth switching element M9. The sixth switching element M6 and the seventh switching element M7 are both N-type transistors, while the eighth switching element M8 and the ninth switching element M9 are both P-type transistors. One end of the sixth switching element M6 is connected to bit line BL through a first node N1, and the other end is connected to a pull-down node NCS. The pull-down node NCS is connected to Vss, and the control terminal of the sixth switching element M6 is connected to the complementary bit line / BL. One end of the seventh switching element M7 is connected to the complementary bit line / BL through a second node N2, and the other end is connected to the pull-down node NCS. The control terminal of the seventh switching element M7 is connected to bit line BL. One end of the eighth switching element M8 is connected to the bit line BL through the first node N1, and the other end is connected to the pull-up node PCS. The pull-up node PCS is connected to Vary (i.e., the power supply voltage of the pull-up node). The control terminal of the eighth switching element M8 is connected to the complementary bit line / BL. One end of the ninth switching element M9 is connected to the complementary bit line / BL through the second node N2, and the other end is connected to the pull-up node PCS. The control terminal of the ninth switching element M9 is connected to the bit line BL.
[0142] By inputting a YS signal to the second switching element M2, the second switching element M2 can be turned on, allowing data to be transmitted from the bit line BL to the LIO signal line. Figures 6 to 8 As can be seen, by writing logic levels into the capacitor cell in storage cell 51, adjusting the voltage of bit lines BL and / BL during pre-charging, and the voltage of the lower plate of capacitor C, a worse reading environment can be created. Furthermore, if the reading result of the capacitor cell in storage cell 51 is not equal to the data previously written to it after the entire test device has been left to stand still for a period of time, it can be determined that the capacitor cell in storage cell 51 has failed.
[0143] Figure 9 This is a schematic diagram of the stability testing process for capacitors in DRAM provided in an embodiment of this disclosure, as shown below. Figure 9 As shown, the solution includes the following steps:
[0144] 1. First, adjust the voltage of the lower plate of the capacitor using DFT and configure the test environment to provide a more suitable environment for exposing memory problems. It is necessary to configure the voltage recovered by BL during the read logic level process. If the logic written is "0", BL can be recovered to a voltage less than 0.5V, for example: 0.42V~0.46V; if the logic written is "1", BL can be recovered to a voltage greater than 0.5V, for example: 0.55V~0.59V.
[0145] 2. Then, through the test circuit, that is... Figure 8 The diagram illustrates writing logic "0" or "1" into each capacitor in the entire memory. Specifically, the logic levels of the capacitors to be written into the memory can be shown in Table 1 or Table 2 below.
[0146] Table 1 shows the scenarios where a logic "1" is written to each capacitor in the entire memory.
[0147]
[0148] Table 2 shows the scenarios where logic "0" is written to each capacitor in the entire memory.
[0149]
[0150] 3. After writing a fixed logic "0" or "1" into each capacitor of the entire memory, let it rest for 2ms to 1024ms.
[0151] 4. Read the logic levels of each capacitor in the entire memory to obtain a set of logic levels written to all capacitors and the corresponding logic levels read out.
[0152] In this step, when reading the logic level of each capacitor arranged in array in the storage, if the voltage written previously was controlled by BL to make all the logic levels written in the capacitors "0", then during the pre-charging process of the sensing amplifier 54, the voltage of BL is restored to a voltage of less than 0.5V, such as 0.42V to 0.46V. This makes it difficult for the sensing amplifier 54 to correctly read the capacitors with failure problems during the sensing and amplification process of "0", and the problem is more easily exposed. Finally, the sensing amplifier 54 transmits the read logic level to the pin through LIO and outputs the specific logic level in the capacitor. If the voltage written to the capacitor was previously controlled by BL to ensure that all logic levels written to the capacitor were "1", then during the pre-charging process of the sensing amplifier 54, the voltage of BL needs to be restored to a voltage greater than 0.5V, such as 0.56V to 0.59V. This makes it difficult for the sensing amplifier 54 to correctly read the faulty capacitor during the sensing and amplification process, making it easier to expose the problem. Finally, the sensing amplifier 54 transmits the read logic level to the pin through LIO to output the specific logic level in the capacitor.
[0153] 5. Repeat steps 2 to 4 above multiple times, for example, N times (N>=20), to obtain N sets of logic levels written to the capacitors in the memory and the logic levels read out.
[0154] After obtaining the logic levels in the N sets of capacitors written to and read from the memory, these logic levels can be transmitted to a computer for analysis and processing to determine the stability of the DRAM capacitors, i.e., the stability of the capacitor dielectric. Furthermore, corresponding stability evaluation curves can be generated to visually display the quality control data of the memory product. Figure 10 A schematic diagram of a stability evaluation curve is provided for an example of this disclosure. Figure 11 Another stability evaluation curve diagram provided for this disclosure example. (See diagram below.) Figure 10 and Figure 11 As shown, with 20 test cycles, for normal memory products (curve 1), the number of capacitor failures (i.e., failed memory cells, or failed chips) stabilizes at a relatively low number after the first few cycles. However, for defective products with poor stability (curve 2), the number of capacitor failures (i.e., failed memory cells, or failed chips) increases with each test cycle, and the number of capacitor failures is relatively large. That is, for memory with good stability, the number of capacitor failures remains stable with a large number of repeated tests; for memory with poor stability, the capacitance decays with a large number of repeated tests, meaning the number of capacitor failures increases. This test can detect memory problems at an earlier stage.
[0155] In summary, the memory capacitor stability testing scheme provided in this disclosure offers a simple testing method that allows for rapid verification of the stability of the capacitor dielectric in the memory during the circuit testing phase. This advances the testing time for the capacitor dielectric, enabling early screening and the early detection of problems. Furthermore, the test scheme only requires a few hundred milliseconds per cycle, resulting in a short overall testing process and significant savings in time and testing costs. Simultaneously, the data analysis process is simple and intuitive, providing a clear view of the results and further improving testing efficiency.
[0156] Figure 12 This is a schematic diagram of the structure of a memory capacitance stability testing apparatus according to an embodiment of this disclosure. Figure 12 As shown, the memory capacitance stability testing apparatus 10 of this embodiment includes:
[0157] The read / write module 11 is used to write logic levels to all the capacitors of the memory to be tested, the memory including multiple capacitors arranged in an array;
[0158] The read / write module 11 is also used to read logic levels from all the capacitors of the memory;
[0159] Processing module 12 is used to repeat the above-described write-to-read steps to obtain multiple sets of logic levels written into the capacitors of the memory and logic levels read out.
[0160] Output module 13 is used to transmit the logic levels written into the capacitors of the memory and the logic levels read out to a computer device; wherein the logic levels written into the capacitors of the memory and the logic levels read out are used to determine the stability of the memory capacitors.
[0161] Optionally, in one possible implementation, the memory is left idle after the read / write module writes logic levels to all the capacitors of the memory under test and before reading logic levels from all the capacitors of the memory.
[0162] Optionally, the resting time of the memory can be any duration between 2ms and 1024ms.
[0163] Optionally, the processing module 12 is further configured to:
[0164] During the circuit testing phase, the voltage of the lower plate of each capacitor and the voltage of the bit line pairs of the memory during pre-charging are set in test mode using DFT.
[0165] Optionally, the processing module 12 is specifically used for:
[0166] In test mode, the voltage difference between the upper and lower plates of all capacitors in the memory is adjusted to be greater than a first preset voltage difference using DFT.
[0167] And / or,
[0168] In test mode, the voltage difference between the voltage read from one bit line and the pre-charge voltage of the other bit line in the bit line pair of the memory is adjusted to be less than a second preset voltage difference by using DFT.
[0169] Optionally, the first preset voltage difference is Vcc / 2, and the second preset voltage difference is (Ccell / (Ccell+Cbl))*(Vcc / 2);
[0170] Wherein, Ccell is the capacitance value on the capacitor, Cbl is the parasitic capacitance value on the bit line, and Vcc is the operating voltage value.
[0171] Optionally, in one possible implementation, the processing module 12 is specifically used for:
[0172] Write logic "0" into all capacitors of the memory;
[0173] The voltage of the lower plate of each capacitor is raised to 1V, and / or the voltage of the bit line pair during pre-charging is applied to be 0.42V to 0.46V.
[0174] Optionally, the processing module 12 is specifically used for:
[0175] Write logic "1" into all capacitors of the memory.
[0176] The voltage of the lower plate of each capacitor is pulled down to 0V, and / or the voltage of the bit line pair during pre-charging is applied to be 0.56V to 0.59V.
[0177] Optionally, the read / write module 11 is specifically used for:
[0178] Repeat the above write-to-read steps N times to obtain N sets of logic levels written to the capacitors of the memory and the logic levels read out, where N is a positive integer greater than or equal to 20.
[0179] The memory capacitance stability testing device provided in the foregoing embodiments is used to execute the various steps in the testing device in the foregoing method embodiments. Its implementation principle and technical effect are similar, and will not be repeated here.
[0180] Figure 13 This is a schematic diagram of a second embodiment of the memory capacitance stability testing apparatus provided in this disclosure. Figure 13 As shown, the memory capacitance stability testing apparatus 20 of this embodiment includes:
[0181] Receiver module 21 is used to receive multiple sets of logic levels written into the capacitors of the memory under test and logic levels read out from the test device.
[0182] Processing module 22 is used to determine the number of capacitor failures in the memory each time based on the logic levels written into the capacitors to be tested and the logic levels read out, and to obtain the number of capacitor failures in multiple sets.
[0183] The processing module 22 is also used to determine the stability of the memory capacitor based on the change in the number of failures of the multiple sets of capacitors.
[0184] Optionally, in one possible implementation, the processing module 22 is specifically used for:
[0185] For each group of capacitors written to the memory and the corresponding logic level read from the memory, if the logic level during writing and the logic level during reading are consistent, then the data in the capacitor is determined to be reliable.
[0186] If there is no consistency, the capacitor is determined to be faulty;
[0187] The number of capacitor failures for each group is obtained by determining the number of capacitor failures based on the logic level written into and read from each group of capacitors in the memory.
[0188] Optionally, the processing module 22 is specifically used for:
[0189] Based on the dynamic changes among the number of capacitor failures in the multiple groups, a stability evaluation curve for the memory capacitor is obtained. The stability evaluation curve is used to represent the relationship between the number of tests and the number of capacitor failures in each group corresponding to each test.
[0190] The stability of the memory capacitor is determined based on the stability evaluation curve.
[0191] The memory capacitance stability testing device provided in the foregoing embodiments is used to perform the various steps in the computer device in the foregoing method embodiments. Its implementation principle and technical effect are similar, and will not be repeated here.
[0192] Figure 14 This is a schematic diagram of the physical structure of the memory capacitance stability testing device provided in the embodiments of this disclosure, as shown below. Figure 14 As shown, the memory capacitance stability testing apparatus 100 includes:
[0193] The test circuit 111, the storage unit 112, at least one processor 113, and the transmission interface 114;
[0194] The storage unit 112 stores instructions that can be executed by the at least one processor 113. The execution of the instructions by the at least one processor 113 enables the test apparatus 100 to perform the method executed by the test apparatus portion of the memory capacitance stability test in the foregoing method embodiment.
[0195] Optionally, the storage unit 112 can be either standalone or integrated with the processor 113.
[0196] When the storage unit 112 is a device independent of the processor 113, the test apparatus also includes a bus that can connect the storage unit 112 and the processor 113.
[0197] Figure 15 This is a schematic diagram of the structure of a computer device entity provided in an embodiment of this disclosure, such as... Figure 15 As shown, the computer device 200 includes:
[0198] At least one processor 211, a storage unit 212 communicatively connected to the at least one processor, a display 213, and a transmission interface 214;
[0199] The storage unit 212 stores instructions that can be executed by the at least one processor 211. The execution of these instructions by the at least one processor 211 enables the computer device 200 to execute the technical solutions on the computer device side of the aforementioned method embodiments.
[0200] Optionally, in the computer device 200, the storage unit 212 can be either independent or integrated with the processor 211.
[0201] When the storage unit 212 is a device independent of the processor 211, the computer device 200 also includes a bus that can connect the storage unit 212 and the processor 211.
[0202] This disclosure also provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, enable the processor to perform the memory capacitance stability test method in any of the foregoing method embodiments.
[0203] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the memory capacitance stability testing method in any of the foregoing method embodiments.
[0204] This disclosure also provides a chip, including a processing module and a communication interface, wherein the processing module is capable of executing the technical solutions in any of the foregoing method embodiments.
[0205] Furthermore, the chip also includes a storage module for storing instructions, and a processing module for executing the instructions stored in the storage module. The execution of the instructions stored in the storage module causes the processing module to execute the technical solution in any of the aforementioned method embodiments.
[0206] It should be understood that the processor mentioned in the embodiments of this disclosure can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.
[0207] It should also be understood that the memory mentioned in the embodiments of this disclosure can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).
[0208] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0209] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated into the processor.
[0210] It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.
[0211] It should be understood that in the various embodiments of this disclosure, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.
[0212] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A method for testing the capacitance stability of a memory, characterized in that, include: During the circuit testing phase, the voltage of the lower plate of each capacitor and the voltage of the bit line pair of the memory during pre-charging are set in test mode using DFT. Specifically, this includes: adjusting the voltage difference between the upper and lower plates of all capacitors in the memory to be greater than a first preset voltage difference using DFT in test mode; and / or adjusting the voltage difference between the voltage read from one bit line and the pre-charging voltage of the other bit line in the memory bit line pair to be less than a second preset voltage difference using DFT in test mode. The first preset voltage difference is Vcc / 2, and the second preset voltage difference is (Ccell / (Ccell+Cbl)) * (Vcc / 2); where Ccell is the capacitance value of the capacitor, Cbl is the parasitic capacitance value of the bit line, and Vcc is the operating voltage value. Write logic levels into all the capacitors of the memory to be tested, the memory comprising multiple capacitors arranged in an array; Read the logic level from all the capacitors in the memory; Repeat the above write-to-read steps to obtain multiple sets of logic levels written into the capacitors of the memory and logic levels read out; The logic levels written into the capacitors of the memory and the logic levels read out are transmitted to a computer device; wherein the logic levels written into the capacitors of the memory and the logic levels read out are used to determine the stability of the memory capacitors.
2. The method according to claim 1, characterized in that, After writing logic levels to all capacitors of the memory under test and before reading logic levels from all capacitors of the memory, the method further includes: Leave the memory idle.
3. The method according to claim 2, characterized in that, The idle time of the memory is any duration between 2ms and 1024ms.
4. The method according to claim 1, characterized in that, The step of setting the voltage of each capacitor's lower plate and the voltage of the memory's bit line pairs during pre-charge via DFT in test mode includes: Write logic "0" into all capacitors of the memory; The voltage of the lower plate of each capacitor is raised to 1V, and / or the voltage of the bit line pair during pre-charging is applied to be 0.42V to 0.46V.
5. The method according to claim 1, characterized in that, The step of setting the voltage of each capacitor's lower plate and the voltage of the memory's bit line pairs during pre-charge via DFT in test mode includes: Write logic "1" into all capacitors of the memory; Pull the voltage of the lower plate of each capacitor down to 0V, and / or apply a voltage of 0.56V to 0.59V to the bit line pair during pre-charging.
6. The method according to any one of claims 1 to 3, characterized in that, The process of repeating the above-described write-to-read steps to obtain multiple sets of logic levels written into the capacitors of the memory and read out the logic levels includes: Repeat the above write-to-read steps N times to obtain N sets of logic levels written to the capacitors of the memory and the logic levels read out, where N is a positive integer greater than or equal to 20.
7. A method for testing the stability of memory capacitance, characterized in that, include: During the circuit testing phase, the voltage of the lower plate of each capacitor and the voltage of the bit line pair of the memory during pre-charging are set in test mode using DFT. Specifically, this includes: adjusting the voltage difference between the upper and lower plates of all capacitors in the memory to be greater than a first preset voltage difference using DFT in test mode; and / or adjusting the voltage difference between the voltage read from one bit line and the pre-charging voltage of the other bit line in the memory bit line pair to be less than a second preset voltage difference using DFT in test mode. The first preset voltage difference is Vcc / 2, and the second preset voltage difference is (Ccell / (Ccell+Cbl)) * (Vcc / 2); where Ccell is the capacitance value of the capacitor, Cbl is the parasitic capacitance value of the bit line, and Vcc is the operating voltage value. Write logic levels to all capacitors of the memory under test, the memory comprising multiple capacitors arranged in an array; read logic levels from all capacitors of the memory; Repeat the above write-to-read steps to obtain multiple sets of logic levels written into the capacitors of the memory and logic levels read out; Receive multiple sets of logic levels written into the capacitors of the memory under test and logic levels read out, transmitted by the test device; Based on the logic levels written into and read from the multiple sets of capacitors in the memory to be tested, the number of capacitor failures in the memory is determined each time, thus obtaining the number of capacitor failures in multiple sets. The stability of the memory capacitors is determined based on the changes in the number of failures of the multiple sets of capacitors.
8. The method according to claim 7, characterized in that, The step of determining the number of capacitor failures in the memory for each test based on the logic levels written to and read from the multiple sets of capacitors to be tested, and obtaining multiple sets of capacitor failure counts, includes: For each group of capacitors written to the memory and the corresponding logic level read from the memory, if the logic level during writing and the logic level during reading are consistent, then the data in the capacitor is determined to be reliable. If there is no consistency, the capacitor is determined to be faulty; The number of capacitor failures for each group is obtained by determining the number of capacitor failures based on the logic level written into and read from each group of capacitors in the memory.
9. The method according to claim 7 or 8, characterized in that, Determining the stability of the memory capacitor based on the changes in the number of capacitor failures in the multiple groups includes: Based on the dynamic changes among the number of capacitor failures in the multiple groups, a stability evaluation curve for the memory capacitor is obtained. The stability evaluation curve is used to represent the relationship between the number of tests and the number of capacitor failures in each group corresponding to each test. The stability of the memory capacitor is determined based on the stability evaluation curve.
10. A testing device for the capacitance stability of a memory, characterized in that, include: Test circuitry, storage unit, at least one processor, and transmission interface; The storage unit stores instructions executable by the at least one processor, which, when executed by the at least one processor, enable the testing device to perform the memory capacitance stability testing method according to any one of claims 1 to 6.
11. A computer device, characterized in that, include: At least one processor, a storage unit communicatively connected to the at least one processor, a display, and a transmission interface; The storage unit stores instructions executable by the at least one processor, which, when executed by the at least one processor, enable the computer device to perform the memory capacitance stability test method according to any one of claims 7 to 9.