Artificial intelligence chip, accelerator and operation method

Abstract

The present disclosure provides an artificial intelligence chip, an accelerator and an operation method, and relates to the technical field of artificial intelligence. The chip comprises: a first operation circuit configured to perform a first operation to output a first operation result; a second operation circuit connected in parallel with the first operation circuit and configured to perform a second operation identical to the first operation to output a second operation result; and a third operation circuit configured to, upon receiving the first operation result and the second operation result, perform a third operation different from the first operation on the first operation result and the second operation result, respectively, to output a third operation result, respectively.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of artificial intelligence, and in particular, to an artificial intelligence chip, an accelerator and an operation method. BACKGROUND

[0002] Artificial intelligence is a technology science for simulating, extending and expanding human intelligence. At present, the research on artificial intelligence involves robots, language recognition, image recognition and natural language processing.

[0003] An artificial neural network is a common algorithm of artificial intelligence. In the calculation of the artificial neural network, convolution operation, point multiplication and point addition operation and activation function operation are often used. SUMMARY

[0004] According to an aspect of an embodiment of the present disclosure, an artificial intelligence chip is provided, comprising: a first operation circuit configured to perform a first operation to output a first operation result; a second operation circuit connected in parallel with the first operation circuit and configured to perform a second operation identical to the first operation to output a second operation result; and a third operation circuit configured to, upon receiving the first operation result and the second operation result, perform a third operation different from the first operation on the first operation result and the second operation result, respectively, to output a third operation result.

[0005] In some embodiments, the artificial intelligence chip further comprises: a first data distributor comprising a first input end, a first output end and a second output end, the first input end being configured to receive the second operation result, the first output end being connected with the third operation circuit; a fourth operation circuit connected with the second output end and configured to, upon receiving the second operation result, perform a fourth operation on the second operation result to output a fourth operation result, the fourth operation being identical to the third operation; and the third operation circuit is further configured to, upon receiving only the first operation result, perform the third operation on the first operation result.

[0006] In some embodiments, the artificial intelligence chip further comprises: a second data distributor connected between the first operation circuit and the third operation circuit, comprising a second input end, a third output end and a fourth output end, the second input end is configured to receive the first operation result; a first processing circuit connected between the second data distributor and the third operation circuit, configured to receive the first operation result from the third output end and the second operation result from the first output end in one clock cycle, and output the first operation result and the second operation result to the third operation circuit in two clock cycles respectively; and a first data selector connected between the first processing circuit and the third operation circuit, comprising a third input end, a fourth input end and a fifth output end, the third input end is connected with the first processing circuit, the fourth input end is connected with the fourth output end, and the fifth output end is connected with the third operation circuit.

[0007] In some embodiments, the artificial intelligence chip further comprises: a third data distributor comprising a fifth input end, a sixth output end and a seventh output end, the fifth input end is configured to receive the third operation result; a second processing circuit configured to receive the third operation result from the seventh output end and the fourth operation result from the fourth operation circuit in one clock cycle, and output the third operation result and the fourth operation result in two clock cycles respectively, or output the third operation result and the fourth operation result synchronously in one clock cycle; and a second data selector comprising a sixth input end, a seventh input end and an eighth output end, the sixth input end is connected with the sixth output end, and the seventh input end is configured to receive the third operation result and the fourth operation result output by the second processing circuit.

[0008] In some embodiments, the artificial intelligence chip further comprises: a fourth data distributor comprising an eighth input end, a ninth output end and a tenth output end, the eighth input end is configured to receive the fourth operation result, and the tenth output end is connected with one end of the second processing circuit close to the third data distributor.

[0009] In some embodiments, the artificial intelligence chip further comprises: a fifth operation circuit connected between the third operation circuit and the fourth operation circuit, configured to perform a fifth operation on the third operation result to output a fifth operation result, the fifth operation being different from the first operation and different from the third operation; a third data selector connected between the fifth operation circuit and the fourth operation circuit, comprising a ninth input end, a tenth input end and an eleventh output end, the ninth input end being configured to receive the fifth operation result, the tenth input end being configured to receive the second operation result, and the eleventh output end being connected with the fourth operation circuit; a fifth data distributor connected between the third operation circuit and the fifth operation circuit, comprising an eleventh input end, a twelfth output end and a thirteenth output end, the eleventh input end being configured to receive the third operation result, and the thirteenth output end being connected with the fifth operation circuit; a fourth data selector comprising a twelfth input end, a thirteenth input end and a fourteenth output end, the twelfth input end being connected with the twelfth output end, and the thirteenth input end being configured to receive the fourth operation result; and the fourth operation circuit is further configured to perform the fourth operation on the fifth operation result to output the fourth operation result upon receiving the fifth operation result.

[0010] In some embodiments, the first operation is one of a first type operation and a second type operation, the fifth operation is the other of the first type operation and the second type operation, the third operation is an activation function operation, the first type operation is a convolution operation, and the second type operation comprises at least one of a dot multiplication operation and a dot addition operation.

[0011] In some embodiments, the first operation is the first type operation, and the fifth operation is the second type operation.

[0012] According to another aspect of the embodiments of the present disclosure, an artificial intelligence accelerator is provided, comprising the artificial intelligence chip of any one of the above embodiments.

[0013] According to another aspect of the embodiments of the present disclosure, an operation method of an artificial intelligence chip is provided, the artificial intelligence chip comprising a first operation circuit, a second operation circuit and a third operation circuit, the method comprising: the first operation circuit performing a first operation to output a first operation result; the second operation circuit performing a second operation identical to the first operation to output a second operation result, the second operation circuit being connected in parallel with the first operation circuit; and the third operation circuit performing a third operation different from the first operation on the first operation result and the second operation result respectively to output a third operation result respectively upon receiving the first operation result and the second operation result.

[0014] In some embodiments, the artificial intelligence chip further comprises a first data distributor and a fourth operation circuit, and the method further comprises: the first data distributor receiving the second operation result via a first input end and outputting the second operation result via a first output end or a second output end, the first output end being connected with the third operation circuit; the fourth operation circuit, upon receiving the second operation result, performing a fourth operation on the second operation result to output a fourth operation result, the fourth operation being the same as the third operation, the fourth operation circuit being connected with the second output end; and the third operation circuit, upon receiving only the first operation result, performing the third operation on the first operation result.

[0015] In some embodiments, the artificial intelligence chip further comprises a second data distributor, a first processing circuit and a first data selector, and the method further comprises, upon the third operation circuit receiving the first operation result and the second operation result: the second data distributor receiving the first operation result via a second input end and outputting the first operation result via a third output end, the second data distributor being connected between the first operation circuit and the third operation circuit; the first processing circuit receiving the first operation result from the third output end and the second operation result from the first output end within one clock cycle and outputting the first operation result and the second operation result respectively within two clock cycles, the first processing circuit being connected between the second data distributor and the third operation circuit; and the first data selector receiving the first operation result and the second operation result output by the first processing circuit via a third input end and outputting the first operation result and the second operation result to the third operation circuit via a fifth output end.

[0016] In some embodiments, the third operation circuit, upon receiving only the first operation result, the method further comprises: the second data distributor receiving the first operation result via a second input end and outputting the first operation result via a fourth output end. The first data selector receives the first operation result via a fourth input end and outputs the first operation result to the third operation circuit via the fifth output end.

[0017] In some embodiments, the artificial intelligence chip further comprises a third data distributor, a second processing circuit, and a second data selector, and the method further comprises: the third data distributor receiving the third operation result via a fifth input end and outputting the third operation result via a sixth output end or a seventh output end; the second processing circuit receiving the third operation result from the seventh output end and the fourth operation result from the fourth operation circuit in one clock cycle, and outputting the third operation result and the fourth operation result in two clock cycles respectively, or outputting the third operation result and the fourth operation result synchronously in one clock cycle; and the second data selector receiving the third operation result from the sixth output end via a sixth input end or receiving the third operation result and the fourth operation result output by the second processing circuit via a seventh input end, and outputting via an eighth output end of the second data selector.

[0018] In some embodiments, the artificial intelligence chip further comprises a fourth data distributor, and the method further comprises: the fourth data distributor receiving the fourth operation result via an eighth input end and outputting the fourth operation result via a ninth output end or a tenth output end, the tenth output end being connected to the second processing circuit near one end of the third data distributor.

[0019] In some embodiments, the artificial intelligence chip further comprises a fifth data distributor, a fifth operation circuit, a fourth data selector, and a third data selector, and the method further comprises: the fifth data distributor receiving the third operation result from the third operation circuit via an eleventh input end and outputting via a twelfth output end or the thirteenth output end; the fifth operation circuit performing a fifth operation on the third operation result from the thirteenth output end to output a fifth operation result, the fifth operation being different from the first operation and different from the third operation; the third data selector receiving the fifth operation result from the fifth operation circuit via a ninth input end or receiving the second operation result from the second output end via a tenth input end and outputting to the fourth operation circuit via an eleventh output end; the fourth operation circuit, upon receiving the fifth operation result, performing the fourth operation on the fifth operation result to output the fourth operation result; and the fourth data selector receiving the third operation result from the twelfth output end via a twelfth input end or receiving the fourth operation result from the fourth operation circuit via a thirteenth input end and outputting via a fourteenth output end.

[0020] In some embodiments, the first operation is one of a first type of operation and a second type of operation, the fifth operation is the other of the first type of operation and the second type of operation, the third operation is an activation function operation, the first type of operation is a convolution operation, and the second type of operation includes at least one of a dot product operation and a dot addition operation.

[0021] In some embodiments, the first operation is the first type of operation, and the fifth operation is the second type of operation.

[0022] In the embodiments of the present disclosure, the first operation circuit and the second operation circuit performing the same operation can share the third operation circuit performing another different operation, so that the computing requirement can be met and the power consumption can be reduced.

[0023] The technical solutions of the present disclosure will be further described in detail below with the aid of the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0025] Figure 1 is a structural schematic diagram of an artificial intelligence chip according to some embodiments of the present disclosure.

[0026] Figure 2 is a structural schematic diagram of an artificial intelligence chip according to some other embodiments of the present disclosure.

[0027] Figure 3 is a structural schematic diagram of an artificial intelligence chip according to some other embodiments of the present disclosure.

[0028] Figure 4 is a structural schematic diagram of an artificial intelligence chip according to some other embodiments of the present disclosure.

[0029] Figure 5 is a structural schematic diagram of an artificial intelligence chip according to some other embodiments of the present disclosure.

[0030] Figure 6 is a structural schematic diagram of an artificial intelligence chip according to some other embodiments of the present disclosure.

[0031] Figure 7 is a structural schematic diagram of an artificial intelligence chip according to some other embodiments of the present disclosure.

[0032] Figure 8is a flowchart of an operation method of an artificial intelligence chip according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present disclosure.

[0034] Unless otherwise specifically stated, the relative arrangement of parts and steps, numerical expressions, and numerical values set forth in the various examples are not limiting.

[0035] It should be understood that the sizes of the various portions shown in the drawings are not necessarily drawn to scale.

[0036] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail in order to avoid obscuring the present disclosure.

[0037] In all examples shown and discussed herein, any specific values should be interpreted as merely illustrative and not as a limitation. Thus, other examples of the example embodiments can have different values.

[0038] It should be noted that like numbers and letters refer to like items throughout the drawings, and once an item is defined in one drawing, that definition is applicable to all like items in the remaining drawings.

[0039] Figure 1 is a structural schematic diagram of an artificial intelligence chip according to some embodiments of the present disclosure.

[0040] As shown in Figure 1 The artificial intelligence chip 10 includes a first operation circuit 100, a second operation circuit 200, and a third operation circuit 300.

[0041] The first operation circuit 100 is configured to perform a first operation to output a first operation result. For example, the first operation is a convolution operation.

[0042] The second operation circuit 200 is connected in parallel with the first operation circuit 100 and is configured to perform a second operation identical to the first operation to output a second operation result. For example, the second operation is also a convolution operation.

[0043] The third operation circuit 300 is configured to, in a case where the first operation result and the second operation result are received, perform a third operation different from the first operation on the first operation result and the second operation result respectively to output a third operation result. For example, the third operation is an activation function operation.

[0044] In the above embodiments, the first operation circuit 100 and the second operation circuit 200 performing the same operation can share the third operation circuit 300 performing another different operation, so that the computing requirement can be met and the power consumption can be reduced.

[0045] In some embodiments, the first operation is one of a first type operation and a second type operation, and the third operation is an activation function operation. The first type operation is a convolution operation, and the second type operation includes at least one of a dot multiplication operation and a dot addition operation.

[0046] For example, the first operation is the first type operation, i.e., the convolution operation.

[0047] For a computing scenario requiring an activation function operation after a convolution operation, the above embodiments can use the first operation circuit 100 and the second operation circuit 200 to respectively perform the convolution operation, and use the third operation circuit 300 to perform the activation function operation. Since the convolution operation is usually a down-sampling calculation, using only one third operation circuit 300 to perform the activation function operation can meet the computing requirement and reduce the power consumption.

[0048] For example, the first operation is the second type operation, i.e., at least one of the dot multiplication operation and the dot addition operation.

[0049] Figure 2 is a structural schematic diagram of an artificial intelligence chip according to another embodiment of the disclosure. Only the differences between the embodiment shown in Figure 2 The embodiments are different from Figure 1 The same parts of the embodiments shown can be referred to the above description.

[0050] Figure 2 In the embodiment shown, in addition to the first operation circuit 100, the second operation circuit 200 and the third operation circuit 300, the artificial intelligence chip 10 further includes a first data distributor 400 and a fourth operation circuit 500.

[0051] The first data distributor 400 includes a first input end 410, a first output end 420 and a second output end 430. The first input end 410 is connected with the second operation circuit 200 and configured to receive the second operation result. The first output end 420 is connected with the third operation circuit 300, and the second output end 430 is connected with the fourth operation circuit 500.

[0052] The fourth operation circuit 500 is connected with the second output end 430, and is configured to perform a fourth operation on the second operation result to output a fourth operation result in a case where the second operation result is received, the fourth operation being the same as the third operation. For example, the fourth operation and the third operation are both activation function operations.

[0053] The third operation circuit 300 is further configured to perform the third operation on the first operation result in a case where only the first operation result is received.

[0054] For example, in a case where the second operation result received by the first input end 410 is output via the first output end 420, the third operation circuit 300 performs the third operation on the first operation result and the second operation result respectively; in a case where the second operation result received by the first input end 410 is output via the second output end 430, the third operation circuit 300 performs the third operation on the first operation result.

[0055] In the above embodiments, the first operation circuit and the second operation circuit can share the function of the third operation circuit to reduce power consumption, or can respectively use the functions of the third operation circuit and the fourth operation circuit to improve computing performance. In this way, the artificial intelligence chip can meet different computing requirements.

[0056] For example, for a computing scenario that only needs to perform convolution operation and activation function operation, different computing modes can be realized by controlling the first data distributor 400. In one computing mode, the first operation circuit 100 and the second operation circuit 200 can be used to respectively perform convolution operation, and then the third operation circuit 300 can be used to perform activation function operation; in another computing mode, the first operation circuit 100 and the second operation circuit 200 can be used to respectively perform convolution operation, and then the third operation circuit 300 and the fourth operation circuit 500 can be used to respectively perform activation function operation.

[0057] Figure 3 is a structural schematic diagram of an artificial intelligence chip according to still another embodiment of the present disclosure. Only the differences between the artificial intelligence chip 10 shown in Figure 3 The embodiments are not limited to Figure 2 The differences and similarities between the embodiments shown in the figures can be referred to the above description.

[0058] Figure 3 In the embodiment shown, in addition to the first operation circuit 100, the second operation circuit 200, the third operation circuit 300, the first data distributor 400 and the fourth operation circuit 500, the artificial intelligence chip 10 further includes a second data distributor 600, a first processing circuit 700 and a first data selector 800.

[0059] The second data distributor 600 is connected between the first operation circuit 100 and the third operation circuit 300, and includes a second input end 610, a third output end 620 and a fourth output end 630. The second input end 610 is configured to receive the first operation result from the first operation circuit 100. The third output end 620 is connected with the first processing circuit 700, and the fourth output end 630 is connected with the fourth input end 820 of the first data selector 800.

[0060] The first processing circuit 700 is connected between the second data distributor 600 and the third operation circuit 300. The first processing circuit 700 is configured to receive the first operation result from the third output end 620 and the second operation result from the first output end 420 in one clock cycle, and output the first operation result and the second operation result to the third operation circuit 300 via the first data selector 800 in two clock cycles respectively. For example, the first processing circuit 700 receives the first operation result and the second operation result in one clock cycle, and can output the first operation result in the first clock cycle of the two clock cycles and output the second operation result in the second clock cycle of the two clock cycles. The first processing circuit 700 is, for example, a data bit width conversion circuit.

[0061] The first data selector 800 is connected between the first processing circuit 700 and the third operation circuit 300, and includes a third input end 810, a fourth input end 820 and a fifth output end 830. The third input end 810 is connected with the first processing circuit 700, the fourth input end 820 is connected with the fourth output end 630, and the fifth output end 830 is connected with the third operation circuit 300.

[0062] In the above embodiment, the first processing circuit is provided to enable the third operation circuit to receive the first operation result and the second operation result in a certain order, which is beneficial to avoid data congestion and thus provides guarantee for the normal operation of the third operation circuit.

[0063] Figure 4 is a structural schematic diagram of an artificial intelligence chip according to some embodiments of the present disclosure. Only the differences between the embodiments shown in FIGS. 1 and 2 will be introduced below. Figure 4 Embodiments and Figure 2 The differences and similarities between the embodiments shown in FIGS. 1 and 2 can be referred to the above description.

[0064] Figure 4 In the embodiment shown in FIG. 2, in addition to including the first operation circuit 100, the second operation circuit 200, the third operation circuit 300, the fourth operation circuit 500 and the first data distributor 400, the artificial intelligence chip 10 further includes a third data distributor 900, a second processing circuit 1000 and a second data selector 1100.

[0065] The third data distributor 900 includes a fifth input end 910, a sixth output end 920 and a seventh output end 930. The fifth input end 910 is configured to receive the third operation result, the sixth output end 920 is connected with a sixth input end 1110 of the second data selector 1100, and the seventh output end 930 is connected with the second processing circuit 1000.

[0066] The second processing circuit 1000 is configured to receive the third operation result from the seventh output end 930 and the fourth operation result from the fourth operation circuit 500 in one clock cycle, and output the third operation result and the fourth operation result in two clock cycles respectively, or receive the third operation result from the seventh output end 930 and the fourth operation result from the fourth operation circuit 500 in one clock cycle, and output the third operation result and the fourth operation result synchronously in one clock cycle. For example, the second processing circuit 1000 receives the third operation result and the fourth operation result in one clock cycle, and can output the third operation result in the first clock cycle of the two clock cycles and output the fourth operation result in the second clock cycle of the two clock cycles. For another example, the second processing circuit 1000 receives the third operation result and the fourth operation result in one clock cycle, and can splice the third operation result and the fourth operation result together and then output the third operation result and the fourth operation result synchronously in one clock cycle. The second processing circuit 1000 is, for example, a bit width conversion circuit.

[0067] The second data selector 1100 includes a sixth input end 1110, a seventh input end 1120 and an eighth output end 1130. The sixth input end 1110 is connected with the sixth output end 920, and the seventh input end 1120 is configured to receive the third operation result and the fourth operation result output by the second processing circuit 1000.

[0068] In the above embodiments, by setting the second processing circuit, the third operation result and the fourth operation result can be sent in a certain order in some scenarios, which is beneficial to avoid data congestion and thus provides guarantee for the normal work of the artificial intelligence chip; in other scenarios, the third operation result and the fourth operation result can be output synchronously, thus maximizing the performance of the artificial intelligence chip.

[0069] Figure 5 is a structural schematic diagram of an artificial intelligence chip according to some embodiments of the present disclosure. Only the differences between the embodiments shown in FIGS. 1 and 2 will be introduced below. Figure 5 The embodiments are not limited to the above description. Figure 2 The differences and similarities between the embodiments shown in FIGS. 1 and 2 can be referred to the above description.

[0070] Figure 5In the illustrated embodiment, in addition to comprising the first operation circuit 100, the second operation circuit 200, the third operation circuit 300, the fourth operation circuit 500, the first data distributor 400, the third data distributor 900, the second processing circuit 1000, and the second data selector 1100, the artificial intelligence chip 10 further comprises a fourth data distributor 1200.

[0071] The fourth data distributor 1200 comprises an eighth input end 1210, a ninth output end 1220, and a tenth output end 1230. The eighth input end 1210 is configured to receive the fourth operation result from the fourth operation circuit 500, the ninth output end 1220 can directly output the fourth operation result, and the tenth output end 1230 is connected to one end of the second processing circuit 1000 close to the third data distributor 900.

[0072] In the above embodiment, the fourth data distributor can output the fourth operation result to the second processing circuit via the tenth output end, or directly output the fourth operation result via the ninth output end, further expanding the operation function of the artificial intelligence chip.

[0073] Figure 6 is a structural schematic diagram of an artificial intelligence chip according to some embodiments of the present disclosure. Only the differences between the above-described embodiment and the embodiment shown in the figure will be introduced below. Figure 6 The embodiment is different from the above-described embodiment in that Figure 2 The differences and similarities between the illustrated embodiment and the above-described embodiment can be referred to the above description.

[0074] Figure 6 In the illustrated embodiment, in addition to comprising the first operation circuit 100, the second operation circuit 200, the third operation circuit 300, the fourth operation circuit 500, and the first data distributor 400, the artificial intelligence chip 10 further comprises a fifth operation circuit 1300, a third data selector 1400, a fifth data distributor 1500, and a fourth data selector 1600.

[0075] The fifth operation circuit 1300 is connected between the third operation circuit 300 and the fourth operation circuit 500, and is configured to perform a fifth operation on the third operation result to output a fifth operation result. The fifth operation is different from the first operation and different from the third operation.

[0076] In some embodiments, the first operation is one of a first type of operation and a second type of operation, the fifth operation is the other of the first type of operation and the second type of operation, and the third operation is an activation function operation. Here, the first type of operation is a convolution operation, and the second type of operation comprises at least one of a dot multiplication operation and a dot addition operation. For example, the fifth operation comprises at least one of a dot multiplication operation and a dot addition operation; for another example, the fifth operation is a convolution operation.

[0077] The third data selector 1400 is connected between the fifth operation circuit 1300 and the fourth operation circuit 500, and includes a ninth input end 1410, a tenth input end 1420 and an eleventh output end 1430. The ninth input end 1410 is configured to receive the fifth operation result from the fifth operation circuit 1300, the tenth input end 1420 is configured to receive the second operation result, and the eleventh output end 1430 is connected with the fourth operation circuit 500.

[0078] The fifth data distributor 1500 is connected between the third operation circuit 300 and the fifth operation circuit 1300, and includes an eleventh input end 1510, a twelfth output end 1520 and a thirteenth output end 1530. The eleventh input end 1510 is configured to receive the third operation result, the twelfth output end 1520 is connected with the twelfth input end 1610 of the fourth data selector, and the thirteenth output end 1530 is connected with the fifth operation circuit 1300.

[0079] The fourth data selector 1600 includes a twelfth input end 1610, a thirteenth input end 1620 and a fourteenth output end 1630. The twelfth input end 1610 is connected with the twelfth output end 1520, the thirteenth input end 1620 is configured to receive the fourth operation result, and the fourteenth output end 1630 is configured to directly output the received operation result.

[0080] The fourth operation circuit 500 is further configured to, in a case where the fifth operation result is received, perform a fourth operation on the fifth operation result to output a fourth operation result.

[0081] In the above embodiment, by setting the fifth operation circuit, the third data selector, the fifth data distributor and the fourth data selector, the first operation circuit and the second operation circuit can share the third operation circuit to reduce power consumption; can also respectively use the functions of the third operation circuit and the fourth operation circuit to improve computing performance; and can also sequentially share the third operation circuit, the fifth operation circuit and the fourth operation circuit to meet more computing requirements.

[0082] Figure 7 is a structural schematic diagram of an artificial intelligence chip according to some embodiments of the present disclosure.

[0083] As Figure 7As shown, the artificial intelligence chip 10 includes a first operation circuit 100, a second operation circuit 200, a first data distributor 400, a second data distributor 600, a first processing circuit 700, a first data selector 800, a third operation circuit 300, a third data distributor 900, a second processing circuit 1000, a second data selector 1100, a fifth data distributor 1500, a fifth operation circuit 1300, a third data selector 1400, a fourth operation circuit 500, a fourth data distributor 1200, and a fourth data selector 1600.

[0084] The first operation circuit 100 is configured to perform a first operation to output a first operation result. For example, the first operation is a convolution operation.

[0085] The second operation circuit 200 is connected in parallel with the first operation circuit 100 and is configured to perform a second operation identical to the first operation to output a second operation result. For example, the first operation and the second operation are both convolution operations.

[0086] The first data distributor 400 includes a first input end 410, a first output end 420, and a second output end 430. The first input end 410 is configured to receive the second operation result, the first output end 420 is connected with the first processing circuit 700. The second output end 430 is connected with the third data selector 1400.

[0087] The second data distributor 600 is connected between the first operation circuit 100 and the third operation circuit 300 and includes a second input end 610, a third output end 620, and a fourth output end 630. The second input end 610 is configured to receive the first operation result. The third output end 620 is connected with the first processing circuit 700, and the fourth output end 630 is connected with the first data selector 800.

[0088] The first processing circuit 700 is connected between the second data distributor 600 and the third operation circuit 300 and is configured to receive the first operation result from the third output end 620 and the second operation result from the first output end 420 in one clock cycle and output the first operation result and the second operation result respectively in two clock cycles.

[0089] The first data selector 800 is connected between the first processing circuit 700 and the third operation circuit 300 and includes a third input end 810, a fourth input end 820, and a fifth output end 830. The third input end 810 is connected with the first processing circuit 700, the fourth input end 820 is connected with the fourth output end 630, and the fifth output end 830 is connected with the third operation circuit 300.

[0090] The third operation circuit 300 is configured to, in a case where the first operation result and the second operation result are received, perform a third operation different from the first operation on the first operation result and the second operation result respectively to output a third operation result respectively. The third operation circuit 300 is further configured to, in a case where only the first operation result is received, perform the third operation on the first operation result. The third operation is, for example, an activation function operation.

[0091] The third data distributor 900 includes a fifth input end 910, a sixth output end 920 and a seventh output end 930. The fifth input end 910 is configured to receive the third operation result.

[0092] The second processing circuit 1000 is configured to, in one clock cycle, receive the third operation result from the seventh output end 930 and the fourth operation result from the fourth operation circuit 500, and output the third operation result and the fourth operation result respectively in two clock cycles, or, in one clock cycle, receive the third operation result from the seventh output end 930 and the fourth operation result from the fourth operation circuit 500, and output the third operation result and the fourth operation result synchronously in one clock cycle.

[0093] The second data selector 1100 includes a sixth input end 1110, a seventh input end 1120 and an eighth output end 1130. The sixth input end 1110 is connected with the sixth output end 920, and the seventh input end 1120 is configured to receive the third operation result and the fourth operation result output by the second processing circuit 1000. The eighth output end 1130 is connected with an eleventh input end 1510 of the fifth data distributor 1500.

[0094] The fifth data distributor 1500 is connected between the third operation circuit 300 and a fifth operation circuit 1300, and includes the eleventh input end 1510, a twelfth output end 1520 and a thirteenth output end 1530. The eleventh input end 1510 is configured to receive the third operation result, the twelfth output end 1520 is connected with a fourth data selector 1600, and the thirteenth output end 1530 is connected with the fifth operation circuit 1300.

[0095] The fifth operation circuit 1300 is connected between the third operation circuit 300 and the fourth operation circuit 500, and is configured to perform a fifth operation on the third operation result to output a fifth operation result. The fifth operation is different from the first operation and different from the third operation. For example, the first operation is a convolution operation, the third operation is an activation function operation, and the fifth operation includes at least one of a point multiplication and a point addition operation.

[0096] The third data selector 1400 is connected between the fifth operation circuit 1300 and the fourth operation circuit 500, and includes a ninth input end 1410, a tenth input end 1420 and an eleventh output end 1430. The ninth input end 1410 is configured to receive the fifth operation result. The tenth input end 1420 is configured to receive the second operation result. The eleventh output end 1430 is connected with the fourth operation circuit 500.

[0097] The fourth operation circuit 500 is connected with the eleventh output end 1510, and is configured to perform a fourth operation on the second operation result to output a fourth operation result in a case where the second operation result is received. The fourth operation is the same as the third operation. The fourth operation circuit 500 is further configured to perform the fourth operation on the fifth operation result to output the fourth operation result in a case where the fifth operation result is received. For example, the fourth operation is an activation function operation.

[0098] The fourth data distributor 1200 includes an eighth input end 1210, a ninth output end 1220 and a tenth output end 1230. The eighth input end 1210 is configured to receive the fourth operation result. The tenth output end 1230 is connected with the second processing circuit 1000 at one end close to the third data distributor 900. The ninth output end 1220 is connected with the fourth data selector 1600.

[0099] The fourth data selector 1600 includes a twelfth input end 1610, a thirteenth input end 1620 and a fourteenth output end 1630. The twelfth input end 1610 is connected with the twelfth output end 1520. The thirteenth input end 1620 is connected with the ninth output end 1220 and is configured to receive the fourth operation result. The fourteenth output end 1630 is configured to directly output the received operation result.

[0100] It can be understood that the first data distributor 400, the second data distributor 600, the third data distributor 900, the fourth data distributor 1200, the fifth data distributor 1500, the first data selector 800, the second data selector 1100, the third data selector 1400, the fourth data selector 1600, the first processing circuit 700 and the second processing circuit 1000 can be controlled by a control signal, so as to select a working mode of a corresponding channel or processing circuit to realize multiple functions.

[0101] For example, a first controller (not shown in the figure) can be configured to control the first data distributor 400, the second data distributor 600, the third data distributor 900, the fourth data distributor 1200, the first data selector 800, the second data selector 1100, the third data selector 1400, the first processing circuit 700, and the second processing circuit 1000, and a second controller (not shown in the figure) can be configured to control the fifth data distributor 1500 and the fourth data selector 1600.

[0102] For another example, each data distributor, data selector, and processing circuit can be controlled by a separate controller.

[0103] Some examples of the working scenarios of the artificial intelligence chip 10 are described below. Figure 7 The working scenarios of the artificial intelligence chip 10 are described below.

[0104] First, a first working scenario is described.

[0105] The first operation circuit 100 performs a convolution operation and outputs a first operation result to the second input end 610 of the second data distributor 600. The second data distributor 600 outputs the first operation result from the third output end 620 to the first processing circuit 700.

[0106] The second operation circuit 200 also performs a convolution operation and outputs a second operation result to the first data distributor 400. The first data distributor 400 outputs the second operation result from the first output end 420 to the first processing circuit 700.

[0107] The first processing circuit 700 receives the first operation result and the second operation result in one clock cycle and outputs the first operation result and the second operation result to the third operation circuit 300 in two clock cycles, respectively.

[0108] The first data selector 800 receives the first operation result and the second operation result from the third input end 810 and outputs the first operation result and the second operation result from the fifth output end 830 to the third operation circuit 300, respectively.

[0109] The third operation circuit 300 performs an activation function operation on the first operation result and the second operation result, respectively, to output a third operation result, respectively. The third data distributor 900 outputs the third operation result from the sixth output end 920.

[0110] The second data selector 1100 receives the third operation result from the sixth input end 1110 and outputs to the eleventh input end 1510 of the fifth data distributor 1500. The fifth data distributor 1500 outputs the third operation result from the twelfth output end 1520 to the twelfth input end 1610 of the fourth data selector 1600. The fourth data selector 1600 directly outputs the third operation result from the fourteenth output end 1630.

[0111] In the above working scenario, the first operation circuit and the second operation circuit performing convolution operation share one third operation circuit performing activation function operation, saving the use of operation circuit for activation function operation and reducing the power consumption required for calculation.

[0112] Next, the second working scenario is introduced.

[0113] The first operation circuit 100 performs convolution operation and outputs the first operation result to the second data distributor 600. The second data distributor 600 outputs the first operation result from the fourth output end 630 to the fourth input end 820 of the first data selector 800. The first data selector 800 outputs the first operation result from the fifth output end 830 to the third operation circuit 300, and the third operation circuit 300 performs activation function operation on the first operation result to output the third operation result to the fifth input end 910 of the third data distributor 900. The third data distributor 900 outputs the third operation result from the seventh output end 930 to the second processing circuit 1000. The second operation circuit 200 performs convolution operation and outputs the second operation result to the first input end 410 of the first data distributor 400. The first data distributor 400 outputs the second operation result from the second output end 430 to the tenth input end 1420 of the third data selector 1400. The third data selector 1400 outputs the second operation result from the eleventh output end 1430 to the fourth operation circuit 500.

[0114] The fourth operation circuit 500 performs activation function operation on the second operation result to output the fourth operation result to the eighth input end 1210 of the fourth data distributor 1200.

[0115] The fourth data distributor outputs the fourth operation result from the tenth output end 1230 to the second processing circuit 1000.

[0116] The second processing circuit 1000 receives the third operation result and the fourth operation result in one clock cycle and synchronously outputs the third operation result and the fourth operation result to the seventh input end 1120 of the second data selector 1100 in one clock cycle.

[0117] The second data selector 1100 outputs the first operation result and the fourth operation result to an eleventh input end 1510 of a fifth data distributor 1500. The fifth data distributor 1500 outputs the first operation result and the fourth operation result from a twelfth output end 1520 to a twelfth input end 1610 of a fourth data selector 1600. The fourth data selector 1600 directly outputs the third operation result and the fourth operation result from a fourteenth output end 1630.

[0118] In the above working scenario, the first operation circuit and the second operation circuit performing convolution operation respectively use two third operation circuits and fourth operation circuits performing activation function operation, and the two groups of convolution-activation function operation are performed in parallel, which is beneficial to improve the calculation speed.

[0119] Finally, the third working scenario is introduced.

[0120] The first operation circuit 100 performs convolution operation and outputs a first operation result to a second input end 610 of a second data distributor 600. The second data distributor 600 outputs the first operation result from a third output end 620 to the first processing circuit 700.

[0121] The second operation circuit 200 also performs convolution operation and outputs a second operation result to the first data distributor 400. The first data distributor 400 outputs the second operation result from a first output end 420 to the first processing circuit 700.

[0122] The first processing circuit 700 receives the first operation result and the second operation result in one clock cycle and outputs the first operation result and the second operation result to the third operation circuit 300 in two clock cycles respectively.

[0123] The first data selector 800 receives the first operation result and the second operation result from a third input end 810 and outputs the first operation result and the second operation result from a fifth output end 830 to the third operation circuit 300 respectively.

[0124] The third operation circuit 300 performs activation function operation on the first operation result and the second operation result respectively to output a third operation result respectively. The third data distributor 900 outputs the third operation result from a sixth output end 920.

[0125] The second data selector 1100 receives the third operation result from the sixth input end 1110 and outputs to the eleventh input end 1510 of the fifth data distributor 1500. The fifth data distributor 1500 outputs the third operation result from the thirteenth output end 1530 to the fifth operation circuit 1300. The fifth operation circuit 1300 performs at least one of point multiplication and point addition operation on the third operation result to output a fifth operation result to the ninth input end 1410 of the third data selector 1400.

[0126] The third data selector 1400 outputs the fifth operation result from the eleventh output end 1430 to the fourth operation circuit 500. The fourth operation circuit 500 performs an activation function operation on the fifth operation result to output a fourth operation result to the eighth input end 1210 of the fourth data distributor 1200. The fourth data distributor 1200 outputs the fourth operation result from the ninth output end 1220 to the thirteenth input end 1620 of the fourth data selector 1600. The fourth data selector 1600 directly outputs the fourth operation result from the fourteenth output end 1630.

[0127] In the above working scenario, the first operation circuit and the second operation circuit performing convolution operation share the third operation circuit performing activation function operation, the fifth operation circuit performing at least one of point multiplication and point addition, and the fourth operation circuit performing activation function operation, which is beneficial to meet specific computing requirements.

[0128] In the above embodiment, the controller is used to control the data selector and the data distributor, and three different working scenarios can be realized by using less hardware. Some working scenarios can save power consumption, some working scenarios can improve performance, and some working scenarios can meet specific computing requirements. In addition, the switching between the three functions is simple and convenient, and easy to operate.

[0129] The disclosure embodiments also provide an artificial intelligence accelerator, which can include the artificial intelligence chip described in any one of the above embodiments, such as the artificial intelligence chip 10.

[0130] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. For method embodiments, since they basically correspond to chip embodiments, the description is relatively simple, and the relevant parts are described in the chip embodiment.

[0131] Figure 8 is a flow diagram of an operation method of an artificial intelligence chip according to some embodiments of the disclosure.

[0132] The artificial intelligence chip 10 can include a first operation circuit 100, a second operation circuit 200, and a third operation circuit 300.

[0133] As shown in FIG. 8, at step S802, the first operation circuit 100 performs a first operation to output a first operation result. Figure 8

[0134] At step S804, the second operation circuit 200 performs a second operation identical to the first operation to output a second operation result. Further, the second operation circuit 200 is connected in parallel with the first operation circuit 100.

[0135] At step S806, the third operation circuit 300, upon receiving the first operation result and the second operation result, performs a third operation different from the first operation on the first operation result and the second operation result, respectively, to output a third operation result.

[0136] In the above embodiment, the first operation circuit 100 and the second operation circuit 200 share the third operation circuit 300, so that the computing requirement can be met and the power consumption can be reduced.

[0137] In some embodiments, the artificial intelligence chip 10 further includes a first data distributor 400 and a fourth operation circuit 500 in addition to the first operation circuit 100, the second operation circuit 200, and the third operation circuit 300.

[0138] The first data distributor 400 includes a first input end 410, a first output end 420, and a second output end 430. The first data distributor 400 receives the second operation result via the first input end 410 and outputs the second operation result via the first output end 420 or the second output end 430. Here, the first output end 420 is connected to the third operation circuit 300. The second output end 430 is connected to the fourth operation circuit 500.

[0139] The fourth operation circuit 500, upon receiving the second operation result, performs a fourth operation on the second operation result to output a fourth operation result. Here, the fourth operation is identical to the third operation, for example, both the fourth operation and the third operation are activation function operations.

[0140] The third operation circuit 300, upon receiving only the first operation result, performs the third operation on the first operation result.

[0141] ​For example, when the second operation result received by the first input terminal 410 is output via the first output terminal 420, the third operation circuit 300 performs the third operation on the first operation result and the second operation result respectively; when the second operation result received by the first input terminal 410 is output via the second output terminal 430, the third operation circuit 300 performs the third operation on the first operation result, and the fourth operation circuit 500 performs the fourth operation on the second operation result.

[0142] In the above embodiment, the first operation circuit and the second operation circuit can share the function of the third operation circuit to reduce power consumption, or can respectively use the functions of the third operation circuit and the fourth operation circuit to improve computing performance. In this way, the operation method of the artificial intelligence chip 10 can meet different computing requirements.

[0143] In some embodiments, the artificial intelligence chip 10 further includes a second data distributor 600, a first processing circuit 700 and a first data selector 800 in addition to the first operation circuit 100, the second operation circuit 200, the third operation circuit 300, the first data distributor 400 and the fourth operation circuit 500.

[0144] The second data distributor 600 includes a second input terminal 610, a third output terminal 620 and a fourth output terminal 630. The second data distributor 600 receives the first operation result via the second input terminal 610 and outputs the first operation result via the third output terminal 620. Here, the second data distributor 600 is connected between the first operation circuit 100 and the third operation circuit 300.

[0145] The first processing circuit 700 receives the first operation result from the third output terminal 620 and the second operation result from the first output terminal 420 in one clock cycle, and outputs the first operation result and the second operation result respectively in two clock cycles. Here, the first processing circuit 700 is connected between the second data distributor 600 and the third operation circuit 300. The first processing circuit 700 is, for example, a bit width conversion circuit.

[0146] For example, the first processing circuit 700 receives the first operation result and the second operation result in one clock cycle, and can output the first operation result in the first clock cycle of two clock cycles and output the second operation result in the second clock cycle of two clock cycles.

[0147] The first data selector 800 includes a third input terminal 810, a fourth output terminal 630 and a fifth output terminal 830. The first data selector 800 receives the first operation result and the second operation result output by the first processing circuit 700 via the third input terminal 810, and outputs the first operation result and the second operation result to the third operation circuit 300 via the fifth output terminal 830.

[0148] In the above embodiment, the first processing circuit 700 is configured to enable the third operation circuit 300 to receive the first operation result and the second operation result in a certain order, so as to avoid data congestion and provide guarantee for normal operation of the third operation circuit 300.

[0149] In some embodiments, the third operation circuit 300 receives the first operation result via the second input end 610 and outputs the first operation result via the fourth output end 630 in the case that only the first operation result is received. The first data selector 800 receives the first operation result via the fourth input end 820 and outputs the first operation result to the third operation circuit 300 via the fifth output end 830.

[0150] In some embodiments, in addition to the first operation circuit 100, the second operation circuit 200, the third operation circuit 300, the fourth operation circuit 500 and the first data distributor 400, the artificial intelligence chip 10 further comprises a third data distributor 900, a second processing circuit 1000 and a second data selector 1100.

[0151] The third data distributor 900 comprises a fifth input end 910, a sixth output end 920 and a seventh output end 930. The third data distributor 900 receives the third operation result via the fifth input end 910 and outputs the third operation result via the sixth output end 920 or the seventh output end 930. Here, the sixth output end 920 is connected with the sixth input end 1110 of the second data selector 1100, and the seventh output end 930 is connected with the second processing circuit 1000.

[0152] The second processing circuit 1000 receives the third operation result from the seventh output end 930 and the fourth operation result from the fourth operation circuit 500 in one clock cycle, and outputs the third operation result and the fourth operation result in two clock cycles respectively, or receives the third operation result from the seventh output end 930 and the fourth operation result from the fourth operation circuit 500 in one clock cycle and outputs the third operation result and the fourth operation result synchronously in one clock cycle. For example, the second processing circuit 1000 receives the third operation result and the fourth operation result in one clock cycle, and outputs the third operation result in the first clock cycle of two clock cycles and outputs the fourth operation result in the second clock cycle of two clock cycles. For another example, the second processing circuit 1000 receives the third operation result and the fourth operation result in one clock cycle, and outputs the third operation result and the fourth operation result synchronously in one clock cycle after splicing and summarizing. The second processing circuit 1000 is, for example, a bit width conversion circuit.

[0153] The second data selector 1100 comprises a sixth input end 1110, a seventh input end 1120 and an eighth output end 1130. The second data selector 1100 receives the third operation result from the sixth output end 920 via the sixth input end 1110 or receives the third operation result and the fourth operation result output by the second processing circuit 1000 via the seventh input end 1120, and outputs via the eighth output end 1130 of the second data selector 1100.

[0154] In the above embodiment, by arranging the second processing circuit 1000, in some scenarios, the third operation result and the fourth operation result can be sent in a certain order, thereby avoiding data congestion; in other scenarios, the third operation circuit and the fourth operation circuit can be output synchronously, thereby maximizing the performance of the artificial intelligence chip.

[0155] In some embodiments, in addition to comprising the first operation circuit 100, the second operation circuit 200, the third operation circuit 300, the fourth operation circuit 500, the first data distributor 400, the third data distributor 900, the second processing circuit 1000 and the second data selector 1100, the artificial intelligence chip 10 further comprises a fourth data distributor 1200.

[0156] The fourth data distributor 1200 comprises an eighth input end 1210, a ninth output end 1220 and a tenth output end 1230. The fourth data distributor 1200 receives the fourth operation result via the eighth input end 1210 and outputs the fourth operation result via the ninth output end 1220 or the tenth output end 1230, the ninth output end 1220 can directly output the fourth operation result, and the tenth output end 1230 is connected to one end of the second processing circuit 1000 close to the third data distributor 900.

[0157] In the above embodiment, the fourth operation result can be output to the second processing circuit 1000 via the tenth output end 1230, or the fourth operation result can be directly output via the ninth output end 1220, thereby further expanding the operation function of the artificial intelligence chip 10.

[0158] In some embodiments, in addition to comprising the first operation circuit 100, the second operation circuit 200, the third operation circuit 300, the fourth operation circuit 500 and the first data distributor 400, the artificial intelligence chip 10 further comprises a fifth data distributor 1500, a fifth operation circuit 1300, a fourth data selector 1600 and a third data selector 1400.

[0159] The fifth data distributor 1500 includes an eleventh input end 1510, a twelfth output end 1520, and a thirteenth output end 1530. The fifth data distributor 1500 receives the third operation result from the third operation circuit 300 via the eleventh input end 1510, and outputs via the twelfth output end 1520 or the thirteenth output end 1530.

[0160] The fifth operation circuit 1300 performs a fifth operation on the third operation result from the thirteenth output end 1530 to output a fifth operation result, the fifth operation being different from the first operation and different from the third operation. In some embodiments, the first operation is one of a first type of operation and a second type of operation, the fifth operation is the other of the first type of operation and the second type of operation, and the third operation is an activation function operation. Here, the first type of operation is a convolution operation, and the second type of operation includes at least one of a dot multiplication operation and a dot addition operation. For example, the fifth operation is at least one of a dot multiplication operation and a dot addition operation.

[0161] The third data selector 1400 includes a ninth input end 1410, a tenth input end 1420, and an eleventh output end 1430. The third data selector 1400 receives the fifth operation result from the fifth operation circuit 1300 via the ninth input end 1410 or receives the second operation result from the second output end 430 via the tenth input end 1420, and outputs via the eleventh output end 1430 to the fourth operation circuit 500.

[0162] The fourth operation circuit 500 is further configured to, in a case where the fifth operation result is received, perform a fourth operation on the fifth operation result to output a fourth operation result.

[0163] The fourth data selector 1600 receives the third operation result from the twelfth output end 1520 via a twelfth input end 1610 or receives the fourth operation result from the fourth operation circuit 500 via a thirteenth input end 1620, and outputs via a fourteenth output end 1630.

[0164] In the above embodiments, the first operation circuit and the second operation circuit can share the third operation circuit to reduce power consumption; can also each use the functions of the third operation circuit and the fourth operation circuit respectively to improve computing performance; and can also share the third operation circuit, the fifth operation circuit, and the fourth operation circuit to meet more computing requirements.

[0165] So far, the embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein according to the above description.

[0166] Although some specific embodiments of the present disclosure have been described in detail by way of example with reference to the drawings, it is to be understood that the above examples are intended to be illustrative only and are not intended to limit the scope of the present disclosure. It is to be understood that modifications or equivalent arrangements of the above embodiments can be made by those skilled in the art without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An artificial intelligence chip, comprising: The first arithmetic circuit (100) is configured to perform a first arithmetic operation to output a first arithmetic result; The second arithmetic circuit (200), connected in parallel with the first arithmetic circuit (100), is configured to perform the same second arithmetic operation as the first arithmetic operation to output the second arithmetic result; The third arithmetic circuit (300) is configured to, upon receiving the first arithmetic result and the second arithmetic result, perform a third arithmetic operation on the first arithmetic result and the second arithmetic result respectively, so as to output the third arithmetic result respectively, and to perform the third arithmetic operation on the first arithmetic result when only the first arithmetic result is received; The first data distributor (400) includes: a first input terminal (410), a first output terminal (420), and a second output terminal (430). The first input terminal (410) is configured to receive the second operation result, and the first output terminal (420) is connected to the third operation circuit (300). as well as The fourth operation circuit (500), connected to the second output terminal (430), is configured to perform a fourth operation on the second operation result to output a fourth operation result upon receiving the second operation result, the fourth operation being the same as the third operation.

2. The artificial intelligence chip according to claim 1 further includes: The second data distributor (600) is connected between the first arithmetic circuit (100) and the third arithmetic circuit (300), and includes a second input terminal (610), a third output terminal (620) and a fourth output terminal (630). The second input terminal (610) is configured to receive the first arithmetic result. A first processing circuit (700), connected between the second data distributor (600) and the third arithmetic circuit (300), is configured to receive the first arithmetic result from the third output terminal (620) and the second arithmetic result from the first output terminal (420) within one clock cycle, and to output the first arithmetic result and the second arithmetic result to the third arithmetic circuit (300) respectively within two clock cycles; and A first data selector (800) is connected between the first processing circuit (700) and the third arithmetic circuit (300), and includes a third input terminal (810), a fourth input terminal (820) and a fifth output terminal (830). The third input terminal (810) is connected to the first processing circuit (700), the fourth input terminal (820) is connected to the fourth output terminal (830), and the fifth output terminal (830) is connected to the third arithmetic circuit (300).

3. The artificial intelligence chip according to claim 1 further includes: The third data distributor (900) includes: a fifth input terminal (910), a sixth output terminal (920) and a seventh output terminal (930), wherein the fifth input terminal (910) is configured to receive the third operation result; The second processing circuit (1000) is configured to receive the third operation result from the seventh output terminal (930) and the fourth operation result from the fourth operation circuit (500) within one clock cycle, and to output the third operation result and the fourth operation result separately within two clock cycles, or to output the third operation result and the fourth operation result synchronously within one clock cycle; and The second data selector (1100) includes a sixth input terminal (1110), a seventh input terminal (1120) and an eighth output terminal (1130). The sixth input terminal (1110) is connected to the sixth output terminal (920). The seventh input terminal (1120) is configured to receive the third operation result and the fourth operation result output by the second processing circuit (1000).

4. The artificial intelligence chip according to claim 3 further includes: The fourth data distributor (1200) includes an eighth input terminal (1210), a ninth output terminal (1220) and a tenth output terminal (1230). The eighth input terminal (1210) is configured to receive the fourth operation result, and the tenth output terminal (1230) is connected to the end of the second processing circuit (1000) near the third data distributor (900).

5. The artificial intelligence chip according to any one of claims 1-4, further comprising: A fifth arithmetic circuit (1300), connected between the third arithmetic circuit (300) and the fourth arithmetic circuit (500), is configured to perform a fifth arithmetic operation on the result of the third arithmetic operation to output a fifth arithmetic operation result, wherein the fifth arithmetic operation is different from the first arithmetic operation and is also different from the third arithmetic operation; A third data selector (1400) is connected between the fifth arithmetic circuit (1300) and the fourth arithmetic circuit (500), and includes a ninth input terminal (1410), a tenth input terminal (1420) and an eleventh output terminal (1430). The ninth input terminal (1410) is configured to receive the result of the fifth arithmetic operation, the tenth input terminal (1420) is configured to receive the result of the second arithmetic operation, and the eleventh output terminal (1430) is connected to the fourth arithmetic circuit (500). A fifth data distributor (1500) is connected between the third arithmetic circuit (300) and the fifth arithmetic circuit (1300), and includes an eleventh input terminal (1510), a twelfth output terminal (1520) and a thirteenth output terminal (1530). The eleventh input terminal (1510) is configured to receive the result of the third arithmetic operation, and the thirteenth output terminal (1530) is connected to the fifth arithmetic circuit (1300). The fourth data selector (1600) includes a twelfth input (1610), a thirteenth input (1620) and a fourteenth output (1630), wherein the twelfth input (1610) is connected to the twelfth output (1620), and the thirteenth input (1620) is configured to receive the fourth operation result; as well as The fourth arithmetic circuit (500) is further configured to perform the fourth arithmetic operation on the fifth arithmetic result to output the fourth arithmetic result upon receiving the fifth arithmetic result.

6. The artificial intelligence chip according to claim 5, wherein, The first operation is one of the first type of operation and the second type of operation, the fifth operation is another of the first type of operation and the second type of operation, the third operation is an activation function operation, the first type of operation is a convolution operation, and the second type of operation includes at least one of dot multiplication and dot addition.

7. The artificial intelligence chip according to claim 6, wherein, The first operation is a first type of operation, and the fifth operation is a second type of operation.

8. An artificial intelligence accelerator, comprising: The artificial intelligence chip according to any one of claims 1-7.

9. A computational method for an artificial intelligence chip, the artificial intelligence chip comprising a first computational circuit (100), a second computational circuit (200), a third computational circuit (300), a first data distributor (400), and a fourth computational circuit (500), the method comprising: The first arithmetic circuit (100) performs a first operation to output a first operation result; The second arithmetic circuit (200) performs the same second operation as the first operation to output the second operation result. The second arithmetic circuit (200) is connected in parallel with the first arithmetic circuit (100). as well as The first data distributor (400) receives the second calculation result via the first input terminal (410) and outputs the second calculation result via the first output terminal (420) or the second output terminal (430). The first output terminal (420) is connected to the third calculation circuit (300). The third arithmetic circuit (300), upon receiving both the first and second arithmetic results, performs a third arithmetic operation different from the first arithmetic operation on both the first and second arithmetic results to output a third arithmetic result respectively; and, upon receiving only the first arithmetic result, performs the third arithmetic operation on the first arithmetic result; and Upon receiving the second operation result, the fourth operation circuit (500) performs a fourth operation on the second operation result to output a fourth operation result. The fourth operation is the same as the third operation. The fourth operation circuit (500) is connected to the second output terminal (430).

10. The computation method according to claim 9, wherein the artificial intelligence chip further comprises a second data distributor (600), a first processing circuit (700), and a first data selector (800), wherein, Upon receiving the first calculation result and the second calculation result, the method further includes: The second data distributor (600) receives the first calculation result via the second input terminal (610) and outputs the first calculation result via the third output terminal (620). The second data distributor (600) is connected between the first calculation circuit (100) and the third calculation circuit (300). The first processing circuit (700) receives the first operation result from the third output terminal (620) and the second operation result from the first output terminal (420) within one clock cycle, and outputs the first operation result and the second operation result respectively within two clock cycles. The first processing circuit (700) is connected between the second data distributor (600) and the third operation circuit (300); and The first data selector (800) receives the first calculation result and the second calculation result output by the first processing circuit (700) via the third input terminal (810), and outputs the first calculation result and the second calculation result to the third calculation circuit (300) via the fifth output terminal (830).

11. The calculation method according to claim 9, wherein, If the third arithmetic circuit (300) receives only the first arithmetic result, the method further includes: The second data distributor (600) receives the first calculation result via the second input terminal (610) and outputs the first calculation result via the fourth output terminal (630); The first data selector (800) receives the first calculation result via the fourth input terminal (820) and outputs the first calculation result to the third calculation circuit (300) via the fifth output terminal (830).

12. The computation method according to claim 9, wherein the artificial intelligence chip further comprises a third data distributor (900), a second processing circuit (1000), and a second data selector (1100), and the method further comprises: The third data distributor (900) receives the third calculation result via the fifth input terminal (910) and outputs the third calculation result via the sixth output terminal (920) or the seventh output terminal (930); The second processing circuit (1000) receives the third operation result from the seventh output terminal (930) and the fourth operation result from the fourth operation circuit (500) within one clock cycle, and outputs the third operation result and the fourth operation result respectively within two clock cycles, or outputs the third operation result and the fourth operation result synchronously within one clock cycle; as well as The second data selector (1100) receives the third operation result from the sixth output terminal (920) via the sixth input terminal (1110) or receives the third operation result and the fourth operation result output by the second processing circuit (1000) via the seventh input terminal (1120), and outputs them via the eighth output terminal (1130) of the second data selector (1100).

13. The computation method according to claim 12, wherein the artificial intelligence chip further includes a fourth data distributor (1200), and the method further includes: The fourth data distributor (1200) receives the fourth operation result via the eighth input terminal (1210) and outputs the fourth operation result via the ninth output terminal (1220) or the tenth output terminal (1230). The tenth output terminal (1230) is connected to the end of the second processing circuit (1000) near the third data distributor (900).

14. The computation method according to claim 9, wherein the artificial intelligence chip further comprises a fifth data distributor (1500), a fifth computation circuit (1300), a fourth data selector (1600), and a third data selector (1400), and the method further comprises: The fifth data distributor (1500) receives the third operation result from the third arithmetic circuit (300) via the eleventh input terminal (1510) and outputs it via the twelfth output terminal (1520) or the thirteenth output terminal (1530); The fifth arithmetic circuit (1300) performs a fifth arithmetic operation on the third arithmetic result from the thirteenth output terminal (1530) to output a fifth arithmetic result, wherein the fifth arithmetic operation is different from the first arithmetic operation and is different from the third arithmetic operation; The third data selector (1400) receives the fifth operation result from the fifth arithmetic circuit (1300) via the ninth input terminal (1410) or receives the second operation result from the second output terminal (430) via the tenth input terminal (1420), and outputs it to the fourth arithmetic circuit (500) via the eleventh output terminal (1430). Upon receiving the fifth operation result, the fourth operation circuit (500) performs the fourth operation on the fifth operation result to output the fourth operation result; as well as The fourth data selector (1600) receives the third operation result from the twelfth output (1520) via the twelfth input (1610) or receives the fourth operation result from the fourth operation circuit (500) via the thirteenth input (1620), and outputs it via the fourteenth output (1630).

15. The calculation method according to claim 14, wherein, The first operation is one of the first type of operation and the second type of operation, the fifth operation is another of the first type of operation and the second type of operation, the third operation is an activation function operation, the first type of operation is a convolution operation, and the second type of operation includes at least one of dot multiplication and dot addition.

16. The calculation method according to claim 15, wherein, The first operation is a first type of operation, and the fifth operation is a second type of operation.

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