Amplifier and method for controlling common-mode voltage thereof

Abstract

This application discloses an amplifier and a method for controlling its common-mode voltage. The amplifier includes: a positive-terminal P-type transistor; a negative-terminal P-type transistor; a positive-terminal N-type transistor having a drain coupled to the drain of the positive-terminal P-type transistor and outputting a positive output signal; a negative-terminal N-type transistor having a drain coupled to the drain of the negative-terminal P-type transistor and outputting a negative output signal; a first resistor coupled between the gate of the negative-terminal N-type transistor and the negative input signal; a second resistor coupled between the gate of the negative-terminal N-type transistor and the positive output signal; a third resistor coupled between the gate of the negative-terminal P-type transistor and the negative input signal; and a fourth resistor coupled between the gate of the negative-terminal P-type transistor and the positive output signal.

Description

Technical Field

[0001] This application relates to circuits, and more particularly to an amplifier circuit. Background Technology

[0002] For differential amplifiers composed of stacked transistors, the input common-mode voltages of the stacked P-type and N-type transistors may not be designed to be equal, meaning different DC bias voltages are required to ensure proper operation. A common practice is to use AC coupling capacitors connected between the gates of the stacked P-type and N-type transistors, but this approach is inefficient and consumes a large area. Summary of the Invention

[0003] This application provides an amplifier, comprising: an amplification unit including: a positive-terminal P-type transistor; a negative-terminal P-type transistor; a positive-terminal N-type transistor, wherein the positive-terminal P-type transistor and the positive-terminal N-type transistor are stacked between a first reference voltage and a second reference voltage, and a drain of the positive-terminal N-type transistor is coupled to a drain of the positive-terminal P-type transistor and outputs a positive-terminal output signal; and a negative-terminal N-type transistor, wherein the negative-terminal P-type transistor and the negative-terminal N-type transistor are stacked between the first reference voltage and the second reference voltage. Between the voltages, one drain of the negative N-type transistor is coupled to one drain of the negative P-type transistor and outputs a negative output signal; a first resistor is coupled between one gate of the negative N-type transistor and a negative input signal; a second resistor is coupled between one gate of the negative N-type transistor and the positive output signal; a third resistor is coupled between one gate of the negative P-type transistor and the negative input signal; and a fourth resistor is coupled between one gate of the negative P-type transistor and the positive output signal.

[0004] This application provides an amplifier, comprising: an amplification unit including: a positive-terminal P-type transistor; a negative-terminal P-type transistor; a positive-terminal N-type transistor, wherein the positive-terminal P-type transistor and the positive-terminal N-type transistor are stacked between a first reference voltage and a second reference voltage, and a drain of the positive-terminal N-type transistor is coupled to a drain of the positive-terminal P-type transistor and outputs a positive-terminal output signal; and a negative-terminal N-type transistor, wherein the negative-terminal P-type transistor and the negative-terminal N-type transistor are stacked between the first reference voltage and the second reference voltage, and a drain of the negative-terminal N-type transistor is coupled to a drain of the negative-terminal P-type transistor and outputs a negative-terminal signal. The output signal includes: a first resistor coupled between a gate of the negative N-type transistor and a negative input signal; a second resistor coupled between a gate of the negative P-type transistor and the negative input signal; a first capacitor coupled between a gate of the negative N-type transistor and the positive output signal; a second capacitor coupled between a gate of the negative P-type transistor and the positive output signal; and a first current source coupled to either a gate of the negative N-type transistor or a gate of the negative P-type transistor to control the DC voltage at either gate of the negative N-type transistor or the negative P-type transistor.

[0005] This application provides an amplifier, comprising: an amplification unit including: a positive-terminal P-type transistor; a negative-terminal P-type transistor; a positive-terminal N-type transistor, wherein the positive-terminal P-type transistor and the positive-terminal N-type transistor are stacked between a first reference voltage and a second reference voltage, and a drain of the positive-terminal N-type transistor is coupled to a drain of the positive-terminal P-type transistor and outputs a positive-terminal output signal; and a negative-terminal N-type transistor, wherein the negative-terminal P-type transistor and the negative-terminal N-type transistor are stacked between the first reference voltage and the second reference voltage, and a drain of the negative-terminal N-type transistor is coupled to a drain of the negative-terminal P-type transistor and outputs a negative-terminal signal. The output signal includes: a first capacitor coupled between a gate of the negative N-type transistor and a negative input signal; a second capacitor coupled between a gate of the negative P-type transistor and the negative input signal; a first resistor coupled between a gate of the negative N-type transistor and the positive output signal; a second resistor coupled between a gate of the negative P-type transistor and the positive output signal; and a first current source coupled to either a gate of the negative N-type transistor or a gate of the negative P-type transistor to control the DC voltage at either gate of the negative N-type transistor or the negative P-type transistor.

[0006] This application can improve the efficiency of amplifiers and reduce their size. Attached Figure Description

[0007] The various embodiments disclosed herein can be best understood by reading the following description and the accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features in the figures are not drawn to scale. In fact, the dimensions of certain features may be intentionally enlarged or reduced for clarity of description.

[0008] Figure 1 This is a schematic diagram of the first embodiment of the amplifier of this application.

[0009] Figure 2 This is a schematic diagram of an embodiment of the amplifier unit of the amplifier of this application.

[0010] Figure 3 This is a schematic diagram of a second embodiment of the amplifier of this application.

[0011] Figure 4 This is a schematic diagram of a third embodiment of the amplifier of this application.

[0012] Figure 5 This is a schematic diagram of the fourth embodiment of the amplifier of this application.

[0013] Figure 6 This is a schematic diagram of the fifth embodiment of the amplifier of this application.

[0014] Figure 7 This is a schematic diagram of the sixth embodiment of the amplifier of this application.

[0015] Figure 8 This is a schematic diagram of the seventh embodiment of the amplifier of this application.

[0016] Figure 9 This is a schematic diagram of the eighth embodiment of the amplifier of this application. Detailed Implementation

[0017] Figure 1 This is a schematic diagram of a first embodiment of the amplifier of this application. The amplifier 100 is a differential input / output amplifier, whose differential input signal pair includes a positive input signal VIP and a negative input signal VIN; its differential output signal pair includes a positive output signal VOP and a negative output signal VON. The amplifier 100 includes an amplification unit 102 and resistors R1 to R8. The amplification unit 102 receives a first positive signal VIP1, a second positive signal VIP2, a first negative signal VIN1, and a second negative signal VIN2, and outputs a positive output signal VOP and a negative output signal VON.

[0018] Figure 2 This is a schematic diagram of an embodiment of the amplifier unit 102 of the amplifier in this application, which is applicable to... Figure 1 , Figures 3 to 9Amplification unit 102 in amplifiers 100 / 300 / 400 / 500 / 600 / 700 / 800 / 900. Amplification unit 102 includes a positive P-type transistor PMp, a negative P-type transistor PMn, a positive N-type transistor NMp, and a negative N-type transistor NMn. The positive P-type transistor PMp and the positive N-type transistor NMp are stacked between reference voltage V1 and reference voltage V2; the negative P-type transistor PMn and the negative N-type transistor NMn are also stacked between reference voltage V1 and reference voltage V2. Specifically, the drain of the positive P-type transistor PMp is coupled to the drain of the positive N-type transistor NMp; the drain of the negative P-type transistor PMn is coupled to the drain of the negative N-type transistor NMn. The gate of the positive-terminal N-type transistor NMp receives the first positive signal VIP1, the gate of the positive-terminal P-type transistor PMp receives the second positive signal VIP2, the gate of the negative-terminal N-type transistor NMn receives the first negative signal VIN1, and the gate of the negative-terminal P-type transistor PMn receives the second negative signal VIN2. In this embodiment, the reference voltage V1 is higher than the reference voltage V2, and the reference voltage V2 is ground voltage. In some embodiments, a current source may also be provided near the reference voltage V1 and / or voltage V2.

[0019] Please also refer to Figure 1 and Figure 2 Resistor R1 is coupled between the gate of the negative N-type transistor NMn and the negative input signal VIN; resistor R2 is coupled between the gate of the negative N-type transistor NMn and the positive output signal VOP; resistor R3 is coupled between the gate of the negative P-type transistor PMn and the negative input signal VIN; resistor R4 is coupled between the gate of the negative P-type transistor PMn and the positive output signal VOP; resistor R5 is coupled between the gate of the positive N-type transistor NMp and the positive input signal VIP; resistor R6 is coupled between the gate of the positive N-type transistor NMp and the negative output signal VON; resistor R7 is coupled between the gate of the positive P-type transistor PMp and the positive input signal VIP; resistor R8 is coupled between the gate of the positive P-type transistor PMp and the negative output signal VON.

[0020] When determining the voltage values ​​of resistors R1 to R8, it is necessary to first determine the proportional relationship between the resistance values ​​of resistors R1 and R4 based on the desired AC gain of amplifier 100 and the DC voltages of the first negative terminal signal VIN1 and the second negative terminal signal VIN2. Similarly, based on the desired AC gain of amplifier 100 and the DC voltages of the first positive terminal signal VIP1 and the second positive terminal signal VIP2, the proportional relationship between the resistance values ​​of resistors R5 and R8 can be determined. Therefore, when the DC voltages of the first negative terminal signal VIN1 and the second negative terminal signal VIN2 are different, the ratio of the resistance values ​​of resistors R1 and R2 will be different from the ratio of the resistance values ​​of resistors R3 and R4; the ratio of the resistance values ​​of resistors R5 and R6 will be different from the ratio of the resistance values ​​of resistors R7 and R8. However, the ratio of the resistance values ​​of resistor R1 to R2 will be the same as the ratio of the resistance values ​​of resistor R5 to R6; the ratio of the resistance values ​​of resistor R3 to R4 will be the same as the ratio of the resistance values ​​of resistor R7 to R8.

[0021] In some embodiments, resistors R1 to R8 can be implemented using switched capacitors. In some embodiments, they can also be implemented as follows: Figure 3 The amplifier 300 has additional current sources 302 and 304 at the gates of the positive N-type transistor NMp and the negative N-type transistor NMn, respectively, to adjust the DC voltages of the first positive signal VIP1 and the first negative signal VIN1. In this way, resistors R1 to R8 only affect the AC gain of the amplifier 300, thus increasing design flexibility and convenience. For example, the ratio of the resistance values ​​of resistor R1 to R2 can be controlled to be the same as the ratio of the resistance values ​​of resistor R3 to R4, resistor R5 to R6, and resistor R7 to R8.

[0022] It should be noted that current source 304 and current source 302 can also be replaced by setting current sources at the gates of the positive P-type transistor PMp and the negative P-type transistor PMn, respectively, or by setting current sources at the gates of the positive N-type transistor NMp, the negative N-type transistor NMn, the positive P-type transistor PMp, and the negative P-type transistor PMn.

[0023] In some embodiments, resistors R2, R4, R6, and R8 of amplifier 300 can be replaced with capacitors C1 to C4, such as... Figure 4 The amplifier 400 is shown. Since capacitors C1 to C4 are open circuits for DC, it is better to use a current source to control the DC voltage. In other words, Figure 4 The amplifier 400 requires current sources 302 and 304 to be respectively located at the gates of the positive N-type transistor NMp and the negative N-type transistor NMn. It should be noted that current sources 302 and 304 can also be replaced by being located at the gates of the positive P-type transistor PMp and the negative P-type transistor PMn, or by being located at the gates of the positive N-type transistor NMp, the negative N-type transistor NMn, the positive P-type transistor PMp, and the negative P-type transistor PMn.

[0024] In some embodiments, amplifiers 300 and 400 can be combined, and resistors R2, R4, R6, and R8 can be connected in series with capacitors C1 to C4, respectively. Figure 5 The amplifier 500 is shown. In some embodiments, resistors R2, R4, R6, and R8 can be connected in parallel with capacitors C1 to C4, as shown below. Figure 6 The amplifier 600 is shown.

[0025] In some embodiments, resistors R1, R3, R5, and R7 of amplifier 300 can be replaced with capacitors C1 to C4, such as... Figure 7 The amplifier 700 is shown. Since capacitors C1 to C4 are open circuits for DC, it is better to use a current source to control the DC voltage. In other words, Figure 7 The amplifier 700 requires current sources 302 and 304 to be respectively located at the gates of the positive N-type transistor NMp and the negative N-type transistor NMn. It should be noted that current sources 302 and 304 can also be located at the gates of the positive P-type transistor PMp and the negative P-type transistor PMn, respectively, or current sources can be located at the gates of the positive N-type transistor NMp, the negative N-type transistor NMn, the positive P-type transistor PMp, and the negative P-type transistor PMn.

[0026] In some embodiments, amplifiers 300 and 700 can be combined, and resistors R1, R3, R5, and R7 can be connected in series with capacitors C1 to C4, respectively. Figure 8 The amplifier 800 is shown. In some embodiments, resistors R1, R3, R5, and R7 can be connected in parallel with capacitors C1 to C4, as shown below. Figure 9 The amplifier 900 is shown.

[0027] This application is not limited to differential architecture. In some embodiments, amplifiers 100 / 300 / 400 / 500 / 600 / 700 / 800 / 900 can also be adjusted to a single-ended amplifier architecture.

[0028] [Symbol Explanation]

[0029] 100, 300, 400, 500, 600, 700, 800, 900: Amplifiers

[0030] 102: Amplification Unit

[0031] R1, R2, R3, R4, R5, R6, R7, R8: Reference voltage

[0032] VIP: Positive Input Signal

[0033] VIN: Negative input signal

[0034] VOP: Positive output signal

[0035] VON: Negative terminal output signal

[0036] VIP1: First positive signal

[0037] VIP2: Second positive terminal signal

[0038] VIN1: First negative terminal signal

[0039] VIN2: Second negative terminal signal

[0040] V1, V2: Reference voltages

[0041] PMp: Positive terminal P-type transistor

[0042] PMn: Negative-terminal P-type transistor

[0043] NMp: Positive-terminal N-type transistor

[0044] NMn: N-type transistor at the negative terminal

[0045] 302, 304: Current source

[0046] C1, C2, C3, C4: Capacitors

Claims

1. An amplifier comprising: One amplification unit, comprising: A positive-terminal P-type transistor; A negative-terminal P-type transistor; A positive-terminal N-type transistor, wherein the positive-terminal P-type transistor and the positive-terminal N-type transistor are stacked between a first reference voltage and a second reference voltage, and a drain of the positive-terminal N-type transistor is coupled to a drain of the positive-terminal P-type transistor and outputs a positive-terminal output signal; and A negative-terminal N-type transistor, wherein the negative-terminal P-type transistor and the negative-terminal N-type transistor are stacked between the first reference voltage and the second reference voltage, and one drain of the negative-terminal N-type transistor is coupled to one drain of the negative-terminal P-type transistor and outputs a negative-terminal output signal; A first resistor is coupled between a gate of the negative-terminal N-type transistor and a negative-terminal input signal; A second resistor is coupled between a gate of the negative N-type transistor and the output signal at the positive terminal. A third resistor is coupled between a gate of the negative terminal P-type transistor and the negative terminal input signal; and A fourth resistor is coupled between a gate of the negative P-type transistor and the output signal at the positive terminal.

2. The amplifier of claim 1, wherein the ratio of the resistance value of the first resistor to the resistance value of the second resistor is different from the ratio of the resistance value of the third resistor to the resistance value of the fourth resistor.

3. The amplifier as claimed in claim 1, wherein the ratio of the resistance value of the first resistor to the resistance value of the second resistor is the same as the ratio of the resistance value of the third resistor to the resistance value of the fourth resistor, and the amplifier further includes a current source coupled to a gate of the negative terminal N-type transistor or a gate of the negative terminal P-type transistor to control the DC voltage of a gate of the negative terminal N-type transistor or the DC voltage of a gate of the negative terminal P-type transistor.

4. The amplifier of claim 1, wherein the DC voltage of a gate of the negative N-type transistor is different from the DC voltage of a gate of the negative P-type transistor.

5. The amplifier of claim 1, further comprising: A fifth resistor is coupled between a gate of the positive-terminal N-type transistor and a positive-terminal input signal. A sixth resistor is coupled between a gate of the positive N-type transistor and the output signal at the negative terminal. A seventh resistor is coupled between a gate of the positive terminal P-type transistor and the positive terminal input signal; and An eighth resistor is coupled between a gate of the positive P-type transistor and the output signal at the negative terminal.

6. The amplifier of claim 5, wherein the ratio of the resistance value of the fifth resistor to the resistance value of the sixth resistor is different from the ratio of the resistance value of the seventh resistor to the resistance value of the eighth resistor.

7. The amplifier of claim 5, further comprising: A first capacitor is coupled between a gate of the negative N-type transistor and the positive output signal; A second capacitor is coupled between a gate of the negative terminal P-type transistor and the output signal at the positive terminal. A third capacitor is coupled between a gate of the positive N-type transistor and the output signal at the negative terminal; and A fourth capacitor is coupled between a gate of the positive P-type transistor and the output signal at the negative terminal.

8. The amplifier of claim 5, further comprising: A first capacitor is coupled between a gate of the negative-terminal N-type transistor and the negative-terminal input signal; A second capacitor is coupled between a gate of the negative terminal P-type transistor and the negative terminal input signal; A third capacitor is coupled between a gate of the positive-terminal N-type transistor and the positive-terminal input signal; and A fourth capacitor is coupled between a gate of the positive P-type transistor and the positive input signal.

9. An amplifier comprising: One amplification unit, comprising: A positive-terminal P-type transistor; A negative-terminal P-type transistor; A positive-terminal N-type transistor, wherein the positive-terminal P-type transistor and the positive-terminal N-type transistor are stacked between a first reference voltage and a second reference voltage, and a drain of the positive-terminal N-type transistor is coupled to a drain of the positive-terminal P-type transistor and outputs a positive-terminal output signal; and A negative-terminal N-type transistor, wherein the negative-terminal P-type transistor and the negative-terminal N-type transistor are stacked between the first reference voltage and the second reference voltage, and one drain of the negative-terminal N-type transistor is coupled to one drain of the negative-terminal P-type transistor and outputs a negative-terminal output signal; A first resistor is coupled between a gate of the negative-terminal N-type transistor and a negative-terminal input signal; A second resistor is coupled between a gate of the negative terminal P-type transistor and the negative terminal input signal; A first capacitor is coupled between a gate of the negative N-type transistor and the positive output signal; A second capacitor is coupled between a gate of the negative terminal P-type transistor and the output signal at the positive terminal; and A first current source is coupled to a gate of the negative N-type transistor or a gate of the negative P-type transistor to control the DC voltage of a gate of the negative N-type transistor or the DC voltage of a gate of the negative P-type transistor.

10. An amplifier comprising: One amplification unit, comprising: A positive-terminal P-type transistor; A negative-terminal P-type transistor; A positive-terminal N-type transistor, wherein the positive-terminal P-type transistor and the positive-terminal N-type transistor are stacked between a first reference voltage and a second reference voltage, and a drain of the positive-terminal N-type transistor is coupled to a drain of the positive-terminal P-type transistor and outputs a positive-terminal output signal; and A negative-terminal N-type transistor, wherein the negative-terminal P-type transistor and the negative-terminal N-type transistor are stacked between the first reference voltage and the second reference voltage, and one drain of the negative-terminal N-type transistor is coupled to one drain of the negative-terminal P-type transistor and outputs a negative-terminal output signal; A first capacitor is coupled between a gate of the negative-terminal N-type transistor and a negative-terminal input signal; A second capacitor is coupled between a gate of the negative terminal P-type transistor and the negative terminal input signal; A first resistor is coupled between a gate of the negative N-type transistor and the output signal at the positive terminal. A second resistor is coupled between a gate of the negative P-type transistor and the output signal at the positive terminal; and A first current source is coupled to a gate of the negative N-type transistor or a gate of the negative P-type transistor to control the DC voltage of a gate of the negative N-type transistor or the DC voltage of a gate of the negative P-type transistor.

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