An HPLC FCH fractionating system and method thereof

Abstract

This invention discloses an HPLC FCH aggregation and merging system, comprising a simplified FCH aggregation and merging offset table and an adjusted merging RAM storage structure. In the aggregation and merging offset table, the I and Q paths use the same offset value, and the initial information bit transmitted by the I path is indicated: 1: currently transmitted information bit data; 0: currently transmitted check bit data. In the RAM storage structure, the check bit and information bit have the same merged RAM address, allowing simultaneous merging of I / Q data at a constellation point using a single RAM block. In this invention, information bit merging and check bit merging use a shared counting unit, reducing storage space and the number of counting operations. The aggregation and merging system of this invention improves the aggregation and merging efficiency of FCH, while reducing storage space and computational load.

Description

An HPLC FCH fractionation and merging system and method thereof Technical Field

[0001] This invention belongs to the field of communication technology and relates to broadband power line carrier communication systems. Specifically, it relates to a collection merging system and its method. Background Technology

[0002] The frame-controlled FCH diversity process in HPLC is as follows:

[0003] The 128-bit control frame is turbo encoded into 256-bit data. Different offsets are used to map the data onto both the I and Q paths of the QPSK for transmission, as shown in Table 1.

[0004] Table 1 FCH diversity offset table:

[0005]

[0006] This section uses the first OFDM (Orthogonal Frequency-Division Multiplexing) symbol as an example to illustrate the FCH diversity copying scenario. As shown in Figure 1, the FCH mapping on the first OFDM symbol involves cyclically acquiring the OFDM symbol length data starting from offset 0 on the I-path. On the Q-path, the OFDM symbol length data is cyclically acquired starting from offset 128.

[0007] The mapping formula is: (i + Vshift) mod 256, where i = 0 ~ NumCarriers-1. Here, NumCarriers represents the number of OFDM carriers, i represents the subcarrier number, and Vshift represents the offset position.

[0008] Due to differences in frequency bands and bandwidth, the number of OFDM symbols copied by FCH diversity copy and the number of OFDM subcarriers also differ, resulting in different LLR combining times.

[0009] In the existing technology, the I / Q paths of FCH are mapped with different offsets. When merging, the offsets of the read and write addresses are different, so the I / Q paths need to be merged separately.

[0010] The storage method in LLR merged RAM is shown in Figure 2.

[0011] This explanation uses the first OFDM symbol of FCH as an example:

[0012] The offset of the I-path is 0. Data is read from position 0 of the merged RAM and LLR merging is performed until LLR merging at position 255 is completed. Then, LLR merging continues from position 0 until all data in the current I-path is merged.

[0013] The offset of Q path is 128. Data is read from position 128 of the merged RAM and LLR merging is performed until LLR merging at position 255. Then, LLR merging continues from position 0 until the current Q path data is merged.

[0014] During each merge, the merge count corresponding to the LLR is read out, incremented by one, and then written back.

[0015] After all OFDM symbols' LLR information has been merged, the merged LLR and the number of merges are read out and divided to obtain the average LLR as the final output.

[0016] The existing technology has the following problems: FCH needs to merge the I / Q channels twice, which makes it impossible to perform real-time merging processing of the received data, thus prolonging the processing time. Summary of the Invention

[0017] To overcome the shortcomings of the prior art, the present invention aims to provide an HPLC FCH splitting and merging system and method, which improves the splitting and merging efficiency of FCH and reduces storage space and computational load.

[0018] To solve the above-mentioned technical problems and achieve the above-mentioned technical effects, the present invention is implemented through the following technical solution:

[0019] An HPLC FCH pooling and merging system includes a simplified FCH pooling and merging offset table and an adjusted merging RAM storage structure; in the RAM storage structure, the test bits and information bits have the same merged RAM address, and a single RAM can be used to simultaneously merge I / Q data at a constellation point.

[0020] Furthermore, in the set-and-offset table, the I-path and Q-path use the same offset value, and the identifier of the information bit transmitted at the beginning of the I-path is given: 1: currently transmitting information bit data; 0: currently transmitting parity bit data.

[0021] Furthermore, assuming the offset value is Vshift and the received QPSK constellation point count is i, the merged RAM address is mod(Vshift+i, 128). When Vshift+i accumulates to a multiple of 128, the information bit indication of the I-path transmission is reversed, i.e., the I-path previously transmitted information bit data, and now transmits parity bit data; or the I-path previously transmitted parity bit data, and now transmits information bit data. The corresponding Q-path transmission maintains the opposite relationship with the I-path, i.e., the I-path transmits information bit data, and the Q-path correspondingly transmits parity bit data; or the I-path transmits parity bit data, and the Q-path correspondingly transmits information bit data.

[0022] Furthermore, the internal storage method of the RAM storage structure is as follows: The RAM has a depth of 128, and each address contains one LLR merged value for information bits, one LLR merged value for parity bits, and one merge count value; address 0 in the RAM stores the LLR merged value corresponding to the first information data, the LLR merged value corresponding to the first parity data, and the merge count value shared by the first information data and the first parity data; address 1 in the RAM stores the LLR merged value corresponding to the second information data, the LLR merged value corresponding to the second parity data, and the merge count value shared by the second information data and the second parity data; and so on, address 127 in the RAM stores the LLR merged value corresponding to the 128th information data, the LLR merged value corresponding to the 128th parity data, and the merge count value shared by the 128th information data and the 128th parity data.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] 1. The offset address of the merged RAM corresponding to the I / Q data in each constellation point is consistent, so the merging process can be performed simultaneously in one RAM.

[0025] 2. Merging information bits and check bits corresponding to the same address in RAM requires the same number of merging operations, reducing storage space and the number of counting operations.

[0026] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the invention and to implement it according to the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Specific embodiments of the present invention are given in detail below with reference to the accompanying drawings. Attached Figure Description

[0027] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0028] Figure 1 is a schematic diagram of the mapping of FCH OFDM symbol 1 in the prior art.

[0029] Figure 2 is a schematic diagram of the internal storage structure of the FCH subset and RAM in the prior art.

[0030] Figure 3 is a schematic diagram of the FCH set-and-merge system structure of the present invention.

[0031] Figure 4 is a schematic diagram of the internal storage structure of the FCH subset and RAM of the present invention. Detailed Implementation

[0032] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings to provide a clearer understanding of the invention's purpose, features, and advantages. It should be understood that the embodiments shown in the drawings are not intended to limit the scope of the invention, but are merely illustrative of the essential spirit of the invention's technical solution.

[0033] In the following description, certain specific details are set forth for the purpose of illustrating various disclosed embodiments in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that embodiments may be practiced without one or more of these specific details. In other instances, well-known apparatuses, structures, and techniques associated with this application may not have been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0034] Unless the context requires otherwise, throughout the specification and claims, the word “comprising” and its variations, such as “including” and “having”, shall be understood to have an open, inclusive meaning, that is, to be interpreted as “including, but not limited to”.

[0035] Throughout this specification, references to "an embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the appearance of "in an embodiment" or "an embodiment" in various places throughout the specification does not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in any manner in one or more embodiments.

[0036] The singular forms “a” and “the” used in this specification and the appended claims include plural references unless otherwise expressly stated herein. It should be noted that the term “or” is generally used to mean “and / or” unless otherwise expressly stated herein.

[0037] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. Example 1

[0038] First, let's clarify the following English abbreviations:

[0039] HPLC: High-speed Power Line Communication, broadband power line carrier communication system.

[0040] FCH: Frame Control Header.

[0041] LLR: Log Likelihood Ratio.

[0042] QPSK: Quadrature Phase Shift Keying.

[0043] As shown in Figure 3, this embodiment discloses an HPLC FCH merging system, wherein the internal structure of the FCH merging RAM is shown in Figure 4.

[0044] The RAM has a depth of 128, and each address contains an information bit LLR merge value, a parity bit LLR merge value, and a merge count value.

[0045] Address 0 in RAM stores the LLR merged value corresponding to the first information data, the LLR merged value corresponding to the first check data, and the merged count value shared by the first information data and the first check data.

[0046] Address 1 in RAM stores the LLR merged value corresponding to the second information data, the LLR merged value corresponding to the second check data, and the merged count value shared by the second information data and the second check data.

[0047] Similarly, address 127 in RAM stores the LLR merged value corresponding to the 128th information data, the LLR merged value corresponding to the 128th check data, and the merged count value shared by the 128th information data and the 128th check data.

[0048] Furthermore, this embodiment constructs a simplified FCH subset and offset table, as shown in Table 2.

[0049] Table 2 FCH diversity offset:

[0050]

[0051] In the table, the I-path and Q-path use the same offset value, and the identifier of the information bits transmitted at the beginning of the I-path is given: 1: the information bit data being transmitted; 0: the parity bit data being transmitted.

[0052] Assuming the offset value is Vshift and the received QPSK constellation point count is i, the merged RAM address is mod(Vshift+i, 128). When Vshift+i accumulates to a multiple of 128, the information bit indication of the I-channel transmission is reversed, i.e., the I-channel previously transmitted information bit data, now it transmits parity bit data; or the I-channel previously transmitted parity bit data, now it transmits information bit data. The corresponding Q-channel transmission maintains the opposite relationship to the I-channel, i.e., the I-channel transmits information bit data, and the Q-channel correspondingly transmits parity bit data; or the I-channel transmits parity bit data, and the Q-channel correspondingly transmits information bit data. Example 2

[0053] This embodiment discloses an HPLC FCH fractionation and merging method:

[0054] The initial offset for the I / Q paths is 112. Initially, the I path transmits the parity bit, and the Q path transmits the information bit.

[0055] The merged offset address is 112. As the receive count i increases, the merged RAM address becomes mod(112+i, 128).

[0056] When i==16, mod(112+i,128)==0, the offset address in the merged RAM is 0, the I-path starts transmitting information bits, and the Q-path starts transmitting parity bits; as i increases, when i=144, mod(112+i,128)==0, the I-path starts transmitting parity bits, and the Q-path starts transmitting information bits.

[0057] Based on the calculated offset address and data type, perform LLR merging at the corresponding positions.

[0058] When the I channel contains information data, the information LLR merged value is read from the corresponding address and merged; the Q channel reads the parity LLR merged value and merges it.

[0059] When the I-channel contains verification data, the verification LLR merged value is read from the corresponding address and merged; the Q-channel reads the information LLR merged value and merges it.

[0060] The merge count is updated during LLR merging until all FCH data has been received.

[0061] Once all FCH data has been merged, the information bit merge LLR, parity bit merge LLR, and the number of merges are read from the merge RAM.

[0062] The average LLR of information bit merging and check bit merging is calculated using the number of merging reads, and the calculation result is output as a subset.

[0063] Through the structural design of this embodiment, the I / Q path LLRs corresponding to each constellation point have the same address in the merged RAM, allowing for simultaneous merging processing and reducing processing latency. Information data and check data at the same address are merged the same number of times, reducing RAM space usage and the number of counting calculations.

[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An HPLC FCH fractionation and merging system, characterized in that: It includes a simplified FCH set-off offset table and an adjusted merge RAM storage structure; in the RAM storage structure, the check bits and information bits have the same merge RAM address, and a single RAM can be used to simultaneously merge I / Q data at a constellation point; the set-off offset table is as follows: The table shows that the I and Q paths use the same offset value, and indicates the type of information bits initially transmitted by the I path: 1: currently transmitted information bit data; 0: Currently transmitting checksum data; Assuming the offset value is Vshift and the received QPSK constellation point count is i, then the merged RAM address is mod(Vshift+i, 128); the RAM depth is 128, and each address contains an information bit LLR merged value, a check bit LLR merged value, and a merged count value.

2. The HPLC FCH separator and collector system according to claim 1, characterized in that: When Vshift+i accumulates to a multiple of 128, the information bit type transmitted on the I-path is reversed. That is, if the I-path previously transmitted information bit data, it now transmits parity bit data; or if the I-path previously transmitted parity bit data, it now transmits information bit data. The corresponding data transmitted on the Q-path maintains the opposite relationship with the I-path. That is, if the I-path transmits information bit data, the Q-path transmits parity bit data; or if the I-path transmits parity bit data, the Q-path transmits information bit data.

3. The HPLC FCH separator and collector system according to claim 2, characterized in that: The internal storage method of the RAM storage structure is as follows: address 0 in RAM stores the LLR merged value corresponding to the first information bit data, the LLR merged value corresponding to the first parity bit data, and the merged count value shared by the first information bit data and the first parity bit data; address 1 in RAM stores the LLR merged value corresponding to the second information bit data, the LLR merged value corresponding to the second parity bit data, and the merged count value shared by the second information bit data and the second parity bit data. Similarly, address 127 in RAM stores the LLR merged value corresponding to the 128th information bit data, the LLR merged value corresponding to the 128th parity bit data, and the merged count value shared by the 128th information bit data and the 128th parity bit data.

4. A method for pooling and merging using the HPLC FCH pooling and merging system as described in any one of claims 1-3, characterized in that: Based on the calculated offset address and data type, perform LLR merging at the corresponding position; when the I channel is information bit data, read the information bit LLR merge value from the corresponding address and merge it; Q-channel reads the parity bit LLR merged value and merges them; When the I-channel contains parity bit data, the parity bit LLR merge value is read from the corresponding address and merged. The Q-path reads the LLR merge value and merges it; while merging the LLR, the merge count value is updated until all FCH data has been received. Once all FCH data has been merged, read the merged information bit LLR merged value, the parity bit LLR merged value, and the merged count value from the merged RAM. The average value of the merged information bit LLR and the merged check bit LLR are calculated using the read merged count value, and the calculation result is output as a subset.

Images