A 5G LDPC code decoding method and device

By optimizing the hierarchical decoding layer update order of 5G LDPC code, the problems of poor decoding performance and slow convergence speed are solved, faster convergence speed and better error correction performance are achieved, and hardware resource consumption is reduced.

CN116961836BActive Publication Date: 2025-08-05NANJING UNIV
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
CN202310971642.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-08-03
Publication Date
2025-08-05
Estimated Expiration
2043-08-03

AI Technical Summary

Technical Problem

The existing 5G LDPC coding and decoding schemes have problems with poor decoding performance and slow convergence speed, especially the failure to effectively utilize the extremely uneven redistribution of its check matrix rows.

Method used

Optimize the layer update order of hierarchical decoding, determine the optimized layer update order by counting the row layer's row layer's row layer's row layer's row layer's adjacency number, and the second-order row layer's degree, and use the optimized layer update order for hierarchical decoding scheduling.

Benefits of technology

It significantly improves the convergence speed and error correction performance of decoding, while reducing hardware resource consumption and not increasing computational complexity.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN116961836B_ABST
    Figure CN116961836B_ABST
Patent Text Reader

Abstract

The present invention provides a 5G LDPC code decoding method and device, the decoding method is: first, the check matrix of the 5G LDPC code is layered according to the lifting value, and then the optimized layer update order is determined according to three indicators: row layer degree, the number of first two column adjacencies, and the second-order row layer degree. In the layered decoding scheduling, decoding according to the aforementioned optimized layer update order can improve the error correction performance of the 5G LDPC code and accelerate the convergence speed of the decoding. The decoding device is a decoding device that adopts the aforementioned optimized layer update order, and the decoding device includes a control module, a memory module, and a computing module. The control module records the aforementioned optimized layer update order, which is used to control the decoding device to read the data of the corresponding layer from the memory module according to the optimized layer update order, and transmit it to the computing module for decoding.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present invention relates to a 5G LDPC code decoding method and device. Background Art

[0002] Because various types of noise inevitably contaminate communication channels, information transmitted by the transmitter in a communication system will inevitably be distorted after passing through a noisy channel. To restore the distorted information to its original state, the receiver must utilize various methods. Channel coding is a particularly effective method for improving the reliability of communication systems. On the transmitter side, the channel encoder adds redundant information to the original information to mitigate noise. On the receiver side, the channel decoder utilizes this redundant information and employs a decoding method adapted to the encoding method to efficiently restore the original information.

[0003] Among the many channel coding schemes, Low-Density Parity-Check (LDPC) codes are a highly advanced scheme, boasting error correction performance very close to the Shannon limit. LDPC codes were first invented in 1962 by Dr. R. Gallager of the Massachusetts Institute of Technology. Due to the limitations of computer performance at the time, LDPC codes received little attention and lay dormant for over three decades. It wasn't until the 1990s, when D. Mackay et al. rediscovered LDPC codes, that they have since garnered widespread attention from both industry and academia, and have been adopted as channel coding schemes in various communication system standards.

[0004] In the latest fifth-generation mobile communications (5G) standard, LDPC codes have become the coding scheme for data channels in enhanced mobile broadband scenarios. LDPC codes have significant advantages, such as low encoding / decoding complexity, strong error correction performance, and easy engineering implementation of encoders and decoders with high parallelism and high throughput. The LDPC codes in the 5G standard have two significant characteristics. First, in the parity check matrix of the 5G LDPC code, the row degree distribution is extremely irregular, and the row degree can vary from a minimum of 3 to a maximum of 19. In addition, in the codeword vector of the 5G LDPC code, the first 2Z bits are never sent, where Z is the boost value.

[0005] There are two decoding scheduling methods for LDPC code decoding. One method is flooding decoding scheduling. In flooding decoding scheduling, all check-to-variable (C2V) messages within the parity check matrix are updated simultaneously. Subsequently, all variable-to-check (V2C) messages are updated simultaneously using the updated C2V messages. An update of a C2V message and an update of its subsequent V2C message are called an iteration. Because the latest V2C message in flooding decoding scheduling can only be used to update the C2V message in the next iteration, flooding decoding scheduling has a slow convergence speed. To achieve good error correction performance, flooding decoding scheduling requires a large number of iterations. In addition, because all C2V messages and all V2C messages are updated simultaneously, hardware implementation of flooding decoding scheduling faces challenges such as high hardware resource consumption and wiring difficulties.

[0006] Another approach is layered decoding scheduling. In layered decoding scheduling, the parity check matrix is divided into several layers. The V2C message within each layer is first updated to the difference between the A-Posteriori Probability (APP) message from the previous layer and the C2V message left over from the previous iteration of this layer. The updated V2C message is then used to update the C2V message. Finally, the APP message is updated to the sum of the latest V2C message and C2V message of this layer. At this point, the decoding of the current layer is completed. The updated APP message is applied to the next layer for corresponding decoding. Traversing all layers of the parity check matrix from top to bottom is called an iteration. Since the latest APP message obtained by decoding each layer can be immediately applied to the next layer for decoding, the convergence speed of layered decoding scheduling is much faster than that of flooding decoding scheduling. Layered decoding scheduling can achieve better error correction performance with fewer decoding times. In addition, since layered decoding scheduling does not simultaneously update the various node messages within the entire check matrix, but only updates the messages of one layer of the check matrix within a certain period of time, the hardware implementation of layered decoding scheduling is more friendly, and the hardware resources it consumes will be greatly reduced compared to flooding decoding scheduling. Summary of the Invention

[0007] Purpose of the Invention: This invention addresses the poor decoding performance and slow convergence of existing solutions. Existing solutions fail to account for the extremely uneven redistribution of punctured bits and parity check matrix rows in 5G LDPC codes, which leads to poor decoding performance and slow convergence. This invention, however, takes these characteristics of 5G LDPC codes into account and optimizes the layer update order in layered decoding, resulting in better decoding performance and faster convergence.

[0008] The present invention provides a 5G LDPC code decoding method, comprising the following steps:

[0009] Step 1: Determine the parameters M, N, and Z of the 5G LDPC code parity check matrix according to the 5G standard based on the transmitted information bit length and transmission code rate. M and N represent the number of rows and columns in the parity check matrix, respectively, and Z is the boost value of the 5G LDPC code used.

[0010] Step 2, divide the check matrix into blocks using the lifting value Z;

[0011] Step 3: Count the row-level degrees, the first two column adjacencies, and the second-order row-level degrees of all row levels;

[0012] Step 4, determine the optimized layer update order;

[0013] Step 5, initialize the number of iterations i to 0;

[0014] Step 6: Perform an iterative decoding using the optimized layer update order;

[0015] Step 7, update i to i+1;

[0016] Step 8: Determine whether the codeword satisfies Hc T =0, where H is the check matrix, c is the codeword vector obtained by decoding, and T represents the matrix transpose. If yes, end decoding; otherwise, determine whether i is equal to the maximum number of iterations. If yes, end decoding; otherwise, return to step 6.

[0017] In step 2, in the check matrix, every Z rows from top to bottom constitute a row layer, and every Z columns from left to right constitute a column layer.

[0018] Step 3 includes:

[0019] Step 3-1: The submatrix at row level i and column level j is indexed by the ordered number pair (i, j). If the submatrix (i, j) is a non-zero matrix, then the row level i and column level j are said to be adjacent; if the submatrix (i, j) is an all-zero matrix, then the row level i and column level j are said to be non-adjacent.

[0020] The number of non-zero submatrices in row layer i is called the row layer degree of row layer i, denoted by R i ;

[0021] In the first two column layers, i.e., column layer 0 and column layer 1, the number of column layers adjacent to row layer i is called the first two column adjacency number of row layer i, denoted by P i ;

[0022] The sum of the row-level degrees of all row-levels adjacent to column-level j is called the cumulative row-level degree of column-level j, denoted by Si ;

[0023] The sum of the accumulated row-level degrees of all column levels adjacent to row-level i is called the second-order row-level degree of row-level i, denoted by T i ;

[0024] Step 3-2: Layer the parity check matrix of any 5G LDPC code in the manner described in step 3-1, and calculate the row-level degree, the first two column adjacency number, and the second-order row-level degree of each row level.

[0025] In step 4, the optimized layer update order is determined by the following method: among all row layers, the row layer with the smallest row layer degree is updated first; among row layers with the same row layer degree, the row layer with the smallest number of first two column adjacencies is updated first; among row layers with the same number of first two column adjacencies, the row layer with the smallest second-order row layer degree is updated first; among row layers with the same second-order row layer degree, the row layer with the smallest index value is updated first.

[0026] The present invention also provides a 5G LDPC code decoding device, wherein the decoding device records the optimized layer update sequence described in step 4;

[0027] The decoding device includes a memory module, a calculation module and a control module;

[0028] The memory module stores the A-Posterior Probability (APP) message, the Variable-to-Check (V2C) message, and the Check-to-Variable (C2V) message required for decoding;

[0029] The computing module is used to update the message stored in the memory module;

[0030] The control module is used to control the order of layer updates.

[0031] The optimized layer update sequence described in step 4 is recorded in the control module.

[0032] The control module controls the decoding device to read the message required by the updated layer from the memory module in each iteration according to the recorded optimized layer update sequence, and the calculation module performs message update.

[0033] The decoding device uses the optimized layer update order to perform message update on each row layer in each iteration.

[0034] Assume that the check matrix of the LDPC code has K row layers after block division, and the row layer indexes are recorded as 0, 1, ..., K-1 in sequence. After the K row layers adopt the optimized layer update sequence described in step 4, the update order is L0, L1, ..., L K-1 , where L i Indicates the index value of the i-th updated layer in an iteration, 0≤L i ≤K-1, 0≤i≤K-1;

[0035] In one iteration, the control module obtains the row layer index value L that needs to be updated in the order of i=0, 1, 2, ..., K-1 i , according to L i The control module controls the memory module to output the L i The information required for updating the row layer is collected, and the calculation module performs corresponding message updates.

[0036] Beneficial effects: The existing flooding decoding scheduling does not perform layered decoding on the LDPC code check matrix, and all variable nodes and check nodes in the check matrix are updated simultaneously in one iteration. The flooding decoding scheduling has slow convergence speed, poor error correction performance, and high hardware implementation resource consumption. In addition, the existing flooding decoding scheduling is not optimized for the extremely irregular degree distribution and the presence of punctured bits of 5G LDPC codes. This scheme adopts layered decoding scheduling, and only updates one layer of the check matrix at a certain moment in one iteration. This scheme has faster convergence speed, better error correction performance, and less hardware implementation resource consumption than the existing flooding decoding scheduling. In addition, this scheme also optimizes the layered update order to address the extremely irregular degree distribution and the presence of punctured bits of 5G LDPC codes, further improving the convergence speed of the layered decoding scheduling and enhancing its error correction performance without adding any additional computational complexity.

[0037] The existing layered decoding scheduling uses a natural order (i.e., from top to bottom, from the first layer to the last layer) to update messages on each layer of the check matrix in one iteration. The existing layered decoding scheduling does not optimize the extremely irregular degree distribution and the presence of punctured bits of 5G LDPC codes. Without optimizing the layer update order for the above characteristics of 5G LDPC codes, directly using the existing layered decoding scheduling for decoding 5G LDPC codes limits the further improvement of the convergence speed and error correction performance of the layered decoding scheduling. This scheme, based on the above characteristics of 5G LDPC codes, optimizes the layer update order in the layered decoding scheduling and adopts a special layer update order that is different from the natural order. Compared with the existing layered decoding scheduling scheme, this scheme significantly improves the convergence speed and error correction performance of decoding, but this scheme does not increase any computational complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more apparent.

[0039] Figure 1 It is a schematic diagram of check matrix partitioning.

[0040] Figure 2 It is a schematic diagram of check matrix partitioning.

[0041] Figure 3 This is a flowchart of 5G LDPC code decoding using an optimized layer update order.

[0042] Figure 4 This is a diagram of an LDPC code decoding device.

[0043] Figure 5 This is a schematic diagram of the error correction performance of 5G LDPC code with an information bit length of 3840 and a code rate of 1 / 5.

[0044] Figure 6 This is a schematic diagram of the average number of iterations of a 5G LDPC code with an information bit length of 3840 and a code rate of 1 / 5.

[0045] Figure 7 This is a schematic diagram of the error correction performance of 5G LDPC code with an information bit length of 3840 and a code rate of 1 / 4.

[0046] Figure 8 This is a diagram showing the average number of iterations of a 5G LDPC code with an information bit length of 3840 and a code rate of 1 / 4. DETAILED DESCRIPTION

[0047] The present invention provides a 5G LDPC code decoding method, wherein the dimension of the parity check matrix of the 5G LDPC code used is M×N, that is, the parity check matrix has M rows and N columns. Assume that the lifting value of the 5G LDPC code used is Z.

[0048] First, the check matrix is partitioned. In the check matrix, every Z rows from top to bottom constitute a row layer, and every Z columns from left to right constitute a column layer. If M and N are both integer multiples of Z, the check matrix can be partitioned into several complete row layers and several complete column layers. Figure 1 A schematic example is shown. The check matrix in the figure can be divided into several complete row layers and several complete column layers. The row layer index (Row Layer Index) and the column layer index (Column Layer Index) both start from 0. Figure 1As shown in the figure, the check matrix is divided into several Z×Z submatrices. The shaded submatrix is a non-zero matrix, and the blank submatrix is an all-zero matrix. If M or N is not an integer multiple of Z, the check matrix will contain an incomplete row layer or an incomplete column layer in addition to the complete row layers and column layers. Figure 2 A schematic example is shown. In the figure, the check matrix is divided into several complete row layers and several complete column layers, and there is also an incomplete row layer and an incomplete column layer. The row layer index (Row Layer Index) and the column layer index (Column Layer Index) both start from 0. Figure 2 As shown, the check matrix is divided into several Z×Z sub-matrices and several sub-matrices with dimensions less than Z×Z. Here, the sub-matrix dimension less than Z×Z means that any dimension of the sub-matrix is less than Z. The sub-matrix represented by the shaded part in the figure is a non-zero matrix, and the sub-matrix represented by the blank part is an all-zero matrix. It should be noted that all the row layers mentioned in the present invention do not distinguish whether they are complete row layers or incomplete row layers. All the column layers mentioned in the present invention do not distinguish whether they are complete column layers or incomplete column layers. All the sub-matrices mentioned in the present invention do not distinguish whether their dimensions are exactly Z×Z or less than Z×Z.

[0049] The submatrix at row level i and column level j is indexed by the ordered number pair (i, j). If the submatrix (i, j) is a non-zero matrix, then the row level i and column level j are said to be "adjacent". If the submatrix (i, j) is an all-zero matrix, then the row level i and column level j are said to be "non-adjacent". The number of non-zero submatrices in row level i is called the "row level degree" of row level i, denoted by R i In the first two column layers, i.e. column layer 0 and column layer 1, the number of column layers adjacent to row layer i is called the “first two column adjacency number” of row layer i, denoted by P i The sum of the row-level degrees of all the row-levels adjacent to column-level j is called the "cumulative row-level degree" of column-level j, denoted by Si. The sum of the cumulative row-level degrees of all the column-levels adjacent to row-level i is called the "second-order row-level degree" of row-level i, denoted by T. i .

[0050] In the manner described above, the check matrix of any 5G LDPC code can be layered, and the row-level degree, the first two-column adjacency number, and the second-order row-level degree of each row level can be calculated.

[0051] In this solution, the following rules are used to determine the update order of the row layers in each iteration: among all row layers, the row layer with the lowest row layer degree is updated first; among row layers with the same row layer degree, the row layer with the smallest number of first two column adjacencies is updated first; among row layers with the same number of first two column adjacencies, the row layer with the smallest second-order row layer degree is updated first; among row layers with the same second-order row layer degree, the row layer with the smallest index value is updated first. The row layer update order determined by the above rules is subsequently referred to as the optimized layer update order.

[0052] The 5G LDPC decoding method implemented in this solution uses the above-mentioned optimized layer update order to perform layered decoding scheduling. The flowchart of the 5G LDP4 decoding method implemented in this solution is as follows: Figure 3 shown.

[0053] exist Figure 3 In the code, M and N represent the number of rows and columns of the 5G LDPC code, Z represents the boost value, and T max Indicates the maximum number of iterations. Figure 3 The decoding process shown is compatible with any LDPC code in the 5G standard. Figure 3 In the decoding process shown, the specific decoding algorithm used in the iterative decoding can be any existing decoding algorithm, such as the Sum-Product (SP) decoding algorithm, the Minimum Sum (MS) decoding algorithm, the Normalized Minimum Sum (NMS) decoding algorithm, the Offset Minimum Sum (OMS) decoding algorithm, the Offset Normalized MS (ONMS) decoding algorithm, etc.

[0054] The 5G LDPC decoding method implemented in this solution uses the above-mentioned optimized layer update order for layered decoding scheduling. Compared with the decoding method using existing layered decoding scheduling, it has the advantages of faster convergence speed, better error correction performance, and no increase in computational complexity.

[0055] The 5G LDPC decoding device implemented in this solution is a decoding device that uses the above-mentioned optimized layer update order to perform layered decoding scheduling. Figure 4 shown.

[0056] like Figure 4The decoding device shown includes a memory module, a calculation module, and a control module. The memory module stores various messages required for decoding. The calculation module implements the update of various messages. The control module is used to control the order of layer updates. The control module records the order of row layer updates. Suppose that the LDPC code check matrix has K row layers after block division. The update order of these K row layers determined by the above optimization rules is L0, L1, ..., L K-1 , where 0≤L i ≤K-1, 0≤i≤K-1. In one iteration, the control module obtains the row layer index value L that needs to be updated in the order of i=0, 1, 2, ..., K-1 i , according to L i The control module controls the memory module to output the L i The information required for the row layer to be updated is updated by the calculation module, and the corresponding message is updated by the calculation module. The decoding algorithm implemented by the calculation module can be any existing decoding algorithm, such as SP decoding algorithm, MS decoding algorithm, NMS decoding algorithm, OMS decoding algorithm, ONMS decoding algorithm, etc.

[0057] Because the 5G LDPC decoding device implemented in this solution uses the optimized layer update order for layered decoding scheduling, it offers faster convergence, better error correction performance, and no additional computational complexity compared to existing decoding devices using layered decoding scheduling. Furthermore, because the 5G LDPC decoding device implemented in this solution converges more quickly and requires fewer iterations to complete decoding, it also offers higher throughput and greater energy efficiency.

[0058] Figure 5 、 Figure 6 、 Figure 7 and Figure 8 The simulation results for two 5G LDPC codes are presented. The simulation conditions are as follows: Quadrature Phase Shift Keying (QPSK) modulation is used, an Additive White Gaussian Noise (AWGN) channel is used, the maximum number of iterations is set to 10, and the simulation is terminated after 100 error frames are collected at each signal-to-noise ratio point. Error correction performance is demonstrated using the Bit Error Rate (BER) and Frame Error Rate (FER). Convergence speed is demonstrated using the Average Number of Iterations (ANI).

[0059] Figure 5The error correction performance curves of 5G LDPC codes with information bit length 3840 and code rate 1 / 5 using the existing layered decoding scheduling scheme and this scheme are shown. Figure 5 It can be seen that the error correction performance obtained by using this solution is much better than the existing solution. -3 When compared with the existing technology solution, this solution has a performance gain of 0.29dB. Figure 6 The corresponding average number of iterations is shown. Figure 6 It can be seen that the convergence speed obtained by using this scheme is much faster than that of the existing scheme. b When / N0=0.9dB, this solution can reduce the average number of iterations by 2.3 times compared with the prior art solution.

[0060] Figure 7 The error correction performance curves of the 5G LDPC code with information bit length 3840 and code rate 1 / 4 using the existing layered decoding scheduling scheme and this scheme are shown. Figure 7 It can be seen that the error correction performance obtained by using this solution is much better than the existing solution. -4 When compared with the existing technology solution, this solution has a performance gain of 0.26dB. Figure 8 The corresponding average number of iterations is shown. Figure 8 It can be seen that the convergence speed obtained by using this scheme is much faster than that of the existing scheme. b When / N0=1.0dB, this solution can reduce the average number of iterations by 2.2 times compared with the prior art solution.

[0061] This invention provides a 5G LDPC code decoding method and apparatus. There are numerous methods and approaches for implementing this technical solution. The foregoing description is merely a preferred embodiment of the invention. It should be noted that those skilled in the art may make improvements and modifications without departing from the principles of the invention, and such improvements and modifications are considered within the scope of protection of the invention. Any components not specified in this embodiment may be implemented using existing technologies.

Claims

1. A 5G LDPC code decoding method, characterized in that: The following steps are involved: Step 1: Determine the parameters M, N, and Z of the 5G LDPC parity check matrix according to the 5G standard based on the transmitted information bit length and transmission code rate, where M and N represent the number of rows and columns in the parity check matrix, respectively, and Z is the boost value of the 5G LDPC code used. Step 2, divide the check matrix into blocks using the lifting value Z; Step 3: Count the row-level degrees, the first two column adjacencies, and the second-order row-level degrees of all row levels; Step 4, determine the optimized layer update order; Step 5, initialize the number of iterations i to 0; Step 6: Perform an iterative decoding using the optimized layer update order; Step 7, update i to i+1; Step 8: Determine whether the codeword satisfies Hc T = 0, where H is the check matrix, c is the codeword vector obtained by decoding, and T represents the matrix transpose. If yes, end decoding. Otherwise, determine whether i is equal to the maximum number of iterations. If yes, end decoding. Otherwise, return to step 6. In step 2, in the check matrix, every Z rows from top to bottom constitute a row layer, and every Z columns from left to right constitute a column layer; Step 3 includes: Step 3-1: The submatrix at row level i and column level j is indexed by the ordered number pair (i, j). If the submatrix (i, j) is a non-zero matrix, then the row level i and column level j are said to be adjacent; if the submatrix (i, j) is an all-zero matrix, then the row level i and column level j are said to be non-adjacent. The number of non-zero submatrices in row layer i is called the row layer degree of row layer i, denoted by R i ; In the first two column layers, i.e., column layer 0 and column layer 1, the number of column layers adjacent to row layer i is called the first two column adjacency number of row layer i, denoted by P i ; The sum of the row-level degrees of all row-levels adjacent to column-level j is called the cumulative row-level degree of column-level j, denoted by S i ; The sum of the accumulated row-level degrees of all column levels adjacent to row-level i is called the second-order row-level degree of row-level i, denoted by T i ; Step 3-2: Layer the parity check matrix of any 5G LDPC code in the same manner as described in step 3-1, and calculate the row-level degree, the first two column adjacency number, and the second-order row-level degree of each row level. In step 4, the optimized layer update order is determined by the following method: among all row layers, the row layer with the smallest row layer degree is updated first; among row layers with the same row layer degree, the row layer with the smallest number of first two column adjacencies is updated first; among row layers with the same number of first two column adjacencies, the row layer with the smallest second-order row layer degree is updated first; among row layers with the same second-order row layer degree, the row layer with the smallest index value is updated first.

2. A 5G LDPC code decoding device implemented by the method according to claim 1, characterized in that: The decoding device records the optimized layer update sequence in step 4; The decoding device includes a memory module, a calculation module and a control module; The memory module stores the posterior probability message, the variable node to check node message, and the check node to variable node message required for decoding; The computing module is used to update the message stored in the memory module; The control module is used to control the order of layer updates.

3. The device according to claim 2, characterized in that The optimized layer update sequence described in step 4 is recorded in the control module.

4. The device according to claim 3, characterized in that The control module controls the decoding device to read the message required by the updated layer from the memory module in each iteration according to the recorded optimized layer update sequence, and the calculation module performs message update.

5. The device according to claim 4, characterized in that The decoding device uses the optimized layer update order to perform message update on each row layer in each iteration.

6. The device according to claim 5, characterized in that Assume that the check matrix of the LDPC code has K row layers after block division, and the row layer indexes are recorded as 0, 1, ..., K-1 in sequence. After the K row layers adopt the optimized layer update sequence described in step 4, the update order is L0, L1, ..., L K-1 , where L i Indicates the index value of the i-th updated layer in one iteration, 0≤L i ≤K-1,0≤i≤K-1; In one iteration, the control module obtains the row layer index value L that needs to be updated in the order of i=0,1,2,…,K-1 i , according to L i The control module controls the memory module to output the L i The information required for updating the row layer is collected, and the calculation module performs corresponding message updates.