Readout Circuit, Column Output Circuit, and Image Sensor of an Image Sensor

Abstract

The present invention provides a readout circuit, a column output circuit and an image sensor for an image sensor. The readout circuit includes a first switch, a second switch, a third switch, a comparison circuit, a pulse signal acquisition circuit, an inversion circuit, a selection output circuit and a counter. In the standby mode, the second switch and the third switch are turned on, and the pixel unit alternately resets and integrates according to the received second pulse signal. At this time, the signal source circuit does not participate in the operation and can be triggered to turn off, reducing power consumption. At the same time, the control circuit determines whether to trigger the working mode according to the change frequency of the digital code value in the standby state, and when triggering the working mode, the first switch is triggered to turn on, and the counter counts according to the first pulse signal output by the comparison circuit and outputs the corresponding digital code value to the control circuit to determine the current picture brightness information, and to make a judgment on the re-switching between the standby mode and the working mode again.

Description

Technical Field

[0001] The present invention belongs to the technical field of image sensors, and particularly relates to a readout circuit, a column output circuit, and an image sensor of an image sensor. Background Art

[0002] Image sensors are widely configured for many fields such as consumer electronics, security monitoring, automatic control, medical treatment, and national defense. Especially in recent years, with the rise of intelligent terminals, more attention has been paid to the demand for low power consumption.

[0003] An image sensor includes a pixel array, a row selection circuit, a column output circuit, a control circuit, etc. The pixel array consists of pixel units arranged in an array. The column output circuit includes a plurality of readout circuits. Each pixel unit is connected to a readout circuit to realize the conversion output of an image signal to a digital code value, so that the control circuit determines the current picture information according to each digital code value.

[0004] Among them, in an image sensor mobile device, there is a need to monitor events and trigger the internal chip to power on and work. This working mode can also be called the always on state, that is, the standby state.

[0005] For example, in a visual doorbell, in most cases, the picture is a static picture. At this time, the image sensor needs to operate with low power consumption in the always on state. When someone appears in the picture, the image sensor outputs a video with a normal frame rate.

[0006] However, in a traditional image sensor, the clock port of a counter is directly connected to a phase-locked loop. The phase-locked loop is in a working state both in the working state and in the standby state, resulting in a large standby power consumption of the image sensor and affecting the usage time of the device. Summary of the Invention

[0007] An object of the present invention is to provide a readout circuit of an image sensor, aiming to solve the problem of large power consumption in the standby state of a traditional image sensor.

[0008] A first aspect of an embodiment of the present invention provides a readout circuit of an image sensor, including:

[0009] A first switch whose first end is connected to the output end of a pixel unit, and is triggered to conduct by a read control signal;

[0010] A comparison circuit connected to the second end of the first switch and a signal source circuit, configured to compare the pixel signal output by the pixel unit with the ramp voltage output by the signal source circuit, and output a first pulse signal;

[0011] A second switch whose first end is connected to the output end of the pixel unit, and is triggered to conduct by a low power consumption control signal;

[0012] A pulse signal acquisition circuit connected to the second end of the second switch, configured to convert the pixel signal output by the pixel unit into a second pulse signal;

[0013] A third switch connected between the output end of the pulse signal acquisition circuit and the controlled end of the reset transistor in the pixel unit is triggered to conduct by the low-power control signal, so that the pixel unit receives the second pulse signal and triggers alternate reset and integration;

[0014] An inverter circuit connected to the output end of the pulse signal acquisition circuit, configured to invert the second pulse signal and output a third pulse signal with a phase opposite to that of the second pulse signal;

[0015] A selection output circuit connected to the output end of the inverter circuit and the signal source circuit respectively, configured to be triggered by the readout control signal to output the clock signal of the signal source circuit, and triggered by the low-power control signal to output the third pulse signal;

[0016] A counter connected to the output end of the comparison circuit and the output end of the selection output circuit, configured to count the number of clock pulses according to the received signal and output the corresponding digital code value to the control circuit, so that the control circuit determines the current picture brightness information according to the digital code value, and triggers the output of the readout control signal or the low-power control signal.

[0017] Optionally, the pulse signal acquisition circuit includes a first inverter and a pulse shaping circuit connected to each other. The first inverter is configured to receive the pixel signal output by the pixel unit and output a pulse signal, and the pulse shaping circuit is configured to perform waveform shaping based on the pulse signal output by the first inverter to output the second pulse signal.

[0018] Optionally, the pulse shaping circuit includes 2n cascaded second inverters, where n≥1.

[0019] Optionally, n = 1.

[0020] Optionally, the inverter circuit includes a third inverter. The input end of the third inverter is connected to the output end of the pulse signal acquisition circuit, and the output end of the third inverter is connected to the signal input end of the selection output circuit to output the third pulse signal.

[0021] Optionally, the selection output circuit includes a two-to-one data selector;

[0022] The first signal input terminal of the one - of - two data selector is connected to the output terminal of the inverter circuit. The second signal input terminal of the one - of - two data selector is connected to the clock signal terminal of the signal source circuit. The signal output terminal of the one - of - two data selector is connected to the clock signal terminal of the counter. The control terminal of the one - of - two data selector is configured to input the read - out control signal or the low - power control signal, and trigger the selection and output of the third pulse signal or the clock signal of the signal source circuit to the counter.

[0023] Optionally, the comparison circuit includes:

[0024] A first capacitor whose first terminal is connected to the power supply terminal of the signal source circuit;

[0025] A second capacitor whose first terminal is connected to the second terminal of the first switch;

[0026] A comparator, the non - inverting input terminal of the comparator is connected to the second terminal of the first capacitor, the inverting input terminal of the comparator is connected to the second terminal of the second capacitor, and the output terminal of the comparator forms the output terminal of the comparison circuit.

[0027] A second aspect of the embodiments of the present invention provides a column output circuit of an image sensor, including a signal source circuit and a plurality of read - out circuits of the image sensor as described above;

[0028] The signal source circuit is respectively connected to the read - out circuits of a plurality of the image sensors, and each read - out circuit of the image sensor is correspondingly connected to a pixel unit;

[0029] Wherein, the signal source circuit includes:

[0030] A reference power supply circuit configured to output a reference power supply;

[0031] A ramp voltage circuit configured to convert the reference power supply into a ramp voltage;

[0032] A phase - locked loop circuit configured to convert an external clock signal into a plurality of internal clock signals and output them to the read - out circuit of the image sensor, the ramp voltage circuit and the control circuit respectively.

[0033] A third aspect of the embodiments of the present invention provides an image sensor, including a pixel array, a control circuit and a column output circuit of the image sensor as described above, and the pixel array includes a plurality of pixel units arranged in an array;

[0034] The column output circuit of the image sensor and the control circuit are correspondingly connected to the pixel units, and the column output circuit of the image sensor is also connected to the control circuit;

[0035] The image sensor includes a normal operating mode and a wake-up pending mode. In the normal operating mode, the control circuit outputs a read control signal, such that the counter receives a first pulse signal and a clock signal output by the phase-locked loop circuit, and outputs a corresponding digital code value; in the wake-up pending mode, the control circuit outputs a low-power control signal, such that the counter receives a third pulse signal and outputs a corresponding digital code value.

[0036] Optionally, in the normal operating mode, the resolution of the counter is m bit, where m≥8; in the wake-up pending mode, the resolution of the counter is 2 bit.

[0037] In the readout circuit corresponding to each pixel unit according to an embodiment of the present invention, a first switch, a second switch, a third switch, a comparison circuit, a pulse signal acquisition circuit, an inversion circuit, a selection output circuit, and a counter are provided. In the wake-up pending mode, the second switch and the third switch are turned on, and the pixel unit alternately resets and integrates according to the received second pulse signal. At this time, the signal source circuit does not participate in the operation and can be triggered to turn off, reducing power consumption. At the same time, the control circuit determines whether to trigger the operating mode according to the change frequency of the digital code value in the wake-up pending state, and when triggering the operating mode, the first switch is triggered to turn on, and the counter counts according to the first pulse signal output by the comparison circuit and outputs a corresponding digital code value to the control circuit to determine the current picture brightness information, and triggers the output of the read control signal or the low-power control signal again to perform the re-switching judgment between the wake-up pending mode and the operating mode. Description of the Drawings

[0038] Figure 1 It is a first schematic structural diagram of a readout circuit of an image sensor provided by an embodiment of the present invention;

[0039] Figure 2 is Figure 1 a waveform schematic diagram of input and output signals of a comparison circuit of a readout circuit of an image sensor in an embodiment;

[0040] Figure 3 It is a waveform schematic diagram of a control signal of a pixel unit provided by an embodiment of the present invention;

[0041] Figure 4 It is a second schematic structural diagram of a readout circuit of an image sensor provided by an embodiment of the present invention;

[0042] Figure 5 It is a third schematic structural diagram of a readout circuit of an image sensor provided by an embodiment of the present invention;

[0043] Figure 6 It is a schematic structural diagram of a column output circuit of an image sensor provided by an embodiment of the present invention;

[0044] Figure 7 It is a schematic structural diagram of the image sensor provided by the embodiment of the present invention. Specific embodiments

[0045] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not configured to limit the present invention.

[0046] In addition, the terms "first" and "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0047] Embodiment 1:

[0048] In the first aspect of the embodiment of the present invention, a readout circuit 2 of an image sensor is proposed. The readout circuit 2 is connected to the output end of the pixel unit 1. Among them, the pixel unit 1 generally includes a photoelectric conversion element, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor ROWSEL. Among them, the photoelectric conversion element includes, but is not limited to, a photodiode PD, such as a Pin-type photodiode PD. At the same time, the number of the photoelectric conversion element, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor ROWSEL can be one or more, that is, the structure of the pixel unit 1 can be selected correspondingly, and the specific structure is not limited. For example Figure 1 As shown, taking the basic pixel unit 1 as an example, the pixel unit 1 includes a photodiode PD, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, a row selection transistor ROWSEL, and a storage capacitor CX. Among them, the cathode of the photodiode PD is connected to the first end of the transfer transistor TX, and the second end of the transfer transistor TX, the first end of the reset transistor RST, the first end of the storage capacitor CX, and the controlled end of the source follower transistor SF are all coupled to the floating diffusion node. The anode of the photodiode PD and the second end of the storage capacitor CX are grounded. The second end of the reset transistor RST and the first end of the source follower transistor SF are both connected to the positive power supply terminal VDD. The second end of the source follower transistor SF is connected to the first end of the row selection transistor ROWSEL. The second end of the row selection transistor ROWSEL constitutes the output end of the pixel unit 1 and is used to output the corresponding pixel signal PIXEL.

[0049] Among them, corresponding to the pixel unit 1 of the corresponding structure, the readout circuit 2 includes:

[0050] A first switch SW1 whose first end is connected to the output end of the pixel unit 1, and is triggered to conduct by a readout control signal. Among them, the first switch SW1 is directly or indirectly connected to the control circuit 4. In the normal operating mode, the control circuit 4 outputs a readout control signal. In the wake-up waiting mode, the control circuit 4 outputs a low-power control signal. The first switch SW1 can adopt a switch circuit or component with a controlled on-off function, such as a relay, a switching tube, etc.

[0051] A comparison circuit 10 connected to the second end of the first switch SW1 and the signal source circuit 3, configured to compare the pixel signal PIXEL output by the pixel unit 1 and the ramp voltage RAMP output by the signal source circuit 3, and output a first pulse signal PULSE1. Among them, as Figure 2 shown, the ramp voltage RAMP and the pixel signal PIXEL change periodically. After the two are compared, a periodically changing first pulse signal PULSE1 is output. The comparison circuit 10 can adopt a comparator U4 and corresponding peripheral auxiliary circuits, and the specific structure is not limited.

[0052] A second switch SW2 whose first end is connected to the output end of the pixel unit 1, and is triggered to conduct by a low-power control signal. The second switch SW2 is controlled to conduct in the wake-up waiting mode, and is controlled to turn off in the normal operating mode. Among them, the controlled ends of the first switch SW1 and the second switch SW2 can be respectively connected to the control circuit 4, or commonly connected to the same signal end of the control circuit 4, and two switch devices or switch circuits with opposite on-off characteristics are adopted. The connection method and type of the controlled ends of the two switches are not limited, and the two switches conduct respectively when receiving the readout control signal and the low-power control signal.

[0053] A pulse signal acquisition circuit 20 connected to the second end of the second switch SW2, configured to convert the pixel signal PIXEL output by the pixel unit 1 into a second pulse signal. The pulse signal acquisition circuit 20 is used to acquire the pixel signal PIXEL in the wake-up waiting mode, and at the same time, perform corresponding signal processing and conversion, such as inversion, shaping, etc. According to the signal processing method, the pulse signal acquisition circuit 20 can adopt a corresponding circuit structure, such as an inverter, a shaping circuit, etc., and the specific structure is not limited.

[0054] The third switch SW3 connected between the output terminal of the pulse signal acquisition circuit 20 and the controlled terminal of the reset transistor RST in the pixel unit 1 is triggered to conduct by a low-power control signal, so that the pixel unit 1 receives the second pulse signal and triggers alternate reset and integration. Among them, the third switch SW3 is synchronously turned on and off with the second switch SW2, and their controlled terminals can be commonly connected to the same signal terminal of the control circuit 4. The third switch SW3 realizes the transfer and output of the second pulse signal. The second pulse signal presents an alternately high and low level state at intervals. After being input to the reset transistor RST, it controls the reset transistor RST to be alternately turned on and off, thereby realizing the alternate reset and integration of the pixel unit 1.

[0055] The inverting circuit 30 connected to the output terminal of the pulse signal acquisition circuit 20 is configured to invert the second pulse signal and output a third pulse signal with a phase opposite to that of the second pulse signal. The inverting circuit 30 realizes the inverting conversion, thereby obtaining a pulse signal corresponding to the same potential change of the pixel unit 1, ensuring the counting accuracy of the backend counter 50 and the accuracy of the mode switching of the control circuit 4.

[0056] The selection output circuit 40 connected to the output terminal of the inverting circuit 30 and the signal source circuit 3 respectively is configured to be triggered by a readout control signal to output the clock signal of the signal source circuit 3, and to be triggered by a low-power control signal to output the third pulse signal. Among them, the clock signal of the signal source circuit 3 corresponds to the normal working mode, and the third pulse signal corresponds to the to-be-awakened mode. The pulse frequency of the clock signal is fixed, and the pulse frequency of the third pulse signal changes according to the current brightness information. The selection output circuit 40 can adopt a multi-switch structure, a selector, etc., and the specific structure is not limited.

[0057] The counter 50 connected to the output terminal of the comparison circuit 10 and the output terminal of the selection output circuit 40 is configured to count the number of clock pulses according to the received signal and output the corresponding digital code value to the control circuit 4, so that the control circuit 4 determines the current picture brightness information according to the digital code value, and triggers the output of a readout control signal or a low-power control signal. The counter 50 is in a working state both in the normal working mode and in the to-be-awakened mode, counts according to the received first pulse signal PULSE1 or the third pulse signal, and converts and outputs the corresponding digital code value to the control circuit 4, so that the control circuit 4 switches correspondingly in the normal working mode and the to-be-awakened mode according to the digital code value.

[0058] When the readout circuit 2 works specifically, for example, when initially working in the normal working mode, the first switch SW1 is controlled to conduct after receiving the readout control signal, referring to Figure 3, the photodiode PD obtains an optical signal through continuous exposure or intermittent exposure, converts it into a current signal, the transmission transistor TX is controlled to conduct, the electrical signal is stored in the storage capacitor CX to form a pixel signal PIXEL, the pixel signal PIXEL is output through the source follower transistor SF, and is output when the row selection transistor ROWSEL conducts. The pixel signal PIXEL is input to the comparison circuit 10, and is compared with the ramp voltage RAMP in the comparison circuit 10, and a first pulse signal PULSE1 is output to the counter 50. The first pulse signal PULSE1 has the same potential change as the pixel signal PIXEL. At the same time, the second switch SW2 and the third switch SW3 remain in the off state. At the same time, the selection output circuit 40 triggers the corresponding transmission channel according to the received read control signal, and transmits the input clock signal to the counter 50. The counter 50 counts the first pulse signal PULSE1 within the cycle time of the comparison completion according to the clock signal, and outputs a first digital code value to the control circuit 4, and stops counting after the output level of the comparison circuit 10 flips, and outputs m-bit data, where m is the number of bits of the counter 50.

[0059] In this operating mode, the signal source circuit 3 needs to be in operation, that is, output the corresponding ramp voltage RAMP, clock signal to the readout circuit 2 and the control circuit 4. The digital code value corresponds to the current picture brightness information. The control circuit 4 determines the current picture brightness information according to the received digital code value, and converts and outputs it to the display module of the image sensor for normal frame rate video display work, and detects whether a brightness change detection event occurs. For example, if a dynamic picture is continuously detected and the brightness changes, the control circuit 4 maintains the normal operating mode according to the current digital code value. When a static picture is detected for a long time, the control circuit 4 switches to the wake-up waiting mode according to the current digital code value to reduce the power consumption of the image sensor.

[0060] When switching to the wake-up waiting mode, refer to Figure 3, the second switch SW2 and the third switch SW3 are turned on, and the first switch SW1 is turned off. Before the row selection transistor ROWSEL is turned on, the transfer transistor TX and the reset transistor RST are turned on to continuously reset the pixel unit 1. After the reset transistor RST is turned off, the row selection transistor ROWSEL is turned on. At this time, the photocurrent output by the photodiode PD is integrated on the storage capacitor CX, and the floating diffusion node voltage slowly decreases. When it drops to the preset threshold voltage, the second pulse signal is a first-level signal and is fed back to the reset transistor RST. The reset transistor RST is turned on to reset the pixel unit 1. After the reset, the pulse signal acquisition circuit 20 outputs a second-level signal that is inverted with respect to the first-level signal. At this time, the reset stops, and the second pulse signal alternates between the first level and the second level, thereby controlling the pixel unit 1 to repeat the integration and reset processes. At the same time, the second pulse signal is inverted by the inversion circuit 30 to output a third pulse signal. The selection output circuit 40 transmits the input third pulse signal to the counter 50. The counter 50 counts the third pulse signal according to the clock signal and outputs a second digital code value to the control circuit 4. The control circuit 4 determines whether to wake up to the normal working mode or maintain the standby wake-up mode according to the brightness information corresponding to the second digital code value.

[0061] In the standby wake-up mode, the counter 50 does not need to input a clock signal. At the same time, the comparison circuit 10 does not work, that is, there is no need to input a ramp voltage RAMP. Therefore, the signal source circuit 3 can be controlled to turn off and maintain the stopped working state to reduce the power consumption in the standby wake-up mode and be controlled to turn on when waking up to the normal working mode.

[0062] Embodiment 2

[0063] As Figure 4 shown, in an example, the pulse signal acquisition circuit 20 includes a first inverter U1 and a pulse shaping circuit 21 connected to each other. The first inverter U1 is configured to receive the pixel signal PIXEL output by the pixel unit 1 and output a pulse signal. The pulse shaping circuit 21 is configured to perform waveform shaping based on the pulse signal output by the first inverter U1 to output a second pulse signal.

[0064] In this embodiment, the first inverter U1 realizes the inverting amplification of the pixel signal PIXEL. Since the voltage of the pixel signal PIXEL is not a fixed value and fluctuates within a small range, the PMOS transistor and the NMOS transistor inside the first inverter U1 work in the saturation region, and the rising and falling edges of the output waveform are slow. Therefore, in order to avoid abnormal reset of the reset transistor RST, a pulse shaping circuit 21 is also provided to make the rising and falling edges of the pulse signal output by the first inverter U1 neat, ensuring the reliable turn-off and turn-on of the reset transistor RST, thereby realizing the alternating control of the reset and integration of the pixel unit 1.

[0065] Among them, the pulse shaping circuit 21 can adopt common Schmitt triggers, limiters, etc. For example, Figure 5 As shown, in order to simplify the circuit structure, in one example, the pulse shaping circuit 21 includes 2n cascaded second inverters U2, where n≥1. Through the cascaded inverter structure, the shaping of the pulse signal is realized. Among them, in order to ensure that the potential change of the pulse signal input and output by the pulse shaping circuit 21 is the same, the number of the second inverters U2 is even. Further, in order to further simplify the structure of the readout circuit 2, in one example, n = 1, that is, the second inverter U2 includes two.

[0066] And in order to ensure that the phase of the pixel signal PIXEL is the same as that of the third pulse signal and to achieve the purpose of simplifying the circuit structure, in one example, the inverting circuit 30 includes a third inverter U3. The input end of the third inverter U3 is connected to the output end of the pulse signal acquisition circuit 20, and the output end of the third inverter U3 is connected to the signal input end of the selection output circuit 40 to output the third pulse signal.

[0067] In one example, the selection output circuit 40 includes a two-to-one data selector U4;

[0068] The first signal input end of the two-to-one data selector U4 is connected to the output end of the inverting circuit 30, the second signal input end of the two-to-one data selector U4 is connected to the clock signal end of the signal source circuit 3, the signal output end of the two-to-one data selector U4 is connected to the clock signal end of the counter 50, and the controlled end of the two-to-one data selector U4 is configured to input a readout control signal or a low-power control signal, and trigger the selection to output the third pulse signal or the clock signal of the signal source circuit 3 to the counter 50.

[0069] Optionally, the comparison circuit 10 includes:

[0070] A first capacitor C1 whose first end is connected to the power supply end of the signal source circuit 3;

[0071] A second capacitor C2 whose first end is connected to the second end of the first switch SW1;

[0072] A comparator U4, the positive-phase input end of the comparator U4 is connected to the second end of the first capacitor C1, the negative-phase input end of the comparator U4 is connected to the second end of the second capacitor C2, and the output end of the comparator U4 constitutes the output end of the comparison circuit 10.

[0073] Referring to the above circuit structure for specific description, when the readout circuit 2 works specifically, such as initially working in the normal working mode, the first switch SW1 is controlled to conduct. Refer to Figure 3, the photodiode PD obtains an optical signal through continuous exposure or intermittent exposure, converts it into a current signal, the transmission transistor TX is controlled to conduct, the electrical signal is stored in the storage capacitor CX to form a pixel signal PIXEL, the pixel signal PIXEL is output through the source follower transistor SF, and is output when the row selection transistor ROWSEL conducts. The pixel signal PIXEL and the ramp voltage RAMP are coupled and input to the comparator U4 through the first capacitor C1 and the second capacitor C2 for voltage comparison, and a first pulse signal PULSE1 is output to the counter 50. The first pulse signal PULSE1 has the same potential change as the pixel signal PIXEL. At this time, the control circuit 4 outputs a read control signal, the second switch SW2 and the third switch SW3 remain off. At the same time, the two-way data selector U4 transmits the input clock signal to the counter 50. The counter 50 counts the first pulse signal PULSE1 within the cycle time after the comparison is completed according to the clock signal and outputs a first digital code value to the control circuit 4, and stops counting after the output level of the comparator U4 flips, and outputs m-bit data, where m is the number of bits of the counter 50.

[0074] In this operating mode, the signal source circuit 3 needs to be in operation, that is, output the corresponding ramp voltage RAMP, clock signal to the readout circuit 2 and the control circuit 4. The digital code value corresponds to the current picture brightness information. The control circuit 4 determines the current picture brightness information according to the received digital code value, and converts and outputs it to the display module of the image sensor for normal frame rate video display work, and detects whether a brightness change detection event occurs. If a dynamic picture is continuously detected and causes a brightness change, the control circuit 4 maintains the normal operating mode according to the current digital code value. When a long-term static picture is detected, the control circuit 4 switches to the standby wake-up mode according to the current digital code value to reduce the power consumption of the image sensor.

[0075] When switching to the standby wake-up mode, refer to Figure 3, the second switch SW2 and the third switch SW3 are turned on, and the first switch SW1 is turned off. Before the row selection transistor ROWSEL is turned on, the transfer transistor TX and the reset transistor RST are turned on to continuously reset the pixel unit 1. After the reset transistor RST is turned off, the row selection transistor ROWSEL is turned on. At this time, the photocurrent output by the photodiode PD is integrated on the storage capacitor CX, and the voltage of the floating diffusion node slowly decreases. When it drops to the preset threshold voltage, the second pulse signal is a first-level signal and is fed back to the reset transistor RST. The reset transistor RST is turned on to reset the pixel unit 1. After the reset, the second output of the second inverter U2 is a second-level signal that is the inverse of the first-level signal. At this time, the reset stops, and the second pulse signal alternates between the first-level signal and the second-level signal, thereby controlling the pixel unit 1 to repeat the integration and reset process. At the same time, the second pulse signal is inverted by the third inverter U3 to output a third pulse signal. The multiplexer U4 transmits the input third clock signal to the counter 50. The counter 50 counts the third pulse signal according to the clock signal and outputs a second digital code value to the control circuit 4. The control circuit 4 determines whether to wake up to the normal working mode or maintain the standby wake-up mode according to the brightness information corresponding to the second digital code value.

[0076] In the standby wake-up mode, the counter 50 does not need to input a clock signal. At the same time, the comparator U4 does not work, that is, it does not need to input a ramp voltage RAMP. Therefore, the signal source circuit 3 can be controlled to turn off and maintain the stopped working state to reduce the power consumption in the standby wake-up mode and be controlled to turn on when waking up to the normal working mode.

[0077] At the same time, the counter 50 can comprehensively select to output a digital code value of m bits under conditions such as power consumption and frame rate. And in the case of further reducing power consumption, that is, when there is no need to quickly switch the working mode, the phase-locked loop inside the counter 50 can be further turned off, and an external reference clock is used as the system clock. The counter 50 can work in a smaller bit mode and output the corresponding level of brightness information so that the control circuit 4 can determine whether there is an event according to the change of the picture brightness.

[0078] Embodiment 3:

[0079] The present invention also provides a column output circuit 200 of an image sensor, as Figure 6As shown, the column output circuit 200 of the image sensor includes a signal source circuit 3 and readout circuits 2 of multiple image sensors. The specific structure of the readout circuit 2 of the image sensor refers to the above embodiments. Since the column output circuit 200 of the present image sensor adopts all the technical solutions of the above all embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated one by one here. Among them, the signal source circuit 3 is respectively connected to the readout circuits 2 of multiple image sensors, and each readout circuit 2 of the image sensor is correspondingly connected to a pixel unit 1. In the normal working mode, the signal source circuit 3 provides a ramp voltage RAMP and a clock signal for each readout circuit 2 respectively, and in the standby wake-up mode, the signal source circuit 3 can be in a closed state to reduce power consumption.

[0080] Among them, the signal source circuit 3 includes:

[0081] A reference power supply circuit 31 configured to output a reference power supply;

[0082] A ramp voltage circuit 32 configured to convert the reference power supply into a ramp voltage RAMP;

[0083] A phase-locked loop circuit 33 configured to convert an external clock signal into multiple internal clock signals and output them to the readout circuit 2, the ramp voltage circuit 32 and the control circuit 4 of the image sensor respectively.

[0084] In this embodiment, the reference power supply circuit 31 is respectively connected to the ramp voltage circuit 32 and the phase-locked loop circuit 33 and provides a working power supply for the ramp voltage circuit 32 and the phase-locked loop circuit 33. Among them, the ramp voltage circuit 32 converts the received reference power supply into a periodically changing ramp voltage RAMP and outputs it to the comparison circuit 10 in the readout circuit 2 in the normal working mode. When the phase-locked loop circuit 33 receives the working power supply and is in the normal working mode, it provides clock signals for the readout circuit 2, the ramp voltage circuit 32 and the control circuit 4 respectively. In the standby wake-up mode, the reference power supply circuit 31, the ramp voltage circuit 32 and the phase-locked loop circuit 33 can all be in a stopped working state to achieve the purpose of reducing power consumption.

[0085] Embodiment 4:

[0086] The present invention also proposes an image sensor, as Figure 7 shown, the image sensor includes a pixel array 100, a control circuit 4 and a column output circuit 200 of the image sensor. The specific structure of the column output circuit 200 of the image sensor refers to the above embodiments. Since the present image sensor adopts all the technical solutions of the above all embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated one by one here. Among them, the pixel array 100 includes multiple pixel units 1 arranged in an array;

[0087] The column output circuit 200 and the control circuit 4 of the image sensor are respectively connected to the pixel unit 1, and the column output circuit 200 of the image sensor is also connected to the control circuit 4;

[0088] The image sensor includes a normal operation mode and a standby wake-up mode. In the normal operation mode, the control circuit 4 outputs a read control signal, so that the counter 50 receives the first pulse signal PULSE1 and the clock signal output by the phase-locked loop circuit 33, and outputs the corresponding digital code value; in the standby wake-up mode, the control circuit 4 outputs a low-power control signal, so that the counter 50 receives the third pulse signal and outputs the corresponding digital code value.

[0089] In this embodiment, the control circuit 4 of the image sensor determines the picture brightness information according to the digital code value received in the current mode, and then judges whether an event occurs. When an event is detected, it switches to or maintains the normal operation mode, and outputs a read control signal to the read circuit 2, so that the first switch SW1 in the read circuit 2 is turned on, outputs the first pulse signal PULSE1 to the counter 50, and controls the selection output circuit 40 to output a clock signal to the counter 50. The counter 50 counts the first pulse signal PULSE1 according to the clock signal and outputs the corresponding digital code value. When no event is detected, it switches to or maintains the standby wake-up mode, selects to turn off the signal source circuit 3, and controls the second switch SW2 and the third switch SW3 inside the read circuit 2 to be turned on, converts and outputs the third pulse signal to the counter 50, and the counter 50 counts the third pulse signal and outputs the corresponding digital code value.

[0090] Among them, in the normal mode, the counter 50 outputs m bit data, that is, the resolution of the counter 50 is m bit, m≥8. When switching to the standby wake-up mode, the counter 50 can comprehensively select to output the digital code value of m bit under the conditions of factors such as power consumption and frame rate, that is, work with a resolution of m bit. Further, in order to reduce power consumption, that is, when there is no need to quickly switch the operation mode, the phase-locked loop inside the counter 50 can be further turned off, and an external reference clock is used as the system clock. The counter 50 works in the 2bit mode, that is, the resolution is 2bit, and outputs 4-order brightness information, so that the control circuit 4 judges whether an event occurs according to the change of the picture brightness.

[0091] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A readout circuit for an image sensor, characterized in that, it includes: A first switch whose first end is connected to the output end of the pixel unit, and is triggered to conduct by a readout control signal; A comparison circuit connected to the second end of the first switch and the signal source circuit, configured to compare the pixel signal output by the pixel unit and the ramp voltage output by the signal source circuit, and output a first pulse signal; A second switch whose first end is connected to the output end of the pixel unit, and is triggered to conduct by a low-power control signal; A pulse signal acquisition circuit connected to the second end of the second switch, configured to convert the pixel signal output by the pixel unit into a second pulse signal; A third switch connected between the output end of the pulse signal acquisition circuit and the controlled end of the reset transistor in the pixel unit, and is triggered to conduct by the low-power control signal, so that the pixel unit receives the second pulse signal and triggers alternate reset and integration; An inverting circuit connected to the output end of the pulse signal acquisition circuit, configured to invert the second pulse signal and output a third pulse signal with a phase opposite to that of the second pulse signal; A selection output circuit connected to the output end of the inverting circuit and the signal source circuit respectively, configured to be triggered by the readout control signal to output the clock signal of the signal source circuit, and to be triggered by the low-power control signal to output the third pulse signal; A counter connected to the output end of the comparison circuit and the output end of the selection output circuit, configured to count the number of clock pulses according to the received signal and output a corresponding digital code value to the control circuit, so that the control circuit determines the current picture brightness information according to the digital code value, and triggers the output of the readout control signal or the low-power control signal.

2. The readout circuit for an image sensor according to claim 1, characterized in that, The pulse signal acquisition circuit includes a first inverter and a pulse shaping circuit connected to each other. The first inverter is configured to receive the pixel signal output by the pixel unit and output a pulse signal, and the pulse shaping circuit is configured to perform waveform shaping based on the pulse signal output by the first inverter to output the second pulse signal.

3. The readout circuit for an image sensor according to claim 2, characterized in that, The pulse shaping circuit includes 2n cascaded second inverters, where n≥1.

4. The readout circuit for an image sensor according to claim 3, characterized in that, n＝1。 5. The readout circuit for an image sensor according to claim 1, characterized in that, The inverting circuit includes a third inverter. The input end of the third inverter is connected to the output end of the pulse signal acquisition circuit, and the output end of the third inverter is connected to the signal input end of the selection output circuit to output the third pulse signal.

6. The readout circuit for an image sensor according to claim 1, characterized in that, The selection output circuit includes a two-to-one data selector; The first signal input terminal of the one - of - two data selector is connected to the output terminal of the inverter circuit. The second signal input terminal of the one - of - two data selector is connected to the clock signal terminal of the signal source circuit. The signal output terminal of the one - of - two data selector is connected to the clock signal terminal of the counter. The control terminal of the one - of - two data selector is configured to input the read - out control signal or the low - power control signal, and trigger the selection to output the third pulse signal or the clock signal of the signal source circuit to the counter.

7. The read - out circuit of the image sensor according to claim 1, characterized in that, the comparison circuit includes: a first capacitor with its first terminal connected to the power supply terminal of the signal source circuit; a second capacitor with its first terminal connected to the second terminal of the first switch; a comparator, the non - inverting input terminal of the comparator is connected to the second terminal of the first capacitor, the inverting input terminal of the comparator is connected to the second terminal of the second capacitor, and the output terminal of the comparator forms the output terminal of the comparison circuit.

8. A column output circuit of an image sensor, characterized in that, it includes a signal source circuit and a plurality of read - out circuits of the image sensor according to any one of claims 1 to 7; the signal source circuit is respectively connected to the plurality of read - out circuits of the image sensor, and each read - out circuit of the image sensor is correspondingly connected to a pixel unit; wherein, the signal source circuit includes: a reference power supply circuit configured to output a reference power supply; a ramp voltage circuit configured to convert the reference power supply into a ramp voltage; a phase - locked loop circuit configured to convert an external clock signal into a plurality of internal clock signals and respectively output them to the read - out circuit of the image sensor, the ramp voltage circuit and the control circuit.

9. An image sensor, characterized in that, it includes a pixel array, a control circuit and a column output circuit of the image sensor according to claim 8, and the pixel array includes a plurality of pixel units arranged in an array; the column output circuit of the image sensor and the control circuit are correspondingly connected to the pixel units, and the column output circuit of the image sensor is also connected to the control circuit; the image sensor includes a normal operating mode and a wake - up - waiting mode. In the normal operating mode, the control circuit outputs a read - out control signal, so that the counter receives the first pulse signal and the clock signal output by the phase - locked loop circuit, and outputs a corresponding digital code value; In the wake - up - waiting mode, the control circuit outputs a low - power control signal, so that the counter receives the third pulse signal and outputs a corresponding digital code value.

10. The image sensor according to claim 9, characterized in that, in the normal operating mode, the resolution of the counter is m bit, where m≥8; in the wake - up - waiting mode, the resolution of the counter is 2 bit.

Images