A circuit transplantation method and apparatus

Abstract

Embodiments of the present application provide a circuit transplantation method and device, which relate to the chip technical field and can improve the efficiency of circuit transplantation under different processes and reduce the complexity during transplantation. The method comprises: extracting a first device lookup table under a source process and a second device lookup table under a target process; determining a second circuit and a second simulation case that have a preset corresponding relationship with the first circuit and the first simulation case under the source process; obtaining a device characteristic value of the first circuit according to a simulation result of direct current simulation on the first circuit and the first device lookup table, and taking the device characteristic value of the first circuit as a first constraint condition for selecting a device of the second circuit; determining a device size of the second circuit that meets the first constraint condition according to the second device lookup table; and performing comprehensive simulation on the second circuit with the device size that meets the first constraint condition according to the second simulation case. Embodiments of the present application are used for circuit transplantation under different processes.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a circuit transplantation method and apparatus. Background Technology

[0002] In traditional analog circuits, when switching processes, designers use Electronic Design Automation (EDA) software to port the circuit diagram and verification test cases from the original process to the target process. They then repeatedly run a device-level integrated circuit simulation program (SPICE) to simulate the circuit, iterating and adjusting based on the simulation results and the device's performance against specifications. If the simulation results fail to meet specifications, the designers iterate again, adjusting the device parameters for the target process.

[0003] As can be seen, during the iteration process, designers rely on SPICE simulation results to determine whether the circuit's operating state under the target process meets expectations. However, SPICE simulation obtains the circuit's operating state by solving circuit equations. When the circuit and its component models are complex, SPICE simulation is time-consuming, requiring multiple iterations to adjust the circuit architecture and component parameters to achieve the desired component performance, resulting in inefficient circuit porting. Summary of the Invention

[0004] This application provides a circuit transplantation method and apparatus, which can improve the efficiency of circuit transplantation under different processes and reduce the complexity of transplantation.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] Firstly, a circuit porting method is provided, comprising: extracting a first device lookup table under a source process and a second device lookup table under a target process, wherein the first device lookup table includes device characteristic values ​​of various types of devices under the source process, and the second device lookup table includes device characteristic values ​​of various types of devices under the target process; determining a second circuit that has a preset correspondence with the first circuit under the source process under the target process, and determining a second simulation case corresponding to the first simulation case under the source process under the target process; obtaining the device characteristic values ​​of the first circuit based on the simulation results of DC simulation of the first circuit and the first device lookup table, and using the device characteristic values ​​of the first circuit as a first constraint condition for selecting devices in the second circuit; determining the device size of the second circuit that satisfies the first constraint condition based on the second device lookup table; and performing a full simulation of the second circuit with device size that satisfies the first constraint condition based on the second simulation case. Here, full simulation can be understood as simulating the second circuit using multiple simulation methods to obtain the performance of the second circuit.

[0007] Therefore, this application addresses the problems of complex and lengthy iteration processes in porting analog circuit integrated circuits to different processes. This application uses the device characteristic values ​​obtained from the simulation results of the first circuit under the source process as the optimization target (first constraint), and matches the device characteristic values ​​of the second circuit under the target process according to the optimization target. This allows designers to identify key device characteristic values ​​as constraints for the circuit under the target process, and automatically adjust device dimensions using an optimization device to achieve key parameter matching between processes, reducing the design and verification workload of porting circuits to different processes. In one possible design, the method further includes: if a full simulation of the second circuit determines that the specifications of the second circuit do not meet the requirements, determining a second constraint, wherein the device characteristic values ​​in the second constraint are proportional to the device characteristic values ​​in the first constraint; determining the device dimensions of the second circuit that meet the second constraint according to a second device lookup table, or performing DC simulation on the second circuit to determine the device dimensions of the second circuit that meet the second constraint; and performing a full simulation of the second circuit according to a second simulation case to determine whether the specifications of the second circuit meet the requirements.

[0008] It should be understood that after a full simulation of the second circuit, if the specifications of some components in the second circuit do not meet the requirements, such as the gain of a certain component not meeting the requirements, the component size can be adjusted. Simultaneously, the optimization objective of the second circuit can be adjusted, using the second constraint as the optimization objective. Typically, the original component eigenvalues ​​and random mismatch values ​​in the first constraint are multiplied by preset coefficients to obtain the original component eigenvalues ​​and random mismatch values ​​in the second constraint. In this way, by continuously and iteratively optimizing the small-signal characteristics in the constraints—that is, optimizing the original component eigenvalues ​​and their corresponding random mismatch values—the specifications of the second circuit can ultimately be achieved.

[0009] In one possible design, extracting the first device lookup table under the source process and the second device lookup table under the target process includes: scanning each type of device in the source process using multidimensional voltage, channel length, and width to obtain device characteristic values ​​for each type of device under the source process with multidimensional voltage, channel length, and channel width; and scanning each type of device in the target process using multidimensional voltage, channel length, and channel width to obtain device characteristic values ​​for each type of device under the target process with multidimensional voltage, channel length, and channel width. These device characteristic values ​​may include, for example, the transconductance (gm), output transconductance (gds), flicker noise (fn), thermal noise (tn), DC current (id), and threshold voltage (Vt). The transconductance (gm) can be expressed as: gm = f(L, W, V). gs V ds V sb V gs V ds V sb This represents multidimensional voltage, where L represents the channel length of the device, and W represents the channel width. For example, in the first device lookup table, you can find a device by looking up its W, L, and V values. gs V ds V sb , thus obtaining the corresponding gm for the device.

[0010] In one possible design, the first constraint includes the device characteristic values ​​of some key components in the user-configured second circuit. These key component characteristics include transconductance, output transconductance, flicker noise, thermal noise, DC current, and threshold voltage. The device characteristic values ​​of these key components are the same as those of the first circuit. This is equivalent to the user processing the key information identified by the second circuit through GUI input, and incorporating the required optimized device characteristic values ​​into the identified key components. This allows for the optimization of small-signal characteristic values ​​in the target area during the user-configured circuit porting process.

[0011] In one possible design, the first constraint also includes key information about some components in the second circuit identified by the tuning tool. This key information includes the shutdown information of some components in the second circuit, the size ratios of some components, and the symmetry of the input transistor pairs of some components. The shutdown information can be understood as the components that are turned off in the second circuit. The size ratios of some components can be understood as the size ratios between components. The turned-off components do not participate in the circuit simulation.

[0012] In one possible design, the device feature values ​​in the first device lookup table also include first random mismatch information corresponding to the device feature values ​​of some devices under the source process. This first random mismatch information indicates the mismatch characteristics of the device feature values ​​obtained from simulating devices under the source process. Similarly, the device feature values ​​in the second device lookup table also include second random mismatch information corresponding to the device feature values ​​of some devices under the target process. This second random mismatch information indicates the mismatch characteristics of the device feature values ​​obtained from simulating devices under the target process. For example, the first random mismatch information is a mismatch coefficient corresponding to the device. This application can determine the random mismatch value corresponding to the device based on the mismatch coefficient. The random mismatch value indicates the bias range of the device feature values, within which the device feature values ​​are acceptable. Thus, during circuit porting, the efficiency of device feature value matching can be improved by adjusting the bias range.

[0013] In one possible design, the device characteristic values ​​of the first circuit are obtained based on the simulation results of a DC simulation of the first circuit and a first device lookup table. This includes: performing a DC simulation of the first circuit to obtain the original device characteristic values ​​of some devices in the first circuit; and determining the random mismatch values ​​of the original device characteristic values ​​of some devices in the first circuit based on the random mismatch information in the first device lookup table. The device characteristic values ​​of the first circuit include both the original device characteristic values ​​of some devices in the first circuit and the random mismatch values ​​of the original device characteristic values ​​of some devices in the first circuit. In other words, the first constraint condition includes the original device characteristic values ​​determined based on the simulation results, and the random mismatch values ​​determined based on the random mismatch information in the first device lookup table. For example, the original device characteristic value is transconductance gm. _org Its random mismatch value is denoted as gm _var At that time, the device characteristic value of the device in the second circuit is in gm _org gm _var All are acceptable, including GM. _org and gm _var This allows for a certain matching range during the device feature matching process, effectively shortening the optimization time and improving circuit porting efficiency.

[0014] In one possible design, determining the device dimensions of the second circuit that satisfy the first constraint based on the second device lookup table includes: searching the second device lookup table for devices whose original device characteristic values ​​and random mismatch values ​​satisfy the first constraint; and determining the device dimensions of the device that satisfies Kirchhoff's laws among these devices. This method of directly finding the device dimensions of devices that match the first constraint and satisfy Kirchhoff's laws in the second device lookup table eliminates the need for simulation tools, effectively shortening the optimization time.

[0015] In one possible design, determining the device dimensions of the second circuit that satisfy the first constraint based on the second device lookup table includes: performing a DC simulation of the second circuit, obtaining the original device characteristic values ​​of some devices in the second circuit based on the simulation results, and obtaining random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit based on the second random mismatch information in the second device lookup table; adjusting the device dimensions of the second circuit when the original device characteristic values ​​of some devices in the second circuit and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit do not satisfy the first constraint and Kirchhoff's law equations; performing a DC simulation of the second circuit after adjusting the device dimensions, obtaining the original device characteristic values ​​of some devices in the second circuit after adjusting the device dimensions based on the simulation results, and obtaining random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit after adjusting the device dimensions based on the second device lookup table; and determining whether the original device characteristic values ​​of some devices in the second circuit after adjusting the device dimensions and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit after adjusting the device dimensions satisfy the first constraint and Kirchhoff's law equations.

[0016] The accuracy of the device dimensions of the second circuit determined by DC simulation is higher than that of determining the device dimensions directly from the second device lookup table.

[0017] In one possible design, the characteristic values ​​of the same type of device differ under the source and target processes. The device dimensions of the same type of device may also differ.

[0018] Secondly, a tuning device is provided, including a processor coupled to a memory; the memory for storing computer programs or instructions; and the processor for executing the computer programs or instructions stored in the memory, such that the tuning device performs the following process: extracting a first device lookup table under a source process and a second device lookup table under a target process, wherein the first device lookup table includes device characteristic values ​​of various types of devices under the source process, and the second device lookup table includes device characteristic values ​​of various types of devices under the target process; determining a second circuit that has a preset correspondence with a first circuit under the source process under the target process, and determining a second simulation case corresponding to a first simulation case under the source process under the target process; obtaining the device characteristic values ​​of the first circuit based on the simulation results of DC simulation of the first circuit and the first device lookup table, and using the device characteristic values ​​of the first circuit as a first constraint condition for selecting devices in the second circuit; determining the device size of the second circuit that satisfies the first constraint condition based on the second device lookup table; and performing a full simulation of the second circuit with the device size that satisfies the first constraint condition based on the second simulation case.

[0019] For the beneficial effects in the second aspect, please refer to the explanation of the beneficial effects in the first aspect.

[0020] In one possible design, when the processor executes a computer program or instructions stored in memory, the process performed by the tuning device further includes: determining a second constraint condition if the specifications of the second circuit do not meet the requirements after performing a full simulation of the second circuit, wherein the device characteristic values ​​in the second constraint condition are proportional to the device characteristic values ​​in the first constraint condition; determining the device dimensions of the second circuit that meet the second constraint condition according to a second device lookup table, or performing a DC simulation of the second circuit to determine the device dimensions of the second circuit that meet the second constraint condition; and performing a full simulation of the second circuit according to a second simulation use case to determine whether the specifications of the second circuit meet the requirements.

[0021] In one possible design, when the processor executes a computer program or instructions stored in memory, including retrieving a first device lookup table under a source process and a second device lookup table under a target process, the specific steps include: performing a multi-dimensional voltage, channel length, and width scan on each type of device among multiple types of devices under the source process to obtain device characteristic values ​​for each type of device under the multi-dimensional voltage, channel length, and channel width; and performing a multi-dimensional voltage, channel length, and channel width scan on each type of device among multiple types of devices under the target process to obtain device characteristic values ​​for each type of device under the multi-dimensional voltage, channel length, and channel width.

[0022] In one possible design, the first constraint includes device characteristic values ​​of some key components in a user-configured second circuit; wherein the device characteristics of some key components include transconductance, output transconductance, flicker noise, thermal noise, DC current, and threshold voltage, and the device characteristic values ​​of some key components are the same as those of the first circuit.

[0023] In one possible design, the first constraint also includes key information about some devices in the second circuit identified by the tuning tool; wherein, the key information includes the turn-off information of some devices in the second circuit, the size ratio of some devices, and the symmetry relationship of the input pairs of some devices.

[0024] In one possible design, the device feature values ​​in the first device lookup table also include first random mismatch information corresponding to the device feature values ​​of some devices under the source process, the first random mismatch information being used to indicate the mismatch characteristics of the device feature values ​​obtained by simulating the devices under the source process; the device feature values ​​in the second device lookup table also include second random mismatch information corresponding to the device feature values ​​of some devices under the target process, the second random mismatch information being used to indicate the mismatch characteristics of the device feature values ​​obtained by simulating the devices under the target process.

[0025] In one possible design, when the processor executes a computer program or instructions stored in memory to obtain device characteristic values ​​of the first circuit based on simulation results of a DC simulation of the first circuit and a first device lookup table, the specific steps include: performing a DC simulation of the first circuit to obtain the original device characteristic values ​​of some devices in the first circuit; and determining random mismatch values ​​of the original device characteristic values ​​of some devices in the first circuit based on random mismatch information in the first device lookup table; wherein the device characteristic values ​​of the first circuit include the original device characteristic values ​​of some devices in the first circuit and the random mismatch values ​​of the original device characteristic values ​​of some devices in the first circuit.

[0026] In one possible design, when the processor executes a computer program or instructions stored in memory, including determining the device size of the second circuit that satisfies the first constraint according to a second device lookup table, specifically includes: searching the second device lookup table for devices that satisfy the original device characteristic values ​​and random mismatch values ​​in the first constraint, and determining the device size of the device that satisfies the Kirchhoff law equation among the devices that satisfy the original device characteristic values ​​and random mismatch values ​​in the first constraint as the device size of the second circuit.

[0027] In one possible design, when the processor executes a computer program or instructions stored in memory, including determining the device dimensions of a second circuit that satisfy the first constraint based on a second device lookup table, the specific steps include: performing a DC simulation on the second circuit; obtaining the original device characteristic values ​​of some devices in the second circuit based on the simulation results; and obtaining random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit based on second random mismatch information in the second device lookup table; adjusting the device dimensions of the second circuit when it is determined that the original device characteristic values ​​of some devices in the second circuit and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit do not satisfy the first constraint and Kirchhoff's laws; performing a DC simulation on the second circuit after adjusting the device dimensions; obtaining the original device characteristic values ​​of some devices in the second circuit after adjusting the device dimensions based on the simulation results; and obtaining random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit after adjusting the device dimensions based on the second device lookup table; and determining whether the original device characteristic values ​​of some devices in the second circuit after adjusting the device dimensions and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit after adjusting the device dimensions satisfy the first constraint and Kirchhoff's laws.

[0028] In one possible design, the device characteristic values ​​of the same type of device differ under the source process and the target process.

[0029] Thirdly, a chip coupled to a memory is provided for reading and executing program instructions stored in the memory to implement the method as described in the first aspect or any one of the first aspects.

[0030] Fourthly, embodiments of this application provide a computer-readable storage medium including computer instructions that, when executed on an electronic device, cause the electronic device to perform the circuit porting method in any of the above aspects and any possible implementations.

[0031] Fifthly, embodiments of this application provide a computer program product that, when run on a computer or processor, causes the computer or processor to execute the circuit porting method in any of the above aspects and any possible implementations.

[0032] For the other beneficial effects mentioned above, please refer to the description of the beneficial effects of the method, which will not be repeated here. Attached Figure Description

[0033] Figure 1 A schematic flowchart of an analog circuit during process switching is provided as an embodiment of this application;

[0034] Figure 2 A schematic diagram of an analog circuit design EDA software interface based on the analog integrated circuit design flow provided in this application embodiment;

[0035] Figure 3 A schematic flowchart illustrating a circuit transplantation method provided in an embodiment of this application;

[0036] Figure 4 A schematic flowchart illustrating a circuit transplantation method provided in an embodiment of this application;

[0037] Figure 5 A circuit diagram of an operational amplifier provided for an embodiment of this application;

[0038] Figure 6 A schematic diagram of a first circuit under a source process and a second circuit under a target process provided for embodiments of this application;

[0039] Figure 7 This is a schematic diagram of the structure of an optimization device provided in an embodiment of this application;

[0040] Figure 8 This is a schematic diagram of the structure of an optimization device provided in an embodiment of this application;

[0041] Figure 9 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0042] For ease of understanding, examples are provided to illustrate some concepts related to the embodiments of this application, as shown below.

[0043] Process Design Kit (PDK): A complete set of process documents for the design of analog / mixed-signal integrated circuits (ICs), serving as a data platform connecting IC design and IC manufacturing processes.

[0044] Electronic design automation (EDA) refers to the design method that uses computer-aided design (CAD) software to complete the functional design, synthesis, verification, and physical design (including placement, routing, layout, design rule checking, etc.) of very large scale integrated circuit (VLSI) chips.

[0045] Analog Circuit Reuse: In analog integrated circuit design, analog circuit reuse is a common design method used to reuse source circuits for target circuits. Analog circuit reuse generally includes circuit-level optimization of integrated circuit device parameter values ​​and layout-level physical optimization of device locations and interconnections. Typically, both the source and target circuits consist of multiple devices connected at multiple nodes. Based on the relatively independent functions implemented by different circuit sections, the source and target circuits can be divided into at least one corresponding module, such as a power supply module, a receiving module, an amplification module, a signal processing module, etc. Each module includes a set of devices, and the modules are connected at nodes between modules, and the devices are connected at nodes within and between modules.

[0046] Source circuit simulation includes DC analysis, AC analysis, transient analysis, and other numerical analyses of the entire source circuit.

[0047] Kirchhoff's laws, also known as Kirchhoff's first law or Kirchhoff's current law, are the manifestation of the continuity of current in lumped-parameter circuits. Their physical basis is the axiom of charge conservation. Kirchhoff's current law determines the relationship between the currents in each branch at any node in a circuit; therefore, it is also called the node current law.

[0048] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0049] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this embodiment, unless otherwise stated, "a plurality of" means two or more.

[0050] The process of switching processes in traditional analog circuits can be as follows: Figure 1 As shown. The process includes the following steps.

[0051] 1) Port the circuits and simulation test cases from the source process to the new process;

[0052] 2) Based on the parameterized devices and simulation models provided by PDK, determine the circuit design specifications to be simulated;

[0053] 3) Manually input and adjust device parameters in the PDK;

[0054] 4) Perform circuit simulation by repeatedly running a device-level integrated circuit general simulation program, and make multiple iterative adjustments based on the circuit output and the specification achievement of the device operating state as presented by the simulation results;

[0055] 5) After each adjustment, use simulation test cases in the circuit's SPICE simulator to verify whether the circuit specifications meet the requirements. If they do, the circuit porting is considered complete.

[0056] 6) If the standard is not met, the designer can adjust the size of the components in the circuit based on experience, and then continue to verify whether the circuit meets the standard through simulation test cases.

[0057] Among them, Figure 1 In the process, analog circuit design EDA software based on the analog integrated circuit design flow can provide simplified schematic diagrams of circuit diagrams and device parameter editing interfaces, simulation operations, and simulation result display interfaces, as shown in the figure. Figure 2 As shown, designers can input circuit diagrams and adjust component size parameters through a graphical interface, set simulation conditions, start the simulation, and view the simulation results. Some EDA software also provides guidance for exploring the gradient relationship between specific component characteristics and simulation specifications, offering designers relevant instructions for circuit design.

[0058] As can be seen, in the aforementioned iterative process, designers rely on SPICE simulation results to determine whether the circuit's operating state meets expectations. However, SPICE simulation obtains the circuit's operating state by solving circuit equations. When the circuit and device models are complex, SPICE simulation is time-consuming, requiring continuous iterations to determine the circuit architecture and device parameters to obtain the desired performance. This process is time-consuming, inefficient, and highly dependent on experienced designers.

[0059] Currently, there are various methods to improve the efficiency of analog circuit porting. A common approach is to use computers and data optimization algorithms to adjust device parameters, finding the optimal design for the ported circuit based on changes in simulation results. Typically, designers specify a design space, such as circuit structure, device types, and size ranges, as well as design specifications and weights, allowing computer software to transform the design problem into a mathematical optimization problem. This problem is then solved using numerical algorithms, leveraging computer-automated design to improve circuit design efficiency.

[0060] For example, an existing multi-objective Bayesian optimization-based analog circuit multi-objective optimization design method mentions the field of automatic optimization design of analog circuit parameters in integrated circuit design. Specifically, it involves a Gaussian process model-based over-objective Bayesian optimization method. In each circuit design iteration of this method, a Gaussian process model is constructed for each circuit index, and then a low-confidence interval function is constructed. The point for the next circuit simulation is selected by multi-objective optimization of the low-confidence interval function. Compared with current mainstream international methods, this method can significantly reduce the number of circuit simulations and find an optimal set of solutions in the multi-objective optimization problem as the final optimization objective of the analog circuit.

[0061] It is evident that these automated circuit design optimizers typically explore and judge designs based solely on the design space range, design weights, and objectives pre-input by the designer. They use optimization algorithms to traverse the design space and obtain the optimal design result or several optimal outputs for the designer to choose from. However, this approach struggles to provide a complete compromise among all design objectives and constraints within a reasonable timeframe when there are too many possible circuit design goals and constraints. Determining appropriate weights is also difficult, generally relying on the designer's experience in allocating device parameters. Furthermore, incorrect weight allocation can lead to inappropriate design results. In addition, the larger the circuit size, the more severe the design difficulties and the lower the efficiency.

[0062] In another design, a circuit optimization method and apparatus for analog circuit porting are provided. This analog circuit porting is used to reuse a source circuit for a target circuit. In this circuit optimization method, the source circuit is divided into at least one DC path; the order of the at least one DC path is determined; and the DC paths of the target circuit are optimized sequentially. Although this circuit optimization method and apparatus can improve the efficiency of circuit optimization in analog circuit porting, this design, for the application scenario of circuit porting, requires that the performance matching of each DC path be optimized through SPICE simulation, and each DC path needs to meet the corresponding specifications, thus failing to achieve automated circuit design.

[0063] Therefore, existing circuit design or circuit porting scenarios suffer from problems such as complex circuit design implementation, low efficiency, or inability to achieve automated design. To address this, this application provides a circuit porting method that proposes a novel automated optimization approach to solve the problems of complex processes and low design efficiency in porting analog integrated circuits across different process technologies. This approach enables automated porting of circuit designs between different process technologies.

[0064] In some embodiments of this application, the process of switching processes for analog circuits is improved by matching the characteristics of each key component of the same architecture circuit under different processes to achieve overall circuit characteristic matching after the porting. Because this application adopts a component characteristic matching method, such as matching the DC small-signal electrical characteristics of components, it can achieve automated circuit optimization with less resource overhead and lower implementation complexity.

[0065] This application can be applied to chip technology, describing the circuit porting process of analog circuits in a chip during process switching. The chip may be, for example, a system-on-a-chip (SoC), with the analog circuit being the analog IP portion of the SoC; or, the chip may be a power management unit (PMU), etc. Of course, it can also be other types of chips; this application does not limit the scope of the chip.

[0066] In some embodiments, process switching can be understood as a process switching of device dimensions in a circuit, such as a process switching of minimum channel length, specifically a process switching of the minimum channel length of some devices under the source process. For example, the minimum channel length of the device under the source process is 180nm, and the minimum channel length of the device under the new process is 65nm.

[0067] The device in this application can be understood, for example, as a metal-oxide-semiconductor (MOS) field-effect transistor, which is simply referred to as a MOS transistor in this application.

[0068] In the application scenario of this application, when implementing circuit portability under different processes, a device lookup table for the source process can be obtained by simulating the devices under the source process, and a device lookup table for the new process can be obtained by simulating the devices under the new process. By automatically identifying the device lookup table for the source process and manually defining certain device characteristics, the device feature values ​​that need to be matched for key devices are obtained, which is equivalent to obtaining the constraints for optimizing the circuit under the new process. When the tuner determines these constraints, it can perform mathematical tuning to obtain the device dimensions that meet the constraints. Then, the tuned circuit is simulated using SPICE, and iterative processing is performed based on the SPICE simulation results.

[0069] The circuit transplantation method of this application is described below.

[0070] refer to Figure 3 This application provides a circuit transplantation method, which includes the following process.

[0071] 301. The optimization device extracts a first device lookup table under the source process and a second device lookup table under the target process. The first device lookup table includes device characteristic values ​​of various types of devices under the source process, and the second device lookup table includes device characteristic values ​​of various types of devices under the target process.

[0072] The tuning device in this application can be understood as a tuner installed in a personal computer (PC). The source process can be understood as the process before circuit migration, and the target process is the new process after circuit migration.

[0073] Under both the source and target processes, there are various types of devices in the circuit. This application can perform DC simulation and noise simulation for each type of device to obtain device characteristic values ​​for various types of devices.

[0074] The device types in this application include, for example, MOSFETs and bipolar junction transistors (BJTs). Device characteristics may include, for example, transconductance (gm), output transconductance (gds), flicker noise (fn), and thermal noise (tn), and may also include other device characteristics, which are not limited in this application.

[0075] In some embodiments, in the first device lookup table, the device feature value of each type of device includes not only the device feature value obtained by simulating the device, but also the first random mismatch information corresponding to the device feature value. The first random mismatch information is used to indicate the mismatch characteristics of the device feature value obtained by simulating the device under the source process.

[0076] In the second device lookup table, the device feature values ​​for each type of device include not only the device feature values ​​obtained by simulating the device, but also the second random mismatch information corresponding to the device feature values. The second random mismatch information is used to indicate the mismatch characteristics of the device feature values ​​obtained by simulating the device under the target process.

[0077] In this application, the tuning device can determine the random mismatch value based on the random mismatch information. The random mismatch value is used to indicate the bias range of the device characteristic value, that is, the device characteristic value within the bias range is acceptable.

[0078] 302. The optimization device determines the second circuit that has a preset correspondence with the first circuit under the source process under the target process, and determines the second simulation case corresponding to the first simulation case under the source process under the target process.

[0079] In some embodiments, the tuning device may store a preset correspondence between various devices in the active process and various devices in the target process. When the tuning device determines that a first circuit needs to be transferred from the active process to the target process, the tuning device determines the corresponding device in the target process for each device in the first circuit according to the preset correspondence.

[0080] For example, when the device is a MOS device, a MOS device with a standard threshold (SVT) of 0.9V under the source process corresponds to a MOS device with a conventional threshold (RVT) of 0.8V under the target process.

[0081] In some embodiments, the first simulation use case and the second simulation use case are the same. For example, in the first simulation use case, the signal-to-noise ratio of the device can be obtained through transient simulation, and the linearity result of the device can be obtained through periodic steady-state simulation.

[0082] 303. The optimization device obtains the device characteristic values ​​of the first circuit based on the simulation results of the DC simulation of the first circuit and the first device lookup table, and uses the device characteristic values ​​of the first circuit as the first constraint condition for selecting the devices of the second circuit.

[0083] In some embodiments, the tuning device may perform DC simulation and noise simulation on the device characteristics of some devices in the first circuit to obtain the original device characteristic values ​​of some devices in the first circuit, and determine the bias range of the original device characteristic values ​​of some devices in the first circuit according to the first random mismatch information in the first device lookup table.

[0084] In other words, the first constraint of this application may include the original device characteristic values ​​and the bias range of the original device characteristic values ​​of some components of the first circuit. Here, the bias range can be understood as the bias values ​​of the original device characteristic values ​​being acceptable within the bias range.

[0085] 304. The optimization device determines the device dimensions of the second circuit that satisfy the first constraint condition based on the second device lookup table.

[0086] In some embodiments, the tuning device can directly search for device feature values ​​that satisfy the first constraint conditions in the second device lookup table extracted in step 301 according to the first constraint conditions, and use the device size of the device corresponding to the device feature value that satisfies the first constraint conditions as the device size of the second circuit that satisfies the first constraint conditions.

[0087] In some embodiments, the tuning device can perform DC simulation on the second circuit to obtain device characteristic values ​​of some components in the second circuit, determine random mismatch values ​​of the device characteristic values ​​according to a second device lookup table, and determine whether the device characteristic values ​​and random mismatch values ​​satisfy the first constraint condition. If they satisfy the constraint condition, the device size of the components in the second circuit is determined; if they do not satisfy the constraint condition, the device size of the components in the second circuit can be adjusted, and then simulation can continue. Based on the device characteristic values ​​obtained from the re-simulation, the random mismatch values ​​of the device characteristic values ​​can be determined in the second device lookup table, and it can be further determined whether the device characteristic values ​​and random mismatch values ​​at this time satisfy the first constraint condition. For example, the initial device size in the second circuit can be determined according to the corresponding device size in the first circuit before circuit porting. If, based on the initial device size of the second circuit, DC simulation is performed on the components in the second circuit, and the simulation result and the result determined by looking up the second device lookup table do not satisfy the first constraint condition, the device size of the second circuit can be adjusted again, and DC simulation and looking up the second device lookup table can be performed again to determine whether the simulation result and the lookup table result satisfy the first constraint condition.

[0088] 305. The optimization device performs a full simulation of the second circuit that meets the device dimensions of the first constraint condition based on the second simulation case.

[0089] Having obtained the device characteristic values ​​and device dimensions of the second circuit through step 304, a comprehensive simulation of the second circuit under the target process can be performed. This involves simulating the second circuit using multiple simulation methods to obtain its performance. For example, comprehensive simulation includes obtaining the overall circuit performance through transient analysis, AC simulation, Periodic SteadyState (PSS) simulation, and Monte Carlo simulation to determine if the overall circuit performance meets the requirements. If it does not meet the requirements, the first constraint condition can be adjusted again to determine a new optimization objective. Based on the adjusted device dimensions, a comprehensive simulation of the second circuit can then be performed again to determine if the overall circuit performance meets the requirements after optimizing the objective.

[0090] In this way, by continuously and iteratively optimizing the device characteristic values ​​and device dimensions, the specifications of the second circuit are ultimately achieved.

[0091] Therefore, this application addresses the problems of complex and long iteration times in the porting process of analog circuit integrated circuits under different processes. By using the matching device characteristic value method of this application, designers can identify the key device characteristic values ​​as constraints for the circuit under the target process, and use the optimization device to automatically adjust the device size to achieve the matching of key parameters between processes, thereby reducing the design and verification workload of porting circuits to different processes.

[0092] The embodiments of this application will be further described below.

[0093] refer to Figure 4 This application provides a circuit transplantation method, which includes the following steps.

[0094] 401. The optimization device performs simulation analysis on the devices under the source process and the devices under the target process, and extracts the first device lookup table under the source process and the second device lookup table under the target process.

[0095] In this application, the characteristic values ​​of the same type of device differ under the source process and the target process.

[0096] The first device lookup table includes device characteristic values ​​of various types of devices under the source process, and the second device lookup table includes device characteristic values ​​of various types of devices under the target process.

[0097] In some embodiments, the tuning device performs multidimensional voltage, channel length and width scanning on each type of device in the source process to obtain device characteristic values ​​of each type of device under multidimensional voltage, channel length and channel width.

[0098] Multidimensional voltage, channel length, and width scans are performed on each type of device under the target process to obtain device characteristic values ​​for each type of device under the target process with multidimensional voltage, channel length, and channel width.

[0099] In this application, the device feature values ​​extracted from the first device lookup table and the second device lookup table can be understood as the small-signal characteristics of the device. The first device lookup table and the second device lookup table can be called lookup tables (LUTs) and are used for subsequent processing by the tuning device.

[0100] For example, the simulation analysis in step 401 can be DC simulation and noise simulation. The device characteristic values ​​in this application may include the transconductance (gm), output transconductance (gds), flicker noise (fn), thermal noise (tn), DC current (id) and threshold voltage (Vt) of the device, and may also include other device characteristic values, which are not limited in this application.

[0101] Multidimensional voltages, such as those of devices, include V. gs (Gate voltage relative to source), V ds (drain voltage) and V sb When the threshold voltage is defined as L (length) and the channel length of the device is defined as W (width), for example, when this application is applied to common functional circuits in analog circuits, such as the circuit transplantation of operational amplifiers, as shown in the example... Figure 5As shown, this is a circuit of an operational amplifier, including devices such as MOS, resistors and capacitors. In this case, the calculation formula for transconductance gm after scanning can be shown as formula (1).

[0102] g m =f(L, W, V) gs V ds V sb ), formula (1).

[0103] Other device characteristic values ​​can also be calculated using the same method as gm.

[0104] It should be noted that when scanning devices in the source or target process, each device can have multiple characteristic values ​​for each type of device. For example, when obtaining the g-value of a certain type of device... m At that time, g m The value of V can be multiple. This is because the multidimensional voltage during scanning can be ergodic; for example, when scanning a device, V... gs The range can be iterated through according to the range of 0 to 1.2V to obtain multiple g values. m The value of V. Similarly, for V ds and V sb It can also iterate through a certain voltage range, corresponding to multiple gm values. Similarly, for other device characteristic values, multiple voltage values ​​can correspond to multiple device characteristic values.

[0105] It is understandable that for the first device lookup table, a set of L, W, V gs V ds V sb The value corresponds to a gm value. The same applies to other device eigenvalues ​​such as gds, fn, tn, id, and Vt; a set of parameters corresponds to a single device eigenvalue.

[0106] Furthermore, in some embodiments, the device feature values ​​in the first device lookup table also include first random mismatch information corresponding to the device feature values ​​of some devices among various types of devices under the source process; the first random mismatch information is used to indicate the mismatch characteristics of the device feature values ​​obtained by simulating the devices under the source process. The second device lookup table also includes second random mismatch information corresponding to the device feature values ​​of some devices among various types of devices under the target process; the second random mismatch information is used to indicate the mismatch characteristics of the device feature values ​​obtained by simulating the devices under the target process.

[0107] The random mismatch information (first random mismatch information and second random mismatch information) includes the mismatch coefficient of the device characteristic values. The random mismatch information is used to determine the deviation range of the device characteristic values, or in other words, the random mismatch value. As long as the device characteristic values ​​are within the deviation range, they are acceptable.

[0108] For example, when simulating various devices using the source process, the mismatch coefficient A of the device's threshold voltage Vt is obtained by scanning the length of the device. vt Therefore, a lookup table for the mismatch coefficient corresponding to each threshold voltage of each device can be obtained. A vt The calculation method is shown in formula (2).

[0109] A vt =f(L), formula (2).

[0110] In this way, when performing circuit transplantation, the random mismatch value corresponding to the device characteristic value can be determined according to the mismatch coefficient of each device characteristic value. The absolute value of the difference between the random mismatch value and the device characteristic value can be understood as the deviation range in this application.

[0111] 402. The optimization device determines the second circuit that has a preset correspondence with the first circuit under the source process under the target process, and determines the second simulation case corresponding to the first simulation case under the source process under the target process.

[0112] When the tuning device determines that the first circuit needs to be ported from the source process to the target process, it can first port the circuit and simulation test cases while keeping the device size unchanged.

[0113] For example, the optimization device stores a preset correspondence between devices in the active process and devices in the target process. The optimization device can read the device type and device size in the active process and determine the corresponding device type and device size in the target process according to the preset correspondence, thus obtaining the device type and device size of the second circuit. At this point, the device type and coupling relationship between the devices in the second circuit have been determined. The device size at this time is only the initial device size, and it is necessary to adjust the device size of the second circuit according to the constraints to make the second circuit meet the optimization target.

[0114] Typically, the first and second simulation use cases are the same.

[0115] like Figure 6 The diagram shows schematics of a first circuit under the source process and a second circuit under the target process. It is evident that the first and second circuits have the same circuit architecture. The differences lie in the device parameters and dimensions. Device parameters include transconductance (gm), output transconductance (gds), flicker noise (fn), thermal noise (tn), DC current (id), and threshold voltage (Vt), as mentioned above.

[0116] 403. The optimization device obtains the device characteristic values ​​of the first circuit based on the simulation results of the DC simulation of the first circuit and the first device lookup table, and uses the device characteristic values ​​of the first circuit as the first constraint condition for selecting the devices of the second circuit.

[0117] In some embodiments, the first constraint includes key information about certain components in the second circuit identified by the tuning tool.

[0118] The key information includes the turn-off information of some devices in the second circuit, the size ratio of some devices (the size ratio between devices, for example, when the second circuit includes a current mirror circuit, the length of different devices must be the same), and the symmetry relationship of the input pairs of some devices. Turn-off information can be understood as the devices that are turned off in the second circuit.

[0119] For example, when the user determines that the tuning tool has obtained the second circuit in step 402, the user can input through a graphical user interface (GUI) to trigger the tuning device to identify key information in the second circuit. Identifying key information in the second circuit can be understood as identifying common electrical structures in the second circuit. Besides the aforementioned turn-off information, size ratios, and input transistor symmetry, this may also include current mirrors, input differential pairs, photodiodes (PDs), and logic function modules. The aforementioned ratios may also include maintaining the ratio of the current mirror. Furthermore, the tuning device can also identify components in the second circuit that do not require optimization, i.e., they can be directly determined based on preset correspondences between components.

[0120] For example, devices whose size ratio needs to be determined include M5 and M6 in the second circuit, while devices that do not require optimization include M7 in the second circuit.

[0121] When the tuning tool obtains key information, it can generate a corresponding file, which is used to store that key information.

[0122] In some embodiments, the first constraint further includes device characteristic values ​​of some key components in the second circuit configured by the user, wherein the device characteristic values ​​of some key components are the same as those of the first circuit.

[0123] Among these, the device characteristic values ​​of some key components include transconductance (gm), output transconductance (gds), flicker noise (fn), thermal noise (tn), DC current (id), and threshold voltage (Vt). This is equivalent to the user inputting key information through a GUI, further processing the information identified by the second circuit, and incorporating the required optimized device characteristic values ​​into the identified components (which can be understood as key components). For example, some key components include... Figure 6 The circuit shown includes M1, M2, M3, M4, and M8.

[0124] In some embodiments, the device characteristic values ​​of the first circuit include, in addition to, the original device characteristic values ​​obtained by performing DC simulation on some of the devices of the first circuit, random mismatch information of the original device characteristic values.

[0125] Once the original device characteristic values ​​and random mismatch information of the first circuit are determined, it is equivalent to determining the first constraint condition for selecting the devices of the second circuit, that is, the original device characteristic values ​​and random mismatch information of the first circuit are used as the optimization target of the second circuit at this time.

[0126] For example, the tuning device can perform DC simulation and noise simulation on the first circuit under the source process to obtain the original device characteristic values ​​of some devices in the first circuit, and determine the random mismatch value of the original device characteristic values ​​of some devices based on the random mismatch information of some devices under the first circuit.

[0127] Alternatively, the tuning device can perform DC simulation and noise simulation on the first circuit under the source process, and perform static characteristic analysis of the devices to obtain the small-signal characteristics of the key devices in the first circuit (such as g mentioned above). m g ds (e.g., fn, tn, id, and Vt), and assist LUK under the source process in determining the random mismatch value of each small signal feature.

[0128] For example, taking one of the device features g m For example, the tuning device obtains the bias voltage V of a device in the first circuit through DC simulation. gs V ds V sb and the original device characteristics gm of the device. _org By combining the device parameters—channel length L and width W—and consulting the first device lookup table, the random mismatch information of the threshold voltage Vt mismatch of the device can be obtained, i.e., the mismatch coefficient A. vt .

[0129] Furthermore, through this mismatch coefficient A vt The tuning device can derive the standard deviation δ of the device's threshold voltage Vt by combining the device's channel length L and device width W. vt δ vt The calculation formula is shown in formula (3).

[0130]

[0131] It is understandable that when the standard deviation δ of the threshold voltage Vt is determined... vt At that time, it can be further determined based on the standard deviation δvt The corrected V is obtained gs The corrected V gs Let V be the denoted V gs At that time, V gs The formula for calculating ' is shown in formula (4).

[0132] V gs '=V gs -n·δ Vt , formula (4).

[0133] Wherein, n is a coefficient of the calculation deviation that the designer needs to consider. For example, the value of n can be 3, which means that the 3Sigma fluctuation is tolerated.

[0134] Then, V can be used gs 'Obtain device characteristics gm _org random mismatch value gm _var , gm _var The calculation formula is shown in formula (5).

[0135] gm _var =f(L, W, V) gs ', V ds V sb ), formula (5).

[0136] At this time, gm _org This can be understood as a primitive characteristic value of the device, that is, the value of gm as an optimization objective of the device under the first constraint condition. _var As this gm _org The random mismatch value. As long as the gm value of the device corresponding to this device in the second circuit is consistent with gm... _org The value is or is close to the value of the device corresponding to this device in the second circuit. _org and gm _var Within the range (including gm) _org and gm _var In all cases, the gm value of the corresponding device in the second circuit can be considered to have satisfied the first constraint condition.

[0137] Other original device eigenvalues ​​such as gds, fn, tn, id, and Vt, and their corresponding random mismatch values, can be obtained using a method similar to gm. Thus, the first constraint includes the original device eigenvalues ​​gm, gds, fn, tn, id, and Vt for each of the multiple devices, and the random mismatch value corresponding to each original device eigenvalue.

[0138] 404. The optimization device determines the device dimensions of the second circuit that satisfy the first constraint condition based on the second device lookup table. Then, step 406 is executed.

[0139] Once the tuning device obtains the first constraint condition for determining the second circuit, the tuning process begins.

[0140] In some embodiments, the tuning device may determine the device dimensions of a second circuit that satisfies the first constraint and Kirchhoff's laws, including the channel length and channel width of the device, based on a second device lookup table.

[0141] Kirchhoff's laws include Kirchhoff's first law and Kirchhoff's second law. Kirchhoff's first law is also known as Kirchhoff's Current Law (KCL), while Kirchhoff's second law is known as Kirchhoff's Voltage Law (KVL).

[0142] For example, the second device lookup table includes device characteristic values ​​for each type of device under the target process, under multi-dimensional voltage, device channel length, and channel width. These device characteristic values ​​include the device characteristic values ​​obtained from simulation of the device under the target process and random mismatch information. When the tuning device determines the first constraint condition through step 403, it uses the first constraint condition as the tuning target. Considering that each original device characteristic value in the first constraint condition corresponds to a random mismatch value, for a device in the second circuit involved in the first constraint condition, multiple sets of device characteristic values ​​satisfying the first constraint condition can be found in the second device lookup table, and the random mismatch values ​​corresponding to these multiple sets of device characteristic values ​​are calculated. It should be understood that the reason for the existence of multiple sets of device characteristic values ​​is that the original device characteristic values ​​in the first constraint condition have a mismatch range caused by random mismatch values. That is, the device characteristic values ​​found in the second device lookup table and the calculated random mismatch values ​​satisfying the original device characteristic values ​​and mismatch range in the first constraint condition are both acceptable. Then, at least one set of device characteristic values ​​that satisfy the KCL equation can be determined from these multiple sets of device characteristic values ​​and corresponding random mismatch values. The device size corresponding to this at least one set of device characteristic values ​​is then selected from the second device lookup table. In this way, the size of the device is determined.

[0143] This implementation method, which combines a second device lookup table to determine device size, eliminates the need for simulation tools and effectively shortens optimization time.

[0144] 405. The optimization device performs DC simulation on the second circuit and determines the device dimensions of the second circuit that satisfy the first constraint condition based on the simulation results and the second device lookup table.

[0145] In some embodiments, when the tuning device obtains the first constraint condition, it can perform DC simulation and noise simulation on the second circuit, and adjust the device size of the second circuit according to the simulation results and the second device lookup table, so that the simulation result of the adjusted second circuit satisfies the first constraint condition and Kirchhoff's law equations.

[0146] For example, the tuning device can perform DC simulation on some devices in the second circuit (devices that are partially turned off or do not require simulation are not included in the simulation) to obtain the bias voltage V of some devices in the second circuit. gs V ds and V sb This allows for the further acquisition of a subset of original device characteristic values ​​(e.g., transconductance gm, output transconductance gds, DC current Id, threshold voltage Vt, etc.) for each device in the second circuit based on the bias voltage. Furthermore, noise simulation is performed on some devices in the second circuit to obtain another subset of original device characteristic values ​​(e.g., including flicker noise fn and thermal noise tn).

[0147] When using the original device characteristic values ​​and random mismatch values ​​of the original device characteristic values ​​in the first constraint as the optimization target for the second circuit, the random mismatch values ​​of the original device characteristic values ​​obtained by performing DC simulation and noise simulation on some devices in the second circuit can be obtained based on the second random mismatch information in the second device lookup table (similar to the process of calculating the random mismatch values ​​of the original device characteristic values ​​of the first circuit in step 403).

[0148] Determine whether the original device characteristic values ​​of some devices in the second circuit and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit satisfy the first constraint condition and Kirchhoff's laws. Determining whether the first constraint condition is satisfied can be understood as determining whether the original device characteristic values ​​of some devices in the second circuit and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit are within the range of the original device characteristic values ​​and corresponding random mismatch values ​​specified in the first constraint condition.

[0149] If the random mismatch between the original device characteristic values ​​of some devices in the second circuit and the original device characteristic values ​​of some devices in the second circuit satisfies the first constraint condition, the tuner determines that it will not continue to iterate on the device dimensions in the second circuit.

[0150] If the original device characteristic values ​​of some devices in the second circuit and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit do not satisfy the first constraint condition and Kirchhoff's law equation, the tuner can adjust the device size of some devices in the second circuit, continue to perform DC simulation on the second circuit after adjusting the device size, obtain the original device characteristic values ​​of some devices in the second circuit after adjusting the device size based on the simulation results, and obtain the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit after adjusting the device size based on the second device lookup table.

[0151] Determine whether the original device characteristic values ​​of some devices in the second circuit after adjusting the device dimensions and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit satisfy the first constraint condition and Kirchhoff's laws. If they satisfy, the device dimensions of some devices in the second circuit are determined. If they do not satisfy, continue adjusting the device dimensions until the original device characteristic values ​​and random mismatch values ​​of the adjusted second circuit satisfy the first constraint condition.

[0152] The accuracy of the device dimensions of the second circuit determined by DC simulation and noise simulation in step 405 is higher than that of the device dimensions determined directly by the second device lookup table in step 404.

[0153] 406. The optimization device simulates the second circuit according to the second simulation case and determines whether the specifications of the second circuit meet the requirements.

[0154] Once the second circuit is determined through step 404 or 405, the circuit with key small-signal characteristics at the device level is essentially obtained. At this point, further simulation using a second simulation test case is needed under the target process to check if the specifications of the second circuit meet the requirements.

[0155] In some embodiments, whether the specifications of the second circuit meet the requirements can be understood as whether the devices in the second circuit meet the specifications after a full simulation using the second simulation case. If all the devices in the second circuit meet the specifications, then the second circuit is determined to be the final ported circuit. If the simulation results of at least one device in the second circuit indicate that the specifications do not meet the requirements, then the critical device feature matching process needs to be entered again, i.e., step 407 is executed.

[0156] In some embodiments, the process of performing a comprehensive simulation using the second simulation case in step 406 can be understood as performing DC simulation, transient simulation, AC simulation, periodic stead-state (PSS) simulation, Monte Carlo simulation, etc., on the second circuit to obtain the overall performance or specifications of the second circuit. Taking the second circuit as an operational amplifier circuit as an example, the transconductance, gate-source capacitance, and output current noise of the MOS device in the circuit can be obtained through DC simulation; the signal-to-noise ratio of the MOS device can be obtained through Fourier analysis of the simulation results by transient simulation; the linearity of the device can be obtained through PSS simulation; and the random mismatch value of the device input equivalent voltage and the average value and random mismatch value of the device performance or specifications under different processes can be obtained through Monte Carlo simulation.

[0157] 407. If the specifications of the second circuit do not meet the requirements, the tuning device determines the second constraint condition, in which the device characteristic value is proportional to the device characteristic value in the first constraint condition.

[0158] If the performance or specifications of at least one device in the second circuit do not meet the requirements, the process of matching the key device characteristic values ​​can be restarted to determine new constraints and repeat the iteration. In this way, by continuously and iteratively optimizing the device characteristic values, the specifications of the second circuit can ultimately be achieved.

[0159] In some embodiments, the device characteristic value in the second constraint may be determined based on a proportional relationship with the device characteristic value in the first constraint.

[0160] For example, the original device characteristic gm in the first constraint is denoted as gm. _org The original device characteristic gm in the second constraint is denoted as gm. _target At that time, gm _target With gm _org The proportional relationship can be shown in formula (6).

[0161] β 0_low· gm _org ≤gm _target ≤β 0_high· gm _org Formula (6).

[0162] Where, β 0_low and β 0_high A pre-defined range coefficient is used to determine the original device characteristic value gm in the second constraint condition. _target The range.

[0163] In some embodiments, β 0_low and β 0_highThe value can be obtained by looking up the first device lookup table. That is, the first device lookup table can include the channel length L, width W, device characteristic values, mismatch factor, and β for each type of device. 0_low and β 0_high The corresponding β of the device can be found by using the channel length L and width W of the device. 0_low and β 0_high .

[0164] Similarly, when the first constraint also includes random mismatch values ​​of the original device characteristic values, the random mismatch values ​​of the original device characteristic values ​​in the second constraint can also be determined. The random mismatch value of the original device characteristic value gm in the first constraint is denoted as gm. _var When the random mismatch value of the original device characteristic value gm in the second constraint is denoted as gm _var_target At that time, gm _var_target With gm _var The proportional relationship can be shown in formula (7).

[0165] β 1_low· gm _var ≤gm _var_target ≤β 1_high· gm _var Formula (7).

[0166] Where, β 1_low and β 1_high The pre-defined lower and upper limits are used to determine the original device characteristic value gm in the second constraint condition. _target random mismatch value gm _var_target The range.

[0167] In some embodiments, β 1_low and β 1_high The value can also be obtained by looking up the first device lookup table. That is, the first device lookup table can include the channel length L, width W, device characteristic value, mismatch factor, and β for each type of device. 0_low and β 0_high In addition, it may include β 1_low and β 1_high The value of β can be found by looking up the channel length L and width W of the device. 1_low and β 1_high The value of .

[0168] Determining the original device characteristic value gm in the second constraint condition _target and random mismatch value gm _var_target Similarly, other original device characteristic values ​​(e.g., gds, fn, tn, id, and Vt) and corresponding random mismatch values ​​in the second constraint can also be determined.

[0169] 408. The optimization device determines the device dimensions of the second circuit that satisfy the second constraint condition based on the second device lookup table.

[0170] Similar to the implementation of step 404, the tuning device can determine the device dimensions of the second circuit that satisfy the second constraint conditions and Kirchhoff's laws equations based on the second device lookup table. The device dimensions include the channel length and channel width of the device. For a detailed implementation, please refer to the description of step 404.

[0171] Similar to the implementation of step 405, the tuning device can perform DC simulation on the second circuit, and determine the device dimensions of the second circuit that satisfy the second constraint condition based on the simulation results and the second device lookup report, so that the second circuit satisfies the constraint condition and Kirchhoff's laws equations. For a detailed implementation, please refer to the description of step 405.

[0172] 409. The optimization device simulates the second circuit according to the second simulation case and determines whether the specifications of the second circuit meet the requirements.

[0173] For details on how to implement step 409, please refer to the description of step 406.

[0174] In this way, by continuously and iteratively optimizing the small-signal characteristics, that is, optimizing the original device characteristic values ​​and the random mismatch values ​​corresponding to the original device characteristic values ​​in the constraints, the second circuit specification is finally achieved.

[0175] Therefore, this application can solve the problems of complex and long iteration times in the migration process of analog integrated circuits under different processes. Using this process, designers can identify the key device characteristics of the devices in the circuit to be migrated as constraints for circuit optimization, and use software to automatically adjust the device size to achieve matching of key parameters between processes, thereby reducing the design and verification workload of migrating the circuit to different processes.

[0176] It is understood that the aforementioned optimization device, in order to achieve the above functions, includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0177] This application embodiment can divide the above-described optimization device into functional modules based on the method example described above. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0178] When dividing each function into modules according to its corresponding function. Figure 7 A schematic diagram of a possible composition of the tuning device 70 involved in the above embodiments is shown, such as... Figure 7 As shown, the optimization device 70 may include: an extraction unit 701, a determination unit 702, and a simulation unit 703.

[0179] The extraction unit 701 can be used to support the tuning device 70 in performing the above steps 301 and 401, and / or other processes used in the technology described herein.

[0180] The determining unit 702 can be used to support the tuning device 70 in performing the above steps 303, 304, 402, 403, 404, 406, 407, 408, etc., and / or other processes used in the technology described herein.

[0181] The simulation unit 703 can be used to support the device 70 in performing the above steps 305, 405, 409, etc., and / or other processes used in the technology described herein.

[0182] It should be noted that all relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0183] The tuning device 70 provided in this embodiment is used to perform the above-described circuit transplantation method, and thus can achieve the same effect as the above-described implementation method.

[0184] When using integrated units, such as Figure 8 As shown in the figure, this application discloses a tuning device 80, which can be the chip in the above embodiment. The tuning device 80 may include a processing module 801 and a storage module 802.

[0185] The processing module 801 can be used to control and manage the operation of the tuning device 80. For example, it can support the tuning device 80 in executing the functions of the extraction unit 701, the determination unit 702, and the simulation unit 703. The storage module 802 can support the tuning device 80 in storing program code and data. For example, the data stored in the storage module 802 includes the first device lookup table and the second device lookup table in this application, as well as the first constraint condition and the second constraint condition. The processing module 801 can be used to load the program code stored in the storage module 802 to execute the functions of the extraction unit 701, the determination unit 702, and the simulation unit 703.

[0186] Of course, the unit modules in the above-mentioned tuning device 80 include, but are not limited to, the processing module 801 and the storage module 802. For example, the tuning device 80 may also include a power supply module, etc. The power supply module is used to supply power to the tuning device 80.

[0187] The processing module 801 may be a processor or a controller. It may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor may also be a combination of functions that implement computing capabilities, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage module 802 may be a memory.

[0188] The tuning device 80 provided in this embodiment can be Figure 9 The chip 90 shown. The aforementioned processor and memory, etc., can be connected together, for example, via a bus.

[0189] This application also provides a tuning device, including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program code, including computer instructions. When the one or more processors execute the computer instructions, the communication device performs the aforementioned method steps to implement the circuit porting method in the above embodiments.

[0190] This application also provides a computer-readable storage medium storing computer program code. When the processor executes the computer program code, the tuning device performs the circuit transplantation method described in the above embodiments.

[0191] Embodiments of this application also provide a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the circuit transplantation method executed by the tuning device in the above embodiments.

[0192] In this embodiment, the tuning device, computer storage medium, computer program product or chip are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0193] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0194] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0195] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0196] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0197] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0198] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit transplantation method, characterized in that, The method includes: Extract a first device lookup table under the source process and a second device lookup table under the target process. The first device lookup table includes device feature values ​​of various types of devices under the source process, and the second device lookup table includes device feature values ​​of various types of devices under the target process. A second circuit is identified that has a preset correspondence with the first circuit under the source process under the target process, and a second simulation use case corresponding to the first simulation use case under the source process under the target process is identified. Based on the simulation results of DC simulation of the first circuit and the first device lookup table, the device characteristic values ​​of the first circuit are obtained, and the device characteristic values ​​of the first circuit are used as the first constraint condition for selecting the device of the second circuit. The device dimensions of the second circuit that satisfy the first constraint are determined according to the second device lookup table; A full simulation of the second circuit with device dimensions that satisfy the first constraint condition is performed based on the second simulation case.

2. The method according to claim 1, characterized in that, The method further includes: After performing a full simulation of the second circuit and determining that the specifications of the second circuit do not meet the requirements, a second constraint is determined, wherein the device characteristic values ​​in the second constraint are proportional to the device characteristic values ​​in the first constraint. The device dimensions of the second circuit that satisfy the second constraint are determined according to the second device lookup table, or DC simulation is performed on the second circuit to determine the device dimensions of the second circuit that satisfy the second constraint. The second circuit is fully simulated based on the second simulation case to determine whether the specifications of the second circuit meet the requirements.

3. The method according to claim 1 or 2, characterized in that, The first device lookup table under the source process and the second device lookup table under the target process include: Multidimensional voltage, channel length, and width scans are performed on each type of device under various source processes to obtain device characteristic values ​​for each type of device under multidimensional voltage, channel length, and channel width. Multidimensional voltage, channel length, and width scans are performed on each type of device under the target process to obtain device characteristic values ​​for each type of device under the target process with respect to multidimensional voltage, channel length, and channel width.

4. The method according to claim 1 or 2, characterized in that, The first constraint includes device characteristic values ​​of some key components in the second circuit configured by the user. The device characteristics of some key components include transconductance, output transconductance, flicker noise, thermal noise, DC current and threshold voltage. The device characteristic values ​​of some key components are the same as those of the first circuit.

5. The method according to claim 4, characterized in that, The first constraint also includes key information about some components in the second circuit identified by the tuning tool; The key information includes the shutdown information of some devices in the second circuit, the size ratio of some devices, and the symmetry relationship of the input transistors of some devices.

6. The method according to claim 1 or 2, characterized in that, The device feature values ​​in the first device lookup table also include first random mismatch information corresponding to the device feature values ​​of some devices under the source process. The first random mismatch information is used to indicate the mismatch characteristics of the device feature values ​​obtained by simulating the devices under the source process. The device feature values ​​in the second device lookup table also include second random mismatch information corresponding to the device feature values ​​of some devices under the target process. The second random mismatch information is used to indicate the mismatch characteristics of the device feature values ​​obtained by simulating the devices under the target process.

7. The method according to claim 6, characterized in that, The step of obtaining the device characteristic values ​​of the first circuit based on the simulation results of DC simulation of the first circuit and the first device lookup table includes: DC simulation was performed on the first circuit to obtain the original device characteristic values ​​of some components of the first circuit; The random mismatch values ​​of the original device feature values ​​of some devices in the first circuit are determined based on the random mismatch information in the first device lookup table. The device characteristic values ​​of the first circuit include the original device characteristic values ​​of some devices in the first circuit and the random mismatch values ​​of the original device characteristic values ​​of some devices in the first circuit.

8. The method according to claim 7, characterized in that, Determining the device dimensions of the second circuit that satisfy the first constraint condition based on the second device lookup table includes: In the second device lookup table, find the device feature value and random mismatch value that satisfy the original device feature value in the first constraint condition. Among the devices that satisfy the original device feature value and random mismatch value in the first constraint condition, determine the device size of the device that satisfies Kirchhoff's law equation as the device size of the second circuit.

9. The method according to claim 7, characterized in that, Determining the device dimensions of the second circuit that satisfy the first constraint condition based on the second device lookup table includes: DC simulation is performed on the second circuit. Based on the simulation results, the original device characteristic values ​​of some devices in the second circuit are obtained. Based on the second random mismatch information in the second device lookup table, the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit are obtained. When the original device characteristic values ​​of some devices in the second circuit and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit do not satisfy the first constraint condition and Kirchhoff's law equation, the device size of the second circuit is adjusted. DC simulation is performed on the second circuit after the device size is adjusted. Based on the simulation results, the original device characteristic values ​​of some devices in the second circuit after the device size is adjusted are obtained. Random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit after the device size is adjusted are obtained based on the second device lookup table. Determine whether the original device characteristic values ​​of some devices in the second circuit after adjusting the device size and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit satisfy the first constraint condition and the Kirchhoff law equation.

10. The method according to claim 1 or 2, characterized in that, The device characteristic values ​​of the same type of device differ under the source process and the target process.

11. An optimization device, characterized in that, The device includes a processor coupled to a memory; the memory is used to store computer programs or instructions; the processor is used to execute the computer programs or instructions stored in the memory, such that the tuning device performs the following process: Extract a first device lookup table under the source process and a second device lookup table under the target process. The first device lookup table includes device feature values ​​of various types of devices under the source process, and the second device lookup table includes device feature values ​​of various types of devices under the target process. A second circuit is identified that has a preset correspondence with the first circuit under the source process under the target process, and a second simulation use case corresponding to the first simulation use case under the source process under the target process is identified. Based on the simulation results of DC simulation of the first circuit and the first device lookup table, the device characteristic values ​​of the first circuit are obtained, and the device characteristic values ​​of the first circuit are used as the first constraint condition for selecting the device of the second circuit. The device dimensions of the second circuit that satisfy the first constraint are determined according to the second device lookup table; A full simulation of the second circuit with device dimensions that satisfy the first constraint condition is performed based on the second simulation case.

12. The tuning device according to claim 11, characterized in that, When the processor executes a computer program or instructions stored in the memory, the process performed by the tuning device further includes: After performing a full simulation of the second circuit and determining that the specifications of the second circuit do not meet the requirements, a second constraint is determined, wherein the device characteristic values ​​in the second constraint are proportional to the device characteristic values ​​in the first constraint. The device dimensions of the second circuit that satisfy the second constraint are determined according to the second device lookup table, or DC simulation is performed on the second circuit to determine the device dimensions of the second circuit that satisfy the second constraint. The second circuit is fully simulated based on the second simulation case to determine whether the specifications of the second circuit meet the requirements.

13. The tuning device according to claim 11 or 12, characterized in that, When the processor executes a computer program or instruction stored in the memory, including retrieving a first device lookup table under the source process and a second device lookup table under the target process, the specific steps include: Multidimensional voltage, channel length, and width scans are performed on each type of device under various source processes to obtain device characteristic values ​​for each type of device under multidimensional voltage, channel length, and channel width. Multidimensional voltage, channel length, and width scans are performed on each type of device under the target process to obtain device characteristic values ​​for each type of device under the target process with respect to multidimensional voltage, channel length, and channel width.

14. The tuning device according to claim 11 or 12, characterized in that, The first constraint includes device characteristic values ​​of some key components in the second circuit configured by the user. The device characteristics of some key components include transconductance, output transconductance, flicker noise, thermal noise, DC current and threshold voltage. The device characteristic values ​​of some key components are the same as those of the first circuit.

15. The tuning device according to claim 14, characterized in that, The first constraint also includes key information about some components in the second circuit identified by the tuning tool; The key information includes the shutdown information of some devices in the second circuit, the size ratio of some devices, and the symmetry relationship of the input transistors of some devices.

16. The tuning apparatus according to claim 11 or 12, characterized in that, The device feature values ​​in the first device lookup table also include first random mismatch information corresponding to the device feature values ​​of some devices under the source process. The first random mismatch information is used to indicate the mismatch characteristics of the device feature values ​​obtained by simulating the devices under the source process. The device feature values ​​in the second device lookup table also include second random mismatch information corresponding to the device feature values ​​of some devices under the target process. The second random mismatch information is used to indicate the mismatch characteristics of the device feature values ​​obtained by simulating the devices under the target process.

17. The tuning device according to claim 16, characterized in that, The processor, used to execute computer programs or instructions stored in the memory, specifically includes obtaining device characteristic values ​​of the first circuit based on simulation results of DC simulation of the first circuit and the first device lookup table, including: DC simulation was performed on the first circuit to obtain the original device characteristic values ​​of some components of the first circuit; The random mismatch values ​​of the original device feature values ​​of some devices in the first circuit are determined based on the random mismatch information in the first device lookup table. The device characteristic values ​​of the first circuit include the original device characteristic values ​​of some devices in the first circuit and the random mismatch values ​​of the original device characteristic values ​​of some devices in the first circuit.

18. The tuning apparatus according to claim 17, characterized in that, The processor, when executing a computer program or instruction stored in the memory, including determining the device size of the second circuit satisfying the first constraint according to the second device lookup table, specifically includes: In the second device lookup table, find the device feature value and random mismatch value that satisfy the original device feature value in the first constraint condition. Among the devices that satisfy the original device feature value and random mismatch value in the first constraint condition, determine the device size of the device that satisfies Kirchhoff's law equation as the device size of the second circuit.

19. The tuning device according to claim 17, characterized in that, The processor, when executing a computer program or instruction stored in the memory, including determining the device size of the second circuit satisfying the first constraint according to the second device lookup table, specifically includes: DC simulation is performed on the second circuit. Based on the simulation results, the original device characteristic values ​​of some devices in the second circuit are obtained. Based on the second random mismatch information in the second device lookup table, the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit are obtained. When the original device characteristic values ​​of some devices in the second circuit and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit do not satisfy the first constraint condition and Kirchhoff's law equation, the device size of the second circuit is adjusted. DC simulation is performed on the second circuit after the device size is adjusted. Based on the simulation results, the original device characteristic values ​​of some devices in the second circuit after the device size is adjusted are obtained. Random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit after the device size is adjusted are obtained based on the second device lookup table. Determine whether the original device characteristic values ​​of some devices in the second circuit after adjusting the device size and the random mismatch values ​​of the original device characteristic values ​​of some devices in the second circuit satisfy the first constraint condition and the Kirchhoff law equation.

20. The tuning apparatus according to claim 11 or 12, characterized in that, The device characteristic values ​​of the same type of device differ under the source process and the target process.

21. A computer-readable storage medium, characterized in that, Includes computer instructions that, when executed on an electronic device, cause the electronic device to perform the method described in any one of claims 1-10.

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