An analyser for capturing voltage drops across resistors and a method of analysis thereof

Abstract

An analyzer for capturing resistance voltage drop and an analysis method thereof are provided. The analysis method for capturing resistance voltage drop includes receiving circuit layout information and package model information, parsing a plurality of circuit blocks corresponding to a plurality of bump current sources in a circuit according to the circuit layout information and the package model information, calculating at least one critical circuit block according to current demand values of each bump current source and each corresponding circuit block, and analyzing a clock tree architecture of the at least one critical circuit block to obtain design structure adjustment information.

Description

Technical Field

[0001] This invention relates to an analyzer and method for capturing resistance voltage drop, and more particularly to an analyzer and method for capturing resistance voltage drop that can reduce analysis time. Background Technology

[0002] In circuit design, voltage drops across resistors often cause abnormal circuit operation. Previously, there were no specific mitigation solutions available for capturing voltage drops, and resistor voltage drop analysis (IR analysis) was typically too time-consuming, and the provided vectors were not representative, making it impossible to perform a comprehensive analysis of resistor voltage drops across the circuit. Summary of the Invention

[0003] This invention relates to an analyzer and analysis method for capturing resistor voltage drop, which can effectively obtain circuit design structure adjustment information.

[0004] According to an embodiment of the present invention, the method for analyzing the voltage drop across a captured resistor includes: receiving circuit layout information and package model information of a circuit; resolving multiple circuit blocks corresponding to multiple bump current sources in the circuit based on the circuit layout information and package model information; calculating at least one critical circuit block based on the current demand values ​​of each bump current source and the corresponding circuit block; and analyzing the clock tree architecture of the at least one critical circuit block to obtain design structure adjustment information.

[0005] According to an embodiment of the present invention, an analyzer for capturing resistor voltage drop includes a transmission interface and a controller. The transmission interface is used to receive circuit layout information and package model information of the circuit. The controller is coupled to the transmission interface and is used to: parse multiple circuit blocks corresponding to multiple bump current sources in the circuit based on the circuit layout information and package model information; calculate at least one critical circuit block based on the current demand values ​​of each bump current source and the corresponding circuit block; and analyze the clock tree architecture for the at least one critical circuit block to obtain design structure adjustment information.

[0006] Based on the above, the capture resistor voltage drop analysis method of the present invention can avoid performing time-consuming voltage drop analysis operations by defining high-risk areas of capture voltage drop on the circuit, and can comprehensively evaluate the voltage drop risk of the circuit scan chain capture mode. Attached Figure Description

[0007] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0008] Figure 1 This is a flowchart of a method for analyzing the captured resistance voltage drop according to an embodiment of the present invention;

[0009] Figure 2 A flowchart illustrating an analysis method for capturing resistor voltage drop according to another embodiment of the present invention;

[0010] Figure 3 as well as Figure 4 A schematic diagram illustrating an implementation of the modeled operation of a convex current source;

[0011] Figure 5 A waveform diagram illustrating the required current of a circuit component under a clock tree structure within a circuit block;

[0012] Figure 6 This is a flowchart of the critical circuit block identification process according to an embodiment of the present invention;

[0013] Figures 7A to 7C These are schematic diagrams of the clock tree architecture of circuit components that contribute large current peaks in the critical circuit blocks of this invention, and the corresponding design structure adjustment information.

[0014] Figure 8 This is a schematic diagram of an analyzer for capturing resistor voltage drop according to an embodiment of the present invention.

[0015] Explanation of icon numbers

[0016] 310: Current calculator;

[0017] 400: Circuit;

[0018] 410~419: Convex point current source;

[0019] 510~540: Waveform;

[0020] 710, 720, 730, 710', 720', 730': Clock tree architecture;

[0021] 711, 712, 741, 742, 751, 771, 772: Integrated control doors;

[0022] 721, 722, 731, 732, 761, 762: Logic circuits;

[0023] 800: Analyzer for capturing voltage drop across resistance;

[0024] 810: Controller;

[0025] 820: Transmission interface;

[0026] AI: Circuit layout information;

[0027] A2: Encapsulates model information;

[0028] A3: Design revision plan;

[0029] A4: ATPG's Restriction Plan;

[0030] CLK1, CLK2, CLK3: Clock signals;

[0031] G1-1, G1-2, G2, G2-1, G2-2, G3, G3-1, G3-2: Triggers;

[0032] IFO: Current Information;

[0033] PI: Assumption Agreement;

[0034] S110~S140, S210~S230: Steps of analysis;

[0035] S610~S650: Identification steps. Detailed Implementation

[0036] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0037] Please refer to Figure 1 , Figure 1 This is a flowchart of a method for analyzing captured IR drop according to an embodiment of the present invention. In step S110, circuit layout information and package model information of the received circuit are analyzed. The package model information is a circuit netlist containing information on resistance, capacitance, and inductance. In this embodiment, the circuit layout information can be received from a DEF (Design Exchange Format) or LEF (Library Exchange Format) file of the received circuit. Next, in step S120, multiple circuit blocks corresponding to multiple bump current sources in the circuit can be parsed based on the received circuit layout information and package model information. The circuit may include multiple bump current sources. Each bump current source can drive a corresponding circuit block. The driven circuit block may include multiple flip-flops, and these flip-flops may belong to one or more clock tree architectures.

[0038] In step S130, each convex current source is analyzed, and at least one critical circuit block is calculated based on the current demand values ​​of each convex current source and its corresponding circuit block. In this embodiment, the current demand values ​​for each circuit block corresponding to each convex current source are calculated one by one. It is then determined whether these current demand values ​​are excessive, and one or more corresponding circuit blocks are designated as critical circuit blocks.

[0039] Furthermore, in step S140, the clock tree architecture of one or more critical circuit blocks is analyzed to obtain design structure adjustment information.

[0040] In this embodiment, the design structure adjustment information can be used to provide designers with adjustments to the circuit architecture of critical circuit blocks, and can also be used as a basis for setting constraints for electronic design automation (EDA) applications, such as Automatic Test Pattern Generation (ATPG).

[0041] In this embodiment, based on the design structure adjustment information, the current requirement of critical circuit blocks in the circuit can be reduced, thereby mitigating the impact of the trap resistor voltage drop on circuit performance. Furthermore, the trap resistor voltage drop analysis method in this embodiment can identify critical circuit blocks. In full-range circuit analysis, design structure adjustment strategies can be quickly calculated for these critical circuit blocks, effectively improving circuit design efficiency.

[0042] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating a method for analyzing the voltage drop across a captured resistor according to another embodiment of the present invention. The circuit layout information A1 and package model information A2 from a DEF (Design Exchange Format) or LEF (Library Exchange Format) file can be received. Next, in step S210, modeling of the spur current source in the circuit can be performed based on the circuit layout information A1 and package model information A2. For details, please refer to... Figure 3 as well as Figure 4 This is a schematic diagram illustrating an implementation method for modeling the operation of a convex current source. Figure 3 In the modeling of the convex current source, the current supply state of each convex current source can be calculated by the current calculator 310 based on the circuit layout information A1, the package model information A2, and the assumption agreement P1. Figure 4In circuit 400, there are multiple spur current sources 410-419. These spur current sources 410-419 are configured at multiple locations within circuit 400. Each of the multiple spur current sources 410-419 supplies operating current to multiple circuit blocks, and each circuit block includes multiple flip-flops, which can belong to one or more different clock tree structures. Taking spur current source 410 as an example, the circuit block corresponding to spur current source 410 has multiple flip-flops REG1-REG3, and flip-flops REG1-REG3 can each belong to three different clock tree structures.

[0043] The current calculator 310 can calculate the current demand value for each of the triggers REG1 to REG3, and also calculate the current demand value for the circuit block corresponding to the spur current source 410. The current calculator 310 can be implemented using a controller with computational capabilities. Please refer to [link / reference needed]. Figure 5 This is a waveform diagram illustrating the current demand of circuit components under a clock tree structure in a circuit block. Waveform 510 represents the operating current generated by the clock signal corresponding to the flip-flop in the clock tree structure; waveform 520 represents the operating current generated by the combinational logic circuit; waveform 530 represents the operating current generated by the data transmission and reception operations; and waveform 540 is the sum of the operating currents of waveforms 510 to 530.

[0044] It is worth mentioning that the current calculator 310 receives clock signals and data transmission and reception operation protocols based on the assumed protocol P1, which is a default clock tree structure, such as the clock signal toggle rate. Through the calculation of various demand currents, the current calculator 310 can generate current information IFO, which includes multiple demand current values ​​corresponding to each convex current source 410 to 419 under different clock signal toggle rates.

[0045] In this embodiment, the current information IFO can be stored in a memory and form a lookup table.

[0046] Please refer to the above again. Figure 2 Following step S210, step S220 performs critical circuit block clock analysis. Specifically, based on the current information IFO obtained in step S210, the critical circuit block identification process can be performed. Please refer to [link / reference needed]. Figure 6 , Figure 6 This is a flowchart of the critical circuit block identification action according to an embodiment of the present invention. In step S610, the bump current source i (the i-th bump current source) can be analyzed, where i = 1 in the initial state. In step S620, it is determined whether the current demand value of bump current source i is less than a reference threshold. The reference threshold is a preset value used as the basis for determining whether the voltage drop across the capture resistor is too large.

[0047] When the current demand value of bump current source i is less than the reference threshold, the value of i is incremented by 1 and steps S610 and S620 are re-executed to analyze the next bump current source i. When the current demand value of bump current source i is not less than the reference threshold, the circuit block corresponding to this bump current source i can be set as a critical circuit block, and step S630 is executed.

[0048] In step S630, current contributor identification can be performed on the critical circuit block. Circuit components within the critical circuit block that contribute significantly to the current peak value of bump current source i are identified. Then, in step S640, clock tree architecture analysis is performed on the identified circuit components with significant current peak contributions.

[0049] In step S650, it is determined whether the analysis of the last bump current source has been completed. If not, the analysis action of the next bump current source is executed. If so, the entire action process ends.

[0050] Please refer to it again. Figure 2 Following step S220, in step S230, it can be based on... Figure 6 The process generates a clock tree architecture to obtain strategies for reducing capture voltage drop. Please refer to [the relevant documentation / reference]. Figures 7A to 7C , Figures 7A to 7C These are schematic diagrams of the clock tree architecture of circuit components that contribute large current peaks in the critical circuit blocks of this invention, and the corresponding design structure adjustment information.

[0051] exist Figure 7A In the clock tree architecture 710, the clock signal CLK1 is corresponding to the clock tree architecture 710. Within the clock tree architecture 710, integrated control gates (ICGs) 711 and 712 control flip-flops G1-1 and G1-2, respectively. When the first quantities of flip-flops G1-1 and G1-2 controlled by the integrated control gates (ICGs) 711 and 712 are both less than a preset reference value k, the resulting design structure adjustment information can be used to add logic circuits 721 and 722 to control the integrated control gates (ICGs) 711 and 712, respectively. The logic circuits 721 and 722 then enable the integrated control gates 711 and 712 to be activated in a time-division multiplexing manner, generating a new clock tree architecture 710'.

[0052] exist Figure 7BIn the clock tree architecture 720, the clock signal CLK2 is corresponding to the clock tree architecture 720. In the clock tree architecture 720, when the number of multiple flip-flops G2 not controlled by the integrated control gates exceeds a preset reference value k, the resulting design structure adjustment information can be used to split the flip-flops G2 into multiple parts, G2-1 and G2-2, and provide multiple auxiliary integrated control gates (ICGs) 741 and 742 to be coupled between the clock signal CLK2 and the flip-flops G2-1 and G2-2, respectively. Furthermore, by adding multiple logic circuits 731 and 732 to be coupled to the auxiliary integrated control gates (ICGs) 741 and 742, and controlling the auxiliary integrated control gates (ICGs) 741 and 742, a new clock tree architecture 720' is generated. The logic circuits 731 and 732 are used to enable the auxiliary integrated control gates (ICGs) 741 and 742 to be activated in a time-division multiplexing manner.

[0053] exist Figure 7C In the clock tree architecture 730, the clock signal CLK3 is corresponding to the clock tree structure 730. Within the clock tree architecture 730, the integrated control gate (ICG) 751 controls the flip-flops G3. When the first number of flip-flops G3 controlled by the integrated control gate (ICG) 751 exceeds a reference value k, the resulting design structure adjustment information can be used to split the flip-flops G3 into a first part (flip-flops G3-1) and a second part (flip-flops G3-2), and to add integrated control gates (ICGs) 771 and 772, as well as logic circuits 761 and 762. Integrated control gates (ICGs) 771 and 772 are coupled to the integrated control gate (ICG) 751, and respectively coupled to flip-flops G3-1 and G3-2, generating a new clock tree architecture 730'. Logic circuits 761 and 762 control the integrated control gates 771 and 772 respectively, so that the integrated control gates 771 and 772 are activated in a time-division multiplexing manner.

[0054] Please refer to the above again. Figure 2 Based on the strategy for reducing capture voltage drop obtained in step S230, a design modification plan A3 and an ATPG constraint plan A4 can be generated.

[0055] Please refer to the following: Figure 8 , Figure 8 This is a schematic diagram of an analyzer for capturing resistor voltage drop according to an embodiment of the present invention. The analyzer 800 for capturing resistor voltage drop includes a transmission interface 820 and a controller 810. The transmission interface 820 and the controller 810 are coupled to each other. The transmission interface 820 can be used to receive circuit layout information and package model information of the circuit. The controller 810 can be used to perform actions such as... Figure 1 The steps S120 to S140 are shown, and design structure adjustment information is obtained.

[0056] In this embodiment, the controller 810 can be designed using a Hardware Description Language (HDL) or any other digital circuit design method well known to those skilled in the art, and implemented as a hardware circuit using a Field Programmable Gate Array (FPGA), Complex Programmable Logic Device (CPLD), or Application-Specific Integrated Circuit (ASIC). The transmission interface 820 can be any form of wired or wireless communication interface well known to those skilled in the art, without specific limitations.

[0057] In summary, this invention defines critical circuit blocks by analyzing the required current values ​​of each convex current source. Furthermore, it performs structural adjustments and analysis on high-risk areas of the capture voltage drop on the critical circuit blocks, thereby reducing the time required for voltage drop analysis and enabling a comprehensive assessment of the voltage drop risk in the circuit scan capture mode.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for analyzing voltage drop across a captured resistor, characterized in that, include: Circuit layout information and packaging model information of the receiving circuit; Based on the circuit layout information and the packaging model information, the multiple circuit blocks corresponding to the multiple bump current sources in the circuit are analyzed. At least one critical circuit block is calculated based on the current demand values ​​of each of the aforementioned convex current sources and the corresponding circuit blocks, including: Calculate multiple operating currents for each of the circuit blocks, and generate the current requirement value corresponding to each of the circuit blocks based on the multiple operating currents; and Determine whether the current demand value of each circuit block is greater than a reference threshold, so as to set each circuit block as the at least one critical circuit block; and Analyzing at least one clock tree architecture for at least one critical circuit block to obtain design structure adjustment information includes: In the at least one clock tree architecture, the analysis considers the first number of first flip-flops controlled by each of the plurality of integrated control gates and the second number of second flip-flops not controlled by the integrated control gates; and The design structure adjustment information is generated based on the relationship between the first quantity and the reference value, and based on the relationship between the second quantity and the reference value.

2. The analytical method according to claim 1, characterized in that, The plurality of operating currents include a first operating current for data passing through each of the circuit blocks; a second operating current generated by the combinational logic circuitry of each of the circuit blocks; and a third operating current generated by each of the circuit blocks receiving a clock signal.

3. The analytical method according to claim 1, characterized in that, When the first quantity is less than the reference value, the design structure adjustment information is provided to: Add multiple logic circuits to control the multiple integrated control gates separately; and The plurality of logic circuits enable the plurality of integrated control gates to be activated in a time-sharing manner.

4. The analytical method according to claim 1, characterized in that, When the first quantity is greater than the reference value, the design structure adjustment information is provided to: Multiple auxiliary integrated control gates are added after each of the aforementioned integrated control gates, wherein the multiple first triggers are divided into multiple parts and respectively coupled to the multiple auxiliary integrated control gates; Multiple logic circuits are added to control the multiple auxiliary integrated control gates respectively; as well as The plurality of logic circuits enable the plurality of auxiliary integrated control gates to be activated in a time-sharing manner.

5. The analytical method according to claim 1, characterized in that, When the second quantity is greater than the reference value, the design structure adjustment information is provided to: Multiple auxiliary integrated control gates are provided to be coupled between a clock signal and the multiple second flip-flops, wherein the multiple second flip-flops are divided into multiple parts and respectively coupled to the multiple auxiliary integrated control gates; Multiple logic circuits are added to control the multiple auxiliary integrated control gates respectively; as well as The plurality of logic circuits enable the plurality of auxiliary integrated control gates to be activated in a time-sharing manner.

6. An analyzer for capturing resistance voltage drop, characterized in that, include: The transmission interface is used to receive circuit layout information and package model information. as well as The controller, coupled to the transmission interface, is used to: Based on the circuit layout information and the packaging model information, the multiple circuit blocks corresponding to the multiple bump current sources in the circuit are analyzed. At least one critical circuit block is calculated based on the current demand values ​​of each of the aforementioned convex current sources and the corresponding circuit blocks, including: Calculate multiple operating currents for each of the circuit blocks, and generate the current requirement value corresponding to each of the circuit blocks based on the multiple operating currents; and Determine whether the current demand value of each circuit block is greater than a reference threshold, so as to set each circuit block as the at least one critical circuit block; and Analyzing at least one clock tree architecture for at least one critical circuit block to obtain design structure adjustment information includes: In the analysis of the at least one clock tree architecture, each of the plurality of integrated control gates and a first number of the plurality of first flip-flops controlled by them, and a second number of the plurality of second flip-flops not controlled by the integrated control gates; and The design structure adjustment information is generated based on the relationship between the first quantity and the reference value, and based on the relationship between the second quantity and the reference value.

7. The analyzer for capturing resistance voltage drop according to claim 6, characterized in that, The plurality of operating currents include a first operating current for data passing through each of the circuit blocks; a second operating current generated by the combinational logic circuitry of each of the circuit blocks; and a third operating current generated by each of the circuit blocks receiving a clock signal.

8. The analyzer for capturing resistance voltage drop according to claim 7, characterized in that, When the first quantity is less than the reference value, the design structure adjustment information provided by the controller includes: Add multiple logic circuits to control the multiple integrated control gates separately; and The plurality of logic circuits enable the plurality of integrated control gates to be activated in a time-sharing manner.

9. The analyzer for capturing resistance voltage drop according to claim 7, characterized in that, When the first quantity is greater than the reference value, the design structure adjustment information provided by the controller includes: Multiple auxiliary integrated control gates are added after each of the aforementioned integrated control gates, wherein the multiple first triggers are divided into multiple parts and respectively coupled to the multiple auxiliary integrated control gates; Multiple logic circuits are added to control the multiple auxiliary integrated control gates respectively; and The plurality of logic circuits enable the plurality of auxiliary integrated control gates to be activated in a time-sharing manner.

10. The analyzer for capturing resistance voltage drop according to claim 7, characterized in that, When the second quantity is greater than the reference value, the design structure adjustment information provided by the controller includes: Multiple auxiliary integrated control gates are provided to be coupled between a clock signal and the multiple second flip-flops, wherein the multiple second flip-flops are divided into multiple parts and respectively coupled to the multiple auxiliary integrated control gates; Multiple logic circuits are added to control the multiple auxiliary integrated control gates respectively; and The plurality of logic circuits enable the plurality of auxiliary integrated control gates to be activated in a time-sharing manner.

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