Data caching method, apparatus and electronic device

Abstract

The application discloses a data caching method and device and electronic equipment, and belongs to the technical field of image processing. The method comprises the following steps: determining an image processing stage according to an instruction signal, wherein the image processing stage comprises an initialization stage and a pixel processing stage; reading parameter values in a random access memory (RAM) according to the image processing stage, and caching the read parameter values into a target register group; wherein the RAM stores a parameter table, and the parameter values in the parameter table are used for bilinear interpolation calculation; the target register group is at least one of six register groups, and the six register groups are used for caching two rows of parameter values in the parameter table for bilinear interpolation calculation.

Description

Technical Field

[0001] This application belongs to the field of image processing technology, specifically relating to a data caching method, apparatus, and electronic device. Background Technology

[0002] In the field of integrated circuits, pixel-level processing of video streams typically involves storing the processing criteria (parameter values) for all pixels in a parameter table. When a pixel arrives at a certain location, its corresponding parameter value is retrieved from the parameter table, and this value is used to process the pixel. Considering that a full-image-size parameter table would consume a significant amount of storage resources, and given the similarity between adjacent parameters in the table, the existing strategy is to perform interval sampling (downsampling) on ​​the full-image-size parameters before storing them. During processing, the full-image-size parameter table is approximately reconstructed based on the stored parameter table and an appropriate interpolation method (upsampling).

[0003] Bilinear interpolation is the most common interpolation method. It requires four parameter values ​​spanning two rows and two columns of a parameter table as the source data (parameter values) for calculation. However, due to power consumption considerations, the parameter table needs to be stored in a single-port RAM (only one data can be output at a time). Therefore, the caching scheme of the source data greatly affects the processing efficiency of the video stream.

[0004] There are two common source data caching schemes: one is the register caching scheme, which reads parameter values ​​directly from RAM line by line and caches them in registers. However, the drawback of this scheme is that caching parameter values ​​line by line requires tens of thousands of bits of register resources, resulting in a large area footprint. The other is the block storage scheme, which divides the parameter values ​​into four blocks based on the parity of the horizontal and vertical axes in the parameter table and stores them in four separate RAMs. However, this scheme increases the RAM used to store the parameter table from one to four, thus dividing previously shared resources into four, leading to an increase in area and power consumption. Summary of the Invention

[0005] The purpose of this application is to provide a data caching method, apparatus, and electronic device that can solve the problems of large storage hardware footprint and high power consumption in existing data caching solutions.

[0006] In a first aspect, embodiments of this application provide a data caching method, the method comprising:

[0007] Based on the indication signal, the current stage of image processing is determined, which includes: an initialization stage and a pixel processing stage;

[0008] According to the current stage of image processing, read the parameter values ​​from the random access memory (RAM) and cache the read parameter values ​​in the target register group;

[0009] The RAM stores a parameter table, and the parameter values ​​in the parameter table are used for bilinear interpolation calculation.

[0010] The target register group is at least one of the six register groups;

[0011] The six register groups include: the first register group, the second register group, the third register group, the fourth register group, the fifth register group, and the sixth register group;

[0012] Specifically, the first register group is used to cache the parameter value in the first row and first column of the four parameter values ​​in the two rows and two columns of the parameter table used for bilinear interpolation calculation; the second register group is used to cache the parameter value in the first row and second column of the four parameter values; the third register group is used to cache the parameter value in the first row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table; the fourth register group is used to cache the parameter value in the second row and first column of the four parameter values; the fifth register group is used to cache the parameter value in the second row and second column of the four parameter values; and the sixth register group is used to cache the parameter value in the second row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table.

[0013] Secondly, embodiments of this application provide a data caching device, including:

[0014] The first processing module is used to determine the current stage of image processing based on the indication signal. The current stage of image processing includes: an initialization stage and a pixel processing stage.

[0015] The second processing module is used to read parameter values ​​from the random access memory (RAM) according to the stage of image processing, and cache the read parameter values ​​into the target register group;

[0016] The RAM stores a parameter table, and the parameter values ​​in the parameter table are used for bilinear interpolation calculation.

[0017] The target register group is at least one of the six register groups;

[0018] The six register groups include: the first register group, the second register group, the third register group, the fourth register group, the fifth register group, and the sixth register group;

[0019] Specifically, the first register group is used to cache the parameter value in the first row and first column of the four parameter values ​​in the two rows and two columns of the parameter table used for bilinear interpolation calculation; the second register group is used to cache the parameter value in the first row and second column of the four parameter values; the third register group is used to cache the parameter value in the first row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table; the fourth register group is used to cache the parameter value in the second row and first column of the four parameter values; the fifth register group is used to cache the parameter value in the second row and second column of the four parameter values; and the sixth register group is used to cache the parameter value in the second row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table.

[0020] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, wherein the memory stores a program or instructions executable on the processor, and the program or instructions, when executed by the processor, implement the steps of the data caching method as described in the first aspect.

[0021] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the data caching method as described in the first aspect.

[0022] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the data caching method as described in the first aspect.

[0023] In a sixth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the data caching method as described in the first aspect.

[0024] In this embodiment, the image processing stage is determined according to an indication signal. The image processing stage includes an initialization stage and a pixel processing stage. Based on the image processing stage, parameter values ​​are read from the random access memory (RAM) and cached in a target register group. The RAM stores a parameter table, and the parameter values ​​in the parameter table are used for bilinear interpolation calculation. The target register group is at least one of six register groups, including a first register group, a second register group, a third register group, a fourth register group, a fifth register group, and a sixth register group. The first register group is used to cache the parameter values ​​in the parameter table that are located in the first row and first column from the four parameter values ​​in the two rows and two columns used for bilinear interpolation calculation. The parameter values ​​are stored in a series of register groups. The second register group is used to cache the parameter value located in the first row and second column of the four parameter values. The third register group is used to cache the parameter value located in the first row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table. The fourth register group is used to cache the parameter value located in the first row and first column of the four parameter values. The fifth register group is used to cache the parameter value located in the second row and second column of the four parameter values. The sixth register group is used to cache the parameter value located in the second row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table. In this way, based on the characteristics of video stream timing and bilinear interpolation calculation in image processing, the parameter table is stored in a single block of single-port RAM and the parameter resources are cached by six register groups, which can significantly reduce the area and power consumption. Attached Figure Description

[0025] Figure 1 This is one of the flowcharts illustrating the data caching method provided in the embodiments of this application;

[0026] Figure 2 This is a schematic diagram of the data caching execution steps in the initialization stage of the image processing in this embodiment of the application;

[0027] Figure 3 This is a schematic diagram showing the positional relationship between image pixels and parameter tables in an embodiment of this application;

[0028] Figure 4 This is one of the schematic diagrams illustrating the data caching execution steps in the pixel processing stage of the image processing embodiment of this application;

[0029] Figure 5 This is the second schematic diagram of the data caching execution steps in the pixel processing stage of this application embodiment;

[0030] Figure 6 This is the third schematic diagram of the data caching execution steps in the pixel processing stage of this application embodiment;

[0031] Figure 7 This is a schematic diagram illustrating the storage pattern of parameter values ​​in RAM according to an embodiment of this application.

[0032] Figure 8 This is a schematic diagram of the logic circuit corresponding to the changing pattern of the RAM read address in an embodiment of this application;

[0033] Figure 9 This is a schematic diagram illustrating the implementation result of the data caching method provided in this application embodiment;

[0034] Figure 10 This is a schematic diagram of the overall implementation flow of the data caching method according to an embodiment of this application;

[0035] Figure 11 This is a schematic diagram of the data caching device provided in the embodiments of this application;

[0036] Figure 12 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;

[0037] Figure 13 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0039] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0040] The data caching method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0041] like Figure 1 The diagram shown is a flowchart illustrating a data caching method provided in an embodiment of this application. This method may specifically include:

[0042] Step 101: Determine the current stage of image processing based on the indication signal. The current stage of image processing includes: initialization stage and pixel processing stage.

[0043] The image processing in this embodiment is pixel-level image processing. The initialization phase refers to the stage at the beginning of an image frame, before pixel processing. Both the initialization phase and the pixel processing phase involve data caching.

[0044] An image is composed of many pixels, and each pixel in an image has a corresponding pixel value. The pixel processing stage here refers to combining each pixel value in the image with its corresponding processing parameter value (such as multiplication) to obtain the final processing result.

[0045] Step 102: Based on the current stage of image processing, read the parameter values ​​from the random access memory (RAM) and cache the read parameter values ​​in the target register group;

[0046] The RAM stores a parameter table, and the parameter values ​​in the parameter table are used for bilinear interpolation calculation; the target register group is at least one of the six register groups.

[0047] It should be noted that the parameter reading and caching methods differ depending on the stage of image processing, as detailed in the following embodiments. These methods are primarily designed based on the characteristics of video stream timing and bilinear interpolation calculations in image processing, aiming to meet the source data caching requirements of bilinear interpolation. By storing the parameter table in a single-port RAM and caching parameter resources in six registers, the area and power consumption can be significantly reduced.

[0048] Optionally, see Figure 2 The six register groups include: first register group LU, second register group RU, third register group BU, fourth register group LD, fifth register group RD and sixth register group BD;

[0049] Specifically, the first register group LU is used to cache the parameter value in the first row and first column (top left position in the figure) of the four parameter values ​​in the two rows and two columns of the parameter table used for bilinear interpolation calculation; the second register group RU is used to cache the parameter value in the first row and second column (top right position in the figure); the third register group BU is used to cache the parameter value in the first row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table; the fourth register group LD is used to cache the parameter value in the second row and first column (bottom left position in the figure); the fifth register group RD is used to cache the parameter value in the second row and second column (bottom right position in the figure); and the sixth register group BD is used to cache the parameter value in the second row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table.

[0050] Here, the first register group LU, the second register group RU, the fourth register group LD, and the fifth register group RD each cache the four parameter values ​​(two rows and two columns) used for bilinear interpolation calculations in the parameter table. The coordinate positions corresponding to these four parameter values ​​form a rectangle. The parameter value (used during pixel processing) for the pixel located within the rectangle can be obtained based on these four parameter values. The parameter values ​​cached in the third register group BU and the sixth register group BD are used to update the cached parameter values ​​in the above four register groups in some cases (such as when the pixel to be processed is not within the rectangle formed by the coordinate positions corresponding to the current four parameter values).

[0051] In an optional embodiment of this application, step 101, which determines the current stage of image processing based on the indication signal, may specifically include:

[0052] When the frame synchronization signal is 1, the image processing stage is determined to be the initialization stage, which is the stage before pixel processing.

[0053] In other words, when the frame synchronization signal fsync_in is 1, it indicates the start of a frame of image, at which point the initialization mode is entered, which is the initialization stage before pixel processing. The initialization stage prepares for the arrival of the first few pixels of the first row of the image by pre-caching parameter values. See the following examples section for the specific implementation process of the cached data.

[0054] After the initialization phase is completed, the image processing phase is determined and the pixel processing phase begins.

[0055] Here, different signal indicators can be used to quickly determine the specific stage of image processing.

[0056] In an optional embodiment, step 102 above, which involves reading parameter values ​​from the random access memory (RAM) according to the current stage of image processing and caching the read parameter values ​​into the target register group, may specifically include:

[0057] When the image processing stage is the initialization stage, the parameter values ​​in the RAM are read three times in succession, and the read parameter values ​​are cached in the first register group, the second register group and the third register group respectively.

[0058] See Figure 2 As shown, the parameter values ​​are read from RAM three times in succession and cached in the first register group LU, the second register group RU, and the third register group BU, respectively.

[0059] The 0th read occurs in the next clock cycle of the frame synchronization signal fsync_in, the 1st read occurs when the first pixel of the first row of the image arrives, and the 2nd read occurs when the second pixel of the first row of the image arrives.

[0060] The reason why parameter values ​​are cached only in the first register group LU, the second register group RU, and the third register group BU during the initialization phase is determined by the characteristics of video stream timing and bilinear interpolation calculation. Specifically, the initialization phase prepares for the arrival of the first few pixels of the first row of the image. Since the first row of image pixels coincides with the first row of the parameter table in the horizontal direction, the parameter values ​​corresponding to the pixels in the first row only need to be calculated using the parameter values ​​of the first row of the parameter table through bilinear interpolation. Therefore, the initialization phase only needs to cache parameter values ​​in the first register group LU, the second register group RU, and the third register group BU.

[0061] In an optional embodiment, step 102 above, which involves reading parameter values ​​from the random access memory (RAM) according to the current stage of image processing and caching the read parameter values ​​into the target register group, may specifically include:

[0062] a) When the image processing stage is the pixel processing stage, and the position of the pixel to be processed in the image is more than the position of the first column parameter value in the parameter table, update the parameter value cached in the relevant register group, wherein the first column parameter value is adjacent to the second column parameter value and is located to the right of the second column parameter value, and the first column parameter value and the second column parameter value are the two columns of parameter values ​​currently used for bilinear interpolation calculation;

[0063] b) After the parameter value is updated, read the parameter value in RAM N times and cache the parameter value read each time in the target register group, where N is a positive integer greater than or equal to 1.

[0064] Step a) Update the parameter values ​​in the relevant register set cache, which may specifically include:

[0065] a-1) If the pixel to be processed is located in the first row of the image, then the parameter value cached in the second register group is transferred to the first register group; and the parameter value cached in the third register group is transferred to the second register group.

[0066] Accordingly, step b) involves reading the parameter value from RAM N times after the parameter value is updated, and caching each read parameter value into the target register group. This can specifically include:

[0067] When the pixel to be processed is located in the first row of the image and is not at the end of the row, after the parameter value is updated, the parameter value in the RAM is read once and the read parameter value is cached in the third register group.

[0068] This situation can be seen in Figure 3 This diagram illustrates the positional relationship between image pixels and the parameter table. For example, if the pixel to be processed is pixel 03 in the first row of the image (0 represents the row number, and 3 represents the column number), the position of the first column of parameter values ​​(i.e., the rightmost column of the two columns of parameter values ​​currently used for bilinear interpolation calculation) refers to the position of the column of parameter values ​​between 02 and 03. Since pixel 03 exceeds this column's position, the first two parameter values ​​of this row (the first row of the parameter table) cannot be used for bilinear interpolation calculation. That is, the parameter values ​​cached in the first register group LU and the second register group RU need to be updated. See [link to documentation]. Figure 4 The left side illustrates the specific update process as follows:

[0069] The parameter values ​​cached in the second register group RU are transferred to the first register group LU; the parameter values ​​cached in the third register group BU are transferred to the second register group RU.

[0070] In other words, the parameter value cached in the second register group RU needs to be used as bilinear interpolation to calculate the parameter value located in the upper left position, cached in the first register group LU, and replace the original cached parameter value; the parameter value cached in the third register group BU needs to be used as bilinear interpolation to calculate the parameter value located in the upper right position, cached in the second register group RU, and replace the original cached parameter value.

[0071] After the parameter value is updated, the parameter value in the RAM is read once, and the read parameter value is cached in the third register group BU. See [link to relevant documentation]. Figure 5 The left side illustrates how this maximizes time savings.

[0072] Step a) Update the parameter values ​​in the relevant register set cache, which may specifically include:

[0073] a-2) If the pixel to be processed is located in a row other than the first row of the image, the parameter value cached in the second register group is transferred to the first register group, and the parameter value cached in the fifth register group is transferred to the fourth register group; the parameter value cached in the third register group is transferred to the second register group, and the parameter value cached in the sixth register group is transferred to the fifth register group.

[0074] Accordingly, step b) involves reading the parameter value from RAM N times after the parameter value is updated, and caching each read parameter value into the target register group. This can specifically include:

[0075] When the pixel to be processed is located in a row other than the first row of the image, and the pixel to be processed is not at the end of the row, after the parameter value is updated, the parameter value in the RAM is read twice, and the read parameter value is cached in the third register group and the sixth register group respectively.

[0076] See also Figure 3 To explain further, for example, if the pixel to be processed is pixel 13 in the second row of the image, the position of the first column of parameter values ​​(i.e., the rightmost column of the two columns of parameter values ​​currently used for bilinear interpolation calculation) refers to the position of the column of parameter values ​​between 12 and 13. Since pixel 013 exceeds this column position, the first four parameter values ​​of these two rows and two columns (the four parameter values ​​at the intersection of the first row, second row, first column, and second column of the parameter table) cannot be used for bilinear interpolation calculation. That is, the parameter values ​​cached in the first register group LU, the second register group RU, the fourth register group LD, and the fifth register group RD need to be updated. See [link to documentation]. Figure 4 The right side illustrates the specific update process as follows:

[0077] The parameter values ​​cached in the second register group are transferred to the first register group, and the parameter values ​​cached in the fifth register group are transferred to the fourth register group.

[0078] The parameter values ​​cached in the third register group are transferred to the second register group, and the parameter values ​​cached in the sixth register group are transferred to the fifth register group.

[0079] In other words, the parameter value cached in the second register group RU needs to be used as bilinear interpolation to calculate the parameter value located in the upper left position, cached in the first register group LU, and replace the original cached parameter value; the parameter value cached in the fifth register group RD needs to be used as bilinear interpolation to calculate the parameter value located in the lower left position, cached in the fourth register group LD, and replace the original cached parameter value.

[0080] The parameter value cached in the third register group BU is used as a bilinear interpolation to calculate the parameter value located in the upper right position and cached in the second register group RU, replacing the original cached parameter value; the parameter value cached in the sixth register group BD is used as a bilinear interpolation to calculate the parameter value located in the lower right position and cached in the fifth register group RD, replacing the original cached parameter value.

[0081] After the parameter value is updated, the parameter value in the RAM is read twice in succession, and the read parameter value is cached in the third register group BU and the sixth register group BD respectively. See [link to relevant documentation]. Figure 5 The right side illustrates how this maximizes time savings.

[0082] In an optional embodiment, step 102 above, which involves reading parameter values ​​from the random access memory (RAM) according to the current stage of image processing and caching the read parameter values ​​into the target register group, may specifically include:

[0083] ① When processing the pixel at the end of the image line, the parameter value in the RAM is read twice, and the read parameter value is cached in the third register group and the sixth register group respectively. After processing the pixel at the end of the image line, the parameter value cached in the third register group is transferred to the first register group, and the parameter value cached in the sixth register group is transferred to the fourth register group.

[0084] ② Read the parameter values ​​in the RAM sequentially, cache the read parameter values ​​in the third register group and the sixth register group respectively, and when the pixel to be processed is located at the beginning of the next row of the image row, transfer the parameter values ​​cached in the third register group to the second register group, and transfer the parameter values ​​cached in the sixth register group to the fifth register group.

[0085] Here, processing pixels located at the end of a line in the image indicates that image processing is about to move on to the next line. See [link / reference]. Figure 3 For example, if the pixel being processed at the end of a row in an image is pixel number 15 in the second row, it means that image pixel processing is about to enter the third row. If a newline occurs, the two columns of parameter values ​​currently used for bilinear interpolation calculation (the four parameter values ​​at the intersection of the first and second rows and the second and third columns of the parameter table) can no longer be used. The parameter values ​​cached in the first register group LU, the second register group RU, the fourth register group LD, and the fifth register group RD need to be updated. See [link to documentation]. Figure 6 The specific update process is as follows:

[0086] In the first stage, the parameter values ​​in RAM are read twice and cached in the third register group (BU) and the sixth register group (BD), respectively. Finally, when the end-of-line flag signal leof_in is 1, the parameter values ​​cached in the third register group (BU) are transferred to the first register group (LU), and the parameter values ​​cached in the sixth register group (BD) are transferred to the fourth register group (LD). See [link to relevant documentation]. Figure 6 The left side illustrates this; this will not affect the current bilinear interpolation calculation, and at the same time, it prepares for pixel processing after line breaks by pre-caching the corresponding parameter values.

[0087] In the second stage, RAM is read twice and cached in the third register group (BU) and the sixth register group (BD) respectively. Finally, when the line header flag (lsof_in) of the next line in the image is 1, it indicates a newline has started. At this point, two more parameter values ​​are needed for bilinear interpolation calculation. Specifically, the parameter values ​​cached in the third register group (BU) are transferred to the second register group (RU), and the parameter values ​​cached in the sixth register group (BD) are transferred to the fifth register group (RD). See [link to relevant documentation]. Figure 6 The right side is shown in the diagram.

[0088] It should be noted that if the pixel to be processed does not cross a parameter column (i.e., the equivalent horizontal position of the pixel to be processed in the parameter table does not exceed the position of the first column parameter value (i.e., the rightmost parameter value of the two columns of parameter values ​​currently used for bilinear interpolation calculation), and the frame end signal feof_in is 1, the processing of this frame ends.

[0089] Specifically, the correspondence between the parameter values ​​in the parameter table and their addresses in RAM is as follows: Figure 7 As shown. That is, the parameter values ​​in the parameter table are stored in the RAM in order from left to right and from top to bottom, and the storage address of the RAM increases sequentially.

[0090] Under the parameter table storage mechanism described above, the variation pattern of the RAM read address (ram_addr) can be described as follows: Figure 8 Here, odd_flag being 1 indicates that the current line has been read from RAM an odd number of times, first_line being 1 indicates that the current line is the first line, across_v being 1 indicates that the pixel is about to cross a parameter table line, line_update being 1 indicates that the pixel is about to cross an image line, and ram_read being 1 indicates that a RAM read operation has been performed.

[0091] Depend on Figure 8It can be seen that: in the first line, ram_addr increments by 1 with each RAM read until all parameter values ​​in the first line are read; in the remaining lines, ram_addr changes according to the pattern j+0, j+N+1, j+1, j+N+2, j+2, ..., j+N, j+2N+1, j+N+1, which can achieve interleaved reading of parameter values ​​from the upper and lower lines of the parameter table; among them, j initially takes the value of 0; when a pixel is about to cross a line, if there is no possibility of crossing a line of the parameter table (e.g. Figure 3 After processing the first row of pixels numbered 0 to the end of the row, it needs to cross over to process the second row of pixels numbered 1 (but the row containing the second row of pixels does not cross the second row of the parameter table). In this case, ram_addr will be restored to j, and the same two rows of parameter values ​​will be read interleaved. Otherwise, the existing value j+N+1 will be retained, the row number will be shifted down, and the new two rows of parameter values ​​will be read interleaved, that is, j+N+1 will be used as the new j. At this time, the change pattern of ram_addr is (j+N+1)+0, (j+N+1)+N+1, (j+N+1)+1, ...

[0092] See Figure 3 It can be seen that the minimum number of columns for image pixels is twice the number of columns in the parameter table. This can also be understood as the minimum horizontal dimension of the image pixels being twice the horizontal dimension of the parameter table. When the multiple is greater than 2, there will be more time available for caching data, making the implementation of the data caching scheme in this application easier, and therefore, the data caching method in this application has greater universal applicability.

[0093] The data caching scheme of this application applies to Figure 3 The implementation results can be found in Figure 9 `data_in_d` is the result of delaying the input pixel value `data_in` by one clock cycle, and is aligned with the four buffered data. It can be seen that at time T23, the first pixel value of `data_in_d` arrives. At this time, only LU in the four registers has buffered the first parameter value 00. This is because... Figure 3 The first pixel and the first parameter value coincide, so only LU is used from the source data required for bilinear interpolation; for the remaining pixels in row 0 (T24~T28), only LU and RU have the correct parameter values ​​cached, because... Figure 3 The parameters in row 0 coincide with the row position of the pixels in row 0, therefore only the data source in row U is used in bilinear interpolation; in other rows, all four registers cache the correct parameters. For example, at time T40, the value of data_in_d is 23, corresponding to the pixel in row U. Figure 3 The position in the middle is the 2nd row and 3rd column. The data source required for bilinear interpolation is exactly the four parameters 11, 21, 12, and 22 stored in LU, LD, RU, and RD, which represent respectively Figure 3The parameters are located in the first row and first column, the second row and first column, the first row and second column, and the second row and second column of the parameter table. The aforementioned method of caching data can reduce power consumption to some extent.

[0094] Optionally, the minimum interval between the end of the current row and the beginning of the next row of an image pixel is one clock cycle; the minimum interval between the start of an image frame and the first data in that frame is one clock cycle.

[0095] Additionally from Figure 9 As can be seen, except for the row blanking interval (specifically, the interval between the end of the current row and the beginning of the next row of an image pixel is one clock cycle), ram_read is always 1, which can make fuller use of time to read data from RAM. T23~T25 execute the initialization mode (that is, the initialization phase), LU, RU, and BU successively receive data read_data from RAM; T28~T30 execute the row update mode (corresponding to the case where the pixel to be processed is close to the end of the row of its image), LU and LD buffer the data from BU and BD respectively at T28, and RU and RD buffer the data from BU and BD respectively at T30; T31~T32 execute the caching mode, BU and BD successively buffer the data read_data from RAM; T33 executes the column update mode (corresponding to the case where the equivalent horizontal position of the pixel to be processed in the parameter table exceeds the position of the first column parameter value (that is, the rightmost parameter value of the two columns of parameter values ​​currently used for bilinear interpolation calculation), LU and LD buffer the data in RU and RD respectively, while RU and RD buffer the data in BU and BD respectively. The above process repeats repeatedly within a single image frame, completing the caching of the data source (parameter values) required for bilinear interpolation throughout the entire frame. Therefore, this invention requires only 6 sets of registers to complete the data source caching, resulting in a smaller footprint.

[0096] The following example (see Figure 10 This section describes the overall implementation flow of the data caching method in this application. Before proceeding, it should be noted that the RAM read-register cache can be divided into four modes: initialization mode (corresponding to the initialization stage described above), column update mode (cached data update corresponding to the scenario where the pixel to be processed crosses a parameter column), cache mode (data cache after cache data update corresponding to the scenario where the pixel to be processed crosses a parameter column), and row-to-row mode (corresponding to the pixel to be processed about to cross an image row). The overall process will be explained below.

[0097] S1001, initialize all control signals and data.

[0098] S1002, determine whether the frame synchronization signal fsync_in is 1.

[0099] If yes, then enter initialization mode; otherwise, return to continue executing S1002.

[0100] Here, the frame synchronization signal fsync_in being 1 indicates the start of a frame, at which point the system enters the initialization mode.

[0101] S1003, execute initialization mode.

[0102] For detailed steps on executing the initialization mode, please refer to [link / reference]. Figure 2 Data will be read from RAM three times in succession and sent to LU, RU and BU respectively. The 0th read occurs in the next clock cycle of fsync_in, the 1st read occurs when the first pixel of the first row of the image arrives, and the 2nd read occurs when the second pixel of the first row of the image arrives.

[0103] S1004, determine whether a pixel crosses a column in the parameter table.

[0104] If yes, then enter column update mode; otherwise, execute step S1010 to determine if the frame tail number feof_in is 1.

[0105] Specifically, an accumulator counter is used to record the equivalent horizontal position coordinates of the pixel to be processed in the parameter table. If the pixel exceeds the position of the first column parameter value (i.e. the rightmost parameter value in the two columns currently used for bilinear interpolation calculation), it indicates that the pixel to be processed crosses the parameter table column and the data source (parameter value) needs to be updated. Therefore, the column update mode is entered.

[0106] S1005, Execute column update mode.

[0107] For detailed steps on executing column update mode, please refer to [link / reference]. Figure 4 In the first row of the image, LU receives data from RU, while RU receives data from BU. In the remaining rows of the image, LU and LD receive data from RU and RD respectively, while RU and RD receive data from BU and BD respectively. In both cases, the column update of the data source can be completed in one cycle.

[0108] S1006, determine whether the pixel is at the end of the line.

[0109] If not, proceed to step S1007; if yes, proceed to step S1008.

[0110] S1007, execute cache mode.

[0111] For specific execution steps of the caching mode, please refer to [link / reference]. Figure 5 In the first row of the image, RAM data is read only once and cached in BU. In the remaining rows of the image, RAM data is read twice and sent to BU and BD respectively. The above reads occur immediately after the column update to maximize time savings.

[0112] S1008 determines whether a pixel is about to cross an image row.

[0113] If yes, proceed to step S1009; otherwise, return to step S1004.

[0114] S1009, Execute row update mode.

[0115] In row update mode, all four data sources need to be updated; the process is visible. Figure 6 There are two stages. In the first stage, RAM is read twice and cached in BU and BD. Finally, when the end-of-line flag signal leof_in is 1, LU and LD simultaneously receive data from BU and BD, completing the data update of LU and LD. In the second stage, RAM is also read twice and cached in BU and BD. Finally, when the beginning-of-line flag signal lsof_in of the next line is 1, RU and RD simultaneously receive data from BU and BD, completing the data update of RU and RD.

[0116] S1010, determine if the frame end number feof_in is 1.

[0117] If yes, then end the processing of this frame; otherwise, return to execute S1004.

[0118] The data caching method provided in this application can be executed by a data caching device. This application uses an example of a data caching device executing the data caching method to illustrate the data caching device provided in this application.

[0119] like Figure 11 This invention provides a data caching device, the device 1100 comprising:

[0120] The first processing module 1110 is used to determine the current stage of image processing according to the indication signal. The current stage of image processing includes: an initialization stage and a pixel processing stage.

[0121] The second processing module 1120 is used to read parameter values ​​from the random access memory (RAM) according to the stage of image processing, and cache the read parameter values ​​into the target register group.

[0122] The RAM stores a parameter table, and the parameter values ​​in the parameter table are used for bilinear interpolation calculation.

[0123] The target register group is at least one of the six register groups.

[0124] Optionally, the six register groups include: a first register group, a second register group, a third register group, a fourth register group, a fifth register group, and a sixth register group;

[0125] The first register group is used to cache the parameter value in the first row and first column of the four parameter values ​​in the two rows and two columns of the parameter table used for bilinear interpolation calculation; the second register group is used to cache the parameter value in the first row and second column of the four parameter values; the third register group is used to cache the parameter value in the first row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table; the fourth register group is used to cache the parameter value in the second row and first column of the four parameter values; the fifth register group is used to cache the parameter value in the second row and second column of the four parameter values; and the sixth register group is used to cache the parameter value in the second row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table.

[0126] Optionally, the second processing module 1120 includes:

[0127] The first processing unit is configured to read parameter values ​​from the RAM three times in sequence when the image processing stage is the initialization stage, and cache the read parameter values ​​into the first register group, the second register group and the third register group respectively.

[0128] Optionally, the second processing module 1120 includes:

[0129] The second processing unit is used to update the parameter values ​​cached in the relevant register group when the image processing stage is the pixel processing stage and the position of the pixel to be processed in the image is more than the position of the first column parameter value in the parameter table. The first column parameter value is adjacent to the second column parameter value and is located to the right of the second column parameter value. The first column parameter value and the second column parameter value are the two columns of parameter values ​​currently used for bilinear interpolation calculation.

[0130] The third processing unit is used to read the parameter value in RAM N times after the parameter value is updated, and to cache the parameter value read each time in the target register group, where N is a positive integer greater than or equal to 1.

[0131] Optionally, the second processing unit is specifically used for:

[0132] If the pixel to be processed is located in the first row of the image, the parameter value cached in the second register group is transferred to the first register group; and the parameter value cached in the third register group is transferred to the second register group.

[0133] If the pixel to be processed is located in a row of the image other than the first row, the parameter value cached in the second register group is transferred to the first register group, and the parameter value cached in the fifth register group is transferred to the fourth register group; the parameter value cached in the third register group is transferred to the second register group, and the parameter value cached in the sixth register group is transferred to the fifth register group.

[0134] Optionally, the third processing unit is specifically used for:

[0135] If the pixel to be processed is located in the first row of the image and is not at the end of the row, after the parameter value is updated, the parameter value in the RAM is read once and the read parameter value is cached in the third register group.

[0136] When the pixel to be processed is located in a row other than the first row of the image, and the pixel to be processed is not at the end of the row, after the parameter value is updated, the parameter value in the RAM is read twice, and the read parameter value is cached in the third register group and the sixth register group respectively.

[0137] Optionally, the second processing module 1120 includes:

[0138] The fourth processing unit is used to read the parameter values ​​in the RAM twice when processing the pixels located at the end of the image line, cache the read parameter values ​​in the third register group and the sixth register group respectively, and after processing the pixels located at the end of the image line, transmit the parameter values ​​cached in the third register group to the first register group and transmit the parameter values ​​cached in the sixth register group to the fourth register group.

[0139] The fifth processing unit is used to read the parameter values ​​in the RAM sequentially, cache the read parameter values ​​in the third register group and the sixth register group respectively, and when the pixel to be processed is located at the beginning of the next row of the image row, transmit the parameter values ​​cached in the third register group to the second register group and the parameter values ​​cached in the sixth register group to the fifth register group.

[0140] Optionally, the parameter values ​​in the parameter table are stored in the RAM in order from left to right and from top to bottom, with the RAM address increasing sequentially.

[0141] Optionally, the minimum number of columns for image pixels is twice the number of columns in the parameter table.

[0142] Optionally, the minimum interval between the end of the current row and the beginning of the next row of an image pixel is one clock cycle;

[0143] The minimum interval between the start of a frame and the first data in that frame is one clock cycle.

[0144] The data caching device of this embodiment determines the current stage of image processing based on an indication signal. The current stage includes an initialization stage and a pixel processing stage. According to the current stage, it reads parameter values ​​from a random access memory (RAM) and caches the read parameter values ​​in a target register group. The RAM stores a parameter table, and the parameter values ​​in the parameter table are used for bilinear interpolation calculation. The target register group is at least one of six register groups, including a first register group, a second register group, a third register group, a fourth register group, a fifth register group, and a sixth register group. The first register group is used to cache the parameter values ​​in the first row and first column of the two rows and two columns of the parameter table used for bilinear interpolation calculation. The parameter values ​​are set in a specific way. The second register group is used to cache the parameter value located in the first row and second column of the four parameter values. The third register group is used to cache the parameter value in the first row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table. The fourth register group is used to cache the parameter value located in the second row and first column of the four parameter values. The fifth register group is used to cache the parameter value in the second row and second column of the four parameter values. The sixth register group is used to cache the parameter value in the second row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table. In this way, based on the characteristics of video stream timing and bilinear interpolation calculation in image processing, by storing the parameter table in a whole block of single-port RAM and caching parameter resources in six register groups, the area and power consumption can be significantly reduced.

[0145] The data caching device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the device.

[0146] The data caching device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0147] The data caching device provided in this application embodiment can achieve... Figure 1 The various processes implemented in the method implementation examples will not be described again here to avoid repetition.

[0148] Optionally, such as Figure 12 As shown, this application embodiment also provides an electronic device 1200, including a processor 1201 and a memory 1202. The memory 1202 stores a program or instructions that can run on the processor 1201. When the program or instructions are executed by the processor 1201, they implement the various steps of the above-described data caching method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0149] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0150] Figure 13 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0151] The electronic device 1300 includes, but is not limited to, components such as: radio frequency unit 1301, network module 1302, audio output unit 1303, input unit 1304, sensor 1305, display unit 1306, user input unit 1307, interface unit 1308, memory 1309, and processor 1310.

[0152] Those skilled in the art will understand that the electronic device 1300 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 1310 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 13 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0153] The processor 1310 is configured to determine the current stage of image processing based on an indication signal, wherein the current stage of image processing includes an initialization stage and a pixel processing stage.

[0154] According to the current stage of image processing, read the parameter values ​​from the random access memory (RAM) and cache the read parameter values ​​in the target register group;

[0155] The RAM stores a parameter table, and the parameter values ​​in the parameter table are used for bilinear interpolation calculation.

[0156] The target register group is at least one of six register groups, including: a first register group, a second register group, a third register group, a fourth register group, a fifth register group, and a sixth register group; wherein, the first register group is used to cache the parameter value in the first row and first column of the four parameter values ​​in the two rows and two columns of the parameter table used for bilinear interpolation calculation; the second register group is used to cache the parameter value in the first row and second column of the four parameter values; the third register group is used to cache the parameter value in the first row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table; the fourth register group is used to cache the parameter value in the second row and first column of the four parameter values; the fifth register group is used to cache the parameter value in the second row and second column of the four parameter values; and the sixth register group is used to cache the parameter value in the second row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table.

[0157] Based on the characteristics of video stream timing and bilinear interpolation calculations in image processing, this application uses a single-port RAM to store the parameter table and six sets of registers to cache parameter resources, which can significantly reduce area and power consumption.

[0158] It should be understood that, in this embodiment, the input unit 1304 may include a graphics processing unit (GPU) 13041 and a microphone 13042. The GPU 13041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 1306 may include a display panel 13061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 1307 includes a touch panel 13071 and at least one of other input devices 13072. The touch panel 13071 is also called a touch screen. The touch panel 13071 may include a touch detection device and a touch controller. Other input devices 13072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0159] The memory 1309 can be used to store software programs and various data. The memory 1309 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 1309 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 1309 in this embodiment includes, but is not limited to, these and any other suitable types of memory.

[0160] Processor 1310 may include one or more processing units; optionally, processor 1310 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 1310.

[0161] Optionally, the processor 1310 is also used for:

[0162] When the image processing stage is the initialization stage, the parameter values ​​in the RAM are read three times in succession, and the read parameter values ​​are cached in the first register group, the second register group and the third register group respectively.

[0163] Optionally, the processor 1310 is also used for:

[0164] When the image processing stage is the pixel processing stage, and the position of the pixel to be processed in the image is more than the position of the first column parameter value in the parameter table, the parameter value cached in the relevant register group is updated. The first column parameter value is adjacent to the second column parameter value and is located to the right of the second column parameter value. The first column parameter value and the second column parameter value are the two columns of parameter values ​​currently used for bilinear interpolation calculation.

[0165] After the parameter value is updated, the parameter value in RAM is read N times, and the parameter value read each time is cached in the target register group, where N is a positive integer greater than or equal to 1.

[0166] Optionally, the processor 1310 is also used for:

[0167] If the pixel to be processed is located in the first row of the image, the parameter value cached in the second register group is transferred to the first register group; and the parameter value cached in the third register group is transferred to the second register group.

[0168] If the pixel to be processed is located in a row of the image other than the first row, the parameter value cached in the second register group is transferred to the first register group, and the parameter value cached in the fifth register group is transferred to the fourth register group; the parameter value cached in the third register group is transferred to the second register group, and the parameter value cached in the sixth register group is transferred to the fifth register group.

[0169] Optionally, the processor 1310 is also used for:

[0170] If the pixel to be processed is located in the first row of the image and is not at the end of the row, after the parameter value is updated, the parameter value in the RAM is read once and the read parameter value is cached in the third register group.

[0171] When the pixel to be processed is located in a row other than the first row of the image, and the pixel to be processed is not at the end of the row, after the parameter value is updated, the parameter value in the RAM is read twice, and the read parameter value is cached in the third register group and the sixth register group respectively.

[0172] Optionally, the processor 1310 is also used for:

[0173] When processing pixels located at the end of an image row, the parameter values ​​in the RAM are read twice, and the read parameter values ​​are cached in the third register group and the sixth register group respectively. After processing the pixels located at the end of the image row, the parameter values ​​cached in the third register group are transferred to the first register group, and the parameter values ​​cached in the sixth register group are transferred to the fourth register group.

[0174] The parameter values ​​in the RAM are read sequentially, and the read parameter values ​​are cached in the third register group and the sixth register group respectively. When the pixel to be processed is located at the beginning of the next row of the image row, the parameter values ​​cached in the third register group are transferred to the second register group, and the parameter values ​​cached in the sixth register group are transferred to the fifth register group.

[0175] Optionally, the parameter values ​​in the parameter table are stored in the RAM in order from left to right and from top to bottom, and the storage address of the RAM increases sequentially.

[0176] Optionally, the minimum number of columns for image pixels is twice the number of columns in the parameter table.

[0177] Optionally, the end of the current row of an image pixel is spaced one clock cycle from the beginning of the next row.

[0178] The start of a frame is separated from the first data in that frame by one clock cycle.

[0179] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described data caching method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0180] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0181] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above data caching method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0182] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0183] This application provides a computer program product that is stored in a storage medium and executed by at least one processor to implement the various processes of the data caching method embodiments described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0184] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0185] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0186] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A data caching method, applied to a data caching device, characterized in that, The data buffer device includes six register groups, and the method includes: Based on the indication signal, the current stage of image processing is determined, which includes: an initialization stage and a pixel processing stage; According to the current stage of image processing, read the parameter values ​​from the random access memory (RAM) and cache the read parameter values ​​in the target register group; The RAM stores a parameter table, and the parameter values ​​in the parameter table are used for bilinear interpolation calculation. The target register group is at least one of the six register groups; The six register groups include: the first register group, the second register group, the third register group, the fourth register group, the fifth register group, and the sixth register group; Specifically, the first register group is used to cache the parameter value in the first row and first column of the four parameter values ​​in the two rows and two columns of the parameter table used for bilinear interpolation calculation; the second register group is used to cache the parameter value in the first row and second column of the four parameter values; the third register group is used to cache the parameter value in the first row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table; the fourth register group is used to cache the parameter value in the second row and first column of the four parameter values; the fifth register group is used to cache the parameter value in the second row and second column of the four parameter values; and the sixth register group is used to cache the parameter value in the second row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table.

2. The method according to claim 1, characterized in that, The step of reading parameter values ​​from the random access memory (RAM) according to the current stage of image processing and caching the read parameter values ​​into the target register group includes: When the image processing stage is the initialization stage, the parameter values ​​in the RAM are read three times in succession, and the read parameter values ​​are cached in the first register group, the second register group and the third register group respectively.

3. The method according to claim 1, characterized in that, The step of reading parameter values ​​from the random access memory (RAM) according to the current stage of image processing and caching the read parameter values ​​into the target register group includes: When the image processing stage is the pixel processing stage, and the position of the pixel to be processed in the image is more than the position of the first column parameter value in the parameter table, the parameter value cached in the relevant register group is updated. The first column parameter value is adjacent to the second column parameter value and is located to the right of the second column parameter value. The first column parameter value and the second column parameter value are the two columns of parameter values ​​currently used for bilinear interpolation calculation. After the parameter value is updated, the parameter value in RAM is read N times, and the parameter value read each time is cached in the target register group, where N is a positive integer greater than or equal to 1.

4. The method according to claim 3, characterized in that, The parameter values ​​for updating the relevant register group cache include: If the pixel to be processed is located in the first row of the image, the parameter value cached in the second register group is transferred to the first register group; and the parameter value cached in the third register group is transferred to the second register group. If the pixel to be processed is located in a row of the image other than the first row, the parameter value cached in the second register group is transferred to the first register group, and the parameter value cached in the fifth register group is transferred to the fourth register group; the parameter value cached in the third register group is transferred to the second register group, and the parameter value cached in the sixth register group is transferred to the fifth register group.

5. The method according to claim 4, characterized in that, The step of reading the parameter value from RAM N times after the parameter value is updated, and caching the parameter value read each time into the target register group, includes: If the pixel to be processed is located in the first row of the image and is not at the end of the row, after the parameter value is updated, the parameter value in the RAM is read once and the read parameter value is cached in the third register group. When the pixel to be processed is located in a row other than the first row of the image, and the pixel to be processed is not at the end of the row, after the parameter value is updated, the parameter value in the RAM is read twice, and the read parameter value is cached in the third register group and the sixth register group respectively.

6. The method according to claim 1, characterized in that, The step of reading parameter values ​​from the random access memory (RAM) according to the current stage of image processing and caching the read parameter values ​​into the target register group includes: When processing pixels located at the end of an image row, the parameter values ​​in the RAM are read twice, and the read parameter values ​​are cached in the third register group and the sixth register group respectively. After processing the pixels located at the end of the image row, the parameter values ​​cached in the third register group are transferred to the first register group, and the parameter values ​​cached in the sixth register group are transferred to the fourth register group. The parameter values ​​in the RAM are read sequentially, and the read parameter values ​​are cached in the third register group and the sixth register group respectively. When the pixel to be processed is located at the beginning of the next row of the image row, the parameter values ​​cached in the third register group are transferred to the second register group, and the parameter values ​​cached in the sixth register group are transferred to the fifth register group.

7. The method according to claim 1, characterized in that, The parameter values ​​in the parameter table are stored in the RAM in order from left to right and from top to bottom, and the storage address of the RAM increases sequentially.

8. The method according to claim 1, characterized in that, The minimum number of columns for image pixels is twice the number of columns in the parameter table.

9. The method according to claim 1, characterized in that, The minimum interval between the end of the current row and the beginning of the next row for image pixels is one clock cycle. The minimum interval between the start of a frame and the first data in that frame is one clock cycle.

10. A data caching device, characterized in that, The data cache device includes six register groups, and, The first processing module is used to determine the current stage of image processing based on the indication signal. The current stage of image processing includes: an initialization stage and a pixel processing stage. The second processing module is used to read parameter values ​​from the random access memory (RAM) according to the stage of image processing, and cache the read parameter values ​​into the target register group; The RAM stores a parameter table, and the parameter values ​​in the parameter table are used for bilinear interpolation calculation. The target register group is at least one of the six register groups; The six register groups include: the first register group, the second register group, the third register group, the fourth register group, the fifth register group, and the sixth register group; Specifically, the first register group is used to cache the parameter value in the first row and first column of the four parameter values ​​in the two rows and two columns of the parameter table used for bilinear interpolation calculation; the second register group is used to cache the parameter value in the first row and second column of the four parameter values; the third register group is used to cache the parameter value in the first row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table; the fourth register group is used to cache the parameter value in the second row and first column of the four parameter values; the fifth register group is used to cache the parameter value in the second row and second column of the four parameter values; and the sixth register group is used to cache the parameter value in the second row of the two rows of parameter values ​​used for bilinear interpolation calculation in the parameter table.

11. The apparatus according to claim 10, characterized in that, The second processing module includes: The first processing unit is configured to read parameter values ​​from the RAM three times in sequence when the image processing stage is the initialization stage, and cache the read parameter values ​​into the first register group, the second register group and the third register group respectively.

12. The apparatus according to claim 10, characterized in that, The second processing module includes: The second processing unit is used to update the parameter values ​​cached in the relevant register group when the image processing stage is the pixel processing stage and the position of the pixel to be processed in the image is more than the position of the first column parameter value in the parameter table. The first column parameter value is adjacent to the second column parameter value and is located to the right of the second column parameter value. The first column parameter value and the second column parameter value are the two columns of parameter values ​​currently used for bilinear interpolation calculation. The third processing unit is used to read the parameter value in RAM N times after the parameter value is updated, and to cache the parameter value read each time in the target register group, where N is a positive integer greater than or equal to 1.

13. The apparatus according to claim 12, characterized in that, The second processing unit is specifically used for: If the pixel to be processed is located in the first row of the image, the parameter value cached in the second register group is transferred to the first register group; and the parameter value cached in the third register group is transferred to the second register group. If the pixel to be processed is located in a row of the image other than the first row, the parameter value cached in the second register group is transferred to the first register group, and the parameter value cached in the fifth register group is transferred to the fourth register group; the parameter value cached in the third register group is transferred to the second register group, and the parameter value cached in the sixth register group is transferred to the fifth register group.

14. The apparatus according to claim 13, characterized in that, The third processing unit is specifically used for: If the pixel to be processed is located in the first row of the image and is not at the end of the row, after the parameter value is updated, the parameter value in the RAM is read once and the read parameter value is cached in the third register group. When the pixel to be processed is located in a row other than the first row of the image, and the pixel to be processed is not at the end of the row, after the parameter value is updated, the parameter value in the RAM is read twice, and the read parameter value is cached in the third register group and the sixth register group respectively.

15. The apparatus according to claim 10, characterized in that, The second processing module includes: The fourth processing unit is used to read the parameter values ​​in the RAM twice when processing the pixels located at the end of the image line, cache the read parameter values ​​in the third register group and the sixth register group respectively, and after processing the pixels located at the end of the image line, transmit the parameter values ​​cached in the third register group to the first register group and transmit the parameter values ​​cached in the sixth register group to the fourth register group. The fifth processing unit is used to read the parameter values ​​in the RAM sequentially, cache the read parameter values ​​in the third register group and the sixth register group respectively, and when the pixel to be processed is located at the beginning of the next row of the image row, transmit the parameter values ​​cached in the third register group to the second register group and the parameter values ​​cached in the sixth register group to the fifth register group.

16. The apparatus according to claim 10, characterized in that, The parameter values ​​in the parameter table are stored in the RAM in order from left to right and from top to bottom, and the storage address of the RAM increases sequentially.

17. The apparatus according to claim 10, characterized in that, The minimum number of columns for image pixels is twice the number of columns in the parameter table.

18. The apparatus according to claim 10, characterized in that, The minimum interval between the end of the current row and the beginning of the next row for image pixels is one clock cycle. The minimum interval between the start of a frame and the first data in that frame is one clock cycle.

19. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the data caching method as described in any one of claims 1 to 9.

20. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the data caching method as described in any one of claims 1 to 9.

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