Capacitive coupled stacked class-d oscillator for galvanic isolation

Abstract

The present disclosure relates to a capacitively coupled stacked class-D oscillator for galvanic isolation. The oscillator circuit includes a total of N (N > 2) class-D oscillator circuits stacked together between a supply voltage node and a reference voltage node. The output ports of adjacent class-D oscillator circuits in the disclosed oscillator circuit are coupled together through capacitors to ensure frequency and phase synchronization of the frequency signals generated by the class-D oscillator circuits. The oscillation amplitude of each class-D oscillator circuit in the disclosed oscillator circuit is 1 / N of the oscillation amplitude of a reference oscillator circuit formed by a single class-D oscillator circuit, and the current consumption of the disclosed oscillator circuit is 1 / N of the current consumption of the reference oscillator circuit.

Description

[0001] Cross-references to related applications

[0002] This application is a continuation-to-file of U.S. Patent Application No. 17 / 732,026, filed April 28, 2022, entitled “Capacitively-Coupled Stacked Class-D Oscillators for Galvanic Isolation,” which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to electronic circuits, and in certain embodiments to current-isolated oscillator circuits suitable for use in semiconductor packages. Background Technology

[0004] Current isolation technology is commonly used in electrical systems to improve the safety and reliability of various applications, such as industrial sensors, medical devices, gate drivers for motor control, etc. Typically, a current-isolated system comprises two currently isolated power domains because, for example, one power domain is subjected to a dangerous voltage, or the power domains have different ground references. Current isolation is generally used to isolate different power domains to prevent current from flowing between the isolated power domains. Energy or information can still be exchanged between the isolated power domains by other means, such as capacitors, inductors, or optical means.

[0005] The key performance parameter for current isolation is the maximum surge isolation voltage V. SURGE Maximum surge isolation voltage V SURGE The ability of an isolator to withstand very high voltage pulses of a transient curve, which may be caused by direct or indirect lightning strikes, faults, or short-circuit events, is quantified. The highest level of isolation, i.e., reinforced isolation, is demonstrated if a single isolation barrier layer passes a 10-kV surge test. Another important parameter for current isolation is common-mode transient immunity (CMTI), which measures the isolator's ability to withstand rapid ground displacement (e.g., high dV / dt), with typical values ​​ranging from 50 kV / μs to 200 kV / μs. Typically, CMTI performance is related to the parasitic capacitance effect of the galvanic barrier. Current isolation can improve isolation levels while still maintaining competitive performance in terms of data rate and CMTI.

[0006] In the near future, applications in fields such as industry, automotive, or medical may require voltage levels as high as 20kV. SURGEFurthermore, the higher switching frequencies achieved by broadband power devices such as gallium nitride high electron mobility transistors (GaN HEMTs) and silicon carbide (SiC) MOSFETs may require CMTIs exceeding 200 kV / μ. Conventional chip-level isolators (where current isolation is achieved by separating different power domains using one or more dielectric layers of a semiconductor chip) are based on capacitors, transformers, or hybrid LC networks, utilizing, for example, thick silicon dioxide or polyimide layers as isolation barriers. These approaches have inherent limitations in terms of isolation level and CMTI due to the maximum manufacturable dielectric thickness and associated capacitive parasitic effects, respectively. There is a need in the art for current isolation techniques with improved isolation levels and CMTI performance. Summary of the Invention

[0007] In some embodiments, a device includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes: a first transistor and a second transistor, wherein the gate terminals of the first transistor and the second transistor are coupled to a first node, wherein a first load path terminal of the first transistor and the second transistor are coupled to a reference voltage node; a first coil coupled between a second load path terminal of the first transistor and a second load path terminal of the second transistor; and a first capacitor coupled in parallel with the first coil. The second oscillator circuit includes: a third transistor and a fourth transistor, wherein the gate terminals of the third transistor and the fourth transistor are coupled to a second node, wherein the first load path terminals of the third transistor and the fourth transistor are coupled to a center tap of the first coil; a second coil coupled between the second load path terminals of the third transistor and the fourth transistor; and a second capacitor coupled in parallel with the second coil. The device further includes: a third capacitor coupled between the second load path terminals of the first transistor and the second load path terminal of the third transistor; and a fourth capacitor coupled between the second load path terminals of the second transistor and the second load path terminal of the fourth transistor.

[0008] In some embodiments, a device includes a first oscillator circuit and a second oscillator circuit cascaded with the first oscillator circuit, wherein the first oscillator circuit and the second oscillator circuit are configured to be coupled between a power supply voltage and electrical ground, wherein each of the first oscillator circuit and the second oscillator circuit is a Class D oscillator circuit, wherein the Class D oscillator circuit includes: a first transistor coupled between a reference voltage node of the Class D oscillator circuit and a first output of the Class D oscillator circuit; a second transistor coupled between the reference voltage node of the Class D oscillator circuit and a second output of the Class D oscillator circuit, wherein the gate terminals of the first transistor and the second transistor are coupled to a bias voltage node of the Class D oscillator circuit; a first coil coupled between the first output and the second output of the Class D oscillator circuit; and a first capacitor coupled in parallel with the first coil. The device further includes: a second capacitor coupled between the first output of the first oscillator circuit and the first output of the second oscillator circuit; and a third capacitor coupled between the second output of the first oscillator circuit and the second output of the second oscillator circuit.

[0009] In some embodiments, the integrated circuit (IC) device includes a first oscillator circuit comprising: a first transistor and a second transistor, wherein the gate terminal of the first transistor is coupled to a first node via a first resistor, and the gate terminal of the second transistor is coupled to the first node via a second resistor; a first capacitor coupled between the drain terminal of the first transistor and the drain terminal of the second transistor; and a first coil coupled in parallel with the first capacitor. The IC device also includes a second oscillator circuit identical to the first oscillator circuit, wherein the source terminals of the first and second transistors of the first oscillator circuit are coupled to a reference voltage node, and the source terminals of the first and second transistors of the second oscillator circuit are coupled to a center tap of a first coil of the first oscillator circuit, wherein the center tap of the first coil of the second oscillator circuit is coupled to a power supply voltage node. The IC device further includes: a second capacitor coupled between the drain terminal of the first transistor in the first oscillator circuit and the drain terminal of the first transistor in the second oscillator circuit; and a third capacitor coupled between the drain terminal of the second transistor in the first oscillator circuit and the drain terminal of the second transistor in the second oscillator circuit. Attached Figure Description

[0010] Details of one or more embodiments of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will be apparent from the specification, the drawings, and the claims. In the drawings, the same reference numerals generally denote the same components in various views and are generally not restated for the sake of brevity. For a more complete understanding of this disclosure, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 A block diagram of an electrical system with current isolation in one embodiment is shown;

[0012] Figure 2 A cross-sectional view of a semiconductor package with package-level current isolation is shown in the embodiment;

[0013] Figure 3 Examples are shown Figure 2 A system block diagram of a semiconductor package;

[0014] Figure 4 The image shows an on / off keyed pulse width modulation (OOKPWM) signal in one embodiment;

[0015] Figure 5 This is a schematic diagram of the oscillator circuit in the embodiment;

[0016] Figure 6 This is a schematic diagram of the oscillator circuit in another embodiment;

[0017] Figure 7 This is a schematic diagram of the oscillator circuit in yet another embodiment;

[0018] Figure 8 A cross-sectional view of a semiconductor chip in one embodiment is shown;

[0019] Figure 9 It is shown in one embodiment in Figure 2 A top view of the microantenna used in the semiconductor package; and

[0020] Figure 10 In another embodiment, it is shown that Figure 2 A top view of the micro-antenna used in a semiconductor package. Detailed Implementation

[0021] The manufacture and use of the presently preferred embodiments are discussed in detail below. However, it should be understood that this disclosure provides many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of particular ways of manufacturing and using this disclosure and do not limit its scope. In the discussion herein, unless otherwise stated, “coupled” is used to refer to electrical coupling, and the term “coupled” is used to describe an electrical connection in which a first electrical component is directly or indirectly coupled to a second electrical component, while the term “direct coupling” is used to describe a direct electrical connection between the first and second electrical components (e.g., via copper wire) without an intermediate electrical component.

[0022] This disclosure will be described in the context of a semiconductor package with package-level current isolation, and in certain embodiments, an oscillator circuit suitable for use in a semiconductor package with package-level current isolation is described.

[0023] Figure 1 A block diagram of an electrical system 10 with current isolation in one embodiment is shown. Figure 1 The electrical system 10 includes a first circuit 13 in a first power domain, for example having a first power supply voltage (e.g., V). DD1 The system includes a first ground level (e.g., GND1) and a second circuit 15 in a second power domain, for example having a second supply voltage (e.g., V). DD2 The electrical system 10 also includes a first circuit 13 and a second ground level (e.g., GND2). The electrical system 10 further includes a current isolation barrier 11 between the first circuit 13 and the second circuit 15.

[0024] Current isolation is commonly used in electrical systems to isolate functional parts of an electrical system (e.g., 13 and 15) to prevent current from flowing between the isolated functional parts. Energy or information can still be exchanged between the parts in other ways, such as by capacitance, inductance, electromagnetic, optical, acoustic, or mechanical means. Current isolation can be used when two or more circuits (e.g., 13 and 15) need to communicate with each other but their grounds may be at different potentials. Current isolation can also be used for safety purposes, such as decoupling a functional block from another block connected to the mains or other high voltages for safety and device protection.

[0025] Figure 2 A cross-sectional view of a semiconductor package 20 with package-level current isolation is shown in the embodiment. The semiconductor package 20 forms a current isolation system by using standard packaging / assembly techniques and radio frequency (RF) coupling between micro-antennas of two side-by-side co-packaged semiconductor chips (also referred to as chips or integrated circuit (IC) chips). A standard molding compound is used as an isolation barrier layer by utilizing near-field coupling between micro-antennas integrated on the two side-by-side co-packaged chips.

[0026] like Figure 2 As shown, semiconductor package 20 includes a chip 21 attached to lead frame 28. Conductive pads of chip 21 are coupled to input / output (I / O) pins 27 of semiconductor package 20 using bonding wires 25. Semiconductor package 20 further includes a chip 23 attached to another lead frame 28 and coupled to its corresponding I / O pin 27 via bonding wires 25. Chips 21 and 23 are arranged adjacent to each other (e.g., side-by-side). The distance between chips 21 and 23, also known as the distance through insulator (DTI), can be, for example, hundreds of micrometers. Figure 2 As shown, microantennas 22 and 24 are formed on chips 21 and 23, respectively. Each of microantennas 22 and 24 is electrically coupled to the corresponding chip (e.g., 21 or 23) and is used to transmit and / or receive RF signals for data communication between chips 21 and 23. A molding compound 29 is formed to encapsulate chips 21 and 23, lead frame 28, microantennas 22 and 24, and bonding wire 25. In some embodiments, microantennas 22 and 24 are pre-formed before being attached to the surfaces of chips 21 and 23. In some embodiments, microantennas 22 and 24 are formed as part of chips 21 and 23 during the semiconductor manufacturing process that forms chips 21 and 23. For example, Figure 8 Microantennas 63A and 63B formed within the upper dielectric layer 53 of chip 50 are shown. Figure 8 Further details are discussed below.

[0027] One advantage of package-level current isolation is the use of molded compound 29 as an isolation layer between two side-by-side co-packaged chips 21 and 23, along with a wider DTI (typically hundreds of micrometers between chip lead frames 28), to achieve an increased level of isolation while reducing capacitive parasitic effects of current shielding. The physical channel for data communication utilizes weak near-field electromagnetic (EM) coupling (e.g., RF coupling) between micro-antennas 22 and 24 integrated on the side-by-side co-packaged chips, such as... Figure 2 As shown. In this method, a DTI is selected to ensure the required level of isolation while maintaining a reasonable level of coupling between microantennas 22 and 24. For example, standard molded compounds exhibit a dielectric strength (EM) of approximately 50–100 kV / mm, thus enabling enhanced isolation with a DTI of only 200 μm (e.g., V). SURGE (≥10kV), which generates very low capacitance parasitics, so CMTI is better than, for example, 200kV / μs.

[0028] Compared to conventional isolation methods, package-level current isolation based on RF coupling offers several advantages. For example, no custom technologies / components are required for package-level current isolation, and standard packages are sufficient to guarantee excellent isolation and CMTI performance. Furthermore, this approach is highly flexible and can be adapted to application specifications without time-consuming and costly technology development. However, achieving these advantages requires significant silicon area consumption due to on-chip antennas (e.g., micro-antennas) on two chips. Figure 2 The RF coupling isolation method is suitable for data transmission. In particular, due to the high isolation channel loss (e.g., 40 dB or greater RF coupling loss), using carrier-based modulation can achieve CMTI performance better than 200 kV / μs at higher power consumption compared to pulse modulation methods used in chip-level isolation schemes.

[0029] Figure 3 Examples are shown Figure 2 A system block diagram of semiconductor package 20. Semiconductor package 20 includes semiconductor chip 21 and semiconductor chip 23. Semiconductor chip 21 includes modulator 31 (e.g., pulse width modulation (PWM) modulator), transmission (Tx) circuit 33, and micro-antenna 22 for transmitting modulated RF signals. In some embodiments, Tx circuit 33 includes oscillator circuitry, and micro-antenna 22 is an inductive element (e.g., coil) that forms an LC energy storage circuit with capacitors of Tx circuit 33 to generate RF signals for transmission. Thus, micro-antenna 22 may be part of oscillator circuitry. In some embodiments, the oscillator circuitry in Tx circuit 33 is turned on and off by a PWM digital stream generated by PWM modulator 31. Note that although in Figure 3 In the block diagram, the micro-antenna 22 is shown as a single coil, but the micro-antenna 22 can be implemented as multiple coils in an oscillator circuit.

[0030] Semiconductor chip 23 includes a microantenna 24 for receiving RF signals transmitted from microantenna 22. Semiconductor chip 23 also includes a receive (Rx) circuit 35 and a demodulator 37 (e.g., a PWM demodulator). The receive (Rx) circuit 35 may include a rectifier, amplifier, filter, etc., and the demodulator 37 is used to demodulate the received signal. In some embodiments, microantenna 24, weakly coupled to microantenna 22, outputs a magnetically induced RF voltage. After rectification by the rectifier in Rx circuit 35, the envelope of the received RF voltage is further amplified by the amplifier (e.g., a gain stage) of Rx circuit 35, driving the hysteresis comparator of Rx circuit 35 to reconstruct the transmitted PWM signal. Finally, a baseband PWM demodulator (e.g., 37) is used to recover the original digital bitstream. Due to high channel loss (approximately 30–45 dB, depending on the technology and chip distance employed), the system operates in narrowband mode, where microantennas 22 and 24 operate at an RF carrier frequency f.RF resonance.

[0031] Figure 4 An on / off keyed pulse width modulation (OOKPWM) signal 401 is shown in an embodiment. In some embodiments, the OOKPWM signal 401 is an RF signal transmitted or received by micro-antennas 22 and 24. Figure 4 An example input / output data sequence, and a clock signal used for the input / output data sequence, are further illustrated. Figure 4 In the example, for bit "1", PWM modulator 31 (see Figure 3 The Tx circuit 33 is controlled to generate an OOKPWM signal 401 with a duration of T1; for a bit "0", the Tx circuit 33 generates an OOKPWM signal 401 with a duration of T2, which is shorter than T1. In other words, digital information (e.g., 1 or 0) is encoded in the length (e.g., duration) of each bit of the OOKPWM signal 401, rather than in the amplitude of the OOKPWM signal. This improves the robustness of the RF signal to interference and noise in the communication channel. The data rate achievable using the OOKPWM signal in the semiconductor package 20 can be, for example, between approximately 100 Mbits / s and approximately 500 Mbits / s.

[0032] Figure 5 This is a schematic diagram of the oscillator circuit 100 in an embodiment. In some embodiments, the oscillator circuit 100 corresponds to Figure 3 The combination of Tx circuit 33 and micro antenna 22 in the middle. Figure 5 An Rx circuit 200 coupled to the oscillator circuit 100 is also shown. The Rx circuit 200 includes an inductor element L magnetically coupled to the oscillator circuit 100. RX (e.g., a coil). The Rx circuit 200 also includes an Rx front-end circuit 203 for decoding the RF signal (e.g., an OOKPWM signal) transmitted by the oscillator circuit 100. Inductor element L RX The Rx front-end circuit 203 can respectively correspond to Figure 3 The micro-antenna 24 and Rx circuit 35 are included.

[0033] Figure 5 The oscillator circuit 100 includes a power supply voltage V DD Two Class D oscillators, 150A and 150B, are stacked (e.g., cascaded) together with a reference voltage (e.g., electrical ground). It is worth noting that capacitor C... SA capacitor CS is coupled between node 103A of class D oscillator 150A and node 103B of class D oscillator 150B, and another capacitor CS is coupled between node 105A of class D oscillator 150A and node 105B of class D oscillator 150B. Capacitor CS ensures synchronization between the outputs of the LC energy storage circuits of class D oscillators 150A and 150B. For ease of discussion, in the context of discussing oscillator circuit 100, class D oscillators 150A and 150B may be referred to as bottom oscillator circuit 150A and top oscillator circuit 150B, respectively. In the illustrated embodiments, the same reference numerals (e.g., R, C) are used. B Electrical components (e.g., resistors, capacitors) have the same nominal value (e.g., the same resistance or the same capacitance).

[0034] like Figure 5 As shown, the bottom oscillator circuit 150A includes a first transistor M1 (e.g., a CMOS transistor) and a second transistor M2 (e.g., a CMOS transistor), wherein the gate terminal of the first transistor M1 is coupled to node 101A via a resistor R, and the gate terminal of the second transistor M2 is coupled to node 101A via another resistor R. Node 101A is configured to provide (e.g., connected to) a bias voltage V for turning the first transistor M1 and the second transistor M2 on and off. BIAS Therefore, node 101A can also be referred to as bias voltage node 101A. The source terminals of the first transistor M1 and the second transistor M2 are coupled to reference voltage node 102A, which is connected to reference voltage 104 (e.g., electrically grounded).

[0035] Figure 5 The bottom oscillator circuit 150A also includes an LC energy storage circuit, which includes an inductor element L TX (e.g., coil) and capacitor C P Inductor L TX (also known as coil L) TX The capacitor C is coupled between node 103A (which is coupled to the drain terminal of the first transistor M1) and node 105A (which is coupled to the drain terminal of the second transistor M2). P With coil L TX Parallel coupling (e.g., between node 103A and node 105A). In the discussion herein, the source / drain terminals of a transistor (e.g., M1 or M2) may be collectively referred to as the load path terminals of the transistor, and the gate terminal of the transistor may also be referred to as the control terminal of the transistor. Those skilled in the art will readily understand that the coil L... TX and capacitor C P The generated frequency of the LC energy storage circuit is f RF The oscillator signal (e.g., a sine wave), fRF Depend on Determined, where L is the coil L TX The inductance of C is the capacitor C. P The capacitance. As an example, the frequency f of the oscillator signal generated by the LC energy storage circuit... RF It can range from hundreds of megahertz to several gigahertz (e.g., between approximately 200 MHz and approximately 2 GHz). In this discussion, the oscillator signal may also be referred to as the oscillator signal or frequency signal. Nodes 103A and 105A may also be collectively referred to as the outputs, output ports, or output terminals of the oscillator circuit 150A.

[0036] like Figure 5 As shown, the bottom oscillator circuit 150A also includes a capacitor C coupled between the gate terminal of the first transistor M1 and node 105A. B And includes another capacitor C coupled between the gate terminal of the second transistor M2 and node 103A. B In some embodiments, capacitor C B The capacitance is less than that of capacitor C. P The capacitor, and the inductor L RX The inductance is greater than that of the inductor element L. TX The inductance.

[0037] See also Figure 5 The top oscillator circuit 150B has the same structure as the bottom oscillator circuit 150A (e.g., equivalent schematic diagram), so details will not be repeated. The transistors in the top oscillator circuit 150B are labeled as transistors M3 and M4. In some embodiments, the transistors (e.g., M1, M2, M3, and M4) in the top oscillator circuit 150B and the bottom oscillator circuit 150A are identical. For ease of discussion, the top oscillator circuit 150B and the bottom oscillator circuit 150A can be collectively referred to as oscillator circuit 150. Note that in Figure 5 In the middle, the reference voltage node 102A of the bottom oscillator circuit 150A is coupled to electrical ground, and the reference voltage node 102B of the top oscillator circuit 150B is coupled to the coil L of the bottom oscillator circuit 150A. TX The center tap. Additionally, the coil L of the top oscillator circuit 150B. TX The center tap is coupled to the power supply voltage V. DD (For example, +5V power supply voltage) power supply voltage node 106. Due to its center tap, the coil L in each oscillator circuit 150 TX It can be described as including a first coil L TX1 (For example, coil L) TX (the part to the left of the center tap) and the second coil L TX2 (For example, coil L)TX (The part to the right of the center tap).

[0038] Coupled between the respective output ports of the top oscillator circuit 150B and the bottom oscillator circuit 150A Figure 5 Capacitor C in S The oscillator signals generated by the top oscillator circuit 150B and the bottom oscillator circuit 150A are synchronized. In other words, the frequency and phase of the oscillator signal generated by the top oscillator circuit 150B are synchronized with the frequency and phase of the oscillator signal generated by the bottom oscillator circuit 150A.

[0039] The bias voltage V applied to the bias voltage node 101A of the bottom oscillator circuit 150A BIAS Used to turn the first transistor M1 and the second transistor M2 on and off, which in turn turns the bottom oscillator circuit 150A on and off. For example, if the bias voltage V BIAS If the voltage is high (e.g., higher than the turn-on voltage of the first transistor M1 and the second transistor M2), then the first transistor M1 and the second transistor M2 are turned on, and the bottom oscillator circuit 150A generates an oscillator signal. Similarly, if the voltage V... BIAS If the bias voltage is low (e.g., below the turn-on voltage of the first transistor M1 and the second transistor M2), then the first transistor M1 and the second transistor M2 are turned off, and the bottom oscillator circuit 150A does not generate an oscillator signal. The bias voltage V can be controlled. BIAS The high voltage duration is used to generate oscillator signals with different durations T1 and T2 (see...). Figure 4 ).

[0040] Similarly, by changing the bias voltage V applied at node 101B of the top oscillator circuit 150B... BIAS2 This is to control the top oscillator circuit 150B. Figure 5 In the example, the bias voltage V BIAS2 Equivalent to bias voltage V BIAS With power supply voltage V DD (e.g. V) BIAS2 =V BIAS +V DD The sum of half of ( / 2) causes the oscillator circuit 150 to be turned on and off synchronously (e.g., simultaneously).

[0041] Figure 5 The coil L of the oscillator circuit 150 is also shown. TX and the coil L of the Rx circuit 200 RX The magnetic coupling factor k between them. In other words, in coil L RX The received RF voltage includes the coil L from the bottom oscillator circuit 150A.TX and the coil L of the top oscillator circuit 150B TX The contribution of magnetic coupling factor k can be, for example, approximately 1 × 10⁻⁶. -3 and approximately 4×10 -3 Within the range between. Furthermore... Figure 5 The coil L of the bottom oscillator circuit 150A and the top oscillator circuit 150B are shown. TX The parasitic magnetic coupling factor kp. As an example, the parasitic magnetic coupling factor kp is greater than (e.g., greater than or greater than an order of magnitude) the magnetic coupling factor k, and can be in the range of, for example, approximately 100 to approximately 100. Parasitic magnetic coupling can reduce the coil L of the Rx circuit 200. RX The combined RF signal level at the location, and therefore should be minimized or reduced below a threshold. In some embodiments, across coil L RX The RF voltage V received by the terminal RX The voltage is given by the following formula: Where k is the magnetic coupling factor, k P It is the leakage magnetic coupling factor, V TX It is coil L TX The voltage across the two ends. Note that in the equation, L... TX and L RX They are used to represent coil L respectively TX and L RX The inductance.

[0042] The disclosed oscillator circuit 100 (or 100A, 100B discussed below) offers advantages that cannot be achieved with existing oscillator circuits. To understand the advantages of this disclosure, a comparison is made between the currently disclosed oscillator circuit and a conventional Class D oscillator circuit, which is equivalent to using only the bottom oscillator circuit 150A (e.g., directly coupled to the supply voltage V). DD (between power supply and ground) serves as an oscillator circuit. The oscillation amplitude (e.g., the amplitude of the oscillator signal) of a typical Class D oscillator circuit is approximately equal to the power supply voltage V. DDThree times that of conventional Class D oscillator circuits. Therefore, the transistors used in conventional Class D oscillator circuits (e.g., M1 and M2) must be special transistors with high breakdown voltage (BV), such as laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOSFETs), high-voltage MOSFETs (HVMOSFETs), or GaN HEMTs. These special transistors are incompatible with standard CMOS technology and can be fabricated using special techniques, leading to increased manufacturing costs and time. Furthermore, the current consumption of conventional Class D oscillator circuits is proportional to the oscillation amplitude, and thus, conventional Class D oscillator circuits suffer from high current consumption, especially when the Q factor of the coil is low (e.g., for bipolar-CMOS-DMOS (BCD) with a conductive substrate).

[0043] In contrast, in the disclosed oscillator circuit 100, each oscillator circuit 150 generates half the oscillation amplitude of a conventional Class D oscillator, and consumes current (e.g., at the reference voltage node 102B of the top oscillator circuit 150B and the coil L of the bottom oscillator circuit 150A). TX The current flowing between the center taps, such as Figure 5 (As indicated by arrow 111) is half the current consumption of a conventional Class D oscillator. Therefore, transistors M1 and M2 can be CMOS transistors formed using standard CMOS technology. Capacitor C S This ensures frequency / phase synchronization of the oscillator signal generated by oscillator circuit 150, and therefore, through magnetic coupling, the RF voltage induced by the oscillator signal generated by oscillator circuit 150 can be transmitted through the coil L of Rx circuit 200. RX The phases are added together to achieve the same received RF voltage as a conventional Class D oscillator circuit.

[0044] Figure 6 This is a schematic diagram of an oscillator circuit 100A in another embodiment. The oscillator circuit 100A is similar to... Figure 5 The oscillator circuit 100 includes a controllable switch 109A (or 109B) (e.g., a transistor) added between the gate terminals of transistors (e.g., M1 and M2, or M3 and M4) and a reference voltage node 102A (or 102B) of each in the oscillator circuit 150. Furthermore, during operation, a bias voltage V is supplied to the bottom oscillator circuit 150A. BIAS and the bias voltage V provided to the top oscillator circuit 150B BIAS2 It is a constant voltage corresponding to the respective turn-on voltage of the transistors (e.g., M1 and M2, or M3 and M4). Control voltage V CTRL_B A controllable switch 109A is coupled to the bottom oscillator circuit 150A and is used to open or close the bottom oscillator circuit 150A. Similarly, the control voltage VCTRL_T A controllable switch 109B is coupled to the top oscillator circuit 150B and is used to open or close the controllable switch 109B of the top oscillator circuit 150B. For example, when the control voltage V CTRL_B When the voltage is high, the controllable switch 109A of the bottom oscillator circuit 150A closes, and the gate voltages of transistors M1 and M2 are pulled down to ground, thereby turning off transistors M1 and M2. Conversely, when the control voltage V... CTRL_B When the voltage is low, the controllable switch 109A of the bottom oscillator circuit 150A is turned off, and the gate voltages of transistors M1 and M2 are pulled up to the bias voltage V. BIAS This turns on transistors M1 and M2. Therefore, the bias voltage (e.g., V) is not switched between high and low values ​​during operation (as in the operation of oscillator circuit 100). BIAS and V BIAS2 Instead, it switches the control voltage V between high and low values ​​during the operation of the oscillator circuit 100A. CTRL_B and V CTRL_T This is to generate the OOKPWM signal.

[0045] Modifications to the disclosed embodiments are possible and are fully intended to be included within the scope of this disclosure. For example, if compatible with the bias point (e.g., when the voltage at the drain terminals of transistors M3 and M4 equals the desired bias voltage V), modifications may be made. BIAS2 At that time, it is basically equal to V. DD Then, by removing the bias voltage V BIAS2 Resistor R and capacitor C B The top oscillator circuit 150B is connected in a self-biased configuration by directly cross-connecting the gate and drain terminals of transistors M3 and M4. In other words, in the self-biased configuration, the gate terminal of transistor M3 is directly coupled to the drain terminal of transistor M4, and the gate terminal of transistor M4 is directly coupled to the drain terminal of transistor M3. This self-biased configuration can be used to reduce the turn-on and turn-off times of the oscillator circuit 100A. As another example, if the bias quiescent point is compatible in the adopted implementation, the top oscillator circuit 150B can be turned on and off using only the controllable switch 109A in the bottom oscillator circuit 150A, where switch 109B, the resistor R of the top oscillator circuit 150B, and the capacitor C of the top oscillator circuit 150B are removed. B .

[0046] Figure 7 This is a schematic diagram of the oscillator circuit 100B in yet another embodiment. The oscillator circuit 100B is... Figure 5Overview of the oscillator circuit 100. Specifically, N conventional Class D oscillator circuits, labeled 150_1, 150_2… and 150_N, operate at a power supply voltage V. DD They are stacked together with a reference voltage (e.g., electrical ground). In the illustrated embodiments, the Class D oscillator circuits 150_1 to 150_N are identical. Similar to... Figure 5 capacitor C S Coupled between the respective output ports of two adjacent (e.g., directly adjacent) Class D oscillator circuits 150_i and 150_(i+1), where i = 1, 2…N-1. Capacitive coupling provided by capacitor CS ensures frequency / phase synchronization among the oscillator signals generated by all Class D oscillator circuits 150_1, 150_2… and 150_N. The bias voltage of the i-th Class D oscillator circuit 150_i is given by: Where i = 1, 2, ..., N.

[0047] The oscillation amplitude of each of the oscillator circuits 150_1, 150_2… and 150_N in oscillator circuit 100B is the oscillation amplitude of a reference design, where only a conventional Class D oscillator circuit is used to generate the transmitted RF signal, and the current consumption of oscillator circuit 100B is the current consumption of the reference design. The reduced oscillation amplitude allows the use of transistors with very low breakdown voltages (e.g., nanometer CMOS). Using transistors with lower breakdown voltages (and therefore higher switching frequencies ft) allows for increased oscillation frequencies, which allows for better data rates or multi-channel capabilities. Note that due to frequency / phase synchronization between the oscillator signals generated by all oscillator circuits 150_1, 150_2… and 150_N, contributions from all oscillator circuits 150_1, 150_2… and 150_N can be used in the coil L of Rx circuit 200. RX The phases are added together to generate the received RF signal, and therefore, coil L RX The received RF signal voltage is substantially the same as that of a conventional Class D oscillator circuit (assuming little or no parasitic magnetic coupling). In some embodiments, coil L RX The received RF signal voltage at the location is given by the following formula: in k is the magnetic coupling factor, N is the number of stacked Class D oscillators, and the symbol “OC” in the equation indicates that the above equation assumes pure capacitive coupling (e.g., no leakage magnetic coupling) between the coils of the stacked oscillator circuits 150_1, 150_2, ... and 150_N.

[0048] Figure 8 A cross-sectional view of a semiconductor chip 50 in one embodiment is shown. The semiconductor chip 50 may be... Figure 3 Chip 21 or 23 in the chip. Figure 8 In the example, during the back-end process (BEOL) of semiconductor manufacturing, micro-antennas (labeled 63A and 63B) are formed in the upper dielectric layer 53 of the semiconductor chip 50.

[0049] Reference Figure 8 The semiconductor chip 50 includes a substrate 51 (e.g., a silicon substrate). Electrical components 52, such as transistors, resistors, etc., are formed on or in the substrate 51. Interconnect structures, including dielectric layers 53 (e.g., silicon oxide) and conductive components (e.g., wires 55 and vias 57) formed in the dielectric layers 53, are formed on the substrate 51 to interconnect the electrical components 52, thereby forming a functional circuit. In some embodiments, etch stop layers 59 (e.g., silicon nitride) are formed between some dielectric layers 53. Figure 8 Also shown are conductive pads 61 (e.g., copper pads) at the topmost dielectric layer 53, and one or more micro-antennas 63A and 63B (e.g., coils) formed within the dielectric layer 53. As an example, the micro-antennas 63A and 63B may be formed as circular copper patterns in one or more upper dielectric layers 53. Figure 9 and 10 Example top views of microantennas 63A and 63B are shown in the figure. Figure 8 Further explanation is provided regarding the passivation layer 65 (e.g., a polymer layer) formed on the topmost dielectric layer 53 and the under-bump metallurgy (UBM) structure 67 formed on the conductive pads 61. Conductive connectors, such as copper pillars, solder balls, or combinations thereof, can be formed on the UMB structure 67 for connection to other devices.

[0050] Figure 9 It is shown in one embodiment in Figure 2 A top view of the microantenna used in the semiconductor package 20. For simplicity, Figure 9 The document does not describe all the features of semiconductor package 20. Figure 9 Microantennas 301A, 301B, and 303, as well as molding compound 29, are shown. Microantennas 301A and 301B can correspond to, for example... Figure 5 The coil L of the oscillator circuit 100 TX And it can be formed within one or more upper dielectric layers 53, for example, chip 21. The boundaries (e.g., sidewalls) of chip 21 are in Figure 9 The micro-antenna 303 is shown in dashed lines. It can correspond to, for example... Figure 5 The coil L in the Rx circuit 200 RX And it can be formed within, for example, the upper dielectric layer 53 of chip 23. The boundaries (e.g., sidewalls) of chip 23 are also... Figure 9 It is shown in dashed lines.

[0051] Figure 9 Microantennas 301A and 301B are placed side-by-side (e.g., without overlap) with a distance between them to reduce parasitic magnetic coupling between microantennas 301A and 301B (e.g., coils). However, Figure 9 The design (e.g., arrangement) of the microantennas 301A and 301B requires more than Figure 10 The design in this case has a larger silicon surface area.

[0052] Figure 10 In another embodiment, it is shown that Figure 2 A top view of the microantenna used in the semiconductor package 20. Figure 10 In the top view, microantennas 301A and 301B overlap. In some embodiments, microantennas 301A and 301B are formed within different upper dielectric layers 53 of chip 21 to avoid direct contact between microantennas 301A and 301B. Figure 10 The overlapping design in the design can lead to increased parasitic magnetic coupling between microantennas 301A and 301B, but has the advantage of requiring a smaller silicon surface area for chip 21. Those skilled in the art will readily understand that other designs for microantennas 301A, 301B, and 303 are also possible, with different trade-offs between parasitic magnetic coupling, silicon area, and magnetic coupling. These and other variations are fully intended to be included within the scope of this disclosure.

[0053] The disclosed embodiments offer advantages. The disclosed embodiments form the oscillator circuit by stacking multiple Class D oscillator circuits and using capacitive coupling (e.g., capacitor CS) between adjacent Class D oscillator circuits for frequency / phase synchronization. The disclosed oscillator circuit reduces the oscillation amplitude of each stacked Class D oscillator circuit and reduces the current consumption of the oscillator circuit. As a result, CMOS transistors formed using standard CMOS technology can be used in the disclosed oscillator circuit, which saves manufacturing costs and time and enables better system performance, such as higher data rates and better multi-channel capabilities.

[0054] Exemplary embodiments of this disclosure are summarized herein. Other embodiments may also be understood from the description and claims submitted herein.

[0055] Example 1. In one embodiment, a device includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes: a first transistor and a second transistor, wherein the gate terminal of the first transistor and the gate terminal of the second transistor are coupled to a first node, wherein a first load path terminal of the first transistor and the first load path terminal of the second transistor are coupled to a reference voltage node; a first coil coupled between a second load path terminal of the first transistor and a second load path terminal of the second transistor; and a first capacitor coupled in parallel with the first coil. The second oscillator circuit includes: a third transistor and a fourth transistor, wherein the gate terminal of the third transistor and the gate terminal of the fourth transistor are coupled to a second node, wherein the first load path terminal of the third transistor and the first load path terminal of the fourth transistor are coupled to a center tap of the first coil; a second coil coupled between the second load path terminal of the third transistor and the second load path terminal of the fourth transistor; and a second capacitor coupled in parallel with the second coil. The device further includes: a third capacitor coupled between the second load path terminal of the first transistor and the second load path terminal of the third transistor; and a fourth capacitor coupled between the second load path terminal of the second transistor and the second load path terminal of the fourth transistor.

[0056] Example 2. According to the device of Example 1, wherein the first node is configured to receive a first bias voltage for the first transistor and the second transistor, and the second node is configured to receive a second bias voltage for the third transistor and the fourth transistor.

[0057] Example 3. According to the device of Example 2, the second bias voltage is higher than the first bias voltage.

[0058] Example 4. According to the device of Example 1, the center tap of the second coil is coupled to the power supply voltage node.

[0059] Example 5. According to the device of Example 1, wherein the first oscillator circuit further includes: a first resistor coupled between the first node and the gate terminal of the first transistor; and a second resistor coupled between the first node and the gate terminal of the second transistor.

[0060] Example 6. According to the device of Example 5, wherein the first oscillator circuit further includes: a fifth capacitor coupled between the gate terminal of the first transistor and the second load path terminal of the second transistor; and a sixth capacitor coupled between the gate terminal of the second transistor and the second load path terminal of the first transistor.

[0061] Example 7. According to the device of Example 6, the second oscillator circuit further includes: a third resistor coupled between the second node and the gate terminal of the third transistor; and a fourth resistor coupled between the second node and the gate terminal of the fourth transistor.

[0062] Example 8. According to the device of Example 7, wherein the second oscillator circuit further includes: a seventh capacitor coupled between the gate terminal of the third transistor and the second load path terminal of the fourth transistor; and an eighth capacitor coupled between the gate terminal of the fourth transistor and the second load path terminal of the third transistor.

[0063] Example 9. According to the device of Example 1, wherein the first coil and the first capacitor form a first LC energy storage circuit configured to generate a first oscillator signal, and wherein the second coil and the second capacitor form a second LC energy storage circuit configured to generate a second oscillator signal.

[0064] Example 10. According to the device of Example 9, wherein the first oscillator signal and the second oscillator signal have the same oscillation frequency and the same phase.

[0065] Example 11. The device according to Example 1 further includes: a third coil, wherein the third coil is electromagnetically coupled to the first coil and the second coil; and a radio frequency (RF) circuit coupled to the third coil.

[0066] Example 12. In an embodiment, a device includes a first oscillator circuit and a second oscillator circuit cascaded with the first oscillator circuit, wherein the first oscillator circuit and the second oscillator circuit are configured to be coupled between a power supply voltage and electrical ground, wherein each of the first oscillator circuit and the second oscillator circuit is a Class D oscillator circuit, wherein the Class D oscillator circuit includes: a first transistor coupled between a reference voltage node of the Class D oscillator circuit and a first output of the Class D oscillator circuit; a second transistor coupled between the reference voltage node of the Class D oscillator circuit and a second output of the Class D oscillator circuit, wherein the gate terminals of the first transistor and the second transistor are coupled to a bias voltage node of the Class D oscillator circuit; a first coil coupled between the first output and the second output of the Class D oscillator circuit; and a first capacitor coupled in parallel with the first coil. The device further includes: a second capacitor coupled between the first output of the first oscillator circuit and the first output of the second oscillator circuit; and a third capacitor coupled between the second output of the first oscillator circuit and the second output of the second oscillator circuit.

[0067] Example 13. According to the device of Example 12, the first coil and the first capacitor of the first oscillator circuit are configured to form a first LC energy storage circuit, the first coil and the first capacitor of the second oscillator circuit are configured to form a second LC energy storage circuit, the first LC energy storage circuit is configured to generate a first oscillator signal, and the second LC energy storage circuit is configured to generate a second oscillator signal, wherein the first oscillator signal and the second oscillator signal have the same frequency and the same phase.

[0068] Example 14. According to the device of Example 12, the reference voltage node of the first oscillator circuit is configured to be coupled to the electrical ground, the reference voltage node of the second oscillator circuit is coupled to the center tap of the first coil of the first oscillator circuit, and the center tap of the first coil of the second oscillator circuit is configured to be coupled to the power supply voltage.

[0069] Example 15. According to the device of Example 12, the bias voltage node of the first oscillator circuit is configured to provide a first bias voltage, and the bias voltage node of the second oscillator circuit is configured to provide a second bias voltage higher than the first bias voltage.

[0070] Example 16. According to the device of Example 12, the Class D oscillator circuit further includes: a first resistor coupled between the bias voltage node and the gate terminal of the first transistor; and a second resistor coupled between the bias voltage node and the gate terminal of the second transistor.

[0071] Example 17. According to the device of Example 16, the Class D oscillator circuit further includes: a fourth capacitor coupled between the gate terminal of the first transistor and the second output of the Class D oscillator circuit; and a fifth capacitor coupled between the gate terminal of the second transistor and the first output of the Class D oscillator circuit.

[0072] Example 18. In one embodiment, an integrated circuit (IC) device includes a first oscillator circuit comprising: a first transistor and a second transistor, wherein the gate terminal of the first transistor is coupled to a first node via a first resistor, and the gate terminal of the second transistor is coupled to the first node via a second resistor; a first capacitor coupled between a drain terminal of the first transistor and a drain terminal of the second transistor; and a first coil coupled in parallel with the first capacitor. The IC device further includes a second oscillator circuit identical to the first oscillator circuit, wherein the source terminals of the first transistor and the second transistor of the first oscillator circuit are coupled to a reference voltage node, wherein the source terminals of the first transistor and the second transistor of the second oscillator circuit are coupled to a center tap of a first coil of the first oscillator circuit, and wherein the center tap of the first coil of the second oscillator circuit is coupled to a power supply voltage node. The IC device further includes: a second capacitor coupled between the drain terminal of the first transistor in the first oscillator circuit and the drain terminal of the first transistor in the second oscillator circuit; and a third capacitor coupled between the drain terminal of the second transistor in the first oscillator circuit and the drain terminal of the second transistor in the second oscillator circuit.

[0073] Example 19. According to the IC device of Example 18, the first node of the first oscillator circuit is configured to be provided with a first bias voltage, and the first node of the second oscillator circuit is configured to be provided with a second bias voltage higher than the first bias voltage.

[0074] Example 20. According to the IC device of Example 18, the first oscillator circuit further includes: a fourth capacitor coupled between the gate terminal of the first transistor and the drain terminal of the second transistor; and a fifth capacitor coupled between the gate terminal of the second transistor and the drain terminal of the first transistor.

[0075] Although this disclosure has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of this disclosure, will be apparent to those skilled in the art based on the specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A device comprising: The first oscillator circuit includes: A first transistor and a second transistor, wherein the gate terminal of the first transistor and the gate terminal of the second transistor are coupled to a first node, and wherein the first load path terminal of the first transistor and the first load path terminal of the second transistor are coupled to a reference voltage node; and The first LC energy storage circuit includes: A first capacitor is coupled between the second load path terminal of the first transistor and the second load path terminal of the second transistor; and The first coil is coupled in parallel with the first capacitor; The second oscillator circuit includes: A third transistor and a fourth transistor, wherein the gate terminals of the third transistor and the fourth transistor are coupled to a second node, and wherein the first load path terminals of the third transistor and the fourth transistor are coupled to the center tap of the first coil; and The second LC energy storage circuit includes: A second capacitor is coupled between the second load path terminal of the third transistor and the second load path terminal of the fourth transistor; and The second coil is coupled in parallel with the second capacitor; A third capacitor is coupled between the second load path terminal of the first transistor and the second load path terminal of the third transistor; A fourth capacitor is coupled between the second load path terminal of the second transistor and the second load path terminal of the fourth transistor; A first controllable switch is coupled between the gate terminal of the first transistor and the reference voltage node; and A second controllable switch is coupled between the gate terminal of the second transistor and the reference voltage node.

2. The device of claim 1, wherein the first node is configured to receive a first bias voltage for the first transistor and the second transistor, wherein the first bias voltage has a first fixed value.

3. The device of claim 2, wherein the first transistor and the second transistor are configured to be turned on by disconnecting the first controllable switch and the second controllable switch, wherein the first transistor and the second transistor are configured to be turned off by closing the first controllable switch and the second controllable switch.

4. The device according to claim 3, further comprising: A third controllable switch is coupled between the gate terminal of the third transistor and the center tap of the first coil; as well as A fourth controllable switch is coupled between the gate terminal of the fourth transistor and the center tap of the first coil.

5. The device of claim 4, wherein the second node is configured to receive a second bias voltage for the third transistor and the fourth transistor, wherein the second bias voltage has a second fixed value higher than the first fixed value.

6. The device of claim 5, wherein the third transistor and the fourth transistor are configured to be turned on by disconnecting the third controllable switch and the fourth controllable switch, wherein the third transistor and the fourth transistor are configured to be turned off by closing the third controllable switch and the fourth controllable switch.

7. The device of claim 6, wherein the first controllable switch, the second controllable switch, the third controllable switch and the fourth controllable switch are configured to be simultaneously turned on and off.

8. The device of claim 1, wherein the center tap of the second coil is coupled to a power supply voltage node.

9. The device of claim 1, wherein the first oscillator circuit further comprises: A first resistor is coupled between the first node and the gate terminal of the first transistor; A second resistor is coupled between the first node and the gate terminal of the second transistor; A fifth capacitor is coupled between the gate terminal of the first transistor and the second load path terminal of the second transistor; as well as A sixth capacitor is coupled between the gate terminal of the second transistor and the second load path terminal of the first transistor.

10. The device of claim 9, wherein the second oscillator circuit further comprises: A third resistor is coupled between the second node and the gate terminal of the third transistor; A fourth resistor is coupled between the second node and the gate terminal of the fourth transistor; A seventh capacitor is coupled between the gate terminal of the third transistor and the second load path terminal of the fourth transistor; as well as An eighth capacitor is coupled between the gate terminal of the fourth transistor and the second load path terminal of the third transistor.

11. The device of claim 1, wherein the first LC energy storage circuit is configured to generate a first oscillator signal, and the second LC energy storage circuit of the second oscillator circuit is configured to generate a second oscillator signal, wherein the first oscillator signal and the second oscillator signal have the same frequency.

12. The device of claim 11, wherein the first oscillator signal and the second oscillator signal further have the same phase.

13. A device comprising: First oscillator circuit; A second oscillator circuit, cascaded with the first oscillator circuit, wherein the first and second oscillator circuits are configured to be coupled between a power supply voltage and electrical ground, wherein each of the first and second oscillator circuits is a Class D oscillator circuit, wherein the Class D oscillator circuit includes: A first transistor is coupled between a reference voltage node of the Class D oscillator circuit and a first output of the Class D oscillator circuit; A second transistor is coupled between the reference voltage node of the Class D oscillator circuit and the second output of the Class D oscillator circuit, wherein the gate terminals of the first transistor and the second transistor are coupled to the bias voltage node of the Class D oscillator circuit; and LC energy storage circuit, including: A first capacitor is coupled between the first output and the second output of the Class D oscillator circuit; and A first coil, coupled in parallel with the first capacitor; and A second capacitor is coupled between the first output of the first oscillator circuit and the first output of the second oscillator circuit; and A third capacitor is coupled between the second output of the first oscillator circuit and the second output of the second oscillator circuit. The Class D oscillator circuit further includes: A first controllable switch is coupled between the gate terminal of the first transistor and the reference voltage node; and A second controllable switch is coupled between the gate terminal of the second transistor and the reference voltage node.

14. The device of claim 13, wherein the LC energy storage circuit of the first oscillator circuit is configured to generate a first oscillator signal, and the LC energy storage circuit of the second oscillator circuit is configured to generate a second oscillator signal, wherein the first oscillator signal and the second oscillator signal have the same frequency and the same phase.

15. The device of claim 13, wherein the reference voltage node of the first oscillator circuit is configured to be coupled to the electrical ground, wherein the reference voltage node of the second oscillator circuit is coupled to the center tap of the first coil of the first oscillator circuit, wherein the center tap of the first coil of the second oscillator circuit is configured to be coupled to the power supply voltage.

16. The device of claim 13, wherein the bias voltage node of the first oscillator circuit is configured to be provided with a first bias voltage, and wherein the bias voltage node of the second oscillator circuit is configured to be provided with a second bias voltage higher than the first bias voltage.

17. The device of claim 16, wherein the first bias voltage and the second bias voltage have corresponding fixed values, wherein the first transistor and the second transistor are configured to be turned on or off by opening or closing the first controllable switch and the second controllable switch.

18. An integrated circuit (IC) device, comprising: The first oscillator circuit includes: A first transistor and a second transistor, wherein the gate terminal of the first transistor and the gate terminal of the second transistor are coupled to a first node; A first coil is coupled between the drain terminal of the first transistor and the drain terminal of the second transistor; and A first capacitor is coupled in parallel with the first coil; A second oscillator circuit, wherein the second oscillator circuit has the same structure as the first oscillator circuit, wherein the source terminal of the first transistor of the first oscillator circuit and the source terminal of the second transistor of the first oscillator circuit are coupled to a reference voltage node, wherein the source terminal of the first transistor of the second oscillator circuit and the source terminal of the second transistor of the second oscillator circuit are coupled to the center tap of the first coil of the first oscillator circuit, wherein the center tap of the first coil of the second oscillator circuit is coupled to a power supply voltage node. A second capacitor is coupled between the drain terminal of the first transistor in the first oscillator circuit and the drain terminal of the first transistor in the second oscillator circuit; and A third capacitor is coupled between the drain terminal of the second transistor in the first oscillator circuit and the drain terminal of the second transistor in the second oscillator circuit. A first controllable switch is coupled between the gate terminal of the first transistor and the reference voltage node; and A second controllable switch is coupled between the gate terminal of the second transistor and the reference voltage node.

19. The IC device of claim 18, wherein the first node of the first oscillator circuit is configured to be provided with a first bias voltage, and the first node of the second oscillator circuit is configured to be provided with a second bias voltage different from the first bias voltage.

20. The IC device of claim 18, wherein the first coil of the first oscillator circuit and the first coil of the second oscillator circuit comprise a metal pattern in one or more dielectric layers of the IC device, wherein, in a top view, the first coil of the first oscillator circuit is spaced apart from the first coil of the second oscillator circuit.

21. The IC device of claim 18, wherein the first coil of the first oscillator circuit and the first coil of the second oscillator circuit comprise metal patterns in different dielectric layers of the IC device, wherein, in a top view, the first coil of the first oscillator circuit overlaps with the first coil of the second oscillator circuit.

22. The IC device of claim 19, wherein the second bias voltage is higher than the first bias voltage.

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