A method for manufacturing a semiconductor structure and a structure thereof

Abstract

Embodiments of the present disclosure relate to the field of semiconductors and provide a method for fabricating a semiconductor structure and its structure. The method may include: providing a substrate, the substrate including word lines extending along a first direction and an active area extending along a second direction; forming an initial mask on the substrate; forming a plurality of first pattern layers spaced apart on the initial mask layer, the first pattern layers extending along a third direction; patterning the initial mask using the first pattern layers as masks; forming a plurality of second pattern layers spaced apart on the patterned initial mask, the second pattern layers extending along a fourth direction; patterning the initial mask using the second pattern layers as masks to form a mask layer; and patterning the substrate using the mask layer as a mask to form a bit line contact pattern in the active area of ​​the substrate. This method can at least reduce the difficulty of forming the bit line contact pattern.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a method for manufacturing a semiconductor structure and the structure thereof. Background Art

[0002] Memory is a storage component used to store programs and various data. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor memory device in computers and is composed of many repeated storage cells.

[0003] Each memory cell generally includes a capacitor and a transistor, wherein the drain of the transistor is connected to the bit line and the source is connected to the capacitor. The transistor is connected to the bit line via a bit line contact structure, and the capacitor is connected to the bit line via a capacitor contact window.

[0004] Before forming a bit line contact structure, a bit line contact pattern needs to be formed first. However, currently, there is a problem of great difficulty in forming the bit line contact pattern. Summary of the Invention

[0005] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a structure thereof, which at least help to reduce the difficulty of forming a bit line contact pattern.

[0006] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising word lines extending along a first direction and an active area extending along a second direction, the first direction being different from the second direction; forming an initial mask on the substrate; forming a plurality of first graphic layers arranged at intervals on the initial mask layer, the first graphic layer extending along a third direction; patterning the initial mask using the first graphic layer as a mask; forming a plurality of second graphic layers arranged at intervals on the patterned initial mask, the second graphic layer extending along a fourth direction, the third direction being different from the fourth direction; patterning the initial mask using the second graphic layer as a mask to form a mask layer; patterning the substrate using the mask layer as a mask to form a bit line contact pattern in the active area of ​​the substrate.

[0007] In some embodiments, the angle between the first direction and the second direction is a first angle, the angle between the third direction and the fourth direction is a second angle, and the first angle and the second angle satisfy Wherein, α is the first angle, and β is the second angle.

[0008] In some embodiments, the first angle ranges from 60° to 80° or from 100° to 120°.

[0009] In some embodiments, the initial mask includes a first initial mask and a second initial mask stacked in sequence, and the material of the first initial mask is different from the material of the second initial mask; using the first graphic layer as a mask, the method of graphicing the initial mask includes: etching at least part of the thickness of the second initial mask to graphic the initial mask.

[0010] In some embodiments, the method of patterning the initial mask using the second pattern layer as a mask includes: etching at least a portion of the thickness of the first initial mask to pattern the initial mask.

[0011] In some embodiments, a material of the first preliminary mask includes silicon dioxide, and a material of the second preliminary mask includes silicon oxynitride.

[0012] In some embodiments, before forming the second initial mask, it also includes: forming a first intermediate layer on the surface of the first initial mask; before patterning the initial mask using the second graphic layer as a mask, it also includes: patterning the first intermediate layer using the second graphic layer as a mask.

[0013] In some embodiments, it also includes: forming a filling layer, the filling layer is located on the surface of the initial mask after patterning, and the top surface of the filling layer is higher than the top surface of the initial mask; forming a first protective layer, the first protective layer is located on the surface of the filling layer; before patterning the initial mask using the second graphic layer as a mask, it also includes patterning the first protective layer and the filling layer.

[0014] In some embodiments, the material of the filling layer includes a spin-coatable reagent, and the material of the first protection layer includes silicon oxynitride.

[0015] In some embodiments, before forming the first graphic layer, it also includes: forming a second intermediate layer, the second intermediate layer is located on the surface of the second initial mask; forming a second protective layer on the surface of the second intermediate layer; using the first graphic layer as a mask, before patterning the initial mask, it also includes: using the first graphic layer as a mask, patterning the second protective layer and the second intermediate layer.

[0016] In some embodiments, a material of the second protective layer includes silicon oxynitride, and a material of the second intermediate layer includes a carbon-containing material.

[0017] In some embodiments, before forming the first initial mask, it also includes: forming a third intermediate layer, wherein the third intermediate layer is located on the surface of the substrate; before patterning the active area using the mask layer as a mask, it also includes: patterning the third intermediate layer using the mask layer as a mask.

[0018] In some embodiments, the material of the third intermediate layer includes a carbon-containing material.

[0019] In some embodiments, a material of the first pattern layer includes photoresist, and a material of the second pattern layer includes photoresist.

[0020] In some embodiments, the orthographic projection of the first graphic layer on the surface of the substrate is a first strip graphic, the orthographic projection of the second graphic layer on the substrate is a second strip graphic, and the angle between the first strip graphic and the second strip graphic is 70° to 95°.

[0021] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a semiconductor structure formed using the above-mentioned method for manufacturing the semiconductor structure.

[0022] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by first forming a first graphic layer arranged at intervals, and patterning an initial mask through the first graphic layer, then forming a second graphic layer arranged at intervals, and patterning the initial mask using the second graphic layer as a mask to form a mask layer, the mask layer is formed by two patternings, and each patterning forms a continuous groove, the first graphic layer and the second graphic layer are etched layer by layer to form a mask layer with a target graphic, and then the substrate is patterned using the mask layer with the target graphic as a mask to form a desired bit line contact pattern on the substrate, which can reduce the difficulty of forming the bit line contact pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in traditional technologies, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians with insufficient skills, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figures 1 to 9 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] As can be seen from the background technology, as the process size decreases, it is becoming increasingly difficult to transfer the graphics of the bit line contact pattern layer by layer through the Litho-Etch-Litho-Etch method. In order to achieve the accuracy of the pattern transfer, a more advanced photolithography process is required, and the corresponding formation cost will also increase a lot.

[0026] The presently disclosed embodiment discloses a method for manufacturing a semiconductor structure, wherein a first pattern layer arranged at intervals is first formed, and an initial mask is patterned using the first pattern layer as a mask. A second pattern layer arranged at intervals is then formed on the initial mask, and the directions of the first pattern layer and the second pattern layer are inconsistent. The initial mask is patterned using the second pattern layer as a mask to form a mask layer having a target pattern. The process difficulty of forming continuous grooves by patterning is low, thereby reducing the difficulty of the entire manufacturing method, reducing the difficulty of the photolithography process, and reducing the cost of the entire manufacturing method.

[0027] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0028] Figures 1 to 9 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure.

[0029] refer to Figure 1 , Figure 1 A cross-sectional view of a semiconductor structure provided for one embodiment of the present disclosure includes: providing a substrate 100, the substrate 100 including word lines 110 extending along a first direction and an active area 120 extending along a second direction, the first direction being different from the second direction; forming an initial mask 140 on the substrate 100; and forming a plurality of first pattern layers 150 arranged at intervals on the initial mask 140, the first pattern layers 150 extending along a third direction.

[0030] In some embodiments, the word line 110 may include a conductive layer 111, a gate oxide layer 112 and a protective layer 113. The gate oxide layer 112 covers at least the side walls of the active area 120. The gate oxide layer 112 may also cover the bottom surface of the conductive layer 111. The protective layer 113 is located on the conductive layer 111. The material of the conductive layer 111 may be a metal material such as tungsten metal, the material of the gate oxide layer 112 may be an oxide such as silicon oxide, and the material of the protective layer 113 may be an insulating material such as silicon nitride.

[0031] In some embodiments, the conductive layer can also be a multi-layer structure, which can include a diffusion barrier layer and a metal layer. The diffusion barrier layer is located between the metal layer and the gate oxide layer to prevent the diffusion of metal ions in the metal layer. The metal layer is used to increase the conduction rate of the word line. The embodiments of the present disclosure do not limit the conductive layer.

[0032] In some embodiments, the base further includes a substrate 130 and an isolation structure 121. The substrate 130 is connected to the active area 120. The isolation structure 121 is located on the substrate 130. The isolation structure 121 is also located between the active areas 120, and the outer surface of part of the word line 110 is also surrounded by the isolation structure 121.

[0033] In some embodiments, the material of the isolation structure 121 may be an STI (Shallow Trench Isolation) structure, and the material of the isolation structure 121 may be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0034] In some embodiments, the surface of the substrate 100 further includes a target layer 131. The target layer 131 is located between the substrate 100 and the initial mask 140, and the target layer 131 is in contact with the surface of the substrate 100. The target layer 131 is used to subsequently form a bit line contact pattern on the target layer 131. The material of the target layer 131 can be polysilicon or other materials. The target layer 131 only serves as a film layer in the intermediate process of forming the bit line contact pattern. The present embodiment does not limit the material of the target layer 131.

[0035] In some embodiments, the material of the substrate 130 can be silicon, germanium, or silicon germanium, and the material of the substrate 130 can also be doped. Taking the material of the substrate 130 being silicon as an example, a trace amount of trivalent elements, such as boron, indium, gallium, or aluminum, can be doped into the substrate 130 to form a P-type substrate; similarly, a trace amount of pentavalent elements, such as phosphorus, antimony, arsenic, etc., can be doped into the substrate 130 to form an N-type substrate. The selection of doping elements for the substrate 130 can be considered based on actual needs and product performance. The present disclosure does not limit the material of the substrate 130 and the doped elements.

[0036] In some embodiments, the initial mask 140 includes a first initial mask 142 and a second initial mask 143 that are stacked, and the material of the first initial mask 142 is different from the material of the second initial mask 143. In some embodiments, the material of the first initial mask 142 includes silicon dioxide, and the material of the second initial mask 143 includes silicon oxynitride. By setting the first initial mask 142 and the second initial mask 143 to different materials, the second initial mask 143 can be patterned to form a target pattern, and the unnecessary film layer after patterning is removed. Then, the target pattern is formed on the first initial mask 142 by a pattern transfer method, and then the pattern of the first initial mask 142 is transferred to the target layer 131. By setting the first initial mask 142 and the second initial mask 143 to different materials, direct contact between the removal reagent or etching ions and the target layer 131 during the removal of the unnecessary film layer after patterning can be avoided, thereby improving the reliability of the semiconductor structure.

[0037] Continue to refer Figure 1 In some embodiments, before forming the first graphic layer 150 , the method further includes: forming a second intermediate layer 180 , the second intermediate layer 180 being located on the surface of the second initial mask 143 ; and forming a second protective layer 190 on the surface of the second intermediate layer 180 .

[0038] Forming the second intermediate layer 180 on the surface of the second preliminary mask 143 can improve the uniformity of the formed first patterned layer 150, thereby improving the accuracy of subsequent patterning. However, in some embodiments, the material of the second intermediate layer 180 is relatively soft, resulting in poor morphology of the formed second intermediate layer 180. Therefore, a second protective layer 190 can be formed on the surface of the second intermediate layer 180. The second protective layer 190 is relatively hard, so the morphology of the second intermediate layer 180 can be improved by limiting the position of the second intermediate layer 180. The formation of the second protective layer 190 can prevent the second preliminary mask 143 from contacting the etching reagent used to remove the first patterned layer 150 during the subsequent removal process of the first patterned layer 150, thereby protecting the second preliminary mask 143 and improving the accuracy of patterning.

[0039] In some embodiments, the material of the second protection layer 190 includes silicon oxynitride, and the material of the second intermediate layer 180 includes a carbon-containing material.

[0040] In some embodiments, a second intermediate layer 180 can be formed by spin-coating a carbon-containing material on the surface of the second initial mask 143. The second intermediate layer 180 is formed by a spin coating process. The spin coating process has a faster formation rate, which is beneficial to shortening the manufacturing process time; the corresponding material of the second intermediate layer 180 includes carbon or carbon-containing material. The texture of carbon or carbon-containing material is relatively soft and can be easily etched and removed, which is beneficial to further shortening the manufacturing process time of the semiconductor structure.

[0041] In some embodiments, silicon oxynitride can be directly deposited on the surface of the second intermediate layer 180. It is understandable that the material of the second intermediate layer 180 is relatively soft. If the first pattern layer 150 is directly formed on the surface of the second intermediate layer 180, the second intermediate layer 180 may be deformed under the action of the gravity of the first pattern layer 150. Therefore, a second protective layer 190 can be formed on the surface of the second intermediate layer 180. The corresponding material of the second protective layer 190 can be silicon oxynitride, which is a relatively hard material. By forming the second protective layer 190 on the surface of the second intermediate layer 180, the second intermediate layer 180 can be protected from deformation, thereby improving the accuracy of the formed pattern.

[0042] In some embodiments, before forming the second initial mask 143, the process further includes forming a first intermediate layer 200 on the surface of the first initial mask 142. The formation of the first intermediate layer 200 can serve as an etching stop during the subsequent patterning of the second initial mask 143. That is, the material of the first intermediate layer 200 is different from that of the second initial mask 143, so the etching agent used to etch the second initial mask 143 is different from the etching agent used to etch the first intermediate layer 200. Therefore, the formation of the first intermediate layer can prevent the etching agent used to etch the second initial mask 143 from contacting the first initial mask 142, thereby preventing the etching agent used to etch the second initial mask 143 from affecting the first initial mask 142, thereby improving the accuracy of the subsequently formed patterns.

[0043] In some embodiments, the material of the first intermediate layer 200 can be the same as the material of the second intermediate layer 180, and the method of forming the first intermediate layer 200 can adopt a spin coating process. The spin coating process has a faster formation rate, which is beneficial to shortening the manufacturing process time; and the material of the first intermediate layer 200 can be carbon or carbon-containing material. The texture of carbon or carbon-containing material is relatively soft and can be easily etched and removed, which is beneficial to further shorten the manufacturing process time of the semiconductor structure.

[0044] In some embodiments, before forming the first initial mask 142, the process further includes forming a third intermediate layer 210, which is located on the surface of the target layer 131. It is understood that the third intermediate layer 210 can be used to act as an etch stop during the subsequent patterning of the first initial mask 142. That is, the material of the third intermediate layer 210 is different from that of the first initial mask 142, and the etching agent used to etch the first initial mask 142 is different from the etching agent used to etch the third intermediate layer 210. Therefore, the formation of the third intermediate layer 210 can prevent the etching agent used to etch the first initial mask 142 from contacting the target layer 131, thereby preventing the etching agent used to etch the first initial mask 142 from affecting the target layer 131, thereby improving the accuracy of the subsequently formed patterns.

[0045] In some embodiments, the material of the third intermediate layer 210 can be the same as the material of the second intermediate layer 180, and the method of forming the third intermediate layer 210 can also adopt a spin coating process. The spin coating process has a faster formation rate, which is beneficial to shortening the manufacturing process time; and the material of the third intermediate layer 210 can include carbon-containing materials. Carbon or carbon-containing materials are relatively soft in texture and can be easily etched and removed, which is beneficial to further shorten the manufacturing process time of the semiconductor structure.

[0046] refer to Figure 2 , with the first graphic layer 150 (reference Figure 1 ) is a mask, patterning the initial mask 140.

[0047] In some embodiments, the initial mask 140 may include a first initial mask 142 and a second initial mask 143 stacked in sequence, and the material of the first initial mask 142 is different from the material of the second initial mask 143; Figure 1 ) is a mask, and the method for patterning the initial mask 140 includes: etching at least a portion of the thickness of the second initial mask 143 to pattern the initial mask 140.

[0048] It can be understood that this time the second initial mask 143 is patterned to form grooves extending along the third direction on the second initial mask 143, and the grooves are arranged at intervals. The difficulty of forming grooves extending along the third direction is lower than directly forming spaced recessed holes on the second initial mask 143, thereby reducing the difficulty of the entire process and reducing the material cost of the entire process.

[0049] In other embodiments, the first pattern layer is used as a mask, and during the process of patterning the initial mask, at least a portion of the first initial mask may be patterned to form grooves arranged at intervals on the first initial mask.

[0050] In some embodiments, before forming the first graphic layer 150, the method further includes forming a second intermediate layer 180 (refer to Figure 1 ), the second intermediate layer 180 (reference Figure 1 ) is located on the surface of the second initial mask 143; in the second intermediate layer 180 (reference Figure 1 ) to form a second protective layer 190 (reference Figure 1 ); with the first graphic layer 150 (reference Figure 1 ) as a mask, before patterning the initial mask 140, it also includes: using the first pattern layer 150 (reference Figure 1 ) is a mask, and the second protective layer 190 is patterned (refer to Figure 1 ) and the second intermediate layer 180 (reference Figure 1 ).

[0051] By forming the second intermediate layer 180 (refer to Figure 1 ) and the second protective layer 190 (reference Figure 1 ) can cooperate with the first graphic layer, by first Figure 1 ) and the second protective layer 190 (reference Figure 1 ) and then forming a corresponding pattern on the second initial mask 143, which can avoid over-etching of the second initial mask 143 and is beneficial to improving the quality of the pattern formed by etching the subsequent second initial mask 143.

[0052] In some embodiments, after patterning the second initial mask 143, the second intermediate layer 180 (see Figure 1 ), the second protective layer 190 (reference Figure 1 ) and the first graphic layer 150 (reference Figure 1 ).

[0053] refer to Figure 3 A plurality of second pattern layers 160 are formed on the patterned initial mask 140 and arranged at intervals. The second pattern layers 160 extend along a fourth direction, and the third direction is different from the fourth direction.

[0054] In some embodiments, the first graphic layer 150 (refer to Figure 1 ) includes photoresist, and the material of the second pattern layer 160 includes photoresist.

[0055] Photoresists are classified into two main categories based on the image they create: positive-working and negative-working. During the photoresist process, after exposure and development, the exposed areas are dissolved, leaving the unexposed areas. This is a positive-working photoresist. If the exposed areas are retained, while the unexposed areas are dissolved, the coating is a negative-working photoresist.

[0056] By selecting the first graphic layer 150 (refer to Figure 1 ) and the second pattern layer 160 is made of photoresist, which can facilitate the first pattern layer 150 (reference Figure 1 ) and a target pattern is formed on the second pattern layer 160.

[0057] In some embodiments, before forming the second graphic layer 160, it also includes: forming a filling layer 220, the filling layer 220 is located on the surface of the patterned initial mask 140, and the top surface of the filling layer 220 is higher than the top surface of the initial mask 140; forming a first protective layer 230, the first protective layer 230 is located on the surface of the filling layer 220.

[0058] By forming the filling layer 220 , the gaps in the patterned second initial mask 143 can be filled, thereby increasing the flatness of the second initial mask 143 , thereby improving the patterning accuracy when the second initial mask 143 is patterned again later.

[0059] It is understandable that the material of the filling layer 220 is relatively soft, and the morphology of the formed filling layer 220 is not good. Therefore, the morphology of the filling layer 220 can be improved by forming a first protective layer 230 on the surface of the filling layer 220 .

[0060] In some embodiments, the filling layer 220 can be formed by a spin coating process, and the first protective layer 230 can be formed by chemical vapor deposition. The spin coating process has a faster formation rate, which is beneficial to shortening the manufacturing process time; the corresponding material of the filling layer 220 can be a spin-coatable reagent, and the etching rate of the material of the spin-coatable reagent is faster, thereby increasing the rate of the entire etching process and reducing the production time of the entire production process.

[0061] refer to Figure 4 , using the second pattern layer 160 as a mask, patterning the initial mask 140 to form a mask layer 141.

[0062] In some embodiments, before patterning the initial mask 140 using the second pattern layer 160 as a mask, the process further includes: patterning the first protective layer 230 (refer to FIG. Figure 3 ) and the filling layer 220 (reference Figure 3 ).

[0063] By forming a filling layer 220 (refer to Figure 3 ) and the first protective layer 230 (reference Figure 3 ) can first be filled in the filling layer 220 (reference Figure 3 ) and the first protective layer 230 (reference Figure 3 ) is formed in a regular pattern, and then the accuracy of the pattern of the patterned initial mask 140 can be improved by patterning the initial mask 140.

[0064] In some embodiments, the patterned fill layer 220 (refer to Figure 3 ) and the first protective layer 230 (reference Figure 3 ) further includes: patterning the second preliminary mask 143 to form a target pattern on the second preliminary mask 143.

[0065] It is understandable that the first graphic layer 150 (refer to Figure 1 ) and the second graphics layer (reference Figure 3 ) has a different extension direction, and the second initial mask 143 is patterned twice. At this time, the remaining second initial mask 143 is the first pattern layer 150 (reference Figure 1 ) and the second graphic layer 160 (reference Figure 3 ) overlapped portion, and the non-overlapped portion is etched to form a bit line contact pattern 132. By patterning the target layer 131 by etching the grooves twice to form the bit line contact pattern 132, the difficulty of the entire production process can be reduced, and the material cost of the entire production process can be reduced.

[0066] In some embodiments, before patterning the initial mask 140 using the second patterned layer 160 as a mask, the process further includes patterning the first intermediate layer 200 using the second patterned layer 160 as a mask.

[0067] It is understandable that the target pattern formed on the first intermediate layer 200 has a higher pattern accuracy, so the pattern accuracy on the initial mask 140 can be improved by first forming the target pattern on the first intermediate layer 200 and patterning the initial mask 140 using the first intermediate layer 200 as a mask.

[0068] In some embodiments, a method for patterning the initial mask 140 using the second patterned layer 160 as a mask includes etching at least a portion of the thickness of the first initial mask 142 to pattern the initial mask 140. Multiple patterning steps can reduce the difficulty of forming the mask layer 141, and can form a mask layer 141 with a precise pattern. Furthermore, the material cost used to form the mask layer 141 is also low.

[0069] After patterning the initial mask 140, the process also includes: removing the second pattern layer 160 (refer to Figure 3 ), the first protective layer 230 (reference Figure 3 ), filling layer 220 (reference Figure 3 ), the second initial mask 143 (reference Figure 3 ) and a first intermediate layer 200.

[0070] In some other embodiments, after patterning the second initial mask 143, the first protection layer 230 may be removed first (see Figure 3 ), filling layer 220 (reference Figure 3) and the second graphic layer 160 (reference Figure 3 ), and with a second initial mask 143 (reference Figure 3 ) is a mask for patterning the first intermediate layer 200 and the first initial mask 142. After patterning the first initial mask 142, the process further includes: removing the first intermediate layer 200.

[0071] It can be understood that the first initial mask 142 formed at this time is a mask layer 141 with a spaced pattern. The process difficulty of forming the mask layer 141 can be reduced through multiple patterning, and a mask layer 141 with a precise pattern can be formed, and the material cost used to form the mask layer 141 is also low.

[0072] refer to Figures 5 to 7 , using the mask layer 141 as a mask, patterning the target layer 131 to form a bit line contact pattern 132. After forming the bit line contact pattern 132, it also includes filling the bit line contact pattern 132 to form a bit line contact structure. After forming the bit line contact structure, a bit line 170 electrically connected to the bit line contact structure can be prepared on the surface of the bit line contact structure.

[0073] Specifically, refer to Figure 5 In some embodiments, before patterning the target layer 131 using the mask layer 141 as a mask, the method further includes: patterning the third intermediate layer 210 using the mask layer 141 as a mask.

[0074] By first forming regular grooves on the third intermediate layer 210 and then forming corresponding patterns on the target layer 131 , over-etching of the target layer 131 can be avoided, which is beneficial to improving the quality of the pattern formed by etching the target layer 131 subsequently.

[0075] refer to Figure 6 , patterning the target layer 131 to form a bit line contact pattern 132 .

[0076] In some embodiments, a portion of the active area 120 is also patterned during the process of patterning the target layer 131 . By patterning the portion of the active area, it is ensured that the subsequently formed bit line contact structure contacts the active area 120 .

[0077] refer to Figure 7 , filling the bit line contact pattern 132 to form a bit line contact structure 133, and after forming the bit line contact structure 133, further comprising removing the target layer 131 (reference Figure 6 ).

[0078] refer to Figure 8 and Figure 9 , Figure 8 A top view of a semiconductor structure provided in one embodiment of the present disclosure is shown. Figure 9A schematic diagram of the extension direction of each film layer provided in an embodiment of the present disclosure is provided. A bit line 170 is formed. In some embodiments, the bit line extends along a fifth direction N.

[0079] In some embodiments, the angle between the first direction X and the second direction Y is a first angle, the angle between the third direction Z and the fourth direction M is a second angle, and the first angle and the second angle satisfy Wherein, α is the first angle, and β is the second angle.

[0080] refer to Figure 9 In some embodiments, the intersection of the first direction X and the second direction Y is C, the intersection of the second direction Y, the third direction Z, and the fifth direction N is A, the intersection of the third direction Z and the fourth direction M is D, the intersection of the first direction X and the third direction Z is B, and the intersection of the first direction, the fourth direction M, and the fifth direction N is O. According to mathematical relationships, ∠ODA = α = ∠OBA + ∠BOD; ∠OBA = ∠BOD = α / 2.

[0081] By controlling the extension directions of the first pattern layer 150 and the second pattern layer 160, the non-overlapping portion of the projection of the first pattern layer 150 on the substrate 100 and the projection of the second pattern layer 160 on the substrate 100 are made to be the desired target pattern, that is, the desired bit line contact pattern 132 can be formed by etching layer by layer.

[0082] In some embodiments, the first angle α is in the range of 60° to 80° or 100° to 120°. It can be understood that after forming the well-spaced active area 120, the direction of the active area 120 is determined. , by adjusting the extension direction of the word line 110, the extension direction of the first pattern layer 150, and the extension direction of the second pattern layer 160, the area of ​​the bit line contact pattern 132 formed on the active area 120 can be increased, so that when the active area 120 is relatively small, a larger area of ​​the bit line contact pattern 132 can be exposed to form the bit line contact pattern, thereby increasing the contact area between the subsequently formed bit line contact structure and the active area 120, reducing the contact resistance between the bit line contact structure and the active area 120, and improving the performance of the semiconductor structure.

[0083] In some embodiments, the orthographic projection of the first graphic layer 150 on the surface of the substrate 100 is a first strip pattern, and the orthographic projection of the second graphic layer 160 on the substrate 100 is a second strip pattern. The angle between the first strip pattern and the second strip pattern is 70° to 95°, for example, 83°, 85° or 92°.

[0084] By limiting the first strip pattern and the second strip pattern, a process basis can be provided for the subsequent formation of a target pattern. By limiting the angle between the first strip pattern and the second strip pattern, a bit line contact pattern directly aligned with the active area 120 is made, which places lower requirements on the resolution accuracy of the photolithography process, reduces the process difficulty and process cost, and can obtain a more accurate bit line contact structure on a smaller structure.

[0085] The present disclosure forms a first pattern layer 150 arranged at intervals, patterns the initial mask 140 through the first pattern layer 150, and then forms a second pattern layer 160 arranged at intervals. The initial mask 140 is patterned using the second pattern layer 160 as a mask to form a mask layer 141. The mask layer 141 is formed by two patterning operations, and each patterning operation forms a continuous groove. The first pattern layer 150 and the second pattern layer 160 are etched layer by layer to form the mask layer 141 having the target pattern, thereby reducing the difficulty of forming the bit line contact pattern 132.

[0086] The embodiments of the present disclosure also provide a semiconductor structure that can be formed using some or all of the above steps.

[0087] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising word lines extending along a first direction and active areas extending along a second direction, wherein the first direction is different from the second direction; forming an initial mask on the substrate; forming a plurality of first pattern layers arranged at intervals on the initial mask, wherein the first pattern layers extend along a third direction; patterning the initial mask using the first pattern layer as a mask; forming a plurality of second pattern layers arranged at intervals on the patterned initial mask, wherein the second pattern layers extend along a fourth direction, and the third direction is different from the fourth direction; Using the second patterned layer as a mask, patterning the initial mask to form a mask layer; Using the mask layer as a mask, patterning the substrate to form a bit line contact pattern in the active area of ​​the substrate; The angle between the first direction and the second direction is a first angle, the angle between the third direction and the fourth direction is a second angle, and the first angle and the second angle satisfy Wherein, α is the first angle, and β is the second angle.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first angle ranges from 60° to 80° or from 100° to 120°.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The initial mask includes a first initial mask and a second initial mask stacked in sequence, and the material of the first initial mask is different from the material of the second initial mask; The method of patterning the initial mask using the first pattern layer as a mask includes: The second initial mask is etched through at least a portion of the thickness to pattern the initial mask.

4. The method for fabricating a semiconductor structure according to claim 3, wherein the method of patterning the initial mask using the second pattern layer as a mask comprises: At least a portion of the thickness of the first initial mask is etched to pattern the initial mask. 5 . The method for manufacturing a semiconductor structure according to claim 3 , wherein a material of the first initial mask comprises silicon dioxide, and a material of the second initial mask comprises silicon oxynitride.

6. The method for manufacturing a semiconductor structure according to claim 3, before forming the second initial mask, further comprising: forming a first intermediate layer on the surface of the first initial mask; Before patterning the initial mask using the second pattern layer as a mask, the method further includes: patterning the first intermediate layer using the second pattern layer as a mask.

7. The method for manufacturing a semiconductor structure according to claim 3, before forming the second patterned layer, further comprising: forming a filling layer, wherein the filling layer is located on the patterned surface of the initial mask, and a top surface of the filling layer is higher than a top surface of the initial mask; forming a first protective layer, wherein the first protective layer is located on the surface of the filling layer; Before patterning the initial mask using the second pattern layer as a mask, the method further includes: The first protection layer and the filling layer are patterned. 8 . The method for manufacturing a semiconductor structure according to claim 7 , wherein the material of the filling layer comprises a spin-coatable reagent, and the material of the first protective layer comprises silicon oxynitride.

9. The method for manufacturing a semiconductor structure according to claim 3, wherein: Before forming the first graphic layer, the method further includes: forming a second intermediate layer, the second intermediate layer being located on the surface of the second initial mask; forming a second protective layer on the surface of the second intermediate layer; and using the first patterned layer as a mask to pattern the initial mask, the method further includes: The second protection layer and the second intermediate layer are patterned using the first patterned layer as a mask. 10 . The method for manufacturing a semiconductor structure according to claim 9 , wherein a material of the second protective layer comprises silicon oxynitride, and a material of the second intermediate layer comprises a carbon-containing material.

11. The method for manufacturing a semiconductor structure according to claim 3, wherein: Before forming the first initial mask, the method further includes: forming a third intermediate layer, the third intermediate layer being located on the surface of the substrate; and before patterning the active area using the mask layer as a mask, further comprising: The third intermediate layer is patterned using the mask layer as a mask.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: The material of the third intermediate layer includes a carbon-containing material.

13. The method for manufacturing a semiconductor structure according to claim 1, wherein: The material of the first pattern layer includes photoresist, and the material of the second pattern layer includes photoresist.

14. The method for manufacturing a semiconductor structure according to claim 1, wherein: The orthographic projection of the first graphic layer on the surface of the substrate is a first stripe graphic, the orthographic projection of the second graphic layer on the substrate is a second stripe graphic, and the angle between the first stripe graphic and the second stripe graphic is 70° to 95°.

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