Display device and its manufacturing method

Abstract

A display device (100) and a method for manufacturing the same are disclosed. The display device (100) includes a substrate (600) and at least one pixel circuit formed on the substrate (600). The pixel circuit includes a driving transistor (140), a first transistor (110), and a second transistor (120). The driving transistor (140) includes a control electrode (143), a first electrode (141), and a second electrode (142), and is configured to control the flow of current through the driving transistor (140) according to the voltage of the control electrode (143). The first electrode (141) and the second electrode (142) of the driving transistor (140) are driven by a driving current for driving the light-emitting element (LE) to emit light; the first transistor (110) includes a first active region (114), the second transistor (120) includes a second active region (124), and the driving transistor (140) includes a fourth active region (144). The doping concentration of at least one of the first active region (114) and the second active region (124) is greater than the doping concentration of the fourth active region (144). The display device can improve the uniformity of light emission by driving the light-emitting element.

Description

[0001] This invention is a divisional application of the patent application filed on August 23, 2019, with application number 201980001452.2 and title "Display Device and Method for Preparing the Same". Technical Field

[0002] Embodiments of this disclosure relate to a display device and a method for manufacturing the same. Background Technology

[0003] Micro-OLED (Micro-Organic Light-Emitting Diode) displays are a new type of OLED display device using a silicon substrate, also known as silicon-based OLED displays. Silicon-based OLED displays offer advantages such as small size and high resolution. They are fabricated using mature CMOS integrated circuit technology, enabling active pixel addressing. Furthermore, various functional circuits, including TCON (Timing Control) circuits and OCP (Operation Control) circuits, can be fabricated on the silicon substrate, allowing for lightweight design. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display device, including a substrate and at least one pixel circuit formed on the substrate. The pixel circuit includes a driving transistor, a first transistor, and a second transistor. The driving transistor includes a control electrode, a first electrode, and a second electrode, and is configured to control a driving current flowing through the first electrode and the second electrode of the driving transistor for driving a light-emitting element to emit light, based on the voltage of the control electrode of the driving transistor. The first transistor is connected to the control electrode of the driving transistor and is configured to write a data signal to the control electrode of the driving transistor in response to a first scan signal. The second transistor is connected to the control electrode of the driving transistor and is configured to write the data signal to the control electrode of the driving transistor in response to a second scan signal. The first transistor includes a first active region, the second transistor includes a second active region, and the driving transistor includes a fourth active region. The doping concentration of at least one of the first active region and the second active region is greater than the doping concentration of the fourth active region.

[0005] For example, in a display device provided in an embodiment of this disclosure, the doping concentrations of the first active region and the second active region are both greater than the doping concentration of the third active region.

[0006] For example, in a display device provided in an embodiment of this disclosure, the pixel circuit further includes a third transistor connected to a first electrode of the driving transistor and configured to apply a first power supply voltage to the first electrode of the driving transistor in response to a light emission control signal; the third transistor includes a third active region, and the doping concentration of the fourth active region is less than the doping concentration of the third active region.

[0007] For example, in a display device provided in one embodiment of this disclosure, the doping concentration of the fourth active region is four orders of magnitude smaller than the doping concentration of the third active region.

[0008] For example, in a display device provided in one embodiment of this disclosure, the doping concentration of the third active region includes 10. 17 cm -3 The doping concentration of the fourth active region includes 10. 13 cm -3 .

[0009] For example, in a display device provided in one embodiment of this disclosure, the doping concentration of the first active region and the second active region is three orders of magnitude greater than the doping concentration of the third active region.

[0010] For example, in a display device provided in one embodiment of this disclosure, the doping concentration of the third active region includes 10. 17 cm -3 The doping concentrations of the first active region and the second active region include 10. 20 cm -3 .

[0011] For example, in a display device provided in an embodiment of this disclosure, the first transistor is a first semiconductor type MOS transistor, and the second transistor, the third transistor and the driving transistor are all second semiconductor type MOS transistors, with the first semiconductor type and the second semiconductor type having opposite doping types.

[0012] For example, in a display device provided in an embodiment of this disclosure, the direction from the first pole of the first transistor to the second pole of the first transistor is a first direction, the direction from the first pole of the second transistor to the second pole of the second transistor is a second direction, the direction from the first pole of the third transistor to the second pole of the third transistor is a third direction, and the direction from the first pole of the driving transistor to the second pole of the driving transistor is a fourth direction, and at least one of the first direction, the second direction, and the third direction intersects with the fourth direction.

[0013] For example, in a display device provided in one embodiment of this disclosure, the first direction, the second direction, and the third direction are all perpendicular to the fourth direction.

[0014] For example, in a display device provided in one embodiment of this disclosure, the first electrode of the first transistor and the first electrode of the second transistor are connected to form a common electrode, and connected to the control electrode of the driving transistor through the common electrode; the control electrode of the first transistor is configured to receive the first scan signal, and the second electrode of the first transistor is configured to receive the data signal; the control electrode of the second transistor is configured to receive the second scan signal, and the second electrode of the second transistor is configured to receive the data signal; the control electrode of the third transistor is configured to receive the light emission control signal, the first electrode of the third transistor is configured to receive the first power supply voltage, and the second electrode of the third transistor is connected to the first electrode of the driving transistor; the second electrode of the driving transistor is configured to be connected to the light emission element.

[0015] For example, in a display device provided in one embodiment of this disclosure, the pixel circuit further includes a storage capacitor, the first terminal of which is connected to the control terminal of the driving transistor, and the second terminal of which is configured to receive a third power supply voltage.

[0016] For example, a display device provided in one embodiment of the present disclosure further includes a first scan signal line for transmitting the first scan signal and a second scan signal line for transmitting the second scan signal, wherein the orthographic projection of the first scan signal line on the substrate is parallel to the orthographic projection of the second scan signal line on the substrate.

[0017] For example, in a display device provided in one embodiment of this disclosure, the extension directions of both the first scan signal line and the second scan signal line are parallel to the fourth direction.

[0018] For example, a display device provided in one embodiment of this disclosure further includes a data line for transmitting the data signal, wherein the orthographic projection of the second scan signal line on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.

[0019] For example, a display device provided in one embodiment of this disclosure further includes a first power supply voltage line for transmitting the first power supply voltage and a light emission control line for transmitting a light emission control signal. The first power supply voltage line and the light emission control line extend in a direction parallel to the fourth direction. The first scan signal line, the second scan signal line, the first power supply voltage line, and the light emission control line are arranged sequentially along a direction perpendicular to the fourth direction in the orthogonal projection of the substrate.

[0020] For example, a display device provided in one embodiment of this disclosure further includes a second power supply voltage line for transmitting a second power supply voltage, wherein the first transistor and the second power supply voltage line are electrically connected to receive the second power supply voltage.

[0021] For example, in a display device provided in an embodiment of this disclosure, the orthographic projection of the second power supply voltage line on the substrate is located between the orthographic projection of the first power supply voltage line on the substrate and the orthographic projection of the light emission control line on the substrate, and a portion of the extension direction of the second power supply voltage line is parallel to the fourth direction.

[0022] For example, a display device provided in one embodiment of this disclosure further includes a first transfer electrode disposed on a first side of the light-emitting control line, and a second transfer electrode extending from the first side of the light-emitting control line to a second side of the light-emitting control line. The orthographic projection of the second transfer electrode on the substrate intersects the orthographic projection of the light-emitting control line on the substrate. The two ends of the first transfer electrode are electrically connected to the first electrode of the first transistor and the first electrode of the second transistor, respectively. The first transfer electrode and the second transfer electrode are electrically connected, and the second transfer electrode is electrically connected to the control electrode of the driving transistor.

[0023] For example, in a display device provided in one embodiment of this disclosure, the extension direction of the second adapter electrode is perpendicular to the extension direction of the first adapter electrode and also perpendicular to the fourth direction.

[0024] For example, in a display device provided in an embodiment of this disclosure, the orthographic projection of the first active region of the first transistor on the substrate and the orthographic projection of the second active region of the second transistor on the substrate are both located between the orthographic projection of the second scan signal line on the substrate and the orthographic projection of the light emission control line on the substrate; the orthographic projection of the first active region of the first transistor on the substrate intersects with the orthographic projection of the first power supply voltage line on the substrate, and the orthographic projection of the first active region of the first transistor on the substrate intersects with the orthographic projection of the second power supply voltage line on the substrate; and the orthographic projection of the second active region of the second transistor on the substrate intersects with the orthographic projection of the first power supply voltage line on the substrate, and the orthographic projection of the second active region of the second transistor on the substrate intersects with the orthographic projection of the second power supply voltage line on the substrate.

[0025] For example, a display device provided in one embodiment of the present disclosure further includes a driving circuit located in the substrate, the driving circuit being configured to provide the first scan signal, the second scan signal, and the light emission control signal to the at least one pixel circuit.

[0026] At least one embodiment of this disclosure also provides a method for fabricating a display device, comprising: forming a pixel circuit on a substrate, the pixel circuit including a driving transistor, a first transistor, and a second transistor; the driving transistor including a control electrode, a first electrode, and a second electrode, and configured to control a driving current flowing through the first electrode and the second electrode of the driving transistor for driving a light-emitting element to emit light according to the voltage of the control electrode of the driving transistor; the first transistor being connected to the control electrode of the driving transistor and configured to write a data signal to the control electrode of the driving transistor in response to a first scan signal; the second transistor being connected to the control electrode of the driving transistor and configured to write the data signal to the control electrode of the driving transistor in response to a second scan signal; the first transistor including a first active region, the second transistor including a second active region, and the driving transistor including a fourth active region; the fabrication method further comprising: doping the first active region, the second active region, and the fourth active region such that the doping concentration of at least one of the first active region and the second active region is greater than the doping concentration of the fourth active region.

[0027] For example, in a fabrication method provided in an embodiment of this disclosure, the pixel circuit further includes a third transistor connected to the first electrode of the driving transistor and configured to apply a first power supply voltage to the first electrode of the driving transistor in response to a light emission control signal. The third transistor includes a third active region. The fabrication method further includes doping the third active region such that the doping concentration of the fourth active region is less than the doping concentration of the third active region. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0029] Figure 1 This is a schematic cross-sectional view of a display substrate;

[0030] Figure 2 A circuit diagram of a display device provided for at least one embodiment of this disclosure;

[0031] Figure 3 The at least one embodiment provided by this disclosure corresponds to Figure 2 Layout diagram;

[0032] Figures 4A-4E They are shown respectively Figure 3 A plan view of the five-layer layout of the display device shown;

[0033] Figure 5 A schematic diagram illustrating the region where a storage capacitor is located, provided for at least one embodiment of this disclosure;

[0034] Figure 6 A schematic diagram of the layout of the storage capacitor provided for at least one embodiment of this disclosure;

[0035] Figures 7A-7D They are shown respectively Figure 6 A plan view showing the distribution of the four layers;

[0036] Figure 7E A cross-sectional schematic diagram of a storage capacitor provided for at least one embodiment of this disclosure;

[0037] Figure 8 A cross-sectional schematic diagram of a first transistor and a second transistor is provided for at least one embodiment of this disclosure;

[0038] Figure 9 Another cross-sectional schematic diagram of the first transistor and the second transistor provided for at least one embodiment of this disclosure;

[0039] Figure 10 Another cross-sectional schematic diagram of the first transistor and the second transistor provided for at least one embodiment of this disclosure; and

[0040] Figure 11 This is a schematic diagram of a display device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0043] Currently, silicon-based OLED display panels are widely used in near-eye display fields such as Virtual Reality (VR) and Augmented Reality (AR). As users demand increasingly higher display quality, such as higher resolution and PPI (Pixels Per Inch), achieving a higher PPI requires designing the display device layout to reduce the occupied area. This allows for more pixel units to be placed within the same display area, thus enabling a higher PPI.

[0044] The display device and its fabrication method provided in at least one embodiment of this disclosure can reduce the layout area occupied by the display device through layout design, thereby making it easier to achieve a high PPI. In addition, at least one embodiment of this disclosure also provides a transistor structural design that can reduce or avoid the risk of high-voltage breakdown.

[0045] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic diagram of the structure of a display substrate 1000. (Example) Figure 1 As shown, the display substrate 1000 includes a substrate 600 and a light-emitting element 620. For example, the light-emitting element 620 is disposed on the substrate 600, and the first electrode 621 of the light-emitting element 620 is closer to the substrate 600 than the second electrode 629 of the light-emitting element 620.

[0047] For example, in some examples, the substrate 600 is a silicon-based substrate, and embodiments of this disclosure include, but are not limited to, this. For example, the semiconductor fabrication process used in silicon-based substrates is mature and has stable performance, which is beneficial for fabricating microdisplay devices.

[0048] For example, in some examples, the silicon substrate 600 includes a driving circuit electrically connected to the light-emitting element 620 for driving the light-emitting element 620 to emit light. For example, as Figure 1 As shown, the driving circuit includes transistor T. It should be noted that the specific circuit structure of the driving circuit can be configured according to actual needs. For example, Figure 1 The complete structure of the driving circuit is not shown in the figure. The driving circuit may also include, for example, other transistors, or storage capacitors, etc. The embodiments of this disclosure do not limit this.

[0049] For example, such as Figure 1 As shown, transistor T includes a gate electrode G, a source electrode S, and a drain electrode D. The three electrodes correspond to three electrode connection portions. For example, the gate electrode G is electrically connected to the gate electrode connection portion 610g, the source electrode S is electrically connected to the source electrode connection portion 610s, and the drain electrode D is electrically connected to the drain electrode connection portion 610d. Alternatively, all three electrodes may be electrically connected to their respective electrode connection portions via tungsten vias 605.

[0050] For example, such as Figure 1 As shown, the source electrode connection portion 610s is electrically connected to the first electrode 621 of the light-emitting element 620 through a tungsten via. For example, the source electrode connection portion 610s is electrically connected to the metal reflective layer 622 of the first electrode 621 through a tungsten via. Simultaneously, in the first electrode 621, the transparent conductive layer 626 is electrically connected to the metal reflective layer 622 through a via 624a in the inorganic insulating layer 624. When the transistor T is in the on state, the electrical signal provided by the power line can be transmitted to the transparent conductive layer 626 through the source electrode S of the transistor T, the source electrode connection portion 610s, and the metal reflective layer 622. Because a voltage difference is formed between the transparent conductive layer 626 and the second electrode 629, an electric field is formed between them. Holes and electrons are injected into the light-emitting functional layer 627, and the light-emitting functional layer 627 emits light under the action of this electric field. It is understandable that in transistor T, the positions of the source electrode S and the drain electrode D can be interchanged (correspondingly, the positions of the source electrode connection portion 610s and the drain electrode connection portion 610d can also be interchanged). That is to say, one of the source electrode S and the drain electrode D of the transistor (i.e., the source electrode S or the drain electrode D) can be electrically connected to the light-emitting element 620.

[0051] For example, the materials of the gate electrode connection portion 610g, the source electrode connection portion 610s, and the drain electrode connection portion 610d may include metallic materials. For example, such as... Figure 1As shown, an anti-oxidation layer 607 can be provided on at least one side (e.g., the upper side and / or the lower side) of each of the gate electrode connection portion 610g, the source electrode connection portion 610s and the drain electrode connection portion 610d, which can effectively prevent these electrode connections from being oxidized and improve their conductivity.

[0052] For example, such as Figure 1 As shown, the display substrate 1000 also includes a defining layer 728 for defining the light-emitting functional layer 727. The defining layer 728 defines the organic light-emitting functional layer 727 in its opening 728a to avoid crosstalk between adjacent sub-pixels.

[0053] It should be noted that, in Figure 1 In the display substrate 1000 shown, the via 624a in the inorganic insulating layer 624 can be disposed between the edge region of the transparent conductive layer 626 and the metal reflective layer 622. For example, in some examples, the orthographic projection of the light-emitting functional layer 627 on the substrate 600 and the orthographic projection of the via 624a on the substrate 600 are both located within the orthographic projection of the metal reflective layer 622 on the substrate 600. At the same time, there is no overlap between the orthographic projection of the light-emitting functional layer 627 on the substrate 600 and the orthographic projection of the via 624a on the substrate 600. Therefore, when the metal reflective layer reflects the light emitted by the light-emitting functional layer 627, the via 624a has virtually no effect on the reflection process.

[0054] At least one embodiment of this disclosure provides a display device 100, which includes a substrate, at least one pixel circuit formed on the substrate, and a light-emitting element driven by the pixel circuit. The substrate is, for example, a silicon-based substrate, which may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The pixel circuit can be fabricated in the substrate using silicon semiconductor processes (e.g., CMOS processes), while the light-emitting element is fabricated on the silicon substrate having the pixel circuit.

[0055] The following is combined Figure 2 and Figure 3 In introducing the display device 100, it should be noted that, Figure 2 and Figure 3 The substrate is not shown. For information on substrates, please refer to [reference needed]. Figure 1 The substrate 600 shown is shown.

[0056] like Figure 2 As shown, the pixel circuit includes a driving transistor 140, a first transistor 110, a second transistor 120, and a third transistor 130. It should be noted that in some embodiments, the pixel circuit may not include the third transistor 130, and the embodiments disclosed herein do not limit this.

[0057] For example, the driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142. The driving transistor 140 is configured to control the driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving the light-emitting element LE to emit light, based on the voltage of the control electrode 143. The light-emitting element LE can emit light of different intensities depending on the magnitude of the driving current.

[0058] It should be noted that the source and drain of the transistors used in the embodiments of this disclosure can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal and the other as the second terminal. Therefore, the first and second terminals of all or some of the transistors in the embodiments of this disclosure can be interchanged as needed. For example, the first terminal of the transistor described in the embodiments of this disclosure can be the source and the second terminal can be the drain; or, the first terminal of the transistor is the drain and the second terminal is the source. The following embodiments use the example of a transistor with the first terminal as the drain and the second terminal as the source for illustration, and will not be repeated.

[0059] For example, the first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1.

[0060] For example, the second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.

[0061] For example, the third transistor 130 is connected to the first terminal 141 of the driving transistor 140 and is configured to apply a first power supply voltage ELVDD to the first terminal 141 of the driving transistor 140 in response to the light emission control signal EN. For example, in embodiments of this disclosure, the first power supply voltage ELVDD is a high-level voltage, such as 5V.

[0062] like Figure 2 As shown, in some embodiments, the first electrode 111 (e.g., drain) of the first transistor 110 and the first electrode 121 (e.g., drain) of the second transistor 120 are connected to form a common electrode, and are connected to the control electrode 143 of the driving transistor 140 through the common electrode.

[0063] In the above embodiments, a first scan signal line SL1, a second scan signal line SL2, a data line DL, a first power supply voltage line VL1, and a light emission control line EL are also provided to provide corresponding electrical signals. The control electrode 113 of the first transistor 110 is configured to receive a first scan signal SCAN1 from the first scan signal line SL1, and the second electrode 112 (e.g., the source) of the first transistor 110 is configured to receive a data signal DATA from the data line DL. The control electrode 123 of the second transistor 120 is configured to receive a second scan signal SCAN2 from the second scan signal line SL2, and the second electrode 122 (e.g., the source) of the second transistor 120 is configured to receive a data signal DATA from the data line DL. The control electrode 133 of the third transistor 130 is configured to receive the light emission control signal EN from the light emission control line EL, the first electrode 131 (e.g., drain) of the third transistor 130 is configured to receive the first power supply voltage ELVDD from the first power supply voltage line VL1, and the second electrode 132 (e.g., source) of the third transistor 130 is connected to the first electrode 141 (e.g., drain) of the driving transistor 140.

[0064] The second terminal 142 (e.g., the source) of the driving transistor 140 is configured to be connected to the first terminal of the light-emitting element LE. For example, when the light-emitting element LE is an OLED, the second terminal 142 of the driving transistor 140 can be connected to the anode of the OLED. For example, the second terminal of the light-emitting element LE is configured to receive a fourth power supply voltage VCOM. For example, in embodiments of this disclosure, the fourth power supply voltage VCOM is a low-level voltage.

[0065] For example, in the embodiments of this disclosure, the light-emitting element LE can be an OLED. When multiple pixel units constitute a pixel array in a display panel, the second electrodes (e.g., cathodes) of multiple light-emitting elements OLED in multiple pixel units can be electrically connected together, for example, respectively connected to the same electrode or integrally formed, to receive a fourth power supply voltage VCOM. That is, the multiple light-emitting elements OLED in multiple pixel units adopt a common cathode connection method.

[0066] For example, the light-emitting element OLED can be of various types, such as top-emitting, bottom-emitting, etc., and can emit red light, green light, blue light or white light, etc. The embodiments disclosed herein do not limit this.

[0067] For example, such as Figure 2As shown, the pixel circuit also includes a storage capacitor CST to store the data signal DATA written to the control terminal 143 of the driving transistor 140, thereby enabling the driving transistor 140 to control the magnitude of the driving current of the light-emitting element LE according to the voltage of the stored data signal DATA. The first terminal of the storage capacitor CST is connected to the control terminal 143 of the driving transistor 140, and the second terminal of the storage capacitor CST is configured to receive a third power supply voltage AVSS. For example, in the embodiments of this disclosure, the third power supply voltage AVSS is a low-level voltage. It should be noted that in the embodiments of this disclosure, the third power supply voltage AVSS can be the same as the fourth power supply voltage VCOM; for example, the third power supply voltage AVSS and the fourth power supply voltage VCOM can both be grounded. Embodiments of this disclosure include, but are not limited to, this.

[0068] like Figure 2 As shown, in some embodiments of this disclosure, the first transistor 110 may be a P-type MOS transistor, and the second transistor 120, the third transistor 130 and the driving transistor 140 may be N-type MOS transistors. For example, the first transistor 110, the second transistor 120, the third transistor 130 and the driving transistor 140 are formed in a substrate.

[0069] For example, such as Figure 2 As shown, the third stage of the first transistor 110 is configured to receive the second power supply voltage VDD. For example, the third stage of the first transistor 110 is connected to the second power supply voltage line VL2 to receive the second power supply voltage VDD.

[0070] For example, the third terminal of the second transistor 120, the third transistor 130, and the driving transistor 140 is configured to ground (GND). It should be noted that in the embodiments of this disclosure, the third terminal of a transistor is the terminal opposite to the control terminal (gate) 113 of the transistor, and the following embodiments are the same and will not be described again.

[0071] In embodiments of this disclosure, since the first transistor 110 and the second transistor 120 employ MOS transistors with opposite semiconductor types, they can constitute a transmission gate switch with complementary characteristics. In this case, for example, the first scan signal SCAN1 provided to the first transistor 110 and the second scan signal SCAN2 provided to the second transistor 120 can be inversely related signals. This ensures that one of the first transistor 110 and the second transistor 120 is always on at any given time, allowing the data signal DATA to be transmitted to the storage capacitor CST without voltage loss, thereby improving the reliability and stability of the pixel circuit.

[0072] Figure 3It shows the corresponding Figure 2 This is a schematic diagram of the layout on the substrate of the display device 100. (See attached diagram.) Figure 3 As shown in the embodiments of this disclosure, the direction along the first electrode 111 to the second electrode 112 of the first transistor 110 is referred to as the first direction D1, the direction along the first electrode 121 to the second electrode 122 of the second transistor 120 is referred to as the second direction D2, the direction along the first electrode 131 to the second electrode 132 of the third transistor 130 is referred to as the third direction D3, and the direction along the first electrode 141 to the second electrode 142 of the driving transistor 140 is referred to as the fourth direction D4.

[0073] For example, at least one of the first direction D1 and the second direction D2 intersects with the fourth direction D4. For example, in the case where the pixel circuit includes a third transistor 130, at least one of the first direction D1, the second direction D2, and the third direction D3 intersects with the fourth direction D4. For example, the fourth direction D4 is... Figure 3 The horizontal direction from left to right in the middle.

[0074] In the pixel circuit, since the size of the driving transistor 140 is generally larger than that of other switching transistors (e.g., the first transistor 110, the second transistor 120, and the third transistor 130), when arranging the position of the transistor, the driving transistor 140 can be arranged along the fourth direction D4, while at least one of the first direction D1, the second direction D2, and the third direction D3 intersects with the fourth direction D4. This makes the layout of the four transistors more compact, thereby reducing the layout area occupied by the display device 100, and making it easier for the display device 100 to achieve a high PPI.

[0075] In some embodiments of this disclosure, the first direction D1 and the second direction D2 can both intersect the fourth direction D4; or, for example, the first direction D1, the second direction D2, and the third direction D3 can all intersect the fourth direction D4. For example, as... Figure 3 As shown, the fourth direction D4 is the lateral direction, while the first direction D1, the second direction D2, and the third direction D3 are all lateral directions. Figure 3 The longitudinal direction that is perpendicular to the horizontal direction.

[0076] For example, in some embodiments of this disclosure, the first direction D1 and the second direction D2 are both perpendicular to the fourth direction D4; or, for example, the first direction D1, the second direction D2, and the third direction D3 are all perpendicular to the fourth direction D4. When multiple pixel units in the display area of ​​a display device are arranged in a multi-row, multi-column manner, this approach makes the layout of the display device 100 more compact, thereby further reducing the layout area occupied by the display device 100, and thus making it easier for the display device 100 to achieve a high PPI.

[0077] For example, such as Figure 3 As shown, the first transistor 110 includes a first active region 114 extending along a first direction D1. The first active region 114 includes a first electrode 111 of the first transistor 110, a second electrode 112 of the first transistor 110, and a channel region formed between the first electrode 111 and the second electrode 112 of the first transistor 110.

[0078] The second transistor 120 includes a second active region 124 extending along the second direction D2. The second active region 124 includes a first electrode 121 of the second transistor 120, a second electrode 122 of the second transistor 120, and a channel region formed between the first electrode 121 and the second electrode 122 of the second transistor 120.

[0079] The third transistor 130 includes a third active region 134 extending along the third direction D3. The third active region 134 includes a first electrode 131 of the third transistor 130, a second electrode 132 of the third transistor 130, and a channel region formed between the first electrode 131 and the second electrode 132 of the third transistor 130.

[0080] The driving transistor 140 includes a fourth active region 144 extending along a fourth direction D4. The fourth active region 144 includes a first electrode 141 of the fourth transistor 140, a second electrode 142 of the fourth transistor 140, and a channel region formed between the first electrode 141 and the second electrode 142 of the fourth transistor 140.

[0081] For example, the substrate in the display device 100 provided in the embodiments of this disclosure is a silicon-based substrate. The first active region 114, the second active region 124, the third active region 134 and the fourth active region 144 are all doped regions in the silicon-based substrate. These doped regions are obtained, for example, by ion implantation or ion diffusion. For amorphous silicon, P-type doping can be achieved by doping boron (B), and N-type doping can be achieved by doping phosphorus (P) or arsenic (As). The embodiments of this disclosure do not limit this.

[0082] For example, in some embodiments of this disclosure, the doping types of the first active region 114 and the second active region 124 are opposite. For example, the first active region 114 is doped with P-type, and the second active region 124 is doped with N-type.

[0083] like Figure 3 As shown, the two ends of the first active region 114 and the two ends of the second active region 124 are aligned with each other in the fourth direction D4, and for example, the two ends of the first active region 114 and the second active region 124 are arranged adjacent to each other. This arrangement simplifies the layout design of the display device 100.

[0084] The line connecting one edge of the first active region 114 along the first direction D1 and one edge of the second active region 124 along the second direction D2 is parallel to the fourth direction D4; the line connecting the other edge of the first active region 114 along the first direction D1 and the other edge of the second active region 124 along the second direction D2 is parallel to the fourth direction D4. This approach simplifies the layout design of the display device 100.

[0085] Compared to silicon-based analog CMOS circuits used for non-display applications, the drive current for the light-emitting element LE in the display device 100 provided in the embodiments of this disclosure is one to two orders of magnitude smaller. The current characteristics of the drive transistor 140 in saturation state are as follows:

[0086]

[0087] Among them, I D The drive current provided for driving transistor 140, W / L is the width-to-length ratio of driving transistor 140, K is a constant value, and V GS4 To drive the voltage difference between the gate and source of transistor 140, V th The threshold voltage for driving transistor 140.

[0088] As can be seen from the formula above, in order to achieve a lower driving current, the L value of the driving transistor 140 must be increased during the size design, which is not conducive to reducing the layout area of ​​the display device 100 that uses the driving transistor 140.

[0089] The pixel circuit 100 provided in some embodiments of this disclosure can improve or avoid the above-mentioned problems by adjusting the relative relationship between the doping concentrations of the first active region 114, the second active region 124, the third active region 134 and the fourth active region 144.

[0090] For example, the doping concentration of the fourth active region 144 is less than the doping concentration of the third active region 134. For example, the doping concentration of the third active region 134 is approximately 10. 17 cm -3The doping concentration of the fourth active region 144 is approximately 10. 13 cm -3 The doping concentration of the fourth active region 144 is four orders of magnitude smaller than that of the third active region 134. By reducing the doping concentration of the fourth active region 144, embodiments of this disclosure, without changing the size of the driving transistor 140 (e.g., the width-to-length ratio W / L remains constant), can enable the driving transistor 140 to output a smaller driving current, resulting in a smoother change in the output driving current. This allows for better uniformity of grayscale values ​​when the pixel circuit using this driving transistor 140 drives the light-emitting element LE (e.g., OLED) to emit light.

[0091] For example, in some embodiments of the display device 100 provided in this disclosure, the doping concentration of at least one of the first active region 114 and the second active region 124 is greater than the doping concentration of the third active region 134.

[0092] For example, the doping concentrations of the first active region 114 and the second active region 124 are both greater than the doping concentration of the third active region. For example, the doping concentrations of the first active region 114 and the second active region 124 are approximately 10. 20 cm -3 In this case, the doping concentration of the first active region 114 and the second active region 124 is three orders of magnitude greater than the doping concentration of the third active region 134.

[0093] like Figure 2 As shown, the first transistor 110 and the second transistor 120 are used as switching transistors in the pixel circuit, so they need to have good switching characteristics. When the doping concentration of the first active region 114 and / or the second active region 124 is large, a larger driving current can be obtained and the driving current changes more rapidly, thereby giving the first transistor 110 and / or the second transistor 120 better switching characteristics.

[0094] For example, in embodiments of this disclosure, the first transistor 110 is a first semiconductor type MOS transistor, and the second transistor, the third transistor, and the driving transistor are all second semiconductor type MOS transistors, with the first semiconductor type and the second semiconductor type being opposite. For example, the first semiconductor type is P-type, and the second semiconductor type is N-type; embodiments of this disclosure include, but are not limited to, these.

[0095] like Figure 3 As shown, some embodiments of the present disclosure provide a display device 100 that further includes a first scan signal line SL1 for transmitting a first scan signal SCAN1 and a second scan signal line SL2 for transmitting a second scan signal SCAN2, wherein the first scan signal line SL1 and the second scan signal line SL2 are arranged in parallel.

[0096] For example, the first scan signal line SL1 is connected to the control electrode 113 of the first transistor 110 to provide the first scan signal SCAN1, and the second scan signal line SL2 is connected to the control electrode 123 of the second transistor 120 to provide the second scan signal SCAN2.

[0097] For example, the extension directions of both the first scan signal line SL1 and the second scan signal line SL2 are parallel to the fourth direction D4. The orthographic projection of the first scan signal line SL1 onto the substrate is parallel to the orthographic projection of the second scan signal line SL2 onto the substrate, for example, both are parallel to the fourth direction D4.

[0098] For example, the area where the pixel circuit is projected onto the substrate is the pixel region, and the first scan signal line SL1 and the second scan signal line SL2 are located side by side on one side of the pixel region.

[0099] like Figure 3 As shown, some embodiments of the display device 100 provided in this disclosure further include a data line DL for transmitting a data signal DATA, wherein the orthographic projection of the second scan signal line SL2 onto the substrate at least partially overlaps with the orthographic projection of the data line DL onto the substrate. For example, the second scan signal line SL2 and the data line DL overlap in a direction perpendicular to the substrate. For example, as... Figure 3 As shown, it can be used to... Figure 3 If the plane in question is considered the plane of the substrate, then it is perpendicular to the substrate, which is also perpendicular to... Figure 3 The plane in which it is located. By making the second scan signal line SL2 overlap with the data line DT in a direction perpendicular to the substrate, the data line DL can be made to not occupy additional layout area, thereby further reducing the layout area occupied by the display device 100 and making it more conducive to achieving high PPI.

[0100] like Figure 3 As shown, some embodiments of the present disclosure provide a display device 100 that further includes a first power supply voltage line VL1 for transmitting a first power supply voltage ELVDD and a light emission control line EL for transmitting a light emission control signal EN.

[0101] For example, the extension directions of the first power supply voltage line VL1 and the light emission control line EL are parallel to the fourth direction D4, and the first scan signal line SL1, the second scan signal line SL2, the first power supply voltage line VL1 and the light emission control line EL are arranged sequentially along the direction perpendicular to the fourth direction D4 in the orthogonal projection of the substrate.

[0102] It should be noted that in some embodiments of the display device 100 provided in this disclosure, such as Figure 3As shown, the orthographic projection of the first power supply voltage line VL1 onto the substrate is positioned between the orthographic projection of the second scan signal line SL2 onto the substrate and the orthographic projection of the light emission control line EL onto the substrate. Since the first power supply voltage ELVDD transmitted by the first power supply voltage line VL1 is a DC signal, and the second scan signal SCAN2 transmitted by the second scan signal line SL2 and the light emission control signal EN transmitted by the light emission control line EL are both transition signals, the above arrangement can effectively shield the mutual interference between the second scan signal SCAN2 and the light emission control signal EN.

[0103] like Figure 3 As shown, some embodiments of the present disclosure provide a display device 100 that further includes a second power supply voltage line VL2 for transmitting a second power supply voltage VDD. The third terminal of the first transistor 110 is electrically connected to the second power supply voltage line VL2 to receive the second power supply voltage VDD. For example, in embodiments of the present disclosure, the second power supply voltage VDD is a high-level voltage, such as 5V.

[0104] For example, the first transistor 110 is a P-type MOS transistor, and its channel region is P-type doped. Figure 2 As shown, the third terminal opposite to the control electrode (gate) 113 of the first transistor 110 receives the second power supply voltage VDD. For example, the second transistor 120, the third transistor 130, and the driving transistor 140 are all N-type MOS transistors with N-type doped channel regions, and the third terminals of the second transistor 120, the third transistor 130, and the driving transistor 140 are all configured to be grounded (GND).

[0105] For example, the orthographic projection of the second power supply voltage line VL2 onto the substrate is located between the orthographic projection of the first power supply voltage line VL1 onto the substrate and the orthographic projection of the light emission control line EL onto the substrate, and part of the extension direction of the second power supply voltage line VL2 is parallel to the fourth direction D4.

[0106] like Figure 3 As shown, the second power supply voltage line VL2 has a bend when extending along the fourth direction D4; additionally, the light-emitting control line EL also has a bend when extending along the fourth direction D4, and the bend directions of the second power supply voltage line VL2 and the light-emitting control line EL are different. This routing method, for example, can provide layout space for the first adapter electrode AE1 described below.

[0107] For example, such as Figure 3As shown, the first transistor 110 and the second transistor 120 are both disposed between the second scan signal line SL2 and the light emission control line EL. The first transistor 110 intersects with the first power supply voltage line VL1 and the second power supply voltage line VL2, and the second transistor 120 intersects with the first power supply voltage line VL1 and the second power supply voltage line VL2.

[0108] For example, the orthographic projection of the first active region 114 of the first transistor 110 onto the substrate and the orthographic projection of the second active region 124 of the second transistor 120 onto the substrate are both located between the orthographic projection of the second scan signal line SL2 onto the substrate and the orthographic projection of the light emission control line EL onto the substrate.

[0109] The orthographic projection of the first active region 114 of the first transistor 110 on the substrate intersects with the orthographic projection of the first power supply voltage line VL1 on the substrate, and the orthographic projection of the first active region 114 of the first transistor 110 on the substrate intersects with the orthographic projection of the second power supply voltage line VL2 on the substrate.

[0110] The orthographic projection of the second active region 124 of the second transistor 120 onto the substrate intersects with the orthographic projection of the first power supply voltage line VL1 onto the substrate, and the orthographic projection of the second active region 124 of the second transistor 120 onto the substrate intersects with the orthographic projection of the second power supply voltage line VL2 onto the substrate.

[0111] like Figure 3 As shown, some embodiments of the present disclosure provide a display device 100 that further includes a first transfer electrode AE1 disposed on a first side of the light emission control line EL, and a second transfer electrode AE2 extending from the first side of the light emission control line EL to a second side of the light emission control line EL.

[0112] For example, the orthographic projection of the second transition electrode AE2 onto the substrate intersects with the orthographic projection of the light-emitting control line EL onto the substrate. The two ends of the first transition electrode AE1 are electrically connected to the first electrode 111 of the first transistor 110 and the first electrode 121 of the second transistor 120, respectively. The first transition electrode AE1 and the second transition electrode AE2 are electrically connected, and the second transition electrode AE2 is electrically connected to the control electrode 143 of the driving transistor 140.

[0113] For example, the extension direction of the second transfer electrode AE2 is perpendicular to the extension direction of the first transfer electrode AE1, and is also perpendicular to the fourth direction D4.

[0114] Since the second transition electrode AE2 is connected to the storage capacitor CST, the voltage level on the second transition electrode AE2 may fluctuate significantly during pixel circuit operation. This fluctuation may cause crosstalk to the first power supply voltage line VL1, generating noise. In the display device 100 provided in the embodiments of this disclosure, the first power supply voltage line VL1 and the second transition electrode AE2 are separated by the second power supply voltage line VL2, thereby reducing the crosstalk caused by the voltage level fluctuation on the second transition electrode AE2 to the first power supply voltage line VL1 and isolating noise.

[0115] In addition, some embodiments of the present disclosure provide a display device 100 that extends the first active region 114 of the first transistor 110 and the second active region 124 of the second transistor 120 to provide a wiring channel for the second power supply voltage line VL2.

[0116] For example, the layout size of the pixel circuit (rectangular shape) provided in the embodiments of this disclosure is approximately 4.5um × 2.9um.

[0117] Figures 4A-4E They are shown respectively Figure 3 The plan view of the layer layout of the display device 100 shown.

[0118] Figure 4A The diagram shows a first active region 114 of a first transistor 110, a second active region 124 of a second transistor 120, a third active region 134 of a third transistor 130, and a fourth active region 144 of a driving transistor 140, which can... Figure 4A The layer shown is called the Active Display (AA) layer.

[0119] Figure 4B The control electrode 113 of the first transistor 110, the control electrode 123 of the second transistor 120, the control electrode 133 of the third transistor 130, and the control electrode 143 of the drive transistor 140 are shown. The layer shown in 4B can be referred to as the first conductive layer, which will be further described below. For example, the material of the first conductive layer can be polycrystalline silicon.

[0120] Figure 4C The diagram shows the first power supply voltage line VL1, the second power supply voltage line VL2, the light control line EL, the data line DL, the ground line GND, and the first adapter electrode AE1. It can be used to... Figure 4C The layer shown is called the first metal layer (metal1).

[0121] Figure 4D The diagram shows the second transfer electrode AE2, the electrode connecting the first scan signal line SL1 to the first transistor 110, and the electrode connecting the second scan signal line SL2 to the second transistor 120. It can be used to... Figure 4DThe layer shown is called the second metal layer (metal2).

[0122] Figure 4E The first scan signal line SL1 and the second scan signal line SL2 are shown, which can... Figure 4E The layer shown is called the third metal layer (metal3).

[0123] It should be noted that, in the embodiments of this disclosure, for the sake of clarity, Figure 3 The storage capacitor CST is not shown in the diagram. Below, we will refer to... Figures 5-7E right Figure 2 The storage capacitor CST shown in the figure will be further described.

[0124] like Figure 5 As shown, Figure 5 The area 800 shown is the area where the storage capacitor CST is set. It should be noted that, for clarity, Figure 5 The table does not show the corresponding markers for all structures; the omitted parts can be found in the reference table. Figure 3 The corresponding marker in.

[0125] Figure 6 This is a layout diagram of the storage capacitor CST. Figures 7A-7D For the corresponding Figure 6 Floor plans showing the layout of each level. Figure 7E This is a schematic diagram of a cross-section of the storage capacitor CST.

[0126] Figure 6 The diagram shows a four-layer structure: a third metal layer (metal3), a fourth metal layer (metal4), an auxiliary metal layer (metal4'), and a fifth metal layer (metal5). It also shows a first via (V1) and a second via (V2), which will be described in detail below with reference to the cross-sectional diagram. Further details will not be provided here.

[0127] For example, Figure 7A A third metal layer, metal3, is shown, for example, this third metal layer and Figure 4E The layers shown are the same layer. For example... Figure 7A As shown, the third metal layer metal3 comprises two parts: an electrode 811 that serves as the first terminal of the first capacitor C1 and an electrode 812 that serves as the second terminal of the first capacitor C1. For example, electrode 811 is configured to receive a third power supply voltage AVSS; electrode 812 is electrically connected to electrode 840 in the fifth metal layer metal5 through a second via V2, thereby achieving electrical connection with the control terminal 143 of the driving transistor 140.

[0128] Electrode 811 includes multiple strip electrodes, and electrode 812 includes multiple strip electrodes. The multiple strip electrodes of electrode 811 and electrode 812 are arranged alternately, and electrodes 811 and 812, as well as the intervals between them, form a first capacitor C1. For example, the first capacitor C1 is part of a storage capacitor CST. For example, the first capacitor C1 and the second capacitor C2 (described below) are connected in parallel to form the storage capacitor CST.

[0129] For example, Figure 7B An electrode 820 located in the fourth metal layer metal4 is shown. For example, electrode 820 is a planar electrode that acts as the first electrode of the second capacitor C2.

[0130] For example, Figure 7C An electrode 830 located in the auxiliary metal layer metal4' is shown. For example, electrode 830 is a planar electrode that acts as the second electrode of the second capacitor C2.

[0131] For example, Figure 7D The electrode 840 located in the fifth metal layer metal5 is shown, as well as the first via V1 and the second via V2.

[0132] Figure 7E A cross-sectional schematic diagram of a portion of the aforementioned storage capacitor CST structure is shown, as follows: Figure 7E As shown, electrode 840 located in the fifth metal layer (metal5) is electrically connected to electrode 830 located in the auxiliary metal layer (metal4') through a first via V1; additionally, electrode 840 located in the fifth metal layer (metal5) is electrically connected to electrode 812 located in the third metal layer (metal3) through a second via V2. It should be noted that the second via V2 penetrates the fourth metal layer (metal4). Figure 7E Not shown in the image.

[0133] like Figure 7E As shown, the electrode 820 located in the fourth metal layer metal4 and the electrode 830 located in the auxiliary metal layer metal4', and the space between them form the second capacitor C2; for example, the first capacitor C1 mentioned above and the second capacitor C2 are connected in parallel to form the storage capacitor CST.

[0134] In embodiments of this disclosure, such as Figure 7E As shown, an auxiliary metal layer metal4' is provided between the fourth metal layer metal4 and the fifth metal layer metal5, so that the spacing between the fourth metal layer metal4 and the auxiliary metal layer metal4' is, for example, about 1 / 10 of the spacing between the fourth metal layer metal4 and the fifth metal layer metal5, thereby effectively increasing the capacitance value per unit area of ​​the second capacitor C2.

[0135] like Figure 2 and Figure 3 As shown, embodiments of this disclosure also provide a display device 100, including a substrate and at least one pixel circuit formed on the substrate. The pixel circuit includes a driving transistor 140, a first transistor 110, a second transistor 120, and a third crystal 130.

[0136] The driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and is configured to control the driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving the light-emitting element LE to emit light, based on the voltage of the control electrode 143 of the driving transistor 140.

[0137] The first transistor 110 is connected to the control terminal 143 of the driving transistor 140 and is configured to write the data signal DATA to the control terminal 143 of the driving transistor 140 in response to the first scan signal SCAN1. The second transistor 120 is connected to the control terminal 143 of the driving transistor 140 and is configured to write the data signal DATA to the control terminal 143 of the driving transistor 140 in response to the second scan signal SCAN2. The third transistor 130 is connected to the first terminal 141 of the driving transistor 140 and is configured to apply the first power supply voltage ELVDD to the first terminal 141 of the driving transistor 140 in response to the light emission control signal EN.

[0138] The display device 100 further includes a first scan signal line SL1 for transmitting a first scan signal SCAN1 and a second scan signal line SL2 for transmitting a second scan signal SCAN2, a first power supply voltage line VL1 for transmitting a first power supply voltage ELVDD and a light emission control line EL for transmitting a light emission control signal EN; the first scan signal line SL1, the second scan signal line SL2, the first power supply voltage line VL1 and the light emission control line EL are arranged sequentially along the direction perpendicular to the fourth direction D4 when projected onto the substrate.

[0139] For example, the direction along the first electrode 111 to the second electrode 112 of the first transistor 110 is the first direction D1; the direction along the first electrode 121 to the second electrode 122 of the second transistor 120 is the second direction D2; the direction along the first electrode 131 to the second electrode 132 of the third transistor 130 is the third direction D3; and the direction along the first electrode 141 to the second electrode 142 of the driving transistor 140 is the fourth direction D4. The first direction D1, the second direction D2, and the third direction D3 all intersect with the fourth direction D4. For example, the first direction D1, the second direction D2, and the third direction D3 are all perpendicular to the fourth direction D4.

[0140] At least one embodiment of this disclosure also provides a method for fabricating a display device 100, the method comprising: forming pixel circuits on a substrate.

[0141] The pixel circuit includes a driving transistor 140, a first transistor 110, and a second transistor 120.

[0142] The driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and is configured to control the driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving the light-emitting element LE to emit light, based on the voltage of the control electrode 143 of the driving transistor 140.

[0143] The first transistor 110 is connected to the control terminal 143 of the driving transistor 140 and is configured to write the data signal DATA to the control terminal 143 of the driving transistor 140 in response to the first scan signal SCAN1. The second transistor 120 is connected to the control terminal 143 of the driving transistor 140 and is configured to write the data signal DATA to the control terminal 143 of the driving transistor 140 in response to the second scan signal SCAN2.

[0144] The direction along the first electrode 111 to the second electrode 112 of the first transistor 110 is the first direction D1, the direction along the first electrode 121 to the second electrode 122 of the second transistor 120 is the second direction D2, and the direction along the first electrode 141 to the second electrode 142 of the driving transistor 140 is the fourth direction D4. At least one of the first direction D1 and the second direction D2 intersects the fourth direction D4; for example, both the first direction D1 and the second direction D2 are perpendicular to the fourth direction D4.

[0145] Currently, as users' demand for high-brightness displays in silicon-based OLED devices continues to increase, the pixel circuits in these devices need to output higher drive currents to the OLED's anode. For example, Figure 2 As shown, when an OLED needs to output higher brightness, the OLED anode voltage needs to be higher, V. anode At this time, a high voltage V will appear at the first terminal 111 (e.g., drain) of the first transistor 110 and the first terminal 121 (e.g., drain) of the second transistor 120. anode +V GS4 (V GS4 To drive the voltage difference between the gate and the first electrode of transistor 140, a high voltage will appear between the gate and the first electrode of both transistors 110 and 120. In this case, transistors 110 and 120 in the pixel circuit will be subjected to high voltage, which may lead to breakdown and potentially affect the reliability and stability of the pixel circuit.

[0146] At least one embodiment of this disclosure also provides a transistor structural design that can reduce or avoid the risk of high voltage breakdown, thereby making the pixel circuit using the transistor less susceptible to high voltage breakdown and enabling high-brightness display driving of the pixel circuit.

[0147] At least one embodiment of this disclosure provides a display device 100, including a substrate and a pixel circuit formed on the substrate. The pixel circuit includes a driving transistor 140, a first transistor 110, and a second transistor 120. The driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and is configured to control a driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving a light-emitting element LE to emit light, based on the voltage of the control electrode 143 of the driving transistor 140. The first electrode 111 of the first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write a data signal DATA to the control electrode 143 of the driving transistor 140 in response to a first scan signal SCAN1. The second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write a data signal DATA to the control electrode 143 of the driving transistor 140 in response to a second scan signal SCAN2.

[0148] For example, such as Figure 8 As shown, the substrate includes a doped semiconductor body 330 and a first conductive layer 310 and a second conductive layer 320 located on the semiconductor body 330.

[0149] The first transistor 110 includes a gate GE1 located in the first conductive layer 310, a second electrode SE1 and a first electrode DE1 located in the second conductive layer 320, a first doped region DR1 contacting the first electrode DE1 of the first transistor 110, and a second doped region SR1 contacting the second electrode SE1 of the first transistor 110. The first doped region DR1 and the second doped region SR1 of the first transistor 110 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330. The channel region of the first transistor 110 is between the first doped region DR1 and the second doped region SR1. When the first transistor 110 is turned on due to the control voltage applied to the gate GE1, the first doped region DR1 and the second doped region SR1 are turned on through the channel region. It should be noted that the gate GE1 of the first transistor 110 here is the control electrode 113 of the first transistor 110 described above. The following embodiments are the same and will not be described again.

[0150] like Figure 8 As shown, the first transistor 110 also includes a drift doped region DF1 in contact with the first doped region DR1. The drift doped region DF1 and the second doped region SR1 of the first transistor 110 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330. For example, the first transistor 110 is a P-type MOS transistor, and the first doped region DR1, the second doped region SR1, and the drift doped region DF1 of the first transistor 110 are all P-type doped, and the semiconductor body 330 is bulk silicon or silicon-on-insulator with P-type doping.

[0151] For example, the orthographic projection of the gate GE1 of the first transistor 110 onto the substrate partially overlaps with the orthographic projection of the drift doped region DF1 of the first transistor 110 onto the substrate, and the orthographic projection of the first doped region DR1 of the first transistor 110 onto the substrate lies within the orthographic projection of the drift doped region DF1 of the first transistor 110 onto the substrate; the doping concentration of the drift doped region DF1 of the first transistor 110 is lower than the doping concentration of the first doped region DR1 of the first transistor 110. When the first transistor 110 is turned on due to the control voltage applied to the gate GE1, the first doped region DR1 and the second doped region SR1 are turned on through the channel region and the drift doped region DF1 of the first transistor 110.

[0152] The pixel circuit in the display device 100 provided in the embodiments of this disclosure increases the breakdown voltage between the first electrode DE1 and the second electrode SE1 of the first transistor 110 by providing a drift doped region DF1 in the first transistor 110 and making the doping concentration of the drift doped region DF1 of the first transistor 110 lower than the doping concentration of the first doped region DR1 of the first transistor 110. This reduces or avoids the risk of the first transistor 110 being broken down by high voltage. For example, the first transistor 110 is a P-type MOS transistor.

[0153] like Figure 8 As shown, in at least one embodiment, the drift doped region DF1 of the first transistor 110 includes a first portion DF11 and a second portion DF12. The orthogonal projection of the second portion DF12 onto the substrate overlaps with the orthogonal projection of the first doped region DR1 of the first transistor 110 onto the substrate. In this case, the second portion DF12 of the first doped region DF1 of the first transistor 110 can be considered to constitute a part of the channel region and is different from other parts of the channel region. For example, the first doped region DR1 of the first transistor 110 is located within the drift doped region DF1 of the first transistor 110. For example, the doping depth of the first doped region DR1 of the first transistor 110 in the semiconductor body 330 can be less than, equal to, or greater than the doping depth of the drift doped region DF1 of the first transistor 110.

[0154] like Figure 8 As shown, in some embodiments of the present disclosure, the first doped region DR1, the second doped region SR1 and the drift doped region DF1 of the first transistor 110 are located in the first well WL1 in the semiconductor body 330. For example, the doping type of the first well WL1 is N-type doping.

[0155] The orthogonal projection of the gate GE1 of the first transistor 110 onto the substrate lies within the orthogonal projection of the first well WL1 onto the substrate, and the portion of the first well WL1 located between the first doped region DR1 and the second doped region SR1 of the first transistor 110 constitutes the channel region of the first transistor 110. For example, Figure 3 The area where the first well WL1 is located is shown in the figure.

[0156] For example, such as Figure 8As shown, the first transistor 110 also includes an auxiliary doped region BR; for example, the auxiliary doped region BR of the first transistor 110 is N-type doped, the auxiliary doped region BR of the first transistor 110 is in contact with the second doped region SR1 of the first transistor 110, the auxiliary doped region BR of the first transistor 110 is electrically connected to the second electrode SE1 of the first transistor 110, and the orthogonal projection of the auxiliary doped region BR of the first transistor 110 on the substrate lies within the orthogonal projection of the first well WL1 on the substrate. This auxiliary doped region BR can serve as an isolation layer to prevent leakage.

[0157] like Figure 8 As shown, in some embodiments of this disclosure, the substrate of the display device 100 further includes a first insulating layer IS1 located between the semiconductor body 330 and the first conductive layer 310. The first insulating layer IS1 can insulate the gate GE1 of the first transistor 110 from the semiconductor body 330. For example, the first insulating layer IS1 can be a gate insulating layer, such as a silicon oxide layer, and can be formed by a vapor deposition process or obtained by directly oxidizing the silicon substrate by a thermal oxidation process.

[0158] The first insulating layer IS1 includes a first portion IS11 close to the first doped region DR1 of the first transistor 110 and a second portion IS12 away from the first doped region DR1 of the first transistor 110.

[0159] For example, in at least one embodiment, the thickness of the first portion IS11 of the first insulating layer IS1 is greater than the thickness of the second portion IS12 of the first insulating layer IS1, and the thickness is the thickness in a direction perpendicular to the substrate. For example, the thickness of the first portion IS11 of the first insulating layer IS1 is 7 to 8 nanometers, and the thickness of the second portion IS12 of the first insulating layer IS1 is 2 to 3 nanometers.

[0160] In embodiments of this disclosure, by increasing the thickness of the first portion IS11 of the first insulating layer IS1, for example, to more than twice the thickness of the second portion IS12, the risk of high-voltage breakdown between the gate GE1 of the first transistor 110 and the first electrode DE1 of the first transistor 110 can be reduced or avoided.

[0161] like Figure 8As shown, the substrate further includes a planarization insulating layer PL, which covers the gate GE1 of the first transistor 110, and the light-emitting element LE is located on the planarization insulating layer PL. The planarization insulating layer PL can cover the aforementioned pixel circuit, thereby making the surface of the planarization insulating layer PL relatively flat, which is more conducive to forming the light-emitting element LE on the planarization insulating layer PL. The planarization insulating layer PL can be silicon oxide, silicon oxynitride, silicon nitride, etc., and can be obtained using processes such as vapor deposition.

[0162] For example, in Figure 8 In the illustrated embodiment, the first transistor 110 employs a structural design that reduces or avoids the risk of breakdown by high voltage, while the second transistor 120 employs a conventional MOS transistor structural design. Figure 8 As shown, the second transistor 120 includes a gate GE2 located in the first conductive layer 310, a first electrode DE2 and a second electrode SE2 located in the second conductive layer 320, a first doped region DR2 contacting the first electrode DE2 of the second transistor 120, and a second doped region SR2 contacting the second electrode SE2 of the second transistor 120. The first doped region DR2 and the second doped region SR2 of the second transistor 120 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330. It should be noted that the gate GE2 of the second transistor 120 here is the control electrode 123 of the second transistor 120 described above. The following embodiments are the same and will not be repeated. For example, the second transistor 120 is an N-type MOS transistor, and the first doped region DR2 and the second doped region SR2 of the second transistor 120 are both N-type doped.

[0163] For example, such as Figure 8 As shown, the second transistor 120 also includes an auxiliary doped region BR2, which is in contact with the second doped region SR2 of the second transistor 120. The auxiliary doped region BR2 is electrically connected to the second electrode SE2 of the second transistor 120. The doping type of the auxiliary doped region BR2 is opposite to that of the second doped region SR2; for example, the auxiliary doped region BR2 is P-type doped. This auxiliary doped region BR2 serves as an isolation layer to prevent leakage.

[0164] It should be noted that the embodiments of this disclosure include, but are not limited to, the above-described situations. The first transistor 110 may also be an N-type MOS transistor. The first doping region DR1 in the first transistor 110 is N-type doped, and the semiconductor body 330 is bulk silicon or silicon-on-insulator with P-type doping.

[0165] For example, if the first transistor 110 is an N-type MOS transistor, the first transistor 110 may further include an auxiliary doped region. In this case, the doping type of the auxiliary doped region of the first transistor 110 is P-type. The auxiliary doped region of the first transistor 110 is in contact with the second doped region SR1 of the first transistor 110, and the auxiliary doped region is electrically connected to the second electrode SE1 of the first transistor 110.

[0166] like Figure 9 As shown, in some embodiments of the pixel unit provided in this disclosure, the second transistor 120 adopts a structural design that can reduce or avoid the risk of being broken down by high voltage, while the first transistor 110 adopts a conventional MOS transistor structural design.

[0167] like Figure 9 As shown, the second transistor 120 includes a gate GE2 located in the first conductive layer 310, a first electrode DE2 and a second electrode SE2 located in the second conductive layer 320, a first doped region DR2 in contact with the first electrode DE2 of the second transistor 120, and a second doped region SR2 in contact with the second electrode SE2 of the second transistor 120. The first doped region DR2 and the second doped region SR2 of the second transistor 120 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330.

[0168] For example, the second transistor 120 also includes a drift doped region DF2 in contact with the first doped region DR2. The drift doped region DF2 and the second doped region SR2 of the second transistor 120 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330. For example, the second transistor 120 is a P-type MOS transistor, and the first doped region DR2, the second doped region SR2, and the drift doped region DF2 of the second transistor 120 are all N-type doped, and the semiconductor body 330 is P-type bulk silicon or silicon-on-insulator.

[0169] For example, the orthogonal projection of the gate GE2 of the second transistor 120 on the substrate partially overlaps with the orthogonal projection of the drift doped region DF2 of the second transistor 120 on the substrate, and the orthogonal projection of the first doped region DR2 of the second transistor 120 on the substrate is located within the orthogonal projection of the drift doped region DF2 of the second transistor 120 on the substrate; the doping concentration of the drift doped region DF2 of the second transistor 120 is lower than the doping concentration of the first doped region DR2 of the second transistor 120.

[0170] The pixel circuit in the display device 100 provided in the embodiments of this disclosure increases the breakdown voltage between the first electrode DE2 and the second electrode SE2 of the second transistor 120 by providing a drift doped region DF2 in the second transistor 120 and making the doping concentration of the drift doped region DF2 of the second transistor 120 lower than the doping concentration of the first doped region DR2 of the second transistor 120, thereby reducing or avoiding the risk of high voltage breakdown of the second transistor 120. Figure 9 As shown, the drift doped region DF2 of the second transistor 120 includes a first portion DF21 and a second portion DF22; the orthographic projection of the second portion DF22 on the substrate overlaps with the orthographic projection of the first doped region DR2 of the second transistor 120 on the substrate. For example, the first doped region DR2 of the second transistor 120 is located within the drift doped region DF2 of the second transistor 120.

[0171] For example, such as Figure 9 As shown, the second transistor 120 also includes an auxiliary doped region BR2; for example, the auxiliary doped region BR2 of the second transistor 120 is P-type doped, the auxiliary doped region BR2 of the second transistor 120 is in contact with the second doped region SR2 of the second transistor 120, and the auxiliary doped region BR2 of the second transistor 120 is electrically connected to the second electrode SE2 of the second transistor 120. This auxiliary doped region BR2 can serve as an isolation layer to prevent leakage.

[0172] like Figure 9 As shown, in some embodiments of this disclosure, the substrate of the display device 100 further includes a second insulating layer IS2 located between the semiconductor body 330 and the first conductive layer 310. This second insulating layer IS2 can insulate the gate GE2 of the second transistor 120 from the semiconductor body 330. For example, the second insulating layer IS2 can be a gate insulating layer, such as a silicon oxide layer, and can be formed by a vapor deposition process or obtained by directly oxidizing the silicon substrate by a thermal oxidation process.

[0173] The second insulating layer IS2 includes a first portion IS21 close to the first doped region DR2 of the second transistor 120 and a second portion IS22 away from the first doped region DR2 of the second transistor 120.

[0174] For example, the thickness of the first portion IS21 of the second insulating layer IS2 is greater than the thickness of the second portion IS22 of the second insulating layer IS2, and the thickness is the thickness in the direction perpendicular to the substrate. For example, the thickness of the first portion IS21 of the second insulating layer IS2 is 7-8 nanometers, and the thickness of the second portion IS22 of the second insulating layer IS2 is 2-3 nanometers.

[0175] In embodiments of this disclosure, by increasing the thickness of the first portion IS21 of the second insulating layer IS2, for example, to more than twice the thickness of the second portion IS22, the risk of high-voltage breakdown between the gate GE2 of the second transistor 120 and the first electrode DE2 of the second transistor 120 can be reduced or avoided.

[0176] like Figure 9 As shown, the substrate further includes a planarization insulating layer PL, which covers the gate GE2 of the second transistor 120, and the light-emitting element LE is located on the planarization insulating layer PL. The planarization insulating layer PL can cover the aforementioned pixel circuit, thereby making the surface of the planarization insulating layer PL relatively flat, which is more conducive to forming the light-emitting element on the planarization insulating layer PL. The planarization insulating layer PL can be silicon oxide, silicon oxynitride, silicon nitride, etc., and can be obtained using processes such as vapor deposition.

[0177] For example, in Figure 9 In the illustrated embodiment, the second transistor 120 employs a structural design that reduces or avoids the risk of breakdown by high voltage, while the first transistor 110 employs a conventional MOS transistor structural design. Figure 9 As shown, the first transistor 110 includes a gate GE1 located in the first conductive layer 310, a first electrode DE1 and a second electrode SE1 located in the second conductive layer 320, a first doped region DR1 in contact with the first electrode DE1 of the first transistor 110, and a second doped region SR1 in contact with the second electrode SE1 of the first transistor 110. The first doped region DR1 and the second doped region SR1 of the first transistor 110 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330. For example, the first transistor 110 is a P-type MOS transistor, and the doping type of the first doped region DR1 and the second doped region SR1 of the first transistor 110 is P-type doped.

[0178] like Figure 9 As shown, in some embodiments of the present disclosure, the first doped region DR1 and the second doped region SR1 of the first transistor 110 are located in the second well WL2 in the semiconductor body 330. For example, the doping type of the second well WL2 is N-type doping.

[0179] The orthogonal projection of the gate GE1 of the first transistor 110 onto the substrate lies in the orthogonal projection of the second well WL2 onto the substrate, and the portion of the second well WL2 located between the first doped region DR1 and the second doped region SR1 of the first transistor 110 constitutes the channel region of the first transistor 110.

[0180] For example, such as Figure 9As shown, the first transistor 110 also includes an auxiliary doped region BR; for example, the auxiliary doped region BR of the first transistor 110 is N-type doped, the auxiliary doped region BR of the first transistor 110 is in contact with the second doped region SR1 of the first transistor 110, the auxiliary doped region BR of the first transistor 110 is electrically connected to the second electrode SE1 of the first transistor 110, and the orthogonal projection of the auxiliary doped region BR of the first transistor 110 on the substrate lies within the orthogonal projection of the second well WL2 on the substrate. This auxiliary doped region BR can serve as an isolation layer to prevent leakage.

[0181] like Figure 10 As shown, in some embodiments of the display device provided in this disclosure, both the first transistor 110 and the second transistor 120 employ a structural design that can reduce or avoid the risk of being broken down by high voltage. For details regarding the specific structure of the first transistor 110 and the second transistor 120, please refer to... Figure 5 and Figure 6 The corresponding descriptions in the illustrated embodiments will not be repeated here.

[0182] In the display device provided in the embodiments of this disclosure, by employing a structural design that reduces or avoids the risk of high voltage breakdown for both the first transistor 110 and the second transistor 120, the risk of high voltage breakdown can be improved or avoided, thereby enhancing the reliability and stability of the display device.

[0183] For example, in some embodiments of the present disclosure, the display device 100 is a P-type silicon substrate, the first transistor 110 is a P-type MOS transistor, and the second transistor 120, the third transistor 130 and the driving transistor 140 are all N-type MOS transistors.

[0184] At least one embodiment of this disclosure also provides a method for fabricating a display device 100, the method comprising: forming pixel circuits on a substrate.

[0185] The pixel circuit includes a driving transistor 140, a first transistor 110, and a second transistor 120.

[0186] The driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and is configured to control the driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving the light-emitting element LE to emit light, based on the voltage of the control electrode 143 of the driving transistor 140.

[0187] The first transistor 110 is connected to the control terminal 143 of the driving transistor 140 and is configured to write the data signal DATA to the control terminal 143 of the driving transistor 140 in response to the first scan signal SCAN1. The second transistor 120 is connected to the control terminal 143 of the driving transistor 140 and is configured to write the data signal DATA to the control terminal 143 of the driving transistor 140 in response to the second scan signal SCAN2.

[0188] The aforementioned substrate further includes a doped semiconductor body 330; the aforementioned preparation method further includes: forming a first conductive layer 310 and a second conductive layer 320 on the semiconductor body 330, wherein the first transistor 110 includes a gate GE1 located in the first conductive layer 310 and a first electrode DE1 and a second electrode SE1 located in the second conductive layer 320.

[0189] The above-mentioned preparation method further includes: forming a first doped region DR1 of the first transistor 110 in the semiconductor body 330, which is in contact with the first electrode DE1 of the first transistor 110 and a second doped region SR1 of the first transistor 110 in contact with the second electrode SE1 of the first transistor 110. The first doped region DR1 and the second doped region SR1 of the first transistor 110 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330.

[0190] The above-described preparation method further includes: forming a drift doped region DF1 of the first transistor 110 in the semiconductor body 330, which has the same doping type as the second doped region SR1 of the first transistor 110; the drift doped region DF1 of the first transistor 110 is located in the semiconductor body 330 and is spaced apart from the second doped region SR1 of the first transistor 110; the orthogonal projection of the gate GE1 of the first transistor 110 on the substrate partially overlaps with the orthogonal projection of the drift doped region DF1 of the first transistor 110 on the substrate; and the orthogonal projection of the first doped region DR1 of the first transistor 110 on the substrate is located within the orthogonal projection of the drift doped region DF1 of the first transistor 110 on the substrate; the doping concentration of the drift doped region DF1 of the first transistor 110 is lower than the doping concentration of the first doped region DR1 of the first transistor 110.

[0191] The above-described fabrication method further includes forming a first insulating layer IS1 between the semiconductor body 330 and the first conductive layer 310. The first insulating layer IS1 includes a first portion IS11 close to the first doped region DR1 of the first transistor 110 and a second portion IS12 away from the first doped region DR1 of the first transistor 110; the thickness of the first portion IS11 of the first insulating layer IS1 is greater than the thickness of the second portion IS12 of the first insulating layer IS1, and the thickness is the thickness in the direction perpendicular to the substrate.

[0192] At least one embodiment of this disclosure also provides a method for fabricating a display device 100, the method comprising: forming pixel circuits on a substrate.

[0193] The pixel circuit includes a driving transistor 140, a first transistor 110, and a second transistor 120.

[0194] The driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and is configured to control the driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving the light-emitting element LE to emit light, based on the voltage of the control electrode 143 of the driving transistor 140.

[0195] The first transistor 110 is connected to the control terminal 143 of the driving transistor 140 and is configured to write the data signal DATA to the control terminal 143 of the driving transistor 140 in response to the first scan signal SCAN1. The second transistor 120 is connected to the control terminal 143 of the driving transistor 140 and is configured to write the data signal DATA to the control terminal 143 of the driving transistor 140 in response to the second scan signal SCAN2.

[0196] The first transistor 110 includes a first active region 114, the second transistor 120 includes a second active region 124, and the driving transistor 140 includes a fourth active region 144. The above-described fabrication method further includes: doping the first active region 114, the second active region 124, and the fourth active region 144 such that the doping concentration of at least one of the first active region 114 and the second active region 124 is greater than the doping concentration of the fourth active region 144.

[0197] The pixel circuit described above also includes a third transistor 130, which is connected to the first terminal 141 of the driving transistor 140 and is configured to apply a first power supply voltage ELVDD to the first terminal 141 of the driving transistor 140 in response to the light emission control signal EN. The third transistor 130 includes a third active region 134. The fabrication method described above also includes doping the third active region 134 such that the doping concentration of the fourth active region 144 is less than the doping concentration of the third active region 134.

[0198] It should be noted that the technical effects of the manufacturing method of the display device 100 provided in the embodiments of this disclosure can be referred to the corresponding descriptions in the above embodiments of the display device 100, and will not be repeated here.

[0199] The following is based on Figure 8 The illustrated embodiment is used to describe the manufacturing method of the display device 100 provided in the present disclosure.

[0200] like Figure 8 As shown, a semiconductor body 330 is first provided. Then, N-type doping is performed on the semiconductor body 330 to form a first well WL1. Then, P-type doping is performed on the first well WL1 to form a drift doped region DF1 of the first transistor 110. Then, P-type doping is performed on the drift doped region DF1 of the first transistor 110 to form a first doped region DR1 of the first transistor 110, the doping concentration of the first doped region DR1 of the first transistor 110 being higher than the doping concentration of the drift doped region DF1 of the first transistor 110. At the same time, P-type doping is performed on the first well WL1 to form a second doped region SR1 of the first transistor 110, and N-type doping is performed to form an auxiliary doped region BR of the first transistor 110.

[0201] Then, a first insulating layer IS1 is formed on the semiconductor body 330, and the thickness of the first portion IS11 of the first insulating layer IS1 is greater than the thickness of the second portion IS12 of the first insulating layer IS1; then, a first conductive layer 310 is formed on the first insulating layer IS1, the first conductive layer 310 including the gate GE1 of the first transistor 110.

[0202] Then, a planarization insulating layer PL is formed to cover the gate GE1 of the first transistor 110; then, vias are formed in the planarization insulating layer PL to expose the first doped region DR1 of the first transistor, the second doped region SR1 of the first transistor 110, and the auxiliary doped region BR of the first transistor 110.

[0203] Finally, a second conductive layer 320 is formed. The second conductive layer 320 includes a first electrode DE1 of the first transistor 110 electrically connected to the first doped region DR1 of the first transistor 110 through a via in the planarized insulating layer PL, and a second electrode SE1 of the first transistor 110 electrically connected to the second doped region SR1 of the first transistor 110 through a via in the planarized insulating layer PL.

[0204] It should be noted that the fabrication method of the second transistor 120 is similar to that described above, and will not be repeated here.

[0205] At least one embodiment of this disclosure also provides a display device 100, such as Figure 11 As shown, for example, the display device 100 includes a display panel, which includes a plurality of pixel units PU arranged in an array in the display area 300. For example, at least one of the plurality of pixel units PU can be a pixel circuit in any of the display devices 100 provided in the embodiments of the present disclosure.

[0206] For example, such as Figure 11As shown, the display device 100 also includes a driving circuit 200 fabricated in a substrate. The driving circuit 200 is configured to provide a first scan signal SCAN1, a second scan signal SCAN2, and a light emission control signal EN to the pixel circuits in the plurality of pixel units PU in the display device 100. For example, the driving circuit 200 is disposed in the peripheral region 400 surrounding the display area 300.

[0207] For example, the display device 100 provided in the embodiments of this disclosure can be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0208] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A display device comprising: A display device including a substrate and at least one pixel circuit and a light emitting element formed over the substrate, The pixel circuit includes a drive transistor including a control electrode, a first electrode, and a second electrode, and configured to control a drive current for driving the light emitting element to emit light, flowing through the first electrode of the drive transistor and the second electrode of the drive transistor, in accordance with a voltage of the control electrode of the drive transistor; a direction from the first electrode of the drive transistor to the second electrode of the drive transistor is a first direction, and a direction perpendicular to the first direction is a second direction, the control electrode includes a first side edge and a second side edge opposite to each other in the second direction, and the pixel circuit further includes a first transistor whose control electrode is connected to a first scan line, and a first connection portion at which the drive transistor is connected to the first transistor and a second connection portion at which the drive transistor is connected to the light emitting element are closer to the first side edge than to the second side edge.

2. The display device according to claim 1, wherein the drive transistor further includes a first active region including a third side edge and a fourth side edge opposite to each other in the second direction, and the first connection portion and the second connection portion are closer to the third side edge than to the fourth side edge.

3. The display device according to claim 2, wherein the first side edge and the third side edge are on the same side in the second direction.

4. The display device according to claim 1, wherein the first scan line includes a first portion and a second portion extending in the first direction, a first distance from the first portion to the first connection portion, and a second distance from the second portion to the first connection portion are not equal to each other, and the first distance and the second distance are distances in the second direction.

5. The display device according to claim 4, wherein the first portion overlaps the control electrode of the first transistor in a direction perpendicular to a main surface of the substrate.

6. The display device according to claim 4, wherein the first distance is larger than the second distance.

7. The display device according to any one of claims 4 to 6, further comprising a first transfer electrode electrically connected to the control electrode of the drive transistor, and overlapping the second portion of the first scan line in a direction perpendicular to a main surface of the substrate.

8. The display device according to claim 7, wherein an extension direction of the first transfer electrode and an extension direction of the second portion of the first scan line are perpendicular to each other.

9. The display device according to claim 7, further comprising a second transfer electrode provided on a first side of the first scan line and electrically connected to the first transfer electrode; wherein the first transfer electrode extends from the first side of the first scan line to a second side of the first scan line; the pixel circuit further includes a second transistor and a third transistor, and both ends of the second transfer electrode are electrically connected to a first electrode of the second transistor and a first electrode of the third transistor, respectively.

10. The display device according to claim 9, wherein an extending direction of the first transfer electrode is perpendicular to an extending direction of the second transfer electrode.

11. The display device according to claim 1, further comprising a first power supply voltage line to which a first electrode of the first transistor is connected, and the first power supply voltage line includes a third portion and a fourth portion which extend in the first direction, a third distance of the third portion from the first connection portion and a fourth distance of the fourth portion from the first connection portion are not equal to each other, and the third distance and the fourth distance are distances in the second direction.

12. The display device according to claim 11, wherein the third distance is larger than the fourth distance.

13. The display device according to claim 11 or 12, wherein the third portion and the fourth portion are connected by a fifth portion, the pixel circuit further comprises a third transistor, and the fifth portion and a control electrode of the third transistor overlap in a direction perpendicular to a main surface of the substrate.

14. The display device according to claim 1, wherein the pixel circuit further comprises a second transistor and a third transistor, and the second transistor and the third transistor are each connected to the control electrode of the driver transistor; the first transistor includes a first active region, the second transistor includes a second active region, the third transistor includes a third active region, and the driver transistor includes a fourth active region; wherein at least one of the second active region and the third active region has a higher doping concentration than the fourth active region.

15. The display device according to claim 14, wherein the fourth active region has a lower doping concentration than the first active region.

16. The display device according to claim 14, wherein the second active region and the third active region each have a higher doping concentration than the first active region and the fourth active region.

17. The display device according to any one of claims 14 to 16, wherein the fourth active region has a doping concentration which is 4 orders of magnitude lower than the doping concentration of the first active region.

18. The display device according to any one of claims 14 to 16, wherein the second active region and the third active region each have a doping concentration which is 3 orders of magnitude higher than the doping concentration of the first active region.

19. The display device according to claim 14, further comprising a second scan signal line to which a control electrode of the second transistor is connected, the second active region and the third active region each have a projection onto the substrate which is between a projection onto the substrate of the second scan signal line and a projection onto the substrate of the first scan line.

20. The display device according to claim 14, further comprising a second power supply voltage line to which the third transistor is electrically connected, and the second active region and the third active region each have a projection onto the substrate which intersects a projection onto the substrate of the second power supply voltage line.

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