Semiconductor structure and method of forming the same
By adopting a horizontal word line structure in the DRAM architecture, the problem of excessive resistance in miniaturized memory was solved, the manufacturing process was simplified, electrical performance was improved, and costs were reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-21
- Publication Date
- 2026-07-03
AI Technical Summary
As the size of memory structures such as DRAM shrinks, the vertical word line structure leads to excessively high internal resistance of the memory, affecting its electrical performance.
The horizontal word line structure is adopted, which forms multiple word lines on the substrate that extend in a direction parallel to the top surface of the substrate. The edges of the word lines are flush with the edges of the channel area and are formed by a one-step deposition process, simplifying the manufacturing process.
It improves the electrical performance of the semiconductor structure, reduces manufacturing costs, and reduces capacitive coupling effects and resistance between adjacent word lines.
Smart Images
Figure CN116997176B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] As memory structures such as DRAM continue to shrink, significant challenges have arisen in the manufacturing process and yield of 3D memory. For example, with the miniaturization of memory structures like DRAM, the vertical word line structure leads to excessively high internal resistance, affecting the electrical performance of the memory.
[0004] Therefore, how to improve the structure of memory to adapt to the ever-shrinking size of memory is a technical problem that urgently needs to be solved. Summary of the Invention
[0005] This disclosure provides semiconductor structures and methods for forming the same in some embodiments to meet the need for continuous miniaturization of semiconductor structures, thereby simplifying the manufacturing process of semiconductor structures while improving their performance.
[0006] According to some embodiments, this disclosure provides a semiconductor structure, including:
[0007] Substrate;
[0008] A stacked structure is located on the substrate. The stacked structure includes a plurality of first semiconductor layers spaced apart along a direction perpendicular to the top surface of the substrate. Each first semiconductor layer includes a plurality of channel regions spaced apart along a first direction, and a first doped region and a second doped region distributed on opposite sides of each channel region along a second direction. Both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects the second direction.
[0009] The character line structure includes multiple character lines extending along the first direction, and along the second direction, the edges of the character lines are flush with the edges of the channel region.
[0010] In some embodiments, the spacing width between two adjacent channel regions along the first direction is smaller than the spacing width between two adjacent channel regions along a direction perpendicular to the top surface of the substrate.
[0011] In some embodiments, each of the word lines continuously covers a plurality of channel regions arranged along the first direction, and the channel regions and the word lines further include:
[0012] A dielectric layer covers the surface of the channel region, the word lines cover the surface of the dielectric layer, and the edges of the dielectric layer are flush with the edges of the word lines in a direction perpendicular to the top surface of the substrate.
[0013] In some embodiments, the stacked structure further includes a capacitor structure, the capacitor structure comprising: a first electrode layer, a dielectric layer, and a second electrode layer disposed sequentially around the surface of the first semiconductor layer; the capacitor structure is adjacent to and electrically connected to the first doped region, and the first semiconductor layer surrounded by the capacitor structure and the first semiconductor layer corresponding to the first doped region are doped with the same ions.
[0014] In some embodiments, the stacked structure further includes a bit line structure adjacent to the second doped region. The bit line structure includes at least one bit line extending in a direction perpendicular to the top surface of the substrate. In the direction perpendicular to the top surface of the substrate, one bit line is electrically connected to a plurality of second doped regions spaced apart in a direction perpendicular to the top surface of the substrate.
[0015] In some embodiments, the stacked structure further includes: a first fill layer and a second fill layer, wherein the first fill layer is located between adjacent word lines, and the second fill layer is located between adjacent first doped regions and adjacent second doped regions.
[0016] In some embodiments, the plurality of word lines are arranged at intervals along a direction perpendicular to the top surface of the substrate; the semiconductor structure further includes:
[0017] An air gap is located within the first filler layer and is located at least between two adjacent word lines in a direction perpendicular to the top surface of the substrate.
[0018] In some embodiments, it also includes:
[0019] At least one support pillar is located on the substrate and on the side of the capacitor structure opposite to the first doped region, and the support pillar is at least connected to the stacked structure.
[0020] In some embodiments, the first semiconductor layer in the stacked structure extends along the second direction into the interior of the support pillar.
[0021] In some embodiments, the support post extends in a direction perpendicular to the top surface of the substrate, and the top surface of the support post is flush with the top surface of the stacked structure.
[0022] According to other embodiments, this disclosure also provides a method for forming a semiconductor structure, comprising the following steps:
[0023] A substrate is formed, and a stacked layer is located on the substrate. The stacked layer includes a first semiconductor layer and a second semiconductor layer that are alternately stacked along a direction perpendicular to the top surface of the substrate. The first semiconductor layer includes a plurality of channel regions spaced apart along a first direction, and a first doped region and a second doped region distributed on opposite sides of each of the channel regions along a second direction. The first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects the second direction.
[0024] Forming multiple first openings that respectively expose multiple said trench regions;
[0025] A character line structure is directly formed in the first opening. The character line structure includes multiple character lines extending along the first direction, and the character lines continuously cover multiple channel regions arranged at intervals.
[0026] In some embodiments, the thickness of the second semiconductor layer is greater than the spacing width between two adjacent first openings spaced apart along the first direction.
[0027] In some embodiments, before forming the plurality of the first openings, the following steps are further included:
[0028] A first region and a second region located outside the first region are defined in the stacked layer;
[0029] Remove a portion of the stacked layers to form a support groove in the second region;
[0030] The support groove is filled to form a support pillar that is connected to the first semiconductor layer in the first region.
[0031] In some embodiments, the specific steps of forming the support groove in the second region include:
[0032] All of the second semiconductor layer and part of the first semiconductor layer in the second region are removed to form a support trench, with the remaining first semiconductor layer extending from the first region into the support trench.
[0033] In some embodiments, before forming the plurality of the first openings, the following steps are further included:
[0034] A transistor region is defined in the first region, and a capacitor region and a bit line region are distributed on opposite sides of the transistor region along the second direction. The channel region, the first doped region and the second doped region are all located in the transistor region, and the first doped region is adjacent to the capacitor region and the second doped region is adjacent to the bit line region.
[0035] A second opening is formed to expose the first doped region, and a third opening is formed to expose the second doped region;
[0036] A third filling layer is formed that fills the second opening and the third opening.
[0037] In some embodiments, before forming the plurality of the first openings, the following steps are further included:
[0038] Remove the second semiconductor layer in the capacitor region to expose the first semiconductor layer located in the capacitor region;
[0039] A first electrode layer covering the surface of the first semiconductor layer is formed in the capacitor region;
[0040] A dielectric layer is formed covering the surface of the first electrode layer;
[0041] A second electrode layer is formed covering the surface of the dielectric layer.
[0042] In some embodiments, the specific steps of forming a first electrode layer covering the surface of the first semiconductor layer in the capacitor region include:
[0043] A first electrode layer covering the surface of the first semiconductor layer is formed using a selective atomic layer deposition process.
[0044] In some embodiments, before forming a first electrode layer covering the surface of the exposed first semiconductor layer in the capacitor region, the following steps are further included:
[0045] The first doped ion is injected into the first semiconductor layer exposed in the capacitor region.
[0046] In some embodiments, before directly forming the word line structure in the first opening, the following steps are further included:
[0047] The surface of the channel region is oxidized using an in-situ oxidation process to form a dielectric layer on the surface of the channel region.
[0048] In some embodiments, the specific steps of directly forming the word line structure in the first opening include:
[0049] Conductive material is deposited in a plurality of the first openings using an atomic layer deposition process to directly form a plurality of word lines spaced apart along a direction perpendicular to the top surface of the substrate, each word line continuously covering a plurality of channel regions spaced apart along the first direction.
[0050] In some embodiments, along the second direction, the edge of the word line is flush with the edge of the channel region.
[0051] In some embodiments, after forming the word line structure, the following steps are further included:
[0052] A first fill layer is formed that fills the first opening and covers the surface of the letter line;
[0053] Remove the third filling layer to expose the first doped region and the second doped region;
[0054] Injecting second doped ions into the first doped region and the second doped region;
[0055] A second filling layer is formed that fills the second opening and the third opening and covers the first doped region and the second doped region.
[0056] In some embodiments, the specific steps for forming the first filling layer include:
[0057] An insulating material is deposited within a plurality of the first openings using an atomic layer deposition process to form a first filling layer covering the surface of the word lines and an air gap located within the first filling layer, wherein the air gap is located at least between two adjacent word lines in a direction perpendicular to the top surface of the substrate.
[0058] In some embodiments, the type of the first doped ion is the same as the type of the second doped ion.
[0059] In some embodiments, after forming the second filling layer, the following steps are further included:
[0060] Remove the stacked layer in the bit line region to form a bit line groove;
[0061] A bit line is formed in the bit line groove, and the bit line is electrically connected to the second doped region.
[0062] The semiconductor structure and its formation method provided in some embodiments of this disclosure, by forming a word line structure above a substrate, wherein the word line structure includes multiple word lines extending in a direction parallel to the top surface of the substrate, thereby forming a horizontal word line structure, can not only be applied to semiconductor structures with continuously shrinking dimensions, but also helps to improve the performance of semiconductor structures. Moreover, since the horizontal word lines in this disclosure are directly deposited in the first opening of the exposed channel region, the edges of the formed word lines are flush with the edges of the channel region, and no additional etching process is required after deposition, thereby simplifying the semiconductor structure formation process and reducing the manufacturing cost of semiconductor structures. Attached Figure Description
[0063] Appendix Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure in a specific embodiment of this disclosure;
[0064] Appendix Figure 2 It is attached Figure 1 A schematic diagram of the cross-section along position a-a';
[0065] Appendix Figure 3 It is attached Figure 1 A schematic diagram of the cross-section along position b-b';
[0066] Appendix Figure 4 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure;
[0067] Appendix Figure 5A-5U This is a schematic diagram of the main process cross-sections during the formation of the semiconductor structure according to a specific embodiment of this disclosure. Detailed Implementation
[0068] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0069] This specific embodiment provides a semiconductor structure, with appended... Figure 1 This is a cross-sectional schematic diagram of the semiconductor structure in a specific embodiment of this disclosure, with attached... Figure 2 It is attached Figure 1 A schematic diagram of the cross-section along position a-a' is attached. Figure 3 It is attached Figure 1 A schematic diagram of the cross-section along position b-b', with attached... Figure 1 It is attached Figure 2 and attached Figure 3 A schematic diagram of a cross-section along c-c'. The semiconductor structure in this specific embodiment can be, but is not limited to, DRAM. For example... Figures 1-3 As shown, the semiconductor structure provided in this specific embodiment includes:
[0070] Substrate 10;
[0071] A stacked structure is located on a substrate 10. The stacked structure includes a plurality of first semiconductor layers arranged at intervals along a direction perpendicular to the top surface of the substrate 10. The first semiconductor layers include a plurality of channel regions 11 arranged at intervals along a first direction D1, and a first doped region 17 and a second doped region 18 distributed on opposite sides of each channel region 11 along a second direction D2. The first direction D1 and the second direction D2 are both parallel to the top surface of the substrate 10, and the first direction D1 and the second direction D2 intersect.
[0072] The character line structure includes multiple character lines 13 extending along a first direction D1, and along a second direction D2, the edges of the character lines 13 are flush with the edges of the channel region 11.
[0073] Specifically, substrate 10 can be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other examples, substrate 10 can be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. Substrate 10 is used to support a stacked structure on its top surface. The plurality of first semiconductor layers in the stacked structure are arranged in a direction perpendicular to the top surface of the substrate (e.g., ...). Figure 1 The first semiconductor layer comprises a plurality of channel regions 11 spaced along a first direction D1, and a first doped region 17 and a second doped region 18 distributed on opposite sides of each channel region 11 along a second direction D2. A word line structure is located above the top surface of the substrate 10 and includes a word line 13 extending along the first direction D1. Each word line 13 continuously covers the plurality of channel regions 11 spaced along the first direction D1 in a first semiconductor layer. Along the second direction D2, the channel regions 11 are flush with the edges of the word lines 13 located on the surface of the channel regions 11.
[0074] This specific embodiment sets up horizontal word lines, i.e., multiple word lines 13 extending along the first direction D1, so that the multiple word lines 13 are at different horizontal heights. This eliminates the need for the word line structure to occupy the top surface of the substrate 10, adapting to the needs of increasingly miniaturized semiconductor structures. When forming the word line leads for the word lines 13, the word line leads can be placed at different horizontal heights, which helps reduce the capacitive coupling effect between adjacent word line leads and the internal resistance of the semiconductor structure, thereby improving the performance of the semiconductor structure. Furthermore, since the horizontal word lines in this specific embodiment are formed through a one-step deposition process, the edges of the formed word lines 13 are flush with the edges of the channel region 11. No additional etching process is required after the deposition process, thus simplifying the semiconductor structure formation process and reducing the manufacturing cost of the semiconductor structure.
[0075] In some embodiments, the spacing width between two adjacent channel regions 11 along the first direction D1 is smaller than the spacing width between two adjacent channel regions 11 along the direction perpendicular to the top surface of the substrate 10.
[0076] Specifically, the spacing between two adjacent channel regions 11 along the first direction D1 is smaller than the spacing between two adjacent channel regions 11 along the direction perpendicular to the top surface of the substrate 10. This allows the conductive material to be deposited to form word lines 13, so that the conductive material along the horizontal direction is first connected into a line along the first direction D1. By controlling the deposition parameters and other conditions, word lines 13 extending only along the first direction D1 can be directly formed, which helps to further simplify the word line 13 formation process.
[0077] In some embodiments, each word line 13 continuously covers a plurality of channel regions 11 arranged along the first direction D1, and the channel regions 11 and the word line 13 further include:
[0078] A dielectric layer 12 covers the surface of the channel region 11, and word lines 13 cover the surface of the dielectric layer 12. In a direction perpendicular to the top surface of the substrate 10, the edge of the dielectric layer 12 is flush with the edge of the word lines 13.
[0079] Specifically, the dielectric layer 12 is located between the channel region 11 and the word line 13. In one example, the material of the first semiconductor layer may be silicon, the material of the dielectric layer 12 may be silicon dioxide, and the dielectric layer 12 may be formed by in-situ oxidation of the surface of the first semiconductor layer, thereby further simplifying the manufacturing process of the semiconductor structure.
[0080] In some embodiments, the stacked structure further includes a capacitor structure, which includes a first electrode layer 19, a dielectric layer 20, and a second electrode layer 21 disposed sequentially around the surface of the first semiconductor layer; the capacitor structure is adjacent to and electrically connected to the first doped region 17, and the first semiconductor layer surrounded by the capacitor structure and the first semiconductor layer corresponding to the first doped region 17 are doped with the same ions.
[0081] Specifically, the top surface of the substrate 10 also includes a capacitor structure adjacent to the first doped region 17 along the second direction D2. The capacitor structure includes multiple capacitors spaced apart along a direction perpendicular to the top surface of the substrate 10. Each capacitor includes: a first electrode layer 19 sequentially disposed around the surface of the first semiconductor layer, a dielectric layer 20 covering the surface of the first electrode layer 19, and a second electrode layer 21 covering the surface of the dielectric layer 20. The first semiconductor layer is located between two adjacent capacitors, and the first semiconductor layer between adjacent capacitors has the same doped ions as the first doped region 17. This makes the first semiconductor layer surrounded by the capacitor structure conductive, and the contact resistance between the first semiconductor layer surrounded by the capacitor structure and the first doped region 17 is small, thereby further improving the electrical performance of the semiconductor structure. The first electrode layer 19 and the second electrode layer 21 can be made of the same material, for example, both being metals such as tungsten or both being TiN. The dielectric layer 20 can be made of a material with a high dielectric constant.
[0082] In some embodiments, the stacked structure further includes a bit line structure adjacent to the second doped region 18. The bit line structure includes at least one bit line 16, the bit line 16 extending in a direction perpendicular to the top surface of the substrate 10. In the direction perpendicular to the top surface of the substrate 10, one bit line 16 is electrically connected to a plurality of second doped regions 18 spaced apart in a direction perpendicular to the top surface of the substrate 10.
[0083] Specifically, the top surface of the substrate 10 also includes a bit line structure adjacent to the second doped region 18 along the second direction D2. The bit line structure includes at least one bit line 16 extending along a direction perpendicular to the top surface of the substrate 10. In the direction perpendicular to the top surface of the substrate 10, a bit line is in direct contact with and electrically connected to a plurality of second doped regions 18 spaced apart along the direction perpendicular to the top surface of the substrate 10.
[0084] In some embodiments, the stacked structure further includes a first filling layer 14 and a second filling layer 15, wherein the first filling layer 14 is located between adjacent word lines 13, and the second filling layer 15 is located between adjacent first doped regions 17 and adjacent second doped regions 18.
[0085] In some embodiments, the plurality of word lines 13 are arranged at intervals along a direction perpendicular to the top surface of the substrate 10; the semiconductor structure further includes:
[0086] An air gap 141 is located within the first filler layer 14 and is located at least between two adjacent word lines 13 in a direction perpendicular to the top surface of the substrate 10.
[0087] Specifically, the first filling layer 14 fills the spaces between adjacent word lines 13 and covers the top surface of the topmost word line 13 in the stacked structure. The second filling layer 15 fills the spaces between adjacent first doped regions 17 and adjacent second doped regions 18, and covers the top surfaces of the topmost first doped region 17 and the topmost second doped region 18 in the stacked structure. In one embodiment, the material of the first filling layer 14 is the same as that of the second filling layer 15 (e.g., both are silicon dioxide), and the top surface of the first filling layer 14 is flush with the top surface of the second filling layer 15 to further simplify the semiconductor structure manufacturing process. Furthermore, by providing an air gap 141 within the first filling layer 14, the electrical isolation effect between adjacent word lines 13 is further enhanced.
[0088] In some embodiments, the semiconductor structure further includes:
[0089] At least one support post 22 is located on the substrate 10 and on the side of the capacitor structure away from the first doped region 17. The support post 22 is connected to at least the stacked structure.
[0090] In some embodiments, the first semiconductor layer in the stacked structure extends along the second direction D2 into the interior of the support pillar 22.
[0091] In some embodiments, the support post 22 extends in a direction perpendicular to the top surface of the substrate 10, and the top surface of the support post 10 is flush with the top surface of the stacked structure.
[0092] Specifically, at least one support post 22 is located on the top surface of the substrate 10 and extends in a direction perpendicular to the top surface of the substrate 10. It connects to the side of the capacitor structure opposite to the first doped region 17, serving to support the stacked structure, improve its stability, and prevent collapse or toppling during the formation of the capacitor structure or other structures. The top surface of the support post 22 is flush with the top surface of the stacked structure, allowing it to support the entire stacked structure and further improving the stability of the top of the stacked structure. In another embodiment, the top surface of the support post 22 may also be located above the top surface of the stacked structure.
[0093] Each first semiconductor layer in this specific embodiment may further include a plurality of channel regions 11 spaced apart along the second direction D2, and a first doped region 17 and a second doped region 18 distributed along the second direction D2 on opposite sides of each channel region 11. A bit line 16 is located between adjacent second doped regions 18 along the second direction D2 and is electrically connected to adjacent second doped regions 18 along the second direction D2. The stacked structure contains multiple capacitor structures, each adjacent to and electrically connected to a plurality of first doped regions 17. The number of support pillars 22 may be multiple, each contacting and connecting to a plurality of capacitor structures. The multiple support pillars may be symmetrically distributed around the outer periphery of the stacked structure to further improve the stability of the stacked structure. In this specific embodiment, there may be two or more support pillars.
[0094] This specific embodiment also provides a method for forming a semiconductor structure, attached... Figure 4 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figure 5A-5U This is a schematic diagram of the main process cross-sections during the formation of the semiconductor structure according to a specific embodiment of this disclosure. A schematic diagram of the semiconductor structure formed according to this embodiment can be found in [reference needed]. Figures 1-3 , Figures 5A-5U The diagram shows cross-sectional views of the semiconductor structure during its formation process at four positions: c-c', a-a', b-b', and d-d', clearly illustrating the formation method. The semiconductor structure in this specific embodiment can be, but is not limited to, DRAM. For example... Figures 1-4 , Figures 5A-5U As shown, the method for forming a semiconductor structure includes the following steps:
[0095] Step S41: Form a substrate 10 and a stacked layer on the substrate 10. The stacked layer includes a first semiconductor layer 51 and a second semiconductor layer 52 that are alternately stacked along a direction perpendicular to the top surface of the substrate 10. The first semiconductor layer 51 includes a plurality of channel regions 11 arranged at intervals along a first direction D1, and a first doped region 17 and a second doped region 18 distributed on opposite sides of each channel region 11 along a second direction D2. The first direction D1 and the second direction D2 are both parallel to the top surface of the substrate 10, and the first direction D1 intersects the second direction D2.
[0096] Step S42, forming multiple first openings 60 that expose multiple channel regions 11 respectively, such as Figure 5M As shown.
[0097] Step S43: A character line structure is directly formed in the first opening 60. The character line structure includes multiple character lines 13 extending along the first direction D1. The character lines 13 continuously cover multiple channel regions 11 arranged at intervals, such as... Figure 5O As shown.
[0098] Specifically, chemical vapor deposition, physical vapor deposition, or atomic layer deposition can be used to alternately deposit the first semiconductor layer 51 and the second semiconductor layer 52 on the top surface of the substrate 10 along a direction perpendicular to the top surface of the substrate 10, such as... Figure 5A As shown, a stacked layer with a superlattice stack structure is formed to further improve the storage density of the semiconductor structure. The specific number of alternating layers of the first semiconductor layer 51 and the second semiconductor layer 52 in the stacked layer can be selected by those skilled in the art according to actual needs. The more alternating layers of the first semiconductor layer 51 and the second semiconductor layer 52, the greater the storage capacity of the semiconductor structure. A large etch selectivity ratio (e.g., greater than 3) should be maintained between the first semiconductor layer 51 and the second semiconductor layer 52 to facilitate subsequent selective etching to remove the second semiconductor layer 52. In one example, the material of the first semiconductor layer 51 can be Si, and the material of the second semiconductor layer 52 can be SiGe.
[0099] In some embodiments, prior to forming the plurality of first openings 60, the following steps are also included:
[0100] Define a first region and a second region located outside the first region in the stacked layer;
[0101] Remove part of the stacked layers to form a support groove 56 in the second region, such as Figure 5D As shown;
[0102] Fill the support groove 56 to form a support pillar 22 connected to the first semiconductor layer 51 of the first region, such as Figure 5E As shown.
[0103] In some embodiments, the specific steps of forming the support groove in the second region include:
[0104] All of the second semiconductor layer 52 and part of the first semiconductor layer 51 are removed from the second region to form a support trench 56. The remaining first semiconductor layer 51 extends from the first region into the support trench 56. Figure 5D As shown.
[0105] Specifically, after forming a stacked layer with alternating first semiconductor layer 51 and second semiconductor layer 52, a dry etching process can be used to etch the stacked layer along a direction perpendicular to the top surface of the substrate 10 to form a first trench 54 exposing the substrate, such as... Figure 5B As shown. The first trench 54 is filled with a material such as an oxide (e.g., silicon dioxide) to form a first isolation structure 55, as shown. Figure 5CAs shown. In one example, the first region may be located in the central region of the top surface of the substrate 10, and the second region may be located in the edge region of the top surface of the substrate 10, and the second region may be distributed around the outer periphery of the first region. A dry etching process can be used to etch all of the second semiconductor layer 52 and part of the first semiconductor layer 51 of the second region along a direction perpendicular to the top surface of the substrate 10 to form a support trench 56. The remaining first semiconductor layer 51 extends from the first region into the support trench 56, as shown. Figure 5D As shown. Subsequently, materials such as nitrides (e.g., silicon nitride) can be deposited within the support groove 56 to form support pillars 22 for supporting the stacked layers in the first region, as shown. Figure 5E As shown. The first semiconductor layer 51 extends into the interior of the support pillar 22, thereby further improving the support pillar 22's ability to support the remaining stacked layers, and thus further improving the structural stability of the remaining stacked layers.
[0106] In some embodiments, prior to forming the plurality of first openings 60, the following steps are also included:
[0107] A transistor region is defined in the first region, and a capacitor region and a bit line region are distributed on opposite sides of the transistor region along the second direction D2. The channel region, the first doped region 17 and the second doped region 18 are both located in the transistor region, and the first doped region 17 is adjacent to the capacitor region and the second doped region 18 is adjacent to the bit line region.
[0108] A second opening 57 is formed to expose the first doped region 17, and a third opening 58 is formed to expose the second doped region 18, as shown below. Figure 5G As shown;
[0109] A third filling layer 53 is formed, filling the second opening 57 and the third opening 58, as shown. Figure 5H As shown.
[0110] Specifically, the first isolation structure 55 is etched to form a second trench 61 within the first isolation structure 55, such as... Figure 5F As shown. Subsequently, a wet etching process can be used to remove a portion of the second semiconductor layer 52 along the second trench 61, forming a second opening 57 exposing the first doped region 17 and a third opening 58 exposing the second doped region 18 in the transistor region of the stacked layer, as shown. Figure 5G As shown. Subsequently, insulating materials such as nitrides (e.g., silicon nitride) can be deposited on the second opening 57 and the third opening 58 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes to form a third filling layer 53, such as... Figure 5H As shown. The third filling layer 53 is used to protect the first doped region 17 and the second doped region 18, and to prevent subsequent processes from damaging the first doped region 17 and the second doped region 18.
[0111] In one embodiment, there can be multiple transistor regions and multiple capacitor regions, with multiple capacitor regions adjacent to multiple transistor regions. The multiple transistor regions can be distributed around the periphery of a bit line region (e.g., two transistor regions are distributed on opposite sides of a bit line region), thereby improving the internal space utilization of the semiconductor structure and further increasing the storage capacity of the semiconductor structure.
[0112] In some embodiments, before forming the plurality of first openings, the following steps are further included:
[0113] Remove the second semiconductor layer 52 from the capacitor region to expose the first semiconductor layer 51 located in the capacitor region, as shown. Figure 5I As shown;
[0114] A first electrode layer 19 is formed in the capacitor region, covering the surface of the first semiconductor layer 51, such as Figure 5K As shown;
[0115] A dielectric layer 20 is formed covering the surface of the first electrode layer 19;
[0116] A second electrode layer 21 is formed covering the surface of the dielectric layer 20, such as Figure 5L As shown.
[0117] In some embodiments, the specific steps of forming a first electrode layer 19 covering the surface of the first semiconductor layer 51 in the capacitor region include:
[0118] A first electrode layer 19 covering the surface of the first semiconductor layer 51 is formed using a selective atomic layer deposition process.
[0119] In some embodiments, before forming a first electrode layer 19 covering the surface of the exposed first semiconductor layer 51 in the capacitor region, the following steps are further included:
[0120] Implanting first doped ions into the first semiconductor layer 51 exposed in the capacitor region, such as Figure 5J As shown.
[0121] Specifically, after forming the third filling layer 53, a wet etching process can be used to remove the second semiconductor layer 52 located in the capacitor region and the first isolation structure 55 located in the capacitor region, thereby exposing the first semiconductor layer 51 in the capacitor region, forming as shown in the image. Figure 5I The structure is shown. Subsequently, first doped ions can be implanted into the first semiconductor layer 51 exposed in the capacitor region using a vapor-phase diffusion method, as shown. Figure 5JAs shown, this enhances the conductivity of the first semiconductor layer 51 in the capacitor region. Subsequently, a conductive material such as tungsten or TiN can be deposited on the surface of the first semiconductor layer 51 doped with the first dopant ions using selective atomic deposition (SAP) to form the first electrode layer 19, as shown. Figure 5K As shown. Selective atomic layer deposition (SALD) can directly form the first electrode layer 19 on the top and bottom surfaces of the first semiconductor layer 51 without depositing conductive material on the sidewalls of the support pillar 22 and the third filler layer 53, thereby helping to further simplify the semiconductor structure manufacturing process. Next, a dielectric layer 20 with a high dielectric constant is deposited on the surface of the first electrode layer 19, and a second electrode layer 21, made of a conductive material such as tungsten or TiN, is deposited on the surface of the dielectric layer 20 to form a capacitor structure. The capacitor structure includes multiple capacitors, each of which includes the first electrode layer 19, the dielectric layer 20, and the second electrode layer 21, as shown. Figure 5L As shown.
[0122] In some embodiments, the thickness of the second semiconductor layer 52 is greater than the spacing width between two adjacent first openings 60 arranged at intervals along the first direction D1.
[0123] In some embodiments, before directly forming the word line structure in the first opening 60, the following steps are also included:
[0124] The surface of the channel region 11 is oxidized using an in-situ oxidation process to form a dielectric layer 12 on the surface of the channel region 11, such as... Figure 5N As shown.
[0125] In some embodiments, the specific steps for directly forming the word line structure in the first opening 60 include:
[0126] Conductive material is deposited in multiple first openings 60 using an atomic layer deposition process to directly form multiple word lines 13 spaced apart along a direction perpendicular to the top surface of the substrate 10. Each word line 13 continuously covers multiple channel regions 11 spaced apart along a first direction D1.
[0127] In some embodiments, along the second direction D2, the edge of the word line 13 is flush with the edge of the channel region 11.
[0128] Specifically, after forming the capacitor structure, a wet etching process can be used to remove the second semiconductor layer 52 and part of the first isolation structure 55 covering the surface of the channel region 11, forming a first opening 60 exposing the channel region 11, such as... Figure 5M As shown. Then, the surface of the channel region 11 is oxidized using a thermal oxidation method to form a dielectric layer 12, as shown. Figure 5NAs shown. Since the thickness of the second semiconductor layer 52 is greater than the spacing width between two adjacent first openings 60 spaced apart along the first direction D1, conductive material is deposited in the plurality of first openings 60 using a selective atomic layer deposition process. The conductive material in the plurality of first openings 60 spaced apart along the first direction is first connected into a line (i.e., word line 13) to directly form a plurality of word lines 13 spaced apart along a direction perpendicular to the top surface of the substrate 10, and each word line 13 only continuously covers the plurality of channel regions 11 spaced apart along the first direction D1, such as... Figure 5O As shown. The thickness of the second semiconductor layer 52 refers to its width along the direction perpendicular to the top surface of the substrate 10. Since the word line structure is formed through a one-step deposition process without additional etching, it not only simplifies the semiconductor structure manufacturing process, but also ensures that the edges of the word lines 13 are flush with the edges of the channel region 11 along the second direction D2, resulting in better morphological characteristics and better dimensional uniformity among multiple word lines 13, thereby further improving the electrical performance of the semiconductor structure.
[0129] In some embodiments, after forming the word line structure, the following steps are also included:
[0130] A first fill layer 14 is formed, filling the first opening 60 and covering the surface of the letter line 13, as follows: Figure 5P As shown;
[0131] Remove the third filler layer 53 to expose the first doped region 17 and the second doped region 18, as shown. Figure 5Q As shown;
[0132] Implanting second doped ions into the first doped region 17 and the second doped region 18, such as... Figure 5R As shown;
[0133] A second filling layer 15 is formed, filling the second opening 57 and the third opening 58 and covering the first doped region 17 and the second doped region 18, as shown. Figure 5S As shown.
[0134] In some embodiments, the specific steps for forming the first filling layer 14 include:
[0135] An insulating material is deposited within a plurality of first openings 60 using an atomic layer deposition process to form a first filling layer 14 covering the surface of word lines 13 and an air gap 141 located within the first filling layer 14, wherein the air gap 141 is located at least between two adjacent word lines 13 in a direction perpendicular to the top surface of the substrate 10.
[0136] Specifically, a vapor-phase diffusion process can be used to implant second doped ions into the first doped region 17 and the second doped region 18. When forming the first fill layer 14 using an atomic layer deposition process, an air gap 141 can also be formed in the first fill layer 14 to increase the electrical isolation effect between adjacent channel regions 11 spaced apart along the first direction D1. In one embodiment, the air gap 141 is located between two adjacent word lines 13 in a direction perpendicular to the top surface of the substrate 10, and between the word lines 13 and the substrate 10. The materials of the first fill layer 14 and the second fill layer 15 can be the same, for example, both can be oxide materials (which can be, but are not limited to, silicon dioxide).
[0137] In order to reduce the contact resistance between the first semiconductor layer 51 and the first doped region 17 in the capacitor region, in some embodiments, the type of the first doped ion is the same as the type of the second doped ion.
[0138] In some embodiments, after forming the second filling layer 15, the following steps are further included:
[0139] Remove the stacked layers in the bit line region to form bit line slot 50, such as Figure 5T As shown;
[0140] Bit lines 16 are formed in bit grooves 50, and bit lines 16 are electrically connected to the second doped region 18. Figure 5U As shown.
[0141] Specifically, a dry etching process can be used to etch away the stacked layers of the bit line region along a direction perpendicular to the top surface of the substrate 10, forming a bit line trench 50 that exposes the substrate 10. Then, a metal material such as tungsten is deposited within the bit line trench 50 to form a bit line 16 that fills the bit line trench 50. One bit line 16 is electrically connected to a plurality of second doped regions 18 spaced apart along a direction perpendicular to the top surface of the substrate 10.
[0142] The semiconductor structure and its formation method provided in some embodiments of this specific implementation form a horizontal word line structure by forming a word line structure above a substrate. This word line structure includes multiple word lines extending in a direction parallel to the top surface of the substrate. This not only enables its application in semiconductor structures with continuously shrinking dimensions but also helps improve the performance of the semiconductor structure. Furthermore, since the horizontal word lines in this specific implementation are directly deposited in the first opening of the exposed channel region, the edges of the formed word lines are flush with the edges of the channel region. No additional etching process is required after deposition, thereby simplifying the semiconductor structure formation process and reducing the manufacturing cost of the semiconductor structure.
[0143] The above are merely preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; A stacked structure is located on the substrate. The stacked structure includes a plurality of first semiconductor layers spaced apart along a direction perpendicular to the top surface of the substrate. Each first semiconductor layer includes a plurality of channel regions spaced apart along a first direction, and a first doped region and a second doped region distributed on opposite sides of each channel region along a second direction. Both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects the second direction. The word line structure includes multiple word lines extending along a first direction, and along a second direction, the edges of the word lines are flush with the edges of the channel region; and the multiple word lines are arranged at intervals along a direction perpendicular to the top surface of the substrate. Wherein, the spacing width between two adjacent channel regions along the first direction is smaller than the spacing width between two adjacent channel regions along the direction perpendicular to the top surface of the substrate; The stacked structure further includes: a first filling layer and a second filling layer, wherein the first filling layer is located between adjacent word lines, and the second filling layer is located between adjacent first doped regions and adjacent second doped regions. The semiconductor structure also includes: An air gap is located within the first filler layer and is located at least between two adjacent word lines in a direction perpendicular to the top surface of the substrate.
2. The semiconductor structure according to claim 1, characterized in that, Each of the word lines continuously covers a plurality of channel regions arranged along the first direction, and the channel regions and the word lines further include: A dielectric layer covers the surface of the channel region, the word lines cover the surface of the dielectric layer, and the edges of the dielectric layer are flush with the edges of the word lines in a direction perpendicular to the top surface of the substrate.
3. The semiconductor structure according to claim 1, characterized in that, The stacked structure further includes a capacitor structure, which includes a first electrode layer, a dielectric layer, and a second electrode layer disposed sequentially around the surface of the first semiconductor layer. The capacitor structure is adjacent to and electrically connected to the first doped region, and the first semiconductor layer surrounded by the capacitor structure and the first semiconductor layer corresponding to the first doped region are doped with the same ions.
4. The semiconductor structure according to claim 3, characterized in that, The stacked structure further includes a bit line structure, which is adjacent to the second doped region. The bit line structure includes at least one bit line, which extends perpendicularly to the top surface of the substrate. In the direction perpendicular to the top surface of the substrate, one bit line is electrically connected to a plurality of second doped regions that are spaced apart along the direction perpendicular to the top surface of the substrate.
5. The semiconductor structure according to claim 4, characterized in that, Also includes: At least one support pillar is located on the substrate and on the side of the capacitor structure opposite to the first doped region, and the support pillar is at least connected to the stacked structure.
6. The semiconductor structure according to claim 5, characterized in that, The first semiconductor layer in the stacked structure extends into the interior of the support column along the second direction.
7. The semiconductor structure according to claim 6, characterized in that, The support pillar extends in a direction perpendicular to the top surface of the substrate, and the top surface of the support pillar is flush with the top surface of the stacked structure.
8. A method for forming a semiconductor structure, used to form the semiconductor structure according to any one of claims 1-7, characterized in that, Includes the following steps: A substrate is formed, and a stacked layer is located on the substrate. The stacked layer includes a first semiconductor layer and a second semiconductor layer that are alternately stacked along a direction perpendicular to the top surface of the substrate. The first semiconductor layer includes a plurality of channel regions spaced apart along a first direction, and a first doped region and a second doped region distributed on opposite sides of each of the channel regions along a second direction. The first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects the second direction. Forming multiple first openings that respectively expose multiple said trench regions; A character line structure is directly formed in the first opening. The character line structure includes multiple character lines extending along the first direction, and the character lines continuously cover multiple channel regions arranged at intervals.
9. The method for forming a semiconductor structure according to claim 8, characterized in that, The thickness of the second semiconductor layer is greater than the spacing width between two adjacent first openings spaced apart along the first direction.
10. The method for forming a semiconductor structure according to claim 9, characterized in that, Before forming the plurality of the first openings, the following steps are also included: A first region and a second region located outside the first region are defined in the stacked layer; Remove a portion of the stacked layers to form a support groove in the second region; The support groove is filled to form a support pillar that is connected to the first semiconductor layer in the first region.
11. The method for forming a semiconductor structure according to claim 10, characterized in that, The specific steps for forming the support groove in the second region include: All of the second semiconductor layer and part of the first semiconductor layer in the second region are removed to form a support trench, with the remaining first semiconductor layer extending from the first region into the support trench.
12. The method for forming a semiconductor structure according to claim 10, characterized in that, Before forming the plurality of the first openings, the following steps are also included: A transistor region is defined in the first region, and a capacitor region and a bit line region are distributed on opposite sides of the transistor region along the second direction. The channel region, the first doped region and the second doped region are all located in the transistor region, and the first doped region is adjacent to the capacitor region and the second doped region is adjacent to the bit line region. A second opening is formed to expose the first doped region, and a third opening is formed to expose the second doped region; A third filling layer is formed that fills the second opening and the third opening.
13. The method for forming a semiconductor structure according to claim 12, characterized in that, Before forming the plurality of the first openings, the following steps are also included: Remove the second semiconductor layer in the capacitor region to expose the first semiconductor layer located in the capacitor region; A first electrode layer covering the surface of the first semiconductor layer is formed in the capacitor region; A dielectric layer is formed covering the surface of the first electrode layer; A second electrode layer is formed covering the surface of the dielectric layer.
14. The method for forming a semiconductor structure according to claim 13, characterized in that, The specific steps for forming a first electrode layer covering the surface of the first semiconductor layer in the capacitor region include: A first electrode layer covering the surface of the first semiconductor layer is formed using a selective atomic layer deposition process.
15. The method for forming a semiconductor structure according to claim 13, characterized in that, Before forming a first electrode layer covering the surface of the exposed first semiconductor layer in the capacitor region, the following steps are further included: The first doped ion is injected into the first semiconductor layer exposed in the capacitor region.
16. The method for forming a semiconductor structure according to claim 12, characterized in that, Before directly forming the character line structure in the first opening, the following steps are also included: The surface of the channel region is oxidized using an in-situ oxidation process to form a dielectric layer on the surface of the channel region.
17. The method for forming a semiconductor structure according to claim 9, characterized in that, The specific steps for directly forming the character line structure in the first opening include: Conductive material is deposited in a plurality of the first openings using an atomic layer deposition process to directly form a plurality of word lines spaced apart along a direction perpendicular to the top surface of the substrate, each word line continuously covering a plurality of channel regions spaced apart along the first direction.
18. The method for forming a semiconductor structure according to claim 17, characterized in that, Along the second direction, the edge of the word line is flush with the edge of the channel region.
19. The method for forming a semiconductor structure according to claim 15, characterized in that, After forming the word line structure, the following steps are also included: A first fill layer is formed that fills the first opening and covers the surface of the letter line; Remove the third filling layer to expose the first doped region and the second doped region; Injecting second doped ions into the first doped region and the second doped region; A second filling layer is formed that fills the second opening and the third opening and covers the first doped region and the second doped region.
20. The method for forming a semiconductor structure according to claim 19, characterized in that, The specific steps for forming the first filling layer include: depositing insulating material in a plurality of first openings using an atomic layer deposition process to form the first filling layer covering the surface of the word lines and an air gap located in the first filling layer, wherein the air gap is located at least between two adjacent word lines in a direction perpendicular to the top surface of the substrate.
21. The method for forming a semiconductor structure according to claim 19, characterized in that, The type of the first doped ion is the same as the type of the second doped ion.
22. The method for forming a semiconductor structure according to claim 19, characterized in that, After the second filling layer is formed, the following steps are also included: Remove the stacked layer in the bit line region to form a bit line groove; A bit line is formed in the bit line groove, and the bit line is electrically connected to the second doped region.