A semiconductor device and a manufacturing method thereof

Abstract

The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, the semiconductor device comprising: a substrate and a plurality of memory structures stacked on the substrate; the memory structure comprising: a first dielectric layer and a channel layer located in the first dielectric layer and extending along a first direction, the first dielectric layer having a first recess separating the channel layer; a capacitor structure covering the sidewall and the bottom surface of the first recess.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In semiconductor devices that include capacitors, such as dynamic random access memory (DRAM), they are typically formed by a single-layer memory cell configuration, which typically includes a transistor and a capacitor post, with the transistor located inside the substrate and the capacitor post located on the substrate.

[0003] However, as various electronic devices continue to demand higher integration and data storage density, ordinary two-dimensional semiconductor devices are finding it increasingly difficult to meet these requirements. Summary of the Invention

[0004] This disclosure provides a semiconductor device, including:

[0005] Substrate and multiple storage structures stacked on the substrate;

[0006] The storage structure includes: a first dielectric layer and a channel layer located within the first dielectric layer and extending along a first direction, wherein the first dielectric layer has a first groove that separates the channel layer; and a capacitor structure covering the sidewalls and bottom surface of the first groove.

[0007] In some embodiments, the first dielectric layer includes a first dielectric sublayer, an etch barrier layer, and a second dielectric sublayer disposed from bottom to top, wherein the first groove penetrates the second dielectric sublayer and exposes the etch barrier layer.

[0008] In some embodiments, there are multiple channel layers, the multiple channel layers are arranged along a second direction, and the multiple channel layers are separated by multiple first grooves, the multiple first grooves are arranged and distributed along the second direction.

[0009] In some embodiments, the capacitor structure includes:

[0010] The first electrode covers the sidewall and bottom surface of the first groove;

[0011] A second dielectric layer covers the first electrode;

[0012] The second electrode covers the second dielectric layer.

[0013] In some embodiments, the storage structure further includes: a third dielectric layer covering the channel layer and the first dielectric layer, wherein the third dielectric layer and the first dielectric layer have a second groove extending in a second direction, the second groove exposing the channel layer.

[0014] In some embodiments, the storage structure further includes a word line layer extending along a second direction, the word line layer being located within the second recess.

[0015] In some embodiments, the storage structure further includes: a fourth dielectric layer that covers the surface of the channel layer exposed by the second groove, and covers the sidewalls and bottom surface of the second groove, the third dielectric layer, and the capacitor structure.

[0016] In some embodiments, the semiconductor device further includes a bit line layer that extends from the topmost memory structure to the bottommost memory structure and is connected to the channel layers in the plurality of memory structures.

[0017] In some embodiments, in a first direction, a single channel layer is separated by a plurality of first grooves, two word line layers are disposed between two adjacent first grooves, and a bit line layer is disposed between the two word line layers.

[0018] In some embodiments, the material of the channel layer includes one or more of indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, and tin aluminum zinc oxide.

[0019] This disclosure also provides a method for manufacturing a semiconductor device, comprising:

[0020] Provide substrate;

[0021] Forming a storage structure on the substrate includes: forming a first dielectric layer; forming a channel layer extending in a first direction within the first dielectric layer; forming a first groove within the first dielectric layer that separates the channel layer; and forming a capacitor structure that covers the sidewalls and bottom surface of the first groove.

[0022] One or more of the storage structures are then stacked on top of the existing storage structure.

[0023] In some embodiments, the first dielectric layer includes a first dielectric sublayer, an etch barrier layer, and a second dielectric sublayer; forming the first dielectric layer includes: forming the first dielectric sublayer; forming the etch barrier layer on the first dielectric sublayer; and forming the second dielectric sublayer on the etch barrier layer.

[0024] In some embodiments, the number of channel layers is plurality of those channel layers, and the plurality of channel layers are arranged along a second direction; forming the channel layers within the first dielectric layer includes:

[0025] The second dielectric sublayer is etched to form a plurality of first trenches extending along a first direction within the second dielectric sublayer, and the plurality of first trenches are arranged along a second direction;

[0026] The channel layer is formed within the first trench.

[0027] In some embodiments, a plurality of the channel layers are separated by a plurality of first grooves, the plurality of first grooves being arranged along a second direction; forming the first groove that separates the channel layers within the first dielectric layer includes: etching the channel layer and the second dielectric sublayer from top to bottom until the etch barrier layer is exposed, thereby forming the first groove.

[0028] In some embodiments, the capacitor structure includes a first electrode, a second dielectric layer, and a second electrode; forming the capacitor structure includes:

[0029] The first electrode is formed in the first groove, and the first electrode covers the sidewall and bottom surface of the first groove;

[0030] A second dielectric material layer is formed on the first dielectric layer, the channel layer, and the first electrode, and a second electrode material layer is formed on the second dielectric material layer;

[0031] A portion of the second electrode material layer and a portion of the second dielectric material layer are removed to form the second electrode and the second dielectric layer, respectively, with the second electrode and the second dielectric layer covering the first electrode.

[0032] In some embodiments, the storage structure further includes a third dielectric layer and a second groove extending along a second direction; after forming the capacitor structure, the method further includes:

[0033] The third dielectric layer is formed on the channel layer and the first dielectric layer;

[0034] A portion of the first dielectric layer and a portion of the third dielectric layer are removed, and a second groove is formed within the first dielectric layer and the third dielectric layer, the second groove exposing the channel layer.

[0035] In some embodiments, the storage structure further includes a word line layer extending along a second direction; after forming the second recess, the method further includes:

[0036] The letter line layer is formed within the second groove.

[0037] In some embodiments, the storage structure further includes a fourth medium layer; before forming the word line layer within the second recess, the method further includes:

[0038] The fourth dielectric layer is formed, which covers the surface of the channel layer exposed by the second groove, and covers the sidewalls and bottom surface of the second groove, the third dielectric layer, and the capacitor structure.

[0039] In some embodiments, after stacking one or more of the storage structures on top of the storage structure, the method further includes:

[0040] Multiple memory structures are etched from top to bottom to form a second trench. The second trench extends from the topmost memory structure to the bottommost memory structure and penetrates the channel layer in the multiple memory structures.

[0041] A bitline layer is formed within the second trench.

[0042] The semiconductor device and its manufacturing method provided in this disclosure include: a substrate and a plurality of memory structures stacked on the substrate; each memory structure includes: a first dielectric layer and a channel layer located within the first dielectric layer and extending along a first direction, the first dielectric layer having a first groove that separates the channel layer; and a capacitor structure covering the sidewalls and bottom surface of the first groove. The semiconductor device provided in this disclosure includes a plurality of memory structures stacked on a substrate, which improves the integration and storage density of the semiconductor device compared to semiconductor devices with single-layer memory cells in related technologies. Furthermore, the capacitor structure provided in this disclosure covers the sidewalls and bottom surface of the first groove, and compared to capacitor pillars with high aspect ratios in related technologies, the manufacturing process of the capacitor structure is simpler.

[0043] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the accompanying drawings and claims. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figures 1a to 1c A schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0046] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0047] Figures 3a to 16c This is a process flow diagram of a semiconductor device provided in an embodiment of this disclosure. Detailed Implementation

[0048] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0049] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0050] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] In semiconductor devices that include capacitors, such as dynamic random access memory (DRAM), they are typically formed by a single-layer memory cell configuration. This memory cell typically includes a transistor and a capacitor pillar, with the transistor located within the substrate and the capacitor pillar on the substrate. However, as the demands for integration and data storage density in various electronic devices continue to increase, ordinary two-dimensional semiconductor devices are increasingly unable to meet these requirements. Furthermore, in related technologies, the capacitor pillars often have a large aspect ratio, their manufacturing process is complex, and the number of capacitor pillars that can be accommodated per unit volume is relatively small, resulting in low storage density in the semiconductor device.

[0055] Based on this, the following technical solutions for embodiments of this disclosure are proposed:

[0056] This disclosure provides a semiconductor device, including: a substrate and a plurality of memory structures stacked on the substrate; the memory structures include: a first dielectric layer and a channel layer located within the first dielectric layer and extending along a first direction, the first dielectric layer having a first groove that isolates the channel layer; and a capacitor structure covering the sidewalls and bottom surface of the first groove.

[0057] The semiconductor device provided in this disclosure includes multiple memory structures stacked on a substrate, which improves the integration and storage density compared to semiconductor devices with single-layer memory cells in related technologies. Furthermore, the capacitor structure provided in this disclosure covers the sidewalls and bottom surface of the first groove, making the manufacturing process of the capacitor structure simpler compared to capacitor pillars with high aspect ratios in related technologies.

[0058] The semiconductor device provided in this disclosure can be a dynamic random access memory (DRAM), but is not limited thereto. The semiconductor device can also be any semiconductor device with capacitance.

[0059] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, the schematic diagrams may be partially enlarged without adhering to the usual proportions for ease of explanation, and the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this disclosure.

[0060] Figures 1a to 1c A schematic diagram of a semiconductor device provided in an embodiment of this disclosure; wherein, Figure 1a This is a top view schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Figure 1b For along Figure 1a A schematic diagram of the cross-sectional structure taken by line AA'. Figure 1c For along Figure 1a A schematic diagram of the cross-sectional structure taken from line BB'. The following is combined with... Figures 1a to 1c The method for manufacturing a semiconductor device provided in the embodiments of this disclosure will be described in further detail.

[0061] As shown in the figure, the semiconductor device includes: a substrate 10 and a plurality of memory structures 20 stacked on the substrate 10; the memory structure 20 includes: a first dielectric layer 11 and a channel layer 12 located in the first dielectric layer 11 and extending along a first direction, the first dielectric layer 11 having a first groove S1 that isolates the channel layer 12; and a capacitor structure 13 covering the sidewalls and bottom surface of the first groove S1.

[0062] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0063] like Figure 1bAs shown, in one embodiment, the first dielectric layer 11 includes a first dielectric sublayer 111, an etch barrier layer 112, and a second dielectric sublayer 113 disposed from bottom to top. The first groove S1 penetrates the second dielectric sublayer 113 and exposes the etch barrier layer 112. The function of the etch barrier layer 112 is to prevent the first groove S1 from penetrating the first dielectric layer 11 during the formation of the first groove S1, thereby preventing the capacitor structure 13 in the first groove S1 from being electrically connected to the substrate 10. The material of the etch barrier layer 112 can be a nitride, such as silicon nitride. The materials of the first dielectric sublayer 111 and the second dielectric sublayer 113 can be oxides. In some embodiments, the materials of the first dielectric sublayer 111 and the second dielectric sublayer 113 are the same, for example, silicon oxide.

[0064] In one embodiment, there are multiple channel layers 12, which are arranged along a second direction and separated by multiple first grooves S1, which are distributed along the second direction. In some embodiments, the channel layers 12 are located within the second dielectric sublayer 113, and the upper surface of the channel layers 12 is flush with the upper surface of the second dielectric sublayer 113. The material of the channel layers 12 includes one or more of indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, and tin aluminum zinc oxide. The material of the channel layers 12 may also include silicon, germanium, silicon germanium, etc. The channel layers 12 may be doped or undoped. When indium gallium zinc oxide (IGZO) is used as the material of the channel layers 12, the electron mobility can be improved, thereby improving the write speed of the semiconductor device.

[0065] In one embodiment, the first direction and the second direction are parallel to the surface of the substrate 10. In some embodiments, the first direction is perpendicular to the second direction. However, it is not limited to this; the first direction may also be oblique to the second direction.

[0066] In one embodiment, a plurality of the first grooves S1 are arranged in an array along a first direction and a second direction, respectively. That is, in the first direction, a single channel layer 12 is separated by a plurality of the first grooves S1, and two adjacent first grooves S1 in the first direction are, for example... Figure 1b The first groove S11 and the first groove S12 are shown in the figure.

[0067] In one embodiment, in a first direction, two adjacent first grooves S11 and S12 divide the channel layer 12 into an active region AA. The active region AA includes a first source / drain doped region d1 located at both ends of the active region AA and a second source / drain doped region d2 located in the middle region of the active region AA. The first source / drain doped region d1 and the second source / drain doped region d2 can be formed in the channel layer 12 by ion implantation. In a specific embodiment, the first source / drain doped region d1 and the second source / drain doped region d2 have the same conductivity type, such as n-type. In a more specific embodiment, the region located between the first source / drain doped region d1 and the second source / drain doped region d2 has p-type doping.

[0068] like Figure 1b As shown, in one embodiment, the capacitor structure 13 includes: a first electrode 131 covering the sidewall and bottom surface of the first groove S1; a second dielectric layer 132 covering the first electrode 131; and a second electrode 133 covering the second dielectric layer 132. The first electrode 131 is connected to the channel layer 12, and the upper surface of the first electrode 131 is flush with the upper surface of the channel layer 12. In a specific embodiment, the first electrode 131 is connected to the first source / drain doped region (not labeled). The material of the second dielectric layer 132 can be a high dielectric constant material, such as tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. The materials of the first electrode 131 and the second electrode 133 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys. In some embodiments, the first electrode 131 and the second electrode 133 are made of the same material, for example, titanium nitride (TiN). In some other embodiments, the materials of the first electrode 131 and the second electrode 133 may be different.

[0069] In some embodiments, the first groove S1 has a smaller aspect ratio. Compared to forming capacitor pillars with a larger aspect ratio in related technologies, the process of forming the capacitor structure 13 on the sidewalls and bottom surface of the first groove S1 is simpler. That is, the process of forming the memory structure 20 in this embodiment is simpler and facilitates stacking a larger number of memory structures 20 on the substrate 10, increasing the memory capacity of the semiconductor device. Furthermore, the shallow depth of the first groove S1, i.e., the smaller height of the capacitor structure 13, allows for more capacitor structures 13 to be accommodated per unit volume, improving the integration and memory density of the semiconductor device.

[0070] In one embodiment, there are multiple capacitor structures 13, which are arranged in an array along a first direction and a second direction. In some embodiments, the second dielectric layer 132 of the multiple capacitor structures 13 arranged along the second direction is interconnected, and the second electrode 133 of the multiple capacitor structures 13 arranged along the second direction is also interconnected. The second dielectric layer 132 covers the first electrode 131 and also partially covers the first dielectric layer 11. In other words, the multiple capacitor structures 13 arranged along the second direction share a common second dielectric layer 132 and a common second electrode 133, which extend along the second direction, thus simplifying the manufacturing process of the semiconductor device. In some embodiments, the second dielectric layer 132 also covers a portion of the channel layer 12.

[0071] In one embodiment, in the first direction, two capacitor structures 13 located on the sidewalls and bottom surfaces of the two adjacent first grooves S1 have a shared second dielectric layer 132 and a first electrode 133, thereby further simplifying the manufacturing process of the semiconductor device.

[0072] In one embodiment, the storage structure 20 further includes an opening 14 located within and above the first recess S1, and a filling layer 15 located within the opening 14, the opening 14 being formed because the capacitor structure 13 does not completely fill the first recess S1. The upper surface of the filling layer 15 is flush with the upper surface of the second electrode 133. The material of the filling layer 15 includes nitrides, such as silicon nitride.

[0073] In one embodiment, the memory structure 20 further includes a third dielectric layer 16 covering the channel layer 12 and the first dielectric layer 11, wherein the third dielectric layer 16 and the first dielectric layer 11 have a second groove S2 extending in a second direction, the second groove S2 exposing the channel layer 12. In a specific embodiment, the memory structure 20 further includes a word line layer 18 extending in the second direction, the word line layer 18 being located within the second groove S2. The material of the third dielectric layer 16 includes oxides, such as silicon oxide. The material of the word line layer 18 includes one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys.

[0074] Here, the upper surface of the third dielectric layer 16 is flush with the upper surface of the third electrode 133 and the filling layer 15. The second groove S2 penetrates the third dielectric layer 16 and the second dielectric sub-layer 113 from top to bottom, and exposes the etching barrier layer 112 and the channel layer 12. The word line layer 18 located in the second groove S2 extends along the second direction and surrounds the channel layer 12. The manufacturing process of the word line layer 18 is relatively simple.

[0075] In one embodiment, there are multiple second grooves S2 arranged along a first direction; there are multiple word line layers 18 arranged along the first direction. In a specific embodiment, two word line layers 18 are disposed between two adjacent first grooves S11, S12 in the first direction. In a more specific embodiment, the word line layers 18 are disposed between the first source / drain doped region d1 and the second source / drain doped region d2, separating the first source / drain doped region d1 and the second source / drain doped region d2.

[0076] In one embodiment, the storage structure 20 further includes a fourth dielectric layer 17, which covers the surface of the channel layer 12 exposed by the second recess S2, and covers the sidewalls and bottom surface of the second recess S2, the third dielectric layer 16, and the capacitor structure 13. The word line layer 18 is separated from the channel layer 12 by the fourth dielectric layer 17, and the upper surface of the word line layer 18 is flush with the upper surface of the fourth dielectric layer 17. In some embodiments, the fourth dielectric layer 17 further covers the filler layer 15. The fourth dielectric layer 17 may be an oxide, such as silicon oxide.

[0077] In one embodiment, the semiconductor device further includes a bit line layer 19 extending downward from the topmost memory structure 20 to the bottommost memory structure 20 and connected to the channel layers 12 in the plurality of memory structures 20. The bit line layer 19 is made of one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys.

[0078] In one embodiment, the bit line layer 19 can be formed by: firstly, etching multiple memory structures 20 from top to bottom to form a second trench T2, the second trench T2 extending from the topmost memory structure 20 to the bottommost memory structure 20 and penetrating the channel layers 12 in the multiple memory structures 20; then, forming the bit line layer 19 within the second trench T2. This embodiment simplifies the manufacturing process of the bit line layer 19 by forming the second trench T2 connecting multiple channel layers 12 in a single drilling step and forming the bit line layer 19 within the second trench T2. In some embodiments, in a first direction, a bit line layer 19 is disposed between the two word line layers 18 located between two adjacent first grooves S11, S12. Thus, the two capacitor structures 13 and the two adjacent word line layers 18 share a single bit line layer 19, further simplifying the manufacturing process of the semiconductor device, saving space, and increasing the storage density of the semiconductor device. In one specific embodiment, the bit line layer 19 is connected to the second source / drain doped region d2.

[0079] In one embodiment, there are multiple bit line layers 19, and these multiple bit line layers 19 are arranged along a second direction, such as... Figure 1a As shown. In some embodiments, the bit line layers 19 may also be arranged in an array along a first direction and a second direction, respectively.

[0080] As can be seen, the semiconductor device provided in this embodiment includes a plurality of memory structures 20 stacked on the substrate 10, which improves the integration and storage density of the semiconductor device.

[0081] This disclosure also provides a method for manufacturing a semiconductor device, such as... Figure 2 As shown, the method includes the following steps:

[0082] Step 201: Provide a substrate;

[0083] Step 202: Forming a storage structure on the substrate, including: forming a first dielectric layer; forming a channel layer extending in a first direction within the first dielectric layer; forming a first groove within the first dielectric layer that separates the channel layer; and forming a capacitor structure that covers the sidewalls and bottom surface of the first groove.

[0084] Step 203: Stack the storage structures on top of the storage structures to form one or more of the storage structures.

[0085] Figures 3a to 16c This is a process flow diagram of a semiconductor device provided in an embodiment of this disclosure. Wherein, Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a , Figure 13a , Figure 14a , Figure 15a , Figure 16a This is a top view schematic diagram of the manufacturing method of the semiconductor device provided in the embodiments of this disclosure at different process steps. Figure 3b , Figure 4b , Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b , Figure 10b , Figure 11b , Figure 12b , Figure 13b , Figure 14b , Figure 15b , Figure 16b respectively along Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a , Figure 13a , Figure 14a , Figure 15a , Figure 16a A schematic diagram of the cross-sectional structure taken by line AA'; Figure 3c , Figure 4c , Figure 5c , Figure 6c , Figure 7c , Figure 8c , Figure 9c , Figure 10c , Figure 11c , Figure 12c , Figure 13c , Figure 14c , Figure 15c , Figure 16c respectively along Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a , Figure 13a , Figure 14a , Figure 15a , Figure 16aA schematic diagram of the cross-sectional structure taken from line BB'. Below, combined with... Figures 3a to 16c The method for manufacturing a semiconductor device according to embodiments of this disclosure will be described in further detail.

[0086] First, perform step 201, such as... Figures 3a to 3c As shown, a substrate 10 is provided.

[0087] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0088] Next, proceed to step 202, as follows: Figures 4a to 16c As shown, a storage structure 20 is formed on the substrate 10, including: forming a first dielectric layer 11; forming a channel layer 12 extending in a first direction within the first dielectric layer 11; forming a first groove S1 that isolates the channel layer 12 within the first dielectric layer 11; and forming a capacitor structure 13 that covers the sidewalls and bottom surface of the first groove S1.

[0089] Specifically, firstly, such as Figures 4a to 4c As shown, the first dielectric layer 11 includes a first dielectric sublayer 111, an etch stop layer 112, and a second dielectric sublayer 113. Forming the first dielectric layer 11 specifically includes: forming the first dielectric sublayer 111; forming the etch stop layer 112 on the first dielectric sublayer 111; and forming the second dielectric sublayer 113 on the etch stop layer 112. The material of the etch stop layer 112 may be a nitride, such as silicon nitride. The materials of the first dielectric sublayer 111 and the second dielectric sublayer 113 may be oxides. In some embodiments, the first dielectric sublayer 111 and the second dielectric sublayer 113 are made of the same material, for example, silicon oxide.

[0090] Next, as Figures 5a to 6c As shown, there are multiple channel layers 12, and the multiple channel layers 12 are arranged along the second direction. The channel layers 12 are formed within the first dielectric layer 11, specifically including:

[0091] The second dielectric sublayer 113 is etched to form a plurality of first trenches T1 extending along a first direction within the second dielectric sublayer 113, and the plurality of first trenches T1 are arranged along a second direction (e.g., Figures 5a to 5c );

[0092] The channel layer 12 is formed within the first trench T1 (e.g., Figures 6a to 6c ).

[0093] In one embodiment, the first direction and the second direction are parallel to the surface of the substrate 10. In some embodiments, the first direction is perpendicular to the second direction. However, it is not limited to this; the first direction may also be oblique to the second direction.

[0094] like Figure 6c As shown, the channel layer 12 is located within the second dielectric sublayer 113, and the upper surface of the channel layer 12 is flush with the upper surface of the second dielectric sublayer 113. The material of the channel layer 12 includes one or more of silicon, germanium, silicon-germanium, indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, and tin aluminum zinc oxide. The channel layer 12 may be doped or undoped. When indium gallium zinc oxide (IGZO) is used as the material of the channel layer 12, electron mobility can be improved, thereby increasing the write speed of the semiconductor device.

[0095] Next, as Figures 7a to 7c As shown, multiple channel layers 12 are separated by multiple first grooves S1, and the multiple first grooves S1 are arranged along a second direction. Forming the first grooves S1 that separate the channel layers 12 within the first dielectric layer 11 specifically includes etching the channel layers 12 and the second dielectric sublayer 113 from top to bottom until the etching barrier layer 112 is exposed, thus forming the first grooves S1. In the above etching process, the function of the etching barrier layer 112 is to prevent the first grooves S1 from penetrating the first dielectric layer 11 during the formation of the first grooves S1, thereby preventing the capacitor structure 13 within the first grooves S1 from being electrically connected to the substrate 10.

[0096] In one embodiment, a plurality of the first grooves S1 are arranged in an array along a first direction and a second direction, that is, in the first direction, a single channel layer 12 is separated by a plurality of the first grooves S1, and two adjacent first grooves S1 in the first direction are the first groove S11 and the first groove S12.

[0097] Next, as Figures 8a to 11c As shown, the capacitor structure 13 includes a first electrode 131, a second dielectric layer 132, and a second electrode 133; forming the capacitor structure 13 includes:

[0098] The first electrode 131 is formed within the first groove S1, and the first electrode 131 covers the sidewalls and bottom surface of the first groove S1 (e.g., Figures 8a to 8c (as shown);

[0099] A second dielectric material layer 132a is formed on the first dielectric layer 11, the channel layer 12, and the first electrode 131, and a second electrode material layer 133a (e.g., ...) is formed on the second dielectric material layer 132a. Figures 9a to 9c (as shown);

[0100] Removing a portion of the second electrode material layer 133a and a portion of the second dielectric material layer 132a to form the second electrode 133 and the second dielectric layer 132 respectively, the second electrode 133 and the second dielectric layer 132 covering the first electrode 131 (e.g. Figures 11a to 11c (As shown).

[0101] like Figure 11b As shown, the first electrode 131 is connected to the channel layer 12, and the upper surface of the first electrode 131 is flush with the upper surface of the channel layer 12. In actual operation, the material of the second dielectric layer 132 can be a high dielectric constant material, such as tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. The materials of the first electrode 131 and the second electrode 133 can include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys. In some embodiments, the first electrode 131 and the second electrode 133 are made of the same material, for example, titanium nitride (TiN).

[0102] In one embodiment, there are multiple capacitor structures 13, which are arranged in an array along a first direction and a second direction. In some embodiments, the second dielectric layers 132 of the multiple capacitor structures 13 arranged along the second direction are interconnected, and the second electrodes 133 of the multiple capacitor structures 13 arranged along the second direction are also interconnected. The second dielectric layer 132 covers the first electrode 131 and also partially covers the first dielectric layer 11, such as... Figure 11a As shown. In other words, the plurality of capacitor structures 13 arranged along the second direction have a common second dielectric layer 132 and a common second electrode 133, which extend along the second direction, thereby simplifying the manufacturing process of the semiconductor device. In some embodiments, the second dielectric layer 132 also covers a portion of the channel layer 12.

[0103] See you again Figures 9a to 9cIn one embodiment, after forming the second electrode material layer 133a on the second dielectric material layer 132a, the storage structure 20 forms an opening 14 located within and above the first groove S1. This opening 14 is formed because the first electrode 131, the second dielectric material layer 132a, and the second electrode material layer 133a do not completely fill the first groove S1. In a specific embodiment, forming the storage structure 20 further includes forming a filling layer 15 within the opening 14, the upper surface of which is flush with the upper surface of the second electrode material layer 133a. Figures 10a to 10c As shown. The material of the filling layer 15 includes nitrides, such as silicon nitride.

[0104] Next, as Figures 12a to 13c As shown, the storage structure 20 further includes a third dielectric layer 16 and a second groove S2 extending along the second direction. After forming the capacitor structure 13, the method further includes:

[0105] The third dielectric layer 16 is formed on the channel layer 12 and the first dielectric layer 11 (e.g., Figures 12a to 12c (as shown); the material of the third dielectric layer 16 includes oxides, such as silicon oxide;

[0106] Removing a portion of the first dielectric layer 11 and a portion of the third dielectric layer 16, forming a second groove S2 within the first dielectric layer 11 and the third dielectric layer 16, the second groove S2 exposing the channel layer 12 (e.g. Figures 13a to 13c (As shown).

[0107] Next, as Figures 15a to 15c As shown, the storage structure further includes a word line layer 18 extending along a second direction; after forming the second recess S2, the method further includes: forming the word line layer 18 within the second recess S2. The material of the word line layer 18 includes one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys.

[0108] In one embodiment, the upper surface of the third dielectric layer 16 is flush with the upper surfaces of the third electrode 133 and the filling layer 15. The second groove S2 penetrates the third dielectric layer 16 and the second dielectric sublayer 113 from top to bottom, and exposes the etching barrier layer 112 and the channel layer 12. The word line layer 18 located in the second groove S2 extends along the second direction and surrounds the channel layer 12. The manufacturing process of the word line layer 18 is relatively simple.

[0109] In some embodiments, there are multiple second grooves S2, and the multiple second grooves S2 are arranged along a first direction; there are multiple word line layers 18, and the multiple word line layers 18 are arranged along the first direction. In a specific embodiment, in the first direction, two word line layers 18 are provided between two adjacent first grooves S11, S12.

[0110] Next, as Figures 14a to 14c As shown, the storage structure 20 further includes a fourth dielectric layer 17; before forming the word line layer 18 within the second recess S2, the method further includes: forming the fourth dielectric layer 17, which covers the surface of the channel layer 12 exposed by the second recess S2, and covers the sidewalls and bottom surface of the second recess S2, the third dielectric layer 16, and the capacitor structure 13. The fourth dielectric layer 17 is formed before forming the word line layer 18, and the word line layer 18 is separated from the channel layer 12 by the fourth dielectric layer 17, with the upper surface of the word line layer 18 flush with the upper surface of the fourth dielectric layer 17. In some embodiments, the fourth dielectric layer 17 further covers the filler layer 15. The fourth dielectric layer 17 may be an oxide, such as silicon oxide.

[0111] Next, proceed to step 203, as follows: Figures 16a to 16c As shown, one or more of the storage structures 20 are further stacked on top of the storage structure 20 to form the storage structure 20.

[0112] The embodiments of this disclosure improve the integration and storage density of the semiconductor device by stacking multiple storage structures 20 on the substrate 10.

[0113] In some embodiments, the first groove S1 has a smaller aspect ratio. Compared to forming capacitor pillars with a larger aspect ratio in related technologies, the process of forming the capacitor structure 13 on the sidewalls and bottom surface of the first groove S1 is simpler. That is, the process of forming the memory structure 20 in this embodiment is simpler and facilitates stacking a larger number of memory structures 20 on the substrate 10, increasing the memory capacity of the semiconductor device. Furthermore, the shallow depth of the first groove S1, i.e., the smaller height of the capacitor structure 13, allows for more capacitor structures 13 to be accommodated per unit volume, improving the integration and memory density of the semiconductor device.

[0114] Next, after stacking one or more memory structures 20 on the memory structure 20, the method further includes: etching the plurality of memory structures 20 from top to bottom to form a second trench T2, the second trench T2 extending from the topmost memory structure 20 to the bottommost memory structure 20 and penetrating the channel layer 12 in the plurality of memory structures 20; forming a bit line layer 19 within the second trench T2, ultimately forming as shown in the figure. Figures 1a to 1c The structure shown. The material of the bit line layer 19 includes one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys.

[0115] This embodiment of the disclosure forms the second trench T2 connecting the multiple channel layers 12 through a one-step drilling method, and forms the bit line layer 19 within the second trench T2, simplifying the manufacturing process of the bit line layer 19. In some embodiments, in a first direction, a bit line layer 19 is disposed between the two word line layers 18 located between two adjacent first grooves S11, S12. Thus, the two capacitor structures 13 located on the sidewalls and bottom surfaces of the two adjacent first grooves S11, S12, and the two adjacent word line layers 18 share a single bit line layer 19, further simplifying the manufacturing process of the semiconductor device, while saving space and increasing the storage density of the semiconductor device.

[0116] In one embodiment, there are multiple bit line layers 19, and these multiple bit line layers 19 are arranged along a second direction, such as... Figure 1a As shown. In some embodiments, the bit line layer 19 may also be arranged in an array along a first direction and a second direction, respectively.

[0117] It should be noted that those skilled in the art can change the order of the above steps without departing from the scope of protection of this disclosure. The above description is only an optional embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Substrate and multiple storage structures stacked on the substrate; The storage structure includes: a first dielectric layer and a channel layer located within the first dielectric layer and extending along a first direction, wherein the first dielectric layer has a first groove that separates the channel layer; A capacitor structure covers the sidewalls and bottom surface of the first groove; The number of the channel layers is multiple, the multiple channel layers are arranged along the second direction, and the multiple channel layers are separated by multiple first grooves, the multiple first grooves are arranged and distributed along the second direction; The storage structure further includes: a third dielectric layer, the third dielectric layer covering the channel layer and the first dielectric layer, the third dielectric layer and the first dielectric layer having a second groove extending in a second direction, the second groove exposing the channel layer; The storage structure further includes a word line layer extending along a second direction, the word line layer being located within the second recess.

2. The semiconductor device according to claim 1, characterized in that, The first dielectric layer includes a first dielectric sublayer, an etch barrier layer, and a second dielectric sublayer disposed from bottom to top. The first groove penetrates the second dielectric sublayer and exposes the etch barrier layer.

3. The semiconductor device according to claim 1, characterized in that, The capacitor structure includes: The first electrode covers the sidewall and bottom surface of the first groove; A second dielectric layer covers the first electrode; The second electrode covers the second dielectric layer.

4. The semiconductor device according to claim 1, characterized in that, The storage structure further includes: a fourth dielectric layer, which covers the surface of the channel layer exposed by the second groove, and covers the sidewalls and bottom surface of the second groove, the third dielectric layer, and the capacitor structure.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a bit line layer that extends from the topmost memory structure to the bottommost memory structure and is connected to the channel layers in the plurality of memory structures.

6. The semiconductor device according to claim 5, characterized in that, In a first direction, a single channel layer is separated by a plurality of first grooves, two word line layers are disposed between two adjacent first grooves, and a bit line layer is disposed between the two word line layers.

7. The semiconductor device according to claim 1, characterized in that, The channel layer material includes one or more of indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, and tin aluminum zinc oxide.

8. A method for manufacturing a semiconductor device, characterized in that, include: Provide substrate; Forming a storage structure on the substrate includes: forming a first dielectric layer; forming a channel layer extending in a first direction within the first dielectric layer; forming a first groove within the first dielectric layer that separates the channel layer; and forming a capacitor structure that covers the sidewalls and bottom surface of the first groove. One or more of the storage structures are then stacked on top of the existing storage structure. The first dielectric layer includes a first dielectric sublayer, an etch barrier layer, and a second dielectric sublayer; Forming the first dielectric layer includes: forming the first dielectric sublayer; forming the etch barrier layer on the first dielectric sublayer; and forming the second dielectric sublayer on the etch barrier layer. The number of channel layers is multiple, and the multiple channel layers are arranged along the second direction; the channel layers are formed within the first dielectric layer, including: The second dielectric sublayer is etched to form a plurality of first trenches extending along a first direction within the second dielectric sublayer, and the plurality of first trenches are arranged along a second direction; The channel layer is formed within the first trench; The plurality of channel layers are separated by a plurality of first grooves, and the plurality of first grooves are arranged along a second direction; forming the first grooves that separate the channel layers within the first dielectric layer includes: etching the channel layers and the second dielectric sublayer from top to bottom until the etching barrier layer is exposed to form the first grooves; The storage structure further includes a third dielectric layer and a second groove extending along a second direction; after forming the capacitor structure, the method further includes: The third dielectric layer is formed on the channel layer and the first dielectric layer; A portion of the first dielectric layer and a portion of the third dielectric layer are removed, and a second groove is formed within the first dielectric layer and the third dielectric layer, the second groove exposing the channel layer; The storage structure further includes a word line layer extending along a second direction; after forming the second recess, the method further includes: The letter line layer is formed within the second groove.

9. The manufacturing method according to claim 8, characterized in that, The capacitor structure includes a first electrode, a second dielectric layer, and a second electrode; forming the capacitor structure includes: The first electrode is formed in the first groove, and the first electrode covers the sidewall and bottom surface of the first groove; A second dielectric material layer is formed on the first dielectric layer, the channel layer, and the first electrode, and a second electrode material layer is formed on the second dielectric material layer; A portion of the second electrode material layer and a portion of the second dielectric material layer are removed to form the second electrode and the second dielectric layer, respectively, with the second electrode and the second dielectric layer covering the first electrode.

10. The manufacturing method according to claim 8, characterized in that, The storage structure further includes a fourth dielectric layer; before forming the word line layer within the second recess, the method further includes: The fourth dielectric layer is formed, which covers the surface of the channel layer exposed by the second groove, and covers the sidewalls and bottom surface of the second groove, the third dielectric layer, and the capacitor structure.

11. The manufacturing method according to claim 10, characterized in that, After stacking one or more of the storage structures on the existing storage structure, the method further includes: Multiple memory structures are etched from top to bottom to form a second trench. The second trench extends from the topmost memory structure to the bottommost memory structure and penetrates the channel layer in the multiple memory structures. A bitline layer is formed within the second trench.

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