Process for manufacturing silicon polishing pieces for 7nm and below node wet etch process particle monitoring applications

Abstract

This invention relates to a processing technology for silicon polished wafers used for particle monitoring in WET (Waste Metal Overlay) processes at 7nm and below nodes, belonging to the field of semiconductor silicon polished wafer processing technology. The process includes the following steps: Step 1: Predicting linear raised defects formed during the polishing and repeated cleaning processes. Step 2: After CMP polishing and cleaning, the silicon wafer undergoes short-term annealing in a high-temperature argon atmosphere, followed by repeated cleaning 20 times, with SP7 (Special Stress Level) measured every 5 cleaning cycles. Step 3: After CMP polishing and cleaning, the silicon wafer undergoes 20 repeated cleaning cycles directly, with SP7 measured every 5 cleaning cycles. Step 4: Comparing the changes in LLS (Limited Latitude Strain) in the experimental and reference processes. Step 5: Rapid annealing is effective in eliminating micro-stress caused by polishing. Step 6: The silicon wafer after the experimental process is inspected for particle size, micro-roughness, and bulk metal content. No significant increase in 19nm LLS was observed before and after annealing. This process allows the wafer to withstand multiple re-washes in the WET process at the chip level without significant particle-level degradation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor silicon polishing wafer processing technology, specifically to a processing technology for silicon polishing wafers used for particle monitoring in WET process at 7nm and below nodes. Background Technology

[0002] In chip manufacturing processes, silicon polished wafers are typically used as particle monitoring wafers to monitor particulate contamination in areas such as cleaning tanks, furnace chambers, and transfer machines. The change in particle size before and after the process is compared, and these monitoring wafers are usually reused repeatedly. As chip manufacturing processes advance to 7nm, 5nm, and 3nm nodes, previously undetected issues are being discovered due to improved detection capabilities.

[0003] The requirements for particle monitoring sheets are: after 20 repeated cleaning cycles, the number of 19nm particles / defects should be less than 100. Before SP7 (KLA-Tencor Corporation) was introduced to China, such requirements could not be met in terms of detection capabilities. Traditional particle detection equipment is based on the photomultiplier principle, referencing US7110106 B2.

[0004] Both particles / defects and the silicon wafer background generate scattered light. A photomultiplier receives the scattered light and generates a voltage signal, which is then converted into particle / defect size based on a standard curve. However, repeated cleaning roughens the silicon wafer surface, causing the signal scattered from the wafer background to mask the signal generated by small particles, resulting in significant noise and making it impossible to determine the actual number of particles / defects.

[0005] The SP7 employs Time Delay Integration (US8772731 B2, CN107110792 B) technology to capture particles / defects (particles and defects are collectively referred to as LLS, Local Laser Scattering) on ​​high-speed rotating surfaces. This is fundamentally different from the SP1 / 2 / 3 / 5 (KLA-Tencor Corporation) series products based on the photomultiplier principle, resulting in a significantly improved signal-to-noise ratio. This makes it possible to detect small particles / defects on rough surfaces. It is precisely because of this improved detection capability that we discovered a new phenomenon: after repeated cleaning, polished silicon wafers exhibited a significant increase in linear bulge defects.

[0006] This type of defect, characterized by linear raised microstructures, is commonly observed after polishing (without repeated cleaning steps) and is generally referred to as a PID (Polishing-Induced Defect). Shin-Etsu's patent (US8569148 B2) explains the formation mechanism of PID, primarily stating that foreign matter in the polishing solution leads to the formation of amorphous silicon oxide on the silicon wafer surface, causing the polishing rate of the silicon oxide-covered area to be lower than that of the normal area, thus forming a raised defect. Other literature suggests that this raised defect is caused by trace amounts of metallic impurities in the polishing solution (US2019 / 0022821 A1). Although the linear raised defect we discovered is extremely similar in microstructure to the PID described in the literature, it does not appear directly after polishing but only after repeated cleaning, thus its formation mechanism differs from that of the commonly understood PID. Summary of the Invention

[0007] This invention addresses the shortcomings of existing technologies by providing a processing technology for silicon polished wafers used in WET process particle monitoring at 7nm and below nodes. The formation mechanism of linear raised defects after repeated cleaning was experimentally verified, and process improvements were made based on this, enabling the wafer to withstand multiple rewashes in the WET process at the chip level without significant particle-level deterioration.

[0008] The above-mentioned technical problems of the present invention are mainly solved by the following technical solutions:

[0009] A processing technology for silicon polished wafers used in WET process particle monitoring at 7nm and below nodes includes the following steps:

[0010] Step 1: The phenomenon of a significant increase in linear raised defects after repeated cleaning is presumably caused by residual stress on the subsurface of the silicon wafer due to mechanical friction during the polishing process. During repeated cleaning, the residual stress causes a difference in corrosion rate between stressed and unstressed areas, thus forming linear raised defects.

[0011] Step 2: After CMP polishing and cleaning, the silicon wafer is subjected to short-term annealing in a high-temperature argon atmosphere. Then, it is repeatedly cleaned 20 times, and SP7 is tested every 5 cleanings. The purpose of short-term annealing in a high-temperature argon atmosphere is to eliminate residual micro-stress caused by CMP polishing. This process is an experimental process.

[0012] Step 3: After CMP polishing and CMP cleaning, the silicon wafer is directly subjected to 20 repeated cleaning cycles. SP7 is tested every 5 cleaning cycles. This process is the reference process.

[0013] Step 4: Compare the changes in LLS in the experimental process and the reference process. In the reference process, the number of LLS in the unannealed silicon wafer gradually increased after repeated cleaning 5, 10, 15 and 20 times, and the increase was significant. In the experimental process, the 19nm LLS of the sample after rapid annealing remained constant after repeated cleaning.

[0014] Step 5: By comparing the experimental process with the reference process, it was confirmed that the increase in linear raised defects after repeated cleaning of polished silicon wafers was due to the different etching rates of the micro-stress area and the normal area during repeated cleaning. Rapid annealing is effective in eliminating the micro-stress caused by polishing.

[0015] Step 6: The silicon wafer after the experimental process was tested for particles, micro-roughness, and bulk metal content. There was no significant increase in 19 nm mL LS before and after annealing.

[0016] As a preferred option, the CMP conditions used in the experimental process and the reference process were completely identical. The silicon wafers were first subjected to rough polishing, using a polishing slurry with a pH value controlled at 11.0±0.2, a polishing cloth of Suba600, and a rough polishing time of 180s. After rough polishing, two fine polishing processes were performed under the same conditions, using a polishing cloth of FNHP-318S, a polishing slurry of NP8020, and a pH value of 10.0±0.2. After polishing, a post-CMP cleaning was performed to remove residual polishing slurry and other contaminants from the silicon wafer surface.

[0017] As a preferred option, the high-temperature argon atmosphere short-time annealing in the experimental process adopts a single-piece rapid annealing furnace with an argon flow rate of 15-40 L / min, a heating rate of 30-50℃ / s, a holding temperature of 600℃-900℃, a holding time of 15-60 s, and a cooling rate of 50℃ / s.

[0018] As a preferred method, repeated cleaning is performed using a single-plate cleaning machine, where ozone water and hydrofluoric acid are alternately sprayed from a nozzle above the center of the silicon wafer.

[0019] Preferably, the concentration of ozone water is 20 ppm and the mass concentration of hydrofluoric acid is 1%.

[0020] As a preferred method, the specific cleaning steps are: O3W cleaning for 20 seconds → HF cleaning for 15 seconds → O3W cleaning for 10 seconds → HF cleaning for 3 seconds → O3W cleaning for 10 seconds → HF cleaning for 3 seconds → O3W cleaning for 20 seconds → DIW cleaning for 10 seconds → Spin Dry cleaning for 20 seconds.

[0021] As a preferred method, the micro-roughness before and after annealing was tested using a KLA SP7 testing device. After rapid annealing, the micro-roughness of the silicon wafer increased slightly, which did not affect the quality of the silicon wafer. Cleaning also increases the micro-roughness of the silicon wafer.

[0022] Preferably, the bulk metal of the silicon wafer is tested using the VPD-ICPMS method. The VPD-ICPMS test of the bulk metal of the silicon wafer involves etching the surface of the silicon wafer with a mixture of ozone and hydrofluoric acid, then extracting the reaction products on the surface of the silicon wafer with a mixture of hydrofluoric acid and hydrogen peroxide, and then passing the mixture into the ICPMS for atomization and plasma treatment, followed by the detection of metal impurity elements using mass spectrometry.

[0023] As a preferred option, the silicon wafers extracted for the bulk metal comparison test used the exact same CMP polishing and post-cleaning process conditions. One group was not annealed, while the other group underwent rapid argon treatment at 700°C for 30 seconds. The etching depth on the surface of the silicon wafers for the bulk metal test was 0.4 μm. The bulk metal test results showed that the bulk metal level of the annealed sample did not deteriorate significantly compared to the unannealed sample.

[0024] The present invention can achieve the following effects:

[0025] This invention provides a processing technology for silicon polished wafers used for particle monitoring in WET process at 7nm and below nodes. The formation mechanism of linear raised defects after repeated cleaning was verified by experiments, and the process was improved based on this, so that it can withstand multiple re-washing in the WET process at the chip level without significant deterioration at the particle level. Detailed Implementation

[0026] The technical solution of the invention will be further described in detail below through examples.

[0027] Example 1: A processing technology for silicon polished wafers used for particle monitoring in WET process at 7nm and below nodes, comprising the following steps:

[0028] Step 1: The phenomenon of a significant increase in linear raised defects after repeated cleaning is presumably caused by residual stress on the subsurface of the silicon wafer due to mechanical friction during the polishing process. During repeated cleaning, the residual stress causes a difference in corrosion rate between stressed and unstressed areas, thus forming linear raised defects.

[0029] Step 2: After CMP polishing and cleaning, the silicon wafer undergoes short-time annealing in a high-temperature argon atmosphere. The experimental process uses a single-wafer rapid annealing furnace with an argon flow rate of 30 L / min, a heating rate of 50 °C / s, a holding temperature of 700 °C, a holding time of 30 s, and a cooling rate of 50 °C / s. The process is repeated 20 times, with SP7 measured every 5 cleaning cycles. The purpose of this short-time annealing in a high-temperature argon atmosphere is to eliminate residual micro-stress caused by CMP polishing. This process is the experimental procedure.

[0030] Step 3: After CMP polishing and CMP cleaning, the silicon wafer is directly subjected to 20 repeated cleaning cycles. SP7 is tested every 5 cleaning cycles. This process is the reference process.

[0031] The experimental process and the reference process used the same CMP conditions. The silicon wafers were first rough polished with a polishing slurry of the following type: pH value controlled at 11.0±0.2, polishing cloth of type Suba600, and a rough polishing time of 180s. After rough polishing, two fine polishing processes were performed under the same conditions: polishing cloth of type FNHP-318S, polishing slurry of type NP8020, and pH value of 10.0±0.2. After polishing, CMP post-cleaning was performed to remove residual polishing slurry and other contaminants from the silicon wafer surface.

[0032] Repeated cleaning is performed using a single-piece cleaning machine, where ozone water and hydrofluoric acid are alternately sprayed from a nozzle above the center of the silicon wafer. The concentration of ozone water is 20 ppm, and the mass concentration of hydrofluoric acid is 1%. The specific cleaning steps are: O3W cleaning 20s → HF cleaning 15s → O3W cleaning 10s → HF cleaning 3s → O3W cleaning 10s → HF cleaning 3s → O3W cleaning 20s → DIW cleaning 10s → Spin Dry cleaning 20s.

[0033] Step 4: Compare the changes in LLS in the experimental process and the reference process. In the reference process, the number of LLS in the unannealed silicon wafer gradually increased after repeated cleaning 5, 10, 15 and 20 times, and the increase was significant. In the experimental process, the 19nm LLS of the sample after rapid annealing remained constant after repeated cleaning.

[0034] Step 5: By comparing the experimental process with the reference process, it was confirmed that the increase in linear raised defects after repeated cleaning of polished silicon wafers was due to the different etching rates of the micro-stress area and the normal area during repeated cleaning. Rapid annealing is effective in eliminating the micro-stress caused by polishing.

[0035] Step 6: The silicon wafer after the experimental process was tested for particles, micro-roughness, and bulk metal content. There was no significant increase in 19 nm mL LS before and after annealing.

[0036] The micro-roughness before and after annealing was tested using a KLA SP7 testing device. After rapid annealing, the micro-roughness of the silicon wafer increased slightly, which did not affect the quality of the silicon wafer. Cleaning also increases the micro-roughness of the silicon wafer.

[0037] The bulk metal content of silicon wafers was tested using the VPD-ICPMS method. VPD-ICPMS testing involves etching the silicon wafer surface with a mixture of ozone and hydrofluoric acid, followed by extraction of the reaction products from the wafer surface using a mixture of hydrofluoric acid and hydrogen peroxide. This mixture is then atomized and plasma-ionized by ICPMS, and metal impurities are detected using mass spectrometry. For the bulk metal comparison test, the silicon wafers used were subjected to identical CMP polishing and post-cleaning conditions. One group underwent no annealing, while the other group underwent rapid argon treatment at 700°C for 30 seconds. The etching depth of the silicon wafer surface for bulk metal testing was 0.4 μm. The results showed that the annealed sample did not exhibit a significant deterioration in bulk metal content compared to the unannealed sample.

[0038] Example 2: A processing technology for silicon polished wafers used for particle monitoring in WET process at 7nm and below nodes, comprising the following steps:

[0039] Step 1: The phenomenon of a significant increase in linear raised defects after repeated cleaning is presumably caused by residual stress on the subsurface of the silicon wafer due to mechanical friction during the polishing process. During repeated cleaning, the residual stress causes a difference in corrosion rate between stressed and unstressed areas, thus forming linear raised defects.

[0040] Step 2: After CMP polishing and cleaning, the silicon wafer undergoes short-time annealing in a high-temperature argon atmosphere. The experimental process uses a single-wafer rapid annealing furnace with an argon flow rate of 20 L / min, a heating rate of 50 °C / s, a holding temperature of 800 °C, a holding time of 20 s, and a cooling rate of 50 °C / s. The process is repeated 20 times, with SP7 measured every 5 cleaning cycles. The purpose of this short-time annealing in a high-temperature argon atmosphere is to eliminate residual micro-stress caused by CMP polishing. This process is the experimental procedure.

[0041] Step 3: After CMP polishing and CMP cleaning, the silicon wafer is directly subjected to 20 repeated cleaning cycles. SP7 is tested every 5 cleaning cycles. This process is the reference process.

[0042] The experimental process and the reference process used the same CMP conditions. The silicon wafers were first rough polished with a polishing slurry of the following type: pH value controlled at 11.0±0.2, polishing cloth of type Suba600, and a rough polishing time of 180s. After rough polishing, two fine polishing processes were performed under the same conditions: polishing cloth of type FNHP-318S, polishing slurry of type NP8020, and pH value of 10.0±0.2. After polishing, CMP post-cleaning was performed to remove residual polishing slurry and other contaminants from the silicon wafer surface.

[0043] Repeated cleaning is performed using a single-piece cleaning machine, where ozone water and hydrofluoric acid are alternately sprayed from a nozzle above the center of the silicon wafer. The concentration of ozone water is 20 ppm, and the mass concentration of hydrofluoric acid is 1%. The specific cleaning steps are: O3W cleaning 20s → HF cleaning 15s → O3W cleaning 10s → HF cleaning 3s → O3W cleaning 10s → HF cleaning 3s → O3W cleaning 20s → DIW cleaning 10s → Spin Dry cleaning 20s.

[0044] Step 4: Compare the changes in LLS in the experimental process and the reference process. In the reference process, the number of LLS in the unannealed silicon wafer gradually increased after repeated cleaning 5, 10, 15 and 20 times, and the increase was significant. In the experimental process, the 19nm LLS of the sample after rapid annealing remained constant after repeated cleaning.

[0045] Step 5: By comparing the experimental process with the reference process, it was confirmed that the increase in linear raised defects after repeated cleaning of polished silicon wafers was due to the different etching rates of the micro-stress area and the normal area during repeated cleaning. Rapid annealing is effective in eliminating the micro-stress caused by polishing.

[0046] Step 6: The silicon wafer after the experimental process was tested for particles, micro-roughness, and bulk metal content. There was no significant increase in 19 nm mL LS before and after annealing.

[0047] The micro-roughness before and after annealing was tested using a KLA SP7 testing device. After rapid annealing, the micro-roughness of the silicon wafer increased slightly, but this did not affect the quality of the silicon wafer. Cleaning also increases the micro-roughness of the silicon wafer.

[0048] The bulk metal content of silicon wafers was tested using the VPD-ICPMS method. VPD-ICPMS testing involves etching the silicon wafer surface with a mixture of ozone and hydrofluoric acid, followed by extraction of the reaction products from the wafer surface using a mixture of hydrofluoric acid and hydrogen peroxide. This mixture is then atomized and plasma-ionized by ICPMS, and metal impurities are detected using mass spectrometry. For the bulk metal comparison test, the silicon wafers used were subjected to identical CMP polishing and post-cleaning conditions. One group underwent no annealing, while the other group underwent rapid argon treatment at 700°C for 30 seconds. The etching depth of the silicon wafer surface for bulk metal testing was 0.4 μm. The results showed that the annealed sample did not exhibit a significant deterioration in bulk metal content compared to the unannealed sample.

[0049] In summary, the processing technology for silicon polished wafers used for particle monitoring in the 7nm and below WET process has experimentally verified the formation mechanism of linear raised defects after repeated cleaning. Based on this, process improvements have been made to enable the wafers to withstand multiple rewashes in the WET process at the chip level without significant deterioration at the particle level.

[0050] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by those skilled in the art within the scope of the present invention are covered by the patent scope of the present invention.

Claims

1. A processing technology for silicon polished wafers used in WET process particle monitoring at 7nm and below nodes, characterized in that... The following steps are included: Step 1: Regarding the phenomenon of a significant increase in linear raised defects after repeated cleaning, it is speculated that this is due to the residual stress on the subsurface of the silicon wafer caused by mechanical friction during the polishing process. During repeated cleaning, the residual stress will cause a difference in corrosion rate between the stressed area and the stress-free area, thus forming linear raised defects. Step 2: After CMP polishing and cleaning, the silicon wafer is subjected to short-term annealing in a high-temperature argon atmosphere. Then, it is repeatedly cleaned 20 times. SP7 is tested every 5 cleaning cycles. The purpose of short-term annealing in a high-temperature argon atmosphere is to eliminate residual micro-stress caused by CMP polishing. This process is an experimental process. Step 3: After CMP polishing and CMP cleaning, the silicon wafer is directly subjected to 20 repeated cleaning cycles. SP7 is tested once every 5 cleaning cycles. This process is the reference process. Step 4: Compare the changes in LLS in the experimental process and the reference process. In the reference process, the number of LLS in the unannealed silicon wafer gradually increased after repeated cleaning 5, 10, 15 and 20 times, and the increase was significant. In the experimental process, the 19nm LLS of the sample after rapid annealing remained constant after repeated cleaning. Step 5: By comparing the experimental process and the reference process, it was confirmed that the increase in linear raised defects after repeated cleaning of polished silicon wafers was due to the different etching rates of the micro-stress area and the normal area during repeated cleaning. Rapid annealing is effective in eliminating micro-stress caused by polishing. Step 6: The silicon wafer after the experimental process was tested for particle size, micro-roughness, and bulk metal content. There was no significant increase in 19nm LLS before and after annealing.

2. The processing technology for silicon polished wafers used for particle monitoring in 7nm and below WET process according to claim 1, characterized in that: The experimental process and the reference process used the same CMP conditions. The silicon wafers were first rough polished with a polishing slurry of the following type: pH value controlled at 11.0±0.2, polishing cloth of type Suba600, and a rough polishing time of 180s. After rough polishing, two fine polishing processes were performed under the same conditions: polishing cloth of type FNHP-318S, polishing slurry of type NP8020, and pH value of 10.0±0.

2. After polishing, CMP post-cleaning was performed to remove residual polishing slurry and other contaminants from the silicon wafer surface.

3. The processing technology for silicon polished wafers used for particle monitoring in 7nm and below WET process according to claim 1, characterized in that: The high-temperature argon atmosphere short-time annealing in the experimental process was carried out using a single-piece rapid annealing furnace with an argon flow rate of 15-40 L / min, a heating rate of 30-50 °C / s, a holding temperature of 600 °C-900 °C, a holding time of 15-60 s, and a cooling rate of 50 °C / s.

4. The processing technology for silicon polished wafers used for particle monitoring in 7nm and below WET process according to claim 1, characterized in that: Repeated cleaning is performed using a single-plate cleaning machine, where ozone water and hydrofluoric acid are alternately sprayed from a nozzle above the center of the silicon wafer.

5. The processing technology for silicon polished wafers used for particle monitoring in 7nm and below WET process according to claim 4, characterized in that: The concentration of ozone water is 20 ppm, and the mass concentration of hydrofluoric acid is 1%.

6. The processing technology for silicon polished wafers used for particle monitoring in 7nm and below WET process according to claim 4, characterized in that: The specific cleaning steps are: O3W cleaning for 20 seconds → HF cleaning for 15 seconds → O3W cleaning for 10 seconds → HF cleaning for 3 seconds → O3W cleaning for 10 seconds → HF cleaning for 3 seconds → O3W cleaning for 20 seconds → DIW cleaning for 10 seconds → Spin Dry cleaning for 20 seconds.

7. The processing technology for silicon polished wafers used for particle monitoring in 7nm and below WET process according to claim 1, characterized in that: The micro-roughness before and after annealing was tested using a KLA SP7 testing device. After rapid annealing, the micro-roughness of the silicon wafer increased slightly, but this did not affect the quality of the silicon wafer. Cleaning also increases the micro-roughness of the silicon wafer.

8. The processing technology for silicon polished wafers used for particle monitoring in 7nm and below WET process according to claim 1, characterized in that: The bulk metal of the silicon wafer was tested using the VPD-ICPMS method. The VPD-ICPMS test of the bulk metal of the silicon wafer involves etching the surface of the silicon wafer with a mixture of ozone and hydrofluoric acid, then extracting the reaction products on the surface of the silicon wafer with a mixture of hydrofluoric acid and hydrogen peroxide, and then passing the mixture into the ICPMS for atomization and plasma treatment, and finally using mass spectrometry to detect the metal impurity elements.

9. The processing technology for silicon polished wafers used for particle monitoring in 7nm and below WET process according to claim 8, characterized in that: The silicon wafers extracted for the bulk metal comparison test were subjected to the same CMP polishing and post-cleaning process conditions. One group was not annealed, while the other group underwent rapid argon treatment at 700℃ for 30s. The etching depth on the surface of the silicon wafers for the bulk metal test was 0.4μm. The bulk metal test results showed that the bulk metal level of the annealed sample did not deteriorate significantly compared to the unannealed sample.