A dynamic adjustment circuit for core voltage in a chip and electronic equipment

Abstract

This invention discloses a dynamic adjustment circuit and electronic device for chip core voltage. The dynamic adjustment circuit includes a DC-DC converter, a low-dropout linear regulator, a voltage switching unit, and a processor unit. The input terminal of the DC-DC converter is connected to the system power supply terminal, its first output terminal is connected to the first input terminal of the voltage switching unit, and its second output terminal is connected to the input terminal of the low-dropout linear regulator. The output terminal of the low-dropout linear regulator is connected to the second input terminal of the voltage switching unit. The output terminal of the voltage switching unit is connected to the core voltage input terminal of the processor unit. The first control signal output terminal of the processor unit is connected to the control signal terminal of the voltage switching unit. This dynamic adjustment circuit can dynamically adjust the supply voltage value of the CPU core voltage according to the actual operating state of the CPU, thereby reducing chip power consumption.

Description

Technical Field

[0001] This invention relates to a dynamic adjustment circuit for chip core voltage, and also to electronic devices including the dynamic adjustment circuit, belonging to the field of chip power supply technology. Background Technology

[0002] With the rapid development of semiconductor manufacturing processes, chips are becoming increasingly integrated, larger in scale, and operate at higher frequencies, leading to a continuous increase in power consumption and a series of problems and drawbacks. These include reduced heat dissipation and circuit performance due to increased chip temperature, as well as issues with power supply and signal noise management. Excessive power consumption can significantly degrade the overall performance of a chip, making it unable to meet practical application requirements, and in severe cases, even causing irreversible device damage.

[0003] In existing technologies, the core voltage of a chip is usually powered by a power supply module, and the supply voltage is a fixed voltage value. For example, a DC-DC converter is used to output a 0.9V voltage to provide the core voltage for the chip's CPU. When the chip is idle for certain periods of time and the CPU resource allocation is low, the fixed core voltage will still cause the chip to have a high power consumption problem.

[0004] Chinese utility model patent ZL 201620392772.9 discloses a numerically controlled dynamic voltage regulating device, including a main control module and a voltage converter. The voltage converter outputs DC voltage to power the main control module. The main control module includes a processor unit, a monitoring unit, and an I2C bus controller. The monitoring unit monitors the operating status of the processor unit and outputs corresponding control signals to the I2C bus controller when the operating status changes. The I2C bus controller converts the control signals into I2C numerical control signals and outputs them to the voltage converter. The voltage converter dynamically adjusts the DC voltage output to the processor unit according to the I2C numerical control signals. Summary of the Invention

[0005] The primary technical problem to be solved by this invention is to provide a dynamic adjustment circuit for chip core voltage.

[0006] Another technical problem to be solved by the present invention is to provide an electronic device including the dynamic adjustment circuit.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] According to a first aspect of the present invention, a dynamic adjustment circuit for chip core voltage is provided, comprising a DC-DC converter, a low-dropout linear regulator, a voltage switching unit, and a processor unit; wherein,

[0009] The DC-DC converter is used to generate a first voltage. Its input terminal is connected to the system power supply terminal, its first output terminal is connected to the first input terminal of the voltage switching unit, and its second output terminal is connected to the input terminal of the low dropout linear regulator.

[0010] The low-dropout linear regulator is used to generate a second voltage, and its output terminal is connected to the second input terminal of the voltage switching unit.

[0011] The first control signal output terminal of the processor unit is connected to the control signal terminal of the voltage switching unit.

[0012] The voltage switching unit is used to switch the switch state according to the first control signal and output a first voltage or a second voltage to the processor unit. Its output terminal is connected to the core voltage input terminal of the processor unit.

[0013] Preferably, the voltage value of the first voltage is equal to the rated core voltage value of the processor unit; the voltage value of the second voltage is less than the voltage value of the first voltage.

[0014] Preferably, the first control signal output by the processor unit is configured by the CPU to be a high-level signal or a low-level signal according to the operating state.

[0015] Preferably, the voltage switching unit comprises a first transistor, a second transistor, a third transistor, a first NMOS transistor, and a second NMOS transistor, as well as a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor, and a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor.

[0016] Preferably, in the voltage switching unit, the first control signal terminal of the processor unit is connected to the first power supply terminal via a sixth resistor, connected to the base of the second transistor via a parallel branch composed of the first resistor and the first capacitor, and connected to the base of the first transistor via a parallel branch composed of a third resistor and the third capacitor. The emitter of the second transistor is connected to ground, and the collector of the second transistor is connected to the second power supply terminal via a seventh resistor and connected to the gate of the first NMOS transistor via a parallel branch composed of a second resistor and the second capacitor. The source of the first NMOS transistor is connected to the core voltage input terminal of the processor unit, and the drain of the first NMOS transistor is connected to the core voltage input terminal of the processor unit. The output terminal of the low-dropout linear regulator is connected as follows: the emitter of the first transistor is connected to the first power supply terminal through the eighth resistor; the collector of the first transistor is connected to the ground potential terminal through the tenth resistor, and is connected to the base of the third transistor through a parallel branch composed of the fourth resistor and the fourth capacitor; the emitter of the third transistor is connected to the ground potential; the collector of the third transistor is connected to the second power supply terminal through the ninth resistor, and is connected to the gate of the second NMOS transistor through a parallel branch composed of the fifth resistor and the fifth capacitor; the source of the second NMOS transistor is connected to the core voltage input terminal of the processor unit; and the drain of the second NMOS transistor is connected to the first output terminal of the DC-DC converter.

[0017] Preferably, when the system is powered on or the processor unit is in normal working condition, the first control signal is a high-level signal, which controls the voltage switching unit to turn off the second voltage output path and turn on the first voltage output path to provide core voltage to the processor unit.

[0018] Preferably, when the processor unit is in standby or idle working state, the first control signal is a low-level signal, which controls the voltage switching unit to turn off the first voltage output path and turn on the second voltage output path to provide core voltage to the processor unit.

[0019] According to a second aspect of the present invention, an electronic device is provided, which includes the aforementioned dynamic adjustment circuit for the chip core voltage.

[0020] Compared with existing technologies, the dynamic adjustment circuit for chip core voltage provided by this invention uses a first control signal to control the switching state of the voltage switching unit. This allows the CPU core voltage of the processor unit to be powered by a first voltage during normal operation and by a second voltage during standby or idle operation. This enables the CPU to dynamically adjust its core voltage supply value according to the actual operating state, thereby reducing chip power consumption. Therefore, the dynamic adjustment circuit for chip core voltage provided by this invention has advantages such as simple structure, low cost, and low power consumption, and is suitable for processor units or CPU chips in various applications. Attached Figure Description

[0021] Figure 1 The structural block diagram of the chip core voltage dynamic adjustment circuit provided by the present invention;

[0022] Figure 2 This is a pinout diagram of a low-dropout linear regulator chip in an embodiment of the present invention;

[0023] Figure 3 This is a circuit diagram of the voltage switching unit in an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of an electronic device employing the chip core voltage dynamic adjustment circuit provided by the present invention. Detailed Implementation

[0025] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0026] like Figure 1 As shown, the dynamic adjustment circuit for the chip core voltage provided by this invention includes a DC-DC converter, a low-dropout linear regulator (LDO), a voltage switching unit (Switch Circuit), and a processor unit (CPU). The input terminal of the DC-DC converter is connected to the system power supply terminal, its first output terminal is connected to the first input terminal of the voltage switching unit, and its second output terminal is connected to the input terminal of the LDO. The output terminal of the LDO is connected to the second input terminal of the voltage switching unit. The output terminal of the voltage switching unit is connected to the core voltage input terminal of the processor unit. The first control signal output terminal of the processor unit is connected to the control signal terminal of the voltage switching unit.

[0027] The DC-DC converter converts the system power supply voltage into a first voltage V1, which is then output to a low-dropout linear regulator and a voltage switching unit. This first voltage V1 is the rated core voltage of the CPU in the processor unit, providing the core voltage to the processor unit under normal operating conditions. The DC-DC converter is typically a buck converter, with an adjustable output voltage to meet the rated core voltage requirements of processor units in different applications.

[0028] A low-dropout linear regulator converts the first voltage V1 into a second voltage V2 and outputs it to the voltage switching unit. The second voltage V2 is less than the first voltage V1, and it provides the core voltage to the processor unit in standby or idle states. The value of the second voltage V2 is determined based on factors such as the CPU's operating frequency in standby or idle states and peripheral conditions.

[0029] The voltage switching unit is used to switch the input first voltage V1 and the second voltage V2 according to the first control signal provided by the processor unit, and then output one of the voltages to provide core voltage power supply for the processor unit.

[0030] The processor unit can be a CPU chip of various application models, such as the MH1905 CPU chip. The output terminal GPIO of the first control signal Vc is a general-purpose I / O port, and the core voltage input terminal is the V_core port.

[0031] In one embodiment of the present invention, such as Figure 2 As shown, the low dropout linear regulator uses an RT9085AWSC LDO chip. Its input pin VIN is connected to the second output of the DC-DC converter, providing the first input voltage V1 to the LDO. Its output pin VOUT is connected to the second input of the voltage switching unit, outputting a second voltage V2 to the voltage switching unit. The output voltage of the LDO can be adjusted by changing the values ​​of resistors R1 and R2 according to the set value of the second voltage V2. Pins EN and BIAS are connected to the bias voltage V_COM, which is typically 3.3V or 5V.

[0032] In one embodiment of the present invention, such as Figure 3As shown, the voltage switching unit consists of a first PNP transistor, a second NPN1 transistor, a third NPN2 transistor, a first NMOS transistor NMOS1 and a second NMOS transistor NMOS2, and resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, and R10, as well as capacitors C1, C2, C3, C4, and C5. The processor unit's first control signal terminal GPIO is connected to the first power supply V_IO terminal via the sixth resistor R6, connected to the base of the second NPN1 via a parallel branch consisting of the first resistor R1 and the first capacitor C1, and connected to the base of the first PNP transistor via a parallel branch consisting of the third resistor R3 and the third capacitor C3. The emitter of the second transistor NPN1 is connected to ground. The collector of the second transistor NPN1 is connected to the second power supply (3.3V) through the seventh resistor R7, and to the gate of the first NMOS transistor NMOS1 through the parallel branch formed by the second resistor R2 and the second capacitor C2. The source of the first NMOS transistor NMOS1 is connected to the core voltage input terminal V_core of the processor unit. The drain of the first NMOS transistor NMOS1 is connected to the output terminal of the low dropout linear regulator. The emitter of the first PNP transistor is connected to the first power supply V_IO terminal through the eighth resistor R8. The collector of the first PNP transistor is connected to the ground potential terminal through the tenth resistor R10, and is connected to the base of the third NPN2 transistor through the parallel branch composed of the fourth resistor R4 and the fourth capacitor C4. The emitter of the third NPN2 transistor is connected to the ground potential. The collector of the third NPN2 transistor is connected to the second power supply (3.3V) terminal through the ninth resistor R9, and is connected to the gate of the second NMOS transistor NMOS2 through the parallel branch composed of the fifth resistor R5 and the fifth capacitor C5. The source of the second NMOS transistor NMOS2 transistor is connected to the core voltage input terminal V_core of the processor unit. The drain of the second NMOS transistor NMOS2 transistor is connected to the first output terminal of the DC-DC converter.

[0033] The voltage value of the first power supply V_IO is the same as the voltage value supported by the I / O port of the CPU chip. For example, when the I / O terminal voltage of the CPU chip is 1.8V or 3.3V, the voltage value of the first power supply V_IO is also 1.8V or 3.3V respectively.

[0034] The composition and structure of the dynamic adjustment circuit for the chip core voltage provided in this embodiment have been described in detail above. The working principle and working process of the dynamic adjustment circuit will be described in detail below.

[0035] In the dynamic adjustment circuit provided in this embodiment, the first control signal Vc output by the processor unit is a control signal configured by the CPU to be high or low level according to the chip's operating state.

[0036] When the system is powered on, the first control signal Vc is high by default, such as Figure 3 As shown, the first control signal output terminal GPIO is in a pull-up state. At this time, the base of the second transistor NPN1, i.e. node 1, is at a high level. After the second transistor NPN1 is turned on, its collector, i.e. node 2, is at a low level. The gate of the first NMOS transistor NMOS1, i.e. node 3, is also at a low level, which makes the first NMOS transistor NMOS1 turn off and shut down the path. That is, at this time, the second voltage V2 output by the low dropout linear regulator cannot provide core voltage power supply for the processor unit. Meanwhile, since the first control signal output terminal GPIO is in a pull-up state, the base of the first transistor PNP, i.e. node 4, is at a high level. After the first transistor PNP is turned off, its collector, i.e. node 5, is at a low level. The base of the third transistor NPN2, i.e. node 6, is also at a low level, causing the third transistor NPN2 to be turned off. Its collector, i.e. node 7, is at a high level, and the gate of the second NMOS transistor NMOS2, i.e. node 8, is also at a high level, causing the second NMOS transistor NMOS2 to be turned on, thus connecting the path. At this time, the first voltage V1 output by the DC-DC converter provides core voltage power to the processor unit, and the CPU is in normal working state.

[0037] When the CPU of the processor unit is in standby or idle working state, the first control signal Vc is low and the first control signal output terminal GPIO is pulled low. At this time, the base of the second transistor NPN1, i.e. node 1, is low. After the second transistor NPN1 is turned off, its collector, i.e. node 2, is high. The gate of the first NMOS transistor NMOS1, i.e. node 3, is also high, which makes the first NMOS transistor NMOS1 conduct and connects the path. That is, at this time, the second voltage V2 output by the low dropout linear regulator provides core voltage power supply for the processor unit. Simultaneously, since the first control signal output terminal GPIO is pulled low, the base of the first PNP transistor (node ​​4) is at a low level. After the first PNP transistor is turned on, its collector (node ​​5) is at a high level, and the base of the third NPN2 transistor (node ​​6) is also at a high level, causing the third NPN2 transistor to turn on. Its collector (node ​​7) becomes low, and the gate of the second NMOS transistor (node ​​8) is also at a low level, causing the second NMOS transistor (node ​​8) to turn off, thus shutting down the path. In other words, at this time, the first voltage V1 output by the DC-DC converter cannot provide core voltage power to the processor unit. That is, when the CPU of the processor unit is in standby or idle working state, its core voltage is powered by the lower voltage V2, which can reduce the power consumption of the CPU chip.

[0038] When the CPU of the processor unit recovers from standby or idle working state to normal working state, the first control signal Vc output by the CPU is high, and the GPIO of the first control signal output terminal is in a pull-up state. At this time, node 1 is high, and after the second transistor NPN1 is turned on, node 2 is low, and node 3 is also low, causing the first NMOS transistor NMOS1 to be turned off, thus shutting off this path. That is, at this time, the second voltage V2 output by the low dropout linear regulator cannot provide core voltage power supply to the processor unit. At the same time, since the first control signal output terminal GPIO is in a pull-up state, node 4 is high, and after the first transistor PNP is turned off, node 5 is low, and node 6 is also low, causing the third transistor NPN2 to be turned off. Node 7 is high, and node 8 is also high, causing the second NMOS transistor NMOS2 to be turned on, thus connecting this path. That is, at this time, the first voltage V1 output by the DC-DC converter provides core voltage power supply to the processor unit, and the CPU is in normal working state.

[0039] As can be seen from the above analysis of the working process, the dynamic adjustment circuit provided in this embodiment dynamically adjusts the power supply voltage of the CPU chip's core voltage according to the actual working state of the CPU chip, thereby reducing the power consumption of the CPU chip.

[0040] This invention also provides an electronic device, including the aforementioned dynamic adjustment circuit for the chip core voltage. This dynamic adjustment circuit serves as a power supply component, used to provide core voltage power to the CPU chip in the electronic device. Figure 4 As shown, this electronic device includes at least a processor, a memory, and a power supply component. It may further include communication components, sensor components, multimedia components, and input / output interfaces, depending on actual needs. The memory, communication components, sensor components, power supply component, multimedia components, and input / output interfaces are all connected to the processor. The memory can be static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, etc. The processor can be a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processing (DSP) chip, etc. Other communication components, sensor components, multimedia components, etc., can be implemented using general-purpose components and will not be specifically described here.

[0041] In summary, compared with existing technologies, the dynamic adjustment circuit for chip core voltage provided by this invention uses a first control signal to control the switching state of the voltage switching unit. This allows the CPU core voltage of the processor unit to be powered by a first voltage during normal operation and by a second voltage during standby or idle operation. This enables the CPU to dynamically adjust its core voltage supply value according to the actual operating state, thereby reducing chip power consumption. Therefore, the dynamic adjustment circuit for chip core voltage provided by this invention has advantages such as simple structure, low cost, and low power consumption, and is suitable for processor units or CPU chips in various applications.

[0042] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0043] The above provides a detailed description of the dynamic adjustment circuit and electronic device for the chip core voltage provided by this invention. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. A dynamic adjustment circuit for chip core voltage, characterized in that... It includes a DC-DC converter, a low-dropout linear regulator, a voltage switching unit, and a processor unit; among which, The DC-DC converter is used to generate a first voltage. Its input terminal is connected to the system power supply terminal, its first output terminal is connected to the first input terminal of the voltage switching unit, and its second output terminal is connected to the input terminal of the low dropout linear regulator. The low-dropout linear regulator is used to generate a second voltage, and its output terminal is connected to the second input terminal of the voltage switching unit. The first control signal output terminal of the processor unit is connected to the control signal terminal of the voltage switching unit; The voltage switching unit is used to switch the switch state according to the first control signal and output a first voltage or a second voltage to the processor unit. Its output terminal is connected to the core voltage input terminal of the processor unit. The voltage switching unit consists of a first transistor, a second transistor, a third transistor, a first NMOS transistor, and a second NMOS transistor; a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor; and a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor. The first control signal terminal of the processor unit is firstly connected to the first power supply terminal through the sixth resistor; secondly, it is connected to the base of the second transistor through a parallel branch composed of the first resistor and the first capacitor; and thirdly, it is connected to the base of the first transistor through a parallel branch composed of the third resistor and the third capacitor. The emitter of the second transistor is connected to ground potential, and the collector of the second transistor is connected to... The first transistor is connected to the second power supply terminal via the seventh resistor, and to the gate of the first NMOS transistor via a parallel branch consisting of the second resistor and the second capacitor. The source of the first NMOS transistor is connected to the core voltage input terminal of the processor unit, and the drain of the first NMOS transistor is connected to the output terminal of the low dropout linear regulator. The emitter of the first transistor is connected to the first power supply terminal via the eighth resistor. The collector of the first transistor is connected to the ground potential terminal via the tenth resistor, and to the base of the third transistor via a parallel branch consisting of the fourth resistor and the fourth capacitor. The emitter of the third transistor is connected to the ground potential. The collector of the third transistor is connected to the second power supply terminal via the ninth resistor, and to the gate of the second NMOS transistor via a parallel branch consisting of the fifth resistor and the fifth capacitor. The source of the second NMOS transistor is connected to the core voltage input terminal of the processor unit, and the drain of the second NMOS transistor is connected to the first output terminal of the DC-DC converter.

2. The dynamic adjustment circuit for the chip core voltage as described in claim 1, characterized in that: The voltage value of the first voltage is equal to the rated core voltage value of the processor unit; the voltage value of the second voltage is less than the voltage value of the first voltage.

3. The dynamic adjustment circuit for the chip core voltage as described in claim 1, characterized in that: The first control signal output by the processor unit is configured by the CPU to be a high-level signal or a low-level signal according to the operating state.

4. The dynamic adjustment circuit for the chip core voltage as described in claim 1, characterized in that: When the system is powered on or the processor unit is in normal working condition, the first control signal is a high-level signal, which controls the voltage switching unit to turn off the second voltage output path and turn on the first voltage output path to provide core voltage to the processor unit.

5. The dynamic adjustment circuit for the chip core voltage as described in claim 1, characterized in that: When the processor unit is in standby or idle working state, the first control signal is a low level signal, which controls the voltage switching unit to turn off the first voltage output path and turn on the second voltage output path to provide core voltage to the processor unit.

6. An electronic device, characterized in that... Includes the dynamic adjustment circuit for the chip core voltage as described in any one of claims 1 to 5.

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