Method for calculating polynomials and related device

Abstract

The application discloses a polynomial calculation method and related equipment, and the method comprises the following steps: constructing a target quantum circuit for calculating the polynomial based on a phase estimation quantum circuit; assigning values to independent variables of each term in the polynomial, and preparing an initial state of a first quantum bit of the target quantum circuit based on the assigned independent variables; and running the target quantum circuit to obtain an output final state, wherein the final state is used for representing a calculation result of the polynomial. Through the technical scheme, quantum calculation of the polynomial can be realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of quantum computing, and particularly relates to a polynomial calculation method and related equipment. BACKGROUND

[0002] In the fields of finance, engineering and scientific research, various polynomials are often used to model and study target objects. For example, for portfolio optimization problems, scheduling optimization problems and related problems of machine learning, the core is the Quadratic Unconstrained Binary Optimization Problem (QUBO), that is, the optimization of a quadratic polynomial with input binary. To achieve optimization, the calculation of the polynomial needs to be completed.

[0003] In related technologies, the QUBO problem can be optimized using quantum computing. The optimization process needs to be based on the quantum computing result of the polynomial, so it is essential to calculate the polynomial based on quantum computing. SUMMARY

[0004] The purpose of the present application is to provide a polynomial calculation method and related equipment, which aims to calculate the polynomial based on quantum computing.

[0005] To achieve the above purpose, the first aspect of the embodiments of the present application provides a polynomial calculation method, which comprises:

[0006] constructing a target quantum circuit for calculating the polynomial based on a phase estimation quantum circuit;

[0007] assigning values to the independent variables of each term in the polynomial, and preparing an initial state of a first quantum bit of the target quantum circuit based on the assigned independent variables;

[0008] running the target quantum circuit to obtain an output final state, which is used to represent the calculation result of the polynomial.

[0009] Optionally, the target quantum circuit for calculating the polynomial is constructed based on a phase estimation quantum circuit, which comprises:

[0010] constructing a controlled quantum logic gate for calculating each term in the polynomial based on a target quantum logic gate in the phase estimation quantum circuit;

[0011] applying the controlled quantum logic gate to the first quantum bit to obtain a target quantum circuit for calculating the polynomial.

[0012] Optionally, the target quantum logic gate in the phase estimation quantum circuit is used to construct a controlled quantum logic gate for calculating each term in the polynomial, including:

[0013] determining the target quantum logic gate in the phase estimation quantum circuit for calculating the corresponding coefficient of each term in the polynomial;

[0014] using the first quantum bit as the control bit of the target quantum logic gate to obtain a controlled quantum logic gate for calculating each term in the polynomial.

[0015] Optionally, the target quantum circuit further includes a second quantum bit and a third quantum bit, and before the running of the target quantum circuit obtains the final state of the output, the method further includes:

[0016] preparing the second quantum bit to an equal-amplitude superposition state, and preparing the third quantum bit to an eigenstate of the target quantum logic gate.

[0017] Optionally, the target quantum logic gate is a controlled RY gate or a controlled RX gate.

[0018] Optionally, the target quantum circuit further includes a fourth quantum bit, and before the running of the target quantum circuit obtains the final state of the output, the method further includes:

[0019] preparing the fourth quantum bit to an equal-amplitude superposition state.

[0020] Optionally, the target quantum logic gate is an RZ gate or a U1 gate.

[0021] In a second aspect of the embodiment of the present application, a device for calculating a polynomial is provided, and the device includes:

[0022] a calculation module configured to construct a target quantum circuit for calculating the polynomial based on a phase estimation quantum circuit;

[0023] an assignment preparation module configured to assign values to independent variables of each term in the polynomial, and prepare an initial state of a first quantum bit of the target quantum circuit based on the assigned independent variables;

[0024] a running module configured to run the target quantum circuit to obtain a final state of an output, and the final state is used to represent a calculation result of the polynomial.

[0025] Optionally, the calculation module is further configured to:

[0026] construct a controlled quantum logic gate for calculating each term in the polynomial based on a target quantum logic gate in the phase estimation quantum circuit;

[0027] The controlled quantum logic gate is applied to the first quantum bit to obtain a target quantum circuit for calculating the polynomial.

[0028] Optionally, the computing module is further configured to:

[0029] determine a target quantum logic gate in the phase estimation quantum circuit for calculating a corresponding coefficient of each term in the polynomial;

[0030] take the first quantum bit as a control bit of the target quantum logic gate to obtain a controlled quantum logic gate for calculating each term in the polynomial.

[0031] Optionally, the target quantum circuit further comprises a second quantum bit and a third quantum bit, and the apparatus further comprises:

[0032] a first preparation module configured to prepare the second quantum bit to an equal-amplitude superposition state and prepare the third quantum bit to an eigenstate of the target quantum logic gate before the running module runs the target quantum circuit to obtain an output final state.

[0033] Optionally, the target quantum logic gate is a controlled RY gate or a controlled RX gate.

[0034] Optionally, the target quantum circuit further comprises a fourth quantum bit, and the apparatus further comprises:

[0035] a second preparation module configured to prepare the fourth quantum bit to an equal-amplitude superposition state before the running module runs the target quantum circuit to obtain an output final state.

[0036] Optionally, the target quantum logic gate is an RZ gate or a U1 gate.

[0037] In a third aspect, the embodiment of the present application provides a storage medium, wherein the storage medium stores a computer program, and the computer program is configured to execute the steps of the method in any one of the first aspect.

[0038] In a fourth aspect, the embodiment of the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to execute the steps of the method in any one of the first aspect.

[0039] Based on the above technical scheme, the target quantum circuit for calculating the polynomial is constructed on the basis of the phase estimation quantum circuit, the independent variable in the polynomial is assigned and prepared to the initial state of the first quantum bit in the target quantum circuit, then the target quantum circuit is run to obtain the final state after the initial state is operated, and finally the calculation result of the polynomial is determined according to the final state, and the calculation process of the polynomial is realized through quantum calculation, so that the optimization process of other quantum calculation-based problems such as the QUBO problem based on quantum calculation can be realized based on the quantum calculation of the polynomial. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 Fig. 1 is a hardware structure block diagram of a computer terminal for a polynomial calculation method according to an exemplary embodiment.

[0041] Figure 2 Fig. 2 is a flowchart of a polynomial calculation method according to an exemplary embodiment.

[0042] Figure 3 Fig. 3 is a flowchart of step S21 included in a polynomial calculation method according to an exemplary embodiment.

[0043] Figure 4 Fig. 4 is a flowchart of step S211 included in a polynomial calculation method according to an exemplary embodiment.

[0044] Figure 5 Fig. 5 is a target quantum circuit diagram according to an exemplary embodiment.

[0045] Figure 6 Fig. 6 is another flowchart of a polynomial calculation method according to an exemplary embodiment.

[0046] Figure 7 Fig. 7 is a measurement result distribution diagram according to an exemplary embodiment.

[0047] Figure 8 Fig. 8 is another flowchart of a polynomial calculation method according to an exemplary embodiment.

[0048] Figure 9 Fig. 9 is a schematic diagram of a controlled quantum logic gate according to an exemplary embodiment.

[0049] Figure 10 Fig. 10 is a block diagram of a polynomial calculation device according to an exemplary embodiment. DETAILED DESCRIPTION

[0050] The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be explained as a limitation of the present application.

[0051] The present invention first provides a method for calculating polynomials, which can be applied to electronic devices, such as computer terminals, specifically ordinary computers, quantum computers, etc.

[0052] The following detailed explanation uses a computer terminal as an example. Figure 1 This is a hardware structure block diagram of a computer terminal illustrating a polynomial calculation method according to an exemplary embodiment. For example... Figure 1 As shown, a computer terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing polynomial computation methods based on quantum circuits are also shown. Optionally, the computer terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the computer terminal described above. For example, the computer terminal may also include components that are more complex than those described above. Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0053] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / modules corresponding to the polynomial calculation method in this embodiment. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0054] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0055] It should be noted that the real quantum computer is a hybrid structure, which includes two parts: one part is a classical computer responsible for performing classical computing and control; the other part is a quantum device responsible for running a quantum program to realize quantum computing. The quantum program is a sequence of instructions written in a quantum language such as QRunes language that can run on a quantum computer, which realizes the support for quantum logic gate operations and finally realizes quantum computing. Specifically, the quantum program is a sequence of instructions for operating quantum logic gates in a certain time sequence.

[0056] In practical applications, due to the limitation of the development of quantum device hardware, quantum computing simulation is usually needed to verify quantum algorithms, quantum applications, etc. Quantum computing simulation is a process of simulating the running of a quantum program corresponding to a specific problem by means of the resources of an ordinary computer (i.e. a quantum virtual machine). Usually, a quantum program corresponding to a specific problem needs to be constructed. The quantum program referred to in the embodiments of the present application is a program written in a classical language representing qubits and their evolution, in which quantum bits, quantum logic gates, etc. related to quantum computing are represented by corresponding classical codes.

[0057] As an embodiment of a quantum program, a quantum circuit, also known as a quantum logic circuit, is the most commonly used general quantum computing model, representing a circuit for operating qubits in an abstract concept, which consists of qubits, circuits (time lines), and various quantum logic gates, and finally the results need to be read out through quantum measurement operations.

[0058] Unlike traditional circuits connected by metal wires to transmit voltage signals or current signals, in a quantum circuit, the circuit can be regarded as being connected by time, that is, the state of the qubit naturally evolves over time, and in this process, it is operated according to the instructions of the Hamiltonian operator until it encounters a logic gate.

[0059] A quantum program corresponds to a total quantum circuit as a whole, and the quantum program described in the present application refers to the total quantum circuit, wherein the total number of qubits in the total quantum circuit is the same as the total number of qubits of the quantum program. It can be understood that: a quantum program can be composed of a quantum circuit, a measurement operation for qubits in the quantum circuit, a register for storing measurement results, and a control flow node (jump instruction), and a quantum circuit can contain tens, hundreds or even thousands of quantum logic gate operations. The execution process of a quantum program is a process of executing all quantum logic gates in a certain time sequence. It should be noted that the time sequence is the time sequence of the execution of a single quantum logic gate.

[0060] It should be noted that in classical computing, the most basic unit is a bit, and the most basic control mode is a logic gate, which can be combined to achieve the purpose of controlling the circuit. Similarly, the way to handle quantum bits is quantum logic gates. Using quantum logic gates, quantum states can evolve, and quantum logic gates are the basis of quantum circuits, including single-bit quantum logic gates such as Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate (RX rotation gate), RY gate (RY rotation gate), RZ gate (RZ rotation gate), and the like; multi-bit quantum logic gates such as CNOT gate, CR gate, iSWAP gate, Toffoli gate, and the like. Quantum logic gates are generally represented by unitary matrices, which are not only matrix forms but also operations and transformations. The effect of a general quantum logic gate on a quantum state is calculated by left multiplying the quantum state right vector corresponding to the vector. For example, the vector corresponding to the quantum state right vector |0> can be The vector corresponding to the quantum state right vector |1> can be

[0061] Figure 2 A flowchart of a polynomial calculation method according to an example embodiment is shown as shown in Figure 2 The method comprises:

[0062] S21, constructing a target quantum circuit for calculating the polynomial based on a phase estimation quantum circuit.

[0063] S22, assigning a value to the independent variable of each term in the polynomial, and preparing an initial state of the first quantum bit of the target quantum circuit based on the assigned independent variable.

[0064] S23, running the target quantum circuit to obtain an output final state, which represents the calculation result of the polynomial.

[0065] The phase estimation quantum circuit is used to solve the eigenvalue of the unitary matrix acting on the quantum circuit and its eigenvector. Since the eigenvalue of the unitary matrix is always of unit modulus, the eigenvalue can be represented as Therefore, solving the eigenvalue is equivalent to solving the phase

[0066] Specifically, in step S21, the phase estimation quantum circuit can be used to represent the coefficients in the polynomial, and then the target quantum circuit for calculating the polynomial can be constructed by modifying the phase estimation quantum circuit. The polynomial can be used to calculate the utility of the portfolio, and the calculation method of the polynomial can be used to calculate the utility of the portfolio.

[0067] Optionally, referring to Figure 3 In step S21, a target quantum circuit for calculating the polynomial is constructed based on the phase estimation quantum circuit, including:

[0068] S211, based on the target quantum logic gate in the phase estimation quantum circuit, a controlled quantum logic gate for calculating each term in the polynomial is constructed.

[0069] S212, the controlled quantum logic gate is applied to the first quantum bit to obtain the target quantum circuit for calculating the polynomial.

[0070] In step S211, the controlled quantum logic gate can be constructed based on the target quantum logic gate in the phase estimation quantum circuit, for calculating each monomial in the polynomial. The target quantum logic gate in the phase estimation quantum circuit can be a quantum logic gate in the phase estimation quantum circuit for representing the coefficients of the polynomial, which can itself be a quantum logic gate controlled by a single or multiple quantum bits, such as a controlled RY gate or a controlled RX gate, and a control bit can be additionally added on the basis of the foregoing, such as the first quantum bit, to make it a controlled quantum logic gate controlled by a larger number of quantum bits. Of course, the target quantum circuit can also be a single quantum logic gate, such as a U1 gate or an RZ gate, and then a controlled quantum logic gate controlled by a single or multiple quantum bits can be constructed on the basis of it. Of course, in other possible implementations, other quantum circuits or other quantum logic gates can also be used to construct the foregoing controlled quantum logic gate or to construct the target quantum circuit, which is not specifically limited in the present application.

[0071] After the controlled quantum logic gate is constructed, step S212 is entered, in which the first quantum bit does not belong to the phase estimation quantum circuit, and the first quantum bit can be obtained separately for inputting the independent variable of the polynomial into the target quantum circuit. The controlled quantum logic gate is applied to the first quantum bit, and the first quantum bit is combined with the phase estimation quantum circuit to obtain the target quantum circuit for calculating the polynomial. It should be noted that the application of the controlled quantum logic gate to the first quantum bit can represent that the controlled quantum logic gate is associated with the first quantum bit in the target quantum circuit, and the quantum state of the first quantum bit will be input into the controlled quantum logic gate, which can be a control bit of the controlled quantum logic gate. After the controlled quantum logic gate is applied to the first quantum bit, the quantum state of the first quantum bit does not necessarily change, for example, when the controlled quantum logic gate is a controlled U1 gate applied to the first quantum bit, the first quantum bit can be a control bit of the controlled U1 gate, and its quantum state does not change after being input into the controlled U1 gate.

[0072] Optionally, referring to Figure 4In step S211, based on the target quantum logic gate in the phase estimation quantum circuit, a controlled quantum logic gate for calculating each term in the polynomial is constructed, including:

[0073] S2111, determining the target quantum logic gate in the phase estimation quantum circuit for calculating the coefficient corresponding to each term in the polynomial.

[0074] S2112, taking the first quantum bit as the control bit of the target quantum logic gate, to obtain a controlled quantum logic gate for calculating each term in the polynomial.

[0075] In step S2111, first find the target quantum logic gate in the phase estimation quantum circuit for calculating the coefficient of each monomial in the polynomial. For convenience of description, taking the case where the polynomial contains only one monomial as an example, see Figure 5 The phase estimation quantum circuit in the target quantum circuit includes quantum bit 513, quantum bit 514, quantum bit 515, quantum bit 516, and quantum logic gates on these quantum bits. The phase estimation quantum circuit is used to calculate the coefficient 2 of the monomial 2x1x2, wherein the target quantum logic gate for calculating the coefficient 2 includes controlled RY gate 501, controlled RY gate 502 and controlled RY gate 503, wherein the controlled RY gate 501 acts on the quantum bit 513 and the quantum bit 516, the quantum bit 513 is the control bit, and the quantum bit 516 is the target bit; the controlled RY gate 502 acts on the quantum bit 514 and the quantum bit 516, the quantum bit 514 is the control bit, and the quantum bit 516 is the target bit; the controlled RY gate 503 acts on the quantum bit 515 and the quantum bit 516, the quantum bit 515 is the control bit, and the quantum bit 516 is the target bit.

[0076] In step S2112, for the first quantum bit in the target quantum circuit, the first quantum bit is added as the control bit of the target quantum logic gate, to obtain a controlled quantum logic gate for calculating each monomial in the polynomial. It should be noted that the target quantum logic gate itself can also be a controlled quantum logic gate, and after adding the first quantum bit as its control bit, the number of control bits of the target quantum logic gate increases, for example, the target quantum logic gate itself is a controlled RY gate controlled by a single quantum bit, and after adding a first quantum bit as its control bit, it is controlled by two quantum bits. Following the foregoing example, see Figure 5, the first qubits are qubit 511 and qubit 512, which are used to represent the inputs of x1 and x2 in the monomial 2x1x2, and the input data can be binary, i.e., the inputs of x1 and x2 are 0 or 1. For the controlled RY gate 501, the controlled RY gate 502 and the controlled RY gate 503 corresponding to the monomial 2x1x2 that has been determined, qubit 511 and qubit 512 are added as control bits for each target quantum logic gate of the controlled RY gate 501, the controlled RY gate 502 and the controlled RY gate 503, thereby obtaining the controlled quantum logic gate 521 corresponding to the controlled RY gate 501, the controlled quantum logic gate 522 corresponding to the controlled RY gate 502, and the controlled quantum logic gate 523 corresponding to the controlled RY gate 503. Specifically, the parameters of the controlled RY gate 501, the controlled RY gate 502 and the controlled RY gate 503 are -π, -2π and -4π respectively. It should be noted that the parameters -π, -2π and -4π correspond to a specific eigenvalue of the controlled RY gate, and for other eigenvalues, the parameter values can be different, and when the number of control bits of the controlled RY gate is different, the parameter values can also be different, which will not be limited in the present application, and the parameter values can be determined by referring to the parameter value determination mode of the phase estimation quantum circuit.

[0077] Similarly, for a polynomial containing multiple monomials, for example, for 2x1x2+3(x1) 2 , and then 3(x1) 2 The foregoing steps are performed on the corresponding target quantum logic gate, which will not be described again. In addition, for decimal input data, it can be converted into binary data and then assigned to the independent variables of each term in the corresponding polynomial, for example, when calculating 4x, x=3, 3 can be converted into binary data 011, and three independent variables x1, x2 and x3 are used to represent it, i.e., x1=0, x2=x3=1, then 4x can be converted into the calculation formula 4*(4x1+2x2+x3) to complete the calculation. Other decimal data can be calculated by referring to this method, which will not be limited in the present application.

[0078] After the target quantum circuit is constructed, the execution step S22 is entered, and the polynomial is assigned a value, that is, a real input value is assigned to each independent variable in the polynomial. In the foregoing example, the real input values of the independent variables x1 and x2 of the monomial 2x1x2 can be combinations of 0 and 1, that is, all inputs are 0, all inputs are 1, and one input is 0 and the other input is 1. These inputs can be assigned to the independent variables at the same time to simultaneously operate the target quantum circuit. After the assignment, an initial state is prepared according to the assigned independent variables to convert the classical data into a quantum state. In the foregoing example, the four cases can be prepared into an equal-amplitude quantum state by applying an H gate to each first quantum bit. When the polynomial represents the utility of a portfolio, the independent variables in each term of the polynomial can be assigned a value based on the portfolio, and the obtained initial state represents the portfolio.

[0079] In step S23, the target quantum circuit is run to obtain a final state output by the target quantum circuit, and the final state contains the calculation result of the polynomial. The final state can be a superposition state, which simultaneously represents the calculation results for multiple input data. The final state can be directly input into other quantum circuits for other application scenarios. When the polynomial represents the utility of a portfolio, the obtained final state can represent the utility of the portfolio.

[0080] Optionally, in step S23, the phase estimation quantum circuit further includes an inverse Fourier transform unit, and running the target quantum circuit to obtain the output final state can include:

[0081] Inputting the initial state of at least the first quantum bit into the controlled quantum logic gate of the target quantum circuit to obtain an intermediate state;

[0082] Inputting the intermediate state into the inverse Fourier transform unit to obtain a final state.

[0083] Specifically, the controlled quantum logic gate operates on the initial state, and the operation result is still in the phase of the quantum state. Then, the inverse Fourier transform unit is used to operate the result, so that the calculation result is in the quantum state of the final state, for example, when the polynomial calculation result is 0, the corresponding final state can be |0>.

[0084] Optionally, after step S23, the method can further include:

[0085] Determining the calculation result of the polynomial based on the final state.

[0086] Specifically, the quantum bits used to represent the final state can be measured to obtain the calculation result corresponding to the final state.

[0087] Optionally, the determining the calculation result of the polynomial based on the final state can comprise:

[0088] measuring the quantum bit acted on by the inverse Fourier transform unit to obtain a binary measurement result;

[0089] converting the binary measurement result into a decimal calculation result.

[0090] Specifically, after the action of the inverse Fourier transform unit, the quantum state of the quantum bit acted on by the inverse Fourier transform unit becomes the final state, and measuring the quantum bit obtains a binary measurement result, i.e., the final state of each quantum bit thereof is |0> or |1>, and the measurement result composed of multiple 0s and 1s is obtained accordingly. Then, the binary measurement result is converted into decimal data according to a certain conversion rule, i.e., the calculation result of the polynomial is obtained.

[0091] Based on the above technical solutions, the target quantum circuit for calculating the polynomial is constructed based on the phase estimation quantum circuit, the independent variable in the polynomial is assigned to the initial state of the first quantum bit in the target quantum circuit, then the target quantum circuit is run to obtain the final state after the operation on the initial state, and finally the calculation result of the polynomial is determined according to the final state, so that the optimization process of the QUBO problem can be realized based on the quantum calculation of the polynomial.

[0092] Optionally, the target quantum circuit further comprises a second quantum bit and a third quantum bit, Figure 6 is another flowchart of a polynomial calculation method according to an example embodiment, referring to Figure 6 The calculation method comprises:

[0093] S61, constructing a target quantum circuit for calculating the polynomial based on a phase estimation quantum circuit.

[0094] S62, assigning a value to the independent variable of each term in the polynomial, and preparing an initial state of a first quantum bit of the target quantum circuit based on the assigned independent variable.

[0095] S63, preparing the second quantum bit to an equal-amplitude superposition state, and preparing the third quantum bit to an eigenstate of the target quantum logic gate.

[0096] S64, running the target quantum circuit to obtain an output final state, wherein the final state is used to represent the calculation result of the polynomial.

[0097] wherein steps S61 and S62 can refer to steps S21 and S22 respectively, and step S64 can refer to step S23.

[0098] Specifically, after the target quantum circuit is constructed, step S63 can be entered, which can be performed simultaneously with step S62 or sequentially in a certain order, and the present application does not make specific limitations thereon. In step S63, the second quantum bit is prepared to an equal-amplitude superposition state, and the third quantum bit is prepared to an eigenstate of the target quantum logic gate to meet the requirements of the operation of the phase estimation quantum circuit. Using the foregoing example, reference is made to Figure 5 , wherein quantum bit 513, quantum bit 514 and quantum bit 515 are the second quantum bits, which are used as the control bits of the target quantum logic gate, and quantum bit 516 is the third quantum bit, which is used as the target bit of the target quantum logic gate. Further, quantum bit 513, quantum bit 514 and quantum bit 515 are first prepared to |0> states respectively, and then an H gate is applied to each of them to obtain an equal-amplitude superposition state. For quantum bit 516, since the target quantum logic gate is a controlled RY gate, quantum bit 516 is first prepared to a |0> state, and then an H gate 541 and an S gate 542 are applied to quantum bit 516 respectively to obtain an eigenstate of the controlled RY gate. Then in step S64, the initial state of the first quantum bit, the equal-amplitude superposition state of the second quantum bit and the eigenstate of the third quantum bit can be input into the controlled quantum logic gate, and then the intermediate state output by the controlled quantum logic gate is input into the inverse Fourier transform unit to obtain the final state of the output.

[0099] Alternatively, the target quantum logic gate is a controlled RY gate or a controlled RX gate. For the controlled RX gate, to prepare its eigenstate, only an H gate needs to be applied to the third quantum bit in the |0> state. For convenience of calculation, when the target quantum logic gate is a controlled RY gate or a controlled RX gate, the corresponding eigenvalue is i is an imaginary symbol, and θ is an input parameter of the target quantum logic gate, and the base angle of the controlled RY gate or the controlled RX gate can be selected as i.e. the parameters of the controlled RY gate and the controlled RX gate are constructed based on the base angle, wherein m is the number of the second quantum bits. In the phase estimation quantum circuit, to represent a real number, for example, c, the product of c and the base angle can be taken as the parameter to construct the target quantum logic gate, and the number of the target quantum logic gates representing the real number c is the same as the number of the second quantum bits, which is also m, and the parameter values of the parameters of each target quantum logic gate are 2 m-1 θ, 2 m-2 θ, …… 2θ, θ, i.e. the product of the represented coefficient c and the base angle, Referring to Figure 5 , the number of the second quantum bits is 3, so 3 controlled RY gates are needed, and the parameters thereof are 4θ, 2θ and θ respectively, since c = 2 and m = 3, so Therefore, the parameters of the 3 controlled RY gates are -4π, -2π and -π respectively.

[0100] In summary, the first quantum bit, the second quantum bit and the third quantum bit can be obtained by the first quantum register, the second quantum register and the third quantum register respectively, in the target quantum circuit, the first quantum bit is used to input the value of the independent variable in the form of the initial state into the target quantum circuit, the second quantum bit can be used to output the final state representing the calculation result of the polynomial, and the third quantum bit plays an auxiliary role, and accordingly, the first quantum register, the second quantum bit and the third quantum register are the key register, the value register and the auxiliary register respectively, wherein the operations in the value register and the auxiliary register are phase estimation.

[0101] It should be noted that when c is an integer, c will be obtained with a probability of 1, and when c is a decimal, the measurement result is a distribution, and the result with the maximum probability in the distribution corresponds to the integer closest to c, for example, when c = 2.16 and m = 3, the distribution of the measurement result is as shown in Figure 7 It can be seen that when c = 2.16, the output with the maximum probability is 010, that is, 2 in decimal.

[0102] Correspondingly, for the target quantum circuit as shown in Figure 5 The inverse Fourier transform unit includes an iSWAP gate 531, an H gate 532, an inverse CR gate 533, an H gate 534, an inverse CR gate 535, an inverse CR gate 536, and an H gate 537. The iSWAP gate 531 acts on the quantum bit 513 and the quantum bit 515 respectively; the H gate 532 acts on the quantum bit 513; the inverse CR gate 533 acts on the quantum bit 513 and the quantum bit 514, wherein the quantum bit 513 is a control bit and the quantum bit 514 is a target bit; the H gate 534 acts on the quantum bit 514, and the inverse CR gate 535 acts on the quantum bit 513 and the quantum bit 515, wherein the quantum bit 513 is a control bit and the quantum bit 515 is a target bit; the inverse CR gate 536 acts on the quantum bit 514 and the quantum bit 515, wherein the quantum bit 514 is a control bit and the quantum bit 515 is a target bit; and the H gate 537 acts on the quantum bit 515. Of course, for other structures of the target quantum circuit, for example, the polynomial expressed by the target quantum circuit has multiple monomials, the specific structure of the corresponding inverse Fourier transform unit is different, and can be designed according to the specific circumstances, as long as it can realize quantum inverse Fourier transform. The inverse CR gate is the conjugate transpose of the CR gate.

[0103] Optionally, the target quantum circuit further includes a fourth quantum bit, Figure 8 is another flow chart of a polynomial calculation method according to an example embodiment, referring to Figure 8 The calculation method comprises:

[0104] S81, constructing a target quantum circuit for calculating the polynomial based on the phase estimation quantum circuit.

[0105] S82, assigning a value to the independent variable of each term in the polynomial, and preparing an initial state of the first quantum bit of the target quantum circuit based on the assigned independent variable.

[0106] S83, preparing the fourth quantum bit to an equal-amplitude superposition state.

[0107] S84, running the target quantum circuit to obtain an output final state, the final state being used to represent the calculation result of the polynomial.

[0108] Wherein, the steps S81 and S82 can refer to steps S21 and S22 respectively, and the step S84 can refer to step S23.

[0109] Specifically, after constructing the target quantum circuit, the step S83 can be entered, which can be executed simultaneously with the step S82 or in a certain order. The present application does not make specific limitation on this. In the step S83, for some target quantum logic gates, no operation is performed when they act on |0> state. At this time, the original second quantum bit and the third quantum bit can be merged, and only one group of quantum bits, i.e. the fourth quantum bit, is used to perform the corresponding operation to meet the requirements of the phase estimation quantum circuit, and the fourth quantum bit is directly prepared to an equal-amplitude superposition state, which can reduce the demand for quantum bits.

[0110] In a possible implementation, the target quantum logic gate is an RZ gate or a U1 gate. Both of them are single quantum logic gates, and the unitary matrix corresponding to the U1 gate is:

[0111]

[0112] Wherein, is a parameter, and i is an imaginary symbol. For the RZ gate and the U1 gate, the corresponding base angle is different from the aforementioned controlled RY gate or RX gate, and the base angle of the RZ gate and the U1 gate is Wherein, m is the number of the fourth quantum bit. Similarly, for the RZ gate and the U1 gate, in the phase estimation quantum circuit, to represent a real number, for example, c, the product of c and the base angle can be used as a parameter to construct the target quantum logic gate, and the number of the target quantum logic gate representing the real number c is the same as the number of the fourth quantum bit, which is also m, and the parameter values of the parameters of each target quantum logic gate are 2 m-1 θ, 2 m-2 θ……2θ, θ, θ, that is, the product of the represented coefficient c and the base angle, For example, refer to Figure 9For calculating 2x1x3, in the first quantum bit 901, the first quantum bit 902, the first quantum bit 903, the first quantum bit 904, the first quantum bit 902 and the first quantum bit 904 can be added as control bits to the U1 gate 911 to obtain a controlled quantum logic gate 921 for constructing a target quantum circuit for calculating 2x1x3, wherein the fourth quantum bit 905 is the target bit of the controlled quantum logic gate 921. Similarly, for a polynomial containing multiple monomials, for example, for 2x1x3+3x1x2, the foregoing steps are performed again on the target quantum logic gate corresponding to 3x1x2, and details are not repeated here.

[0113] For a quadratic unconstrained binary optimization problem, that is, a QUBO problem, the core is to find the minimum value of a binary quadratic polynomial, for example, to find the minimum value of y=2x1x3+4x2x3+x2, and the input of each independent variable is a binary value, that is, 0 or 1. To find the minimum value, one possible algorithm is to find the minimum value in all calculation results, which requires a large number of calculations, and then the foregoing polynomial calculation method can be used. Referring to the foregoing method, for each monomial in the polynomial, all the first quantum bits corresponding to the independent variables of the monomial are added as control bits of the target quantum logic gate, for example, for the first term 2x1x3, the first quantum bits corresponding to x1 and x3 are added as control bits of the target quantum logic gate, and for x2, only the first quantum bit corresponding to x2 is added as a control bit of the target quantum logic gate. In some cases, the degree of the independent variable in the polynomial can be 2 or more, for example, it can contain (x1) n And for a binary polynomial, since the input is 0 or 1, (x1) n = x1, n is an integer greater than or equal to 2, so the high-order independent variable of the binary polynomial can be converted to the first order.

[0114] Figure 10 is a block diagram of a polynomial calculation device according to an exemplary embodiment, referring to Figure 10 The device 100 comprises:

[0115] The calculation module 101 is configured to construct a target quantum circuit for calculating the polynomial based on a phase estimation quantum circuit;

[0116] The assignment preparation module 102 is configured to assign values to the independent variables of each term in the polynomial, and prepare initial states of the first quantum bits of the target quantum circuit based on the assigned independent variables;

[0117] The running module 103 is configured to run the target quantum circuit to obtain an output final state, and the final state is used to represent the calculation result of the polynomial.

[0118] Optionally, the computing module 101 is further configured to:

[0119] constructing a controlled quantum logic gate for computing each term in the polynomial based on a target quantum logic gate in the phase estimation quantum circuit;

[0120] applying the controlled quantum logic gate to the first quantum bit to obtain a target quantum circuit for computing the polynomial.

[0121] Optionally, the computing module 101 is further configured to:

[0122] determining a target quantum logic gate in the phase estimation quantum circuit for computing a corresponding coefficient of each term in the polynomial;

[0123] taking the first quantum bit as a control bit of the target quantum logic gate to obtain a controlled quantum logic gate for computing each term in the polynomial.

[0124] Optionally, the target quantum circuit further comprises a second quantum bit and a third quantum bit, and the apparatus 100 further comprises:

[0125] a first preparation module configured to prepare the second quantum bit to an equal-amplitude superposition state and prepare the third quantum bit to an eigenstate of the target quantum logic gate before the running module runs the target quantum circuit to obtain an output of a final state.

[0126] Optionally, the target quantum logic gate is a controlled RY gate or a controlled RX gate.

[0127] Optionally, the target quantum circuit further comprises a fourth quantum bit, and the apparatus 100 further comprises:

[0128] a second preparation module configured to prepare the fourth quantum bit to an equal-amplitude superposition state before the running module runs the target quantum circuit to obtain an output of a final state.

[0129] Optionally, the target quantum logic gate is an RZ gate or a U1 gate.

[0130] As to the apparatus in the above-mentioned embodiments, the specific manners in which various modules perform operations have been described in detail in the embodiments of the method, and thus will not be described here in detail.

[0131] Still another embodiment of the present application further provides a storage medium having a computer program stored therein, wherein the computer program is configured to perform the steps in the above-mentioned polynomial computing method embodiments when running.

[0132] Specifically, in the embodiment, the storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various storage media that can store computer programs.

[0133] Another embodiment of the present application also provides an electronic device including a memory and a processor, the memory storing a computer program, and the processor being configured to execute the computer program to perform the steps in the polynomial calculation method embodiments.

[0134] Specifically, the electronic device can further include a transmission device connected to the processor and an input / output device connected to the processor.

[0135] Specifically, in the embodiment, the processor can be configured to execute the following steps through the computer program:

[0136] A target quantum circuit for calculating the polynomial is constructed based on a phase estimation quantum circuit.

[0137] Each variable in the polynomial is assigned a value, and an initial state of a first quantum bit of the target quantum circuit is prepared based on the assigned variable.

[0138] An output final state of the target quantum circuit is obtained, and the final state is used to represent the calculation result of the polynomial.

[0139] The above embodiments according to the drawings illustrate the structure, features and effects of the present application. The above description is only a preferred embodiment of the present application, but the present application is not limited by the drawings. Any changes or modifications made in accordance with the concept of the present application, or equivalent embodiments with equivalent changes, are still within the scope of the present application.

Claims

1. A method of calculating a polynomial, characterized by, The method comprises: constructing a target quantum circuit for calculating the polynomial based on a phase estimation quantum circuit, wherein the construction of the target quantum circuit comprises: determining a target quantum logic gate in the phase estimation quantum circuit for calculating a corresponding coefficient of each term in the polynomial; based on the target quantum logic gate, constructing a controlled quantum logic gate for calculating each term in the polynomial, and applying the controlled quantum logic gate to a first quantum bit; assigning values to the independent variables of each term in the polynomial, and preparing an initial state of the first quantum bit of the target quantum circuit based on the assigned values of the independent variables; running the target quantum circuit to obtain an output final state, which is used to represent the calculation result of the polynomial.

2. The method of claim 1, wherein, The method comprises: constructing a controlled quantum logic gate for calculating each term in the polynomial based on the target quantum logic gate, comprising:

3. The method of claim 1, wherein, taking the first quantum bit as the control bit of the target quantum logic gate to obtain the controlled quantum logic gate for calculating each term in the polynomial. The target quantum circuit further comprises a second quantum bit and a third quantum bit, and before running the target quantum circuit to obtain an output final state, the method further comprises:

4. The method of claim 3, wherein, preparing the second quantum bit to an equal-amplitude superposition state, and preparing the third quantum bit to an eigenstate of the target quantum logic gate.

5. The method of claim 1, wherein, The target quantum logic gate is a controlled RY gate or a controlled RX gate. The target quantum circuit further comprises a fourth quantum bit, and before running the target quantum circuit to obtain an output final state, the method further comprises:

6. The method of claim 5, wherein, preparing the fourth quantum bit to an equal-amplitude superposition state.

7. An apparatus for calculating a polynomial, characterized by The target quantum logic gate is an RZ gate or a U1 gate. The device comprises: a calculation module configured to construct a target quantum circuit for calculating the polynomial based on a phase estimation quantum circuit, wherein the construction of the target quantum circuit comprises: determining a target quantum logic gate in the phase estimation quantum circuit for calculating a corresponding coefficient of each term in the polynomial; based on the target quantum logic gate, constructing a controlled quantum logic gate for calculating each term in the polynomial, and applying the controlled quantum logic gate to a first quantum bit; an assignment preparation module configured to assign values to the independent variables of each term in the polynomial, and prepare an initial state of the first quantum bit of the target quantum circuit based on the assigned values of the independent variables; 8. A storage medium, characterized by a running module configured to run the target quantum circuit to obtain an output final state, which is used to represent the calculation result of the polynomial. 9.An electronic device comprising a memory and a processor, the electronic device characterized by, The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1 to 6 when running. The memory stores a computer program, and the processor is configured to execute the computer program to execute the method described in any one of claims 1 to 6.

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