A test structure for crosstalk and methods of testing and shielding

Abstract

The application discloses a crosstalk test structure and a test and shielding method thereof, and belongs to the field of quantum computing. The crosstalk test structure comprises an opposite bit layer and a line layer. The bit layer has a first quantum bit, a second quantum bit and a bit reading structure; and the line layer has corresponding first control lines and second control lines. The projection track of the bit layer does not pass through quantum bits other than the first quantum bit except for the first quantum bit, and the projection track of the bit layer passes through the first quantum bit. By using the control lines designed to operate one bit, another bit is operated, and whether crosstalk exists is judged according to the operation result. The scheme can provide a beneficial reference for constructing a complex multi-bit system and avoid adverse mutual interference between bits in a manufactured quantum computing system.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of quantum information, in particular, the field of quantum computing technology. Specifically, the present application relates to a crosstalk test structure and a test and shielding method thereof. BACKGROUND

[0002] In a large chip package, each superconducting quantum bit has a resonant cavity, a bus, an XY line, a Z line, etc.; and these structures need to be connected to the pins on the edge of the chip through wiring. When multiple superconducting quantum bits are arranged, the signal lines of the bits in the middle pass through the remaining bits, and at the same time, due to the increase in the number of signals, the spacing between the lines is reduced. These can cause crosstalk of signals, thereby affecting the reading and control operations of other bits. If the causes of crosstalk can be accurately identified, it will help to propose solutions, so as to realize more accurate and effective quantum computing. SUMMARY

[0003] Examples of the present application provide a crosstalk test structure and a test and shielding method thereof. The scheme can be used to determine or verify whether there is crosstalk between adjacent bits and their accessories in the designed multi-bit expansion system, thereby helping to improve and adjust the design scheme, and thus to reduce or even eliminate the aforementioned crosstalk when expanding multiple bits.

[0004] The scheme of the examples of the present application is implemented by the following contents.

[0005] In a first aspect, examples of the present application propose a crosstalk test structure, comprising:

[0006] a bit layer having a first quantum bit, a second quantum bit, and a bit reading structure;

[0007] a line layer opposite to the bit layer, having a first control line and a second control line respectively corresponding to the first quantum bit and the second quantum bit;

[0008] wherein the first control line and the second control line are respectively positioned so that the first control line is configured to operate the first quantum bit, and the projection track of the first control line on the bit layer does not pass through other quantum bits except the first quantum bit, and the second control line is configured to operate the second quantum bit, and the projection track of the second control line on the bit layer passes through the first quantum bit.

[0009] According to some examples of the present application, the first control line and the second control line are bit transition control lines or bit frequency control lines;

[0010] And / or, the bit read structure includes a read bus, a first read resonator cavity coupled with the first qubit, and a second read resonator cavity coupled with the second qubit, wherein the read bus is coupled with the first read resonator cavity and the second read resonator cavity, respectively.

[0011] According to some examples of the present application, the wiring layer further includes a third control line configured to operate the first qubit, and the third control line passes through other qubits except the first qubit in the projection trajectory of the bit layer;

[0012] The first control line and the third control line are bit transition control lines, respectively, and the first control line and the third control line are coupled with the first qubit at different positions, respectively.

[0013] According to some examples of the present application, the distance between the first control line and the first qubit is equal to the distance between the third control line and the first qubit.

[0014] According to some examples of the present application, the wiring layer further includes a fourth control line configured to operate the second qubit, and the fourth control line passes through other qubits except the second qubit in the projection trajectory of the bit layer;

[0015] The second control line and the fourth control line are bit transition control lines, respectively, and the second control line and the fourth control line are coupled with the second qubit at different positions, respectively.

[0016] According to some examples of the present application, the distance between the first control line and the first qubit is defined by the vertical distance between the end of the projection of the first control line in the bit layer and the capacitor plate of the first qubit; and the distance between the second control line and the first qubit is defined by the vertical distance between the end of the projection of the second control line in the bit layer and the capacitor plate of the first qubit.

[0017] According to some examples of the present application, the wiring layer further includes a fourth control line configured to operate the second qubit, and the fourth control line passes through the first qubit in the projection trajectory of the bit layer;

[0018] The first control line and the second control line are bit transition control lines, respectively, and the second control line and the fourth control line are frequency control lines, respectively.

[0019] According to some examples of the present application, the distance between the first control line and the second control line is not equal to the distance between the second control line and the third control line.

[0020] According to some examples of the present application, the first control line and the second control line are bit transition control lines, and the test structure further has a first frequency control line at the wiring layer and configured to correspondingly control the frequency of the first quantum bit, and a second frequency control line configured to control the frequency of the second quantum bit, wherein the first frequency control line does not pass through other quantum bits except the first quantum bit in the projection track of the bit layer, and the second frequency control line is configured to operate the second quantum bit, and the second control line passes through the first quantum bit in the projection track of the bit layer.

[0021] In a second aspect, examples of the present application propose a crosstalk test method for determining whether a control line of a first quantum bit has crosstalk with a control line of a second quantum bit, comprising:

[0022] obtaining the test structure as described above;

[0023] transmitting a first control signal for operating the first quantum bit by using the first control line, and performing an operation of reading the first quantum bit by using the reading structure to obtain a first reading result;

[0024] transmitting the first control signal by using the second control line, and performing an operation of reading the first quantum bit by using the reading structure to obtain a second reading result;

[0025] comparing the first reading result and the second reading result to determine whether the second control line has crosstalk with the first quantum bit.

[0026] In a third aspect, examples of the present application propose a crosstalk shielding method, comprising:

[0027] performing the crosstalk test method as described above;

[0028] when it is determined that there is crosstalk, configuring a shielding structure between the bit layer and the wiring layer, the shielding structure spans the position where the projection track of the second control line passes through the first quantum bit in the bit layer, and the shielding structure comprises an air strip or an air bridge.

[0029] In a fourth aspect, examples of the present application propose a crosstalk test structure, comprising:

[0030] a first chip configured with a first superconducting quantum bit and a second superconducting quantum bit, wherein the first superconducting quantum bit is coupled with a reading structure;

[0031] a second chip connected and supported to each other in a predetermined interval opposite to the first chip by an interconnection structure, and provided with a bit control line configured to cause the second superconducting quantum bit to transition or change frequency;

[0032] wherein the bit control line passes through the capacitive arm of the first superconducting quantum bit in the projection of the first chip in the opposite direction.

[0033] In a fifth aspect, examples of the present application provide a crosstalk test method for determining whether a bit control line of a second superconducting qubit has crosstalk to a first superconducting qubit, comprising:

[0034] obtaining the test structure described above;

[0035] transmitting a control signal of the first superconducting qubit through the bit control line, and performing a read operation of the first superconducting qubit through the read structure to obtain a read result;

[0036] determining whether the bit control line has crosstalk to the first superconducting qubit according to the read result.

[0037] Advantages:

[0038] In view of the limited substrate area, in a multi-bit expansion structure, the arrangement of bits relative to each other can be relatively close, and the spacing between the control structures and read structures of these bits can also be reduced, thereby significantly increasing the design and manufacturing difficulty of the quantum chip. In order to alleviate the above problems, the planar layout structure of the chip can be adjusted to a three-dimensional layout structure. However, in a three-dimensional architecture, when the number of bits is large, there can still be crosstalk and other problems. Therefore, if the source of crosstalk or the reason for its formation can be accurately identified, it will help to avoid at the beginning of design, so as to obtain a quantum chip with higher quality and lower crosstalk. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to make the description clearer, the drawings needed to be used in the description will be briefly introduced below.

[0040] Figure 1 A structure diagram of a quantum bit on a quantum chip in the related art;

[0041] Figure 2 A structure diagram showing a control line passing through a bit in a two-bit structure with two capacitor plates in examples of the present application;

[0042] Figure 3 A structure diagram of a crosstalk test structure realized based on a two-layer chip in examples of the present application;

[0043] Figure 4 A structure diagram showing a bit structure with two control lines located at different positions of the bit in examples of the present application;

[0044] Figure 5 A structure diagram showing three different construction forms of the width and ground clearance of the control line in examples of the present application;

[0045] Figure 6A structural diagram showing the distance between two control lines in a qubit;

[0046] Figure 7 A method flow chart for determining whether a control line of a bit is another control line of a bit in an example of the present application;

[0047] Figure 8 A structural diagram for configuring an air bridge to shield crosstalk when it is determined that there is crosstalk between a control line and a bit in an example of the present application;

[0048] Figure 9 A structural diagram for configuring multiple air bridges to shield crosstalk when it is determined that there is crosstalk between a control line and a bit in an example of the present application.

[0049] BRIEF DESCRIPTION OF DRAWINGS 101-bit layer; 102-wiring layer; 201-first chip; 2011-first superconducting qubit; 2012-second superconducting qubit; 202-second chip; 2021-bit control line; 301-first control line; 303-third control line. DETAILED DESCRIPTION

[0050] A quantum chip is a processor that performs quantum computation in a quantum computer. The quantum chip contains a core processing unit named a quantum bit or qubit or qunbit for the processor. The quantum bit is a two-level system that follows the laws of quantum mechanics and can be in a state of 0, or 1, or any superposition of the two.

[0051] Depending on the different physical systems used to construct the quantum bit, the quantum bit includes superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological quantum, photons, etc. in terms of physical implementation. Among them, superconducting quantum computing is the fastest and best solid quantum computing implementation scheme at present; the quantum bit based on the superconducting system corresponding to it can be called a superconducting quantum bit or a superconducting qubit.

[0052] The energy level structure of the superconducting quantum circuit can be controlled by an external electromagnetic signal, and the controllability of the circuit design is strong. At the same time, thanks to the existing mature integrated circuit process and micro-nano processing technology, the superconducting quantum circuit has unmatched scalability and advantages compared with other quantum bit physical systems.

[0053] A quantum chip based on superconducting quantum circuit contains superconducting circuit structures such as quantum bits and microwave resonant cavities. The quantum bits are two-level systems composed of a capacitor and a Josephson junction with nonlinear inductance characteristics. Capacitors, inductors, and other electrical parameters are designed in different shapes to achieve different goals. The shape of the transmon quantum bit looks like a "+" shape, which is composed of a cross-shaped capacitor and a superconducting quantum interference device (squid) connected to the end of one branch of the capacitor. The superconducting quantum interference device (squid) contains one or more Josephson junctions; a Josephson junction is a device that includes two electrodes and a thin insulating barrier layer separating the two electrodes, and the materials of the two electrodes can exhibit superconducting characteristics at their critical temperature or below the critical temperature.

[0054] In the above quantum bit system, there are various circuit structures with different functions around the quantum bit, such as read resonant cavities and couplers for coupling between quantum bits.

[0055] The circuit structure can also include a drive control signal line (XY-Control Line, also known as xy control line or pulse control signal line or transition control line) that implements XY rotation operations on the quantum bit. By applying a driving voltage signal in the circuit, the quantum bit transition can be excited; it is associated with the quantum bit through capacitive coupling.

[0056] The circuit structure can also include circuit structures for Z rotation operations on the quantum bit, and can be completed by a control signal line near the superconducting quantum interference device (squid); it is called a magnetic flux control signal line (Z-Control Line, also known as z control signal line or frequency control signal line or frequency control line). As mentioned earlier, the magnetic flux control signal line is arranged near the superconducting quantum interference device (squid), which excites current and inductively couples with the superconducting quantum interference device (squid) through the magnetic field.

[0057] It should be noted that the magnetic flux control signal line and the drive control line can be used to control the quantum bit, but their control forms and purposes are different.

[0058] The drive control signal line applies a pulse to the quantum bit in the form of an electric field, which causes the energy level of the quantum bit to transition. The signal transmitted by the magnetic flux control signal line generates a magnetic field and is applied to the superconducting quantum interference device (SQUID) region, and the magnetic flux passing through the SQUID region can cause a change in the critical current of the SQUID. The change in the critical current causes a change in the frequency of the tunable quantum bit, i.e., the frequency of the quantum bit can be controlled by the signal transmitted by the magnetic flux control signal line.

[0059] Figure 1 A schematic diagram of the structure of a quantum bit arranged on a quantum chip in the related art.

[0060] In combination Figure 1 As shown in the figure, a structure of a transmission-type quantum bit often uses a single ground-connected capacitor and a superconducting quantum interference device (SQUID) with one end connected to the ground and the other end connected to the capacitor. Moreover, the capacitor is often a cross-shaped parallel-plate capacitor.

[0061] As shown in the figure, the cross-shaped capacitor plate C q (i.e., the bit capacitor) is surrounded by a ground plane (GND), and the cross-shaped capacitor plate C q has a gap (usually an air gap, which is insulating) between the cross-shaped capacitor plate C q and the ground plane (GND).

[0062] One end of the superconducting quantum interference device is connected to the first end of the cross-shaped capacitor plate C q (one end of a capacitor arm, as mentioned later), and the other end is connected to the ground plane (GND).

[0063] Since the first end of the cross-shaped capacitor plate C q is usually used to connect the superconducting quantum interference device, the second end is used to couple with the readout resonator. The other two ends of the cross-shaped capacitor plate C are used to couple with adjacent quantum bits to achieve bit extension. A certain space is usually reserved near the first end and the second end for the arrangement of microwave transmission lines such as the drive control signal line and the magnetic flux control signal line. Similarly, a certain space is usually reserved near the resonator for the arrangement of the readout signal transmission line that forms a coupling with the resonator.

[0064] When performing quantum computation, the magnetic flux control signal on the magnetic flux control signal line is used to first adjust the frequency of the quantum bit to the working frequency (initial state preparation), and then the quantum state of the quantum bit in the initial state is controlled by applying a quantum state control signal through the drive control signal line. The quantum state of the controlled quantum bit is then read by the resonator.

[0065] Specifically, the quantum state that the qubit is in can be determined by applying a read probe signal (e.g., a microwave signal with a frequency of 4 GHz - 8 GHz) on a read signal transmission line coupled with the resonant cavity, and then analyzing a read feedback signal (a signal in response to the read probe signal) output by the read signal transmission line. The flux control signal line, the drive control signal line, and the read signal transmission line can all be implemented in a microwave transmission line structure, which will not be described here.

[0066] When multiple qubits are configured, a one-dimensional linear layout can be selected, and to reduce the difficulty of configuring the qubits and their accessories (such as various control structures, read structures, etc.), a flip-chip form can be selected. Among them, the qubits are configured as transmission sub-qubits on one layer of the chip, and the accessories such as the control lines are configured on another layer of the chip. Since there are multiple qubit configurations, when it is necessary to control or read the internal qubits, for example, one or more qubits between two qubits, the corresponding lines can pass through the two qubits to access the one or more qubits that need to be operated.

[0067] For example, similar to the qubit structure with cross-capacitance in Figure 1 , the lines passing through the qubit include lines passing through the capacitor arms of the cross-capacitance. And under the premise of layering the qubit and the lines, the lines passing through the capacitor arms of the cross-capacitance means that the projection of the lines on the qubit layer 101 passes through the capacitor arms of the qubit in the qubit layer 101.

[0068] In the double-layer chip, the control lines passing through the qubit can be disclosed by the following description.

[0069] Please refer to Figure 2 , where qubit one and qubit two are located in the same layer, which can be expressed as qubit layer 101; or, in the flip-chip as in Figure 3 , the chip where the qubits are configured can be described as the first chip 201. Accordingly, in Figure 2 , line one and line two are located in the same layer, which can be expressed as line layer 102; or, in the flip-chip as in Figure 3 , the chip where the lines are configured can be described as the second chip 202.

[0070] Among them, line one belonging to qubit one is used to operate the transition or frequency adjustment of qubit one. The belonging indicates that line one is intentionally designed to operate qubit one, not qubit two. Similarly, line two belonging to qubit two is used to operate the transition or frequency adjustment of qubit two. In Figure 2 , line one and line two are given as examples of control lines operating the transition of the qubit.

[0071] In the process of performing quantum computation on a superconducting quantum chip, various signals / control, read signals, and various electronic components such as transmission lines, capacitors, inductors, etc. may be involved. Considering the noise sensitivity and vulnerability of superconducting qubits, in a complex multi-qubit quantum computing system, various crosstalk signals may exist, which greatly reduces the effectiveness of quantum computation. Therefore, accurately identifying potential crosstalk will help design and manufacture superconducting quantum chips and computers that are more resistant to interference and can effectively perform computation. It is worth noting that in the examples of the present application, the main concern is the noise that the constituent components inside the quantum chip may generate.

[0072] For example, in order to determine whether there is crosstalk effect in the bit and the corresponding line configuration scheme in Figure 2 , a crosstalk test structure can be constructed.

[0073] In the examples of the present application, the inventors propose a crosstalk test structure as shown in Figure 3 .

[0074] The crosstalk test structure includes a first chip 201 and a second chip 202 that are opposite to each other and connected to each other through an interconnection structure.

[0075] The interconnection structure therein may be, for example, a solder pad, a bump, a ball, or a column. In a superconducting quantum chip, the interconnection structure can be instantiated as an indium column; the two chips are each soldered to the indium column, and the connection is achieved by soldering the ends of the two. The indium column can serve as a provider of mutual support between the first chip 201 and the second chip 202, and can also keep the relative positions (including vertical and horizontal positions) of the two chips fixed. It can be known that the distance between the first chip 201 and the second chip 202 in the vertical direction is defined by the interconnection structure.

[0076] In some examples, part of the interconnection structure can also serve as a signal communication or physical connection structure between components in the two chips. For example, part of the signal line or transmission line may need to transmit signals from one chip to another chip; then some interconnection structures can be used as signal communication components.

[0077] The first chip 201 is configured with a bit layer 101, which includes a first superconducting qubit (first superconducting qubit 2011) and a second superconducting qubit 2012 (second superconducting qubit 2012). The first superconducting qubit is coupled to a readout structure such as a readout resonator. The readout resonator can be coupled to the qubit and perform readout operations by detecting the bit with a readout input (readout in) signal.

[0078] In the wiring layer 102 of the second chip 202, there is provided a bit control line 2021 configured to cause the second superconducting qubit to undergo a transition or frequency change (in examples, to control the transition). The bit state adjustment can be achieved by using the bit control line 2021 to adjust the bit from the ground state to the excited state. When the qubit is constructed in the form of an adjustable frequency (for example, a qubit implemented based on a direct current superconducting quantum interference device and a shunt capacitor), then in some examples, the bit control line 2021 can also be configured as a magnetic flux control line to adjust the frequency of the qubit.

[0079] Alternatively, in some examples, there are multiple bit control lines 2021, and different lines are designed as transition control and frequency control according to functional requirements. In addition, the test structure can also have multiple bit control lines 2021 of the same control type.

[0080] For example, the first control line and the second control line are bit transition control lines, and the test structure further has a first frequency control line located in the wiring layer 102 and used to correspondingly control the frequency of the first qubit, and a second frequency control line used to control the frequency of the second qubit.

[0081] Based on the different cases of whether the control line passes through the bit, and the need for the correlation between the crosstalk, the first frequency control line is configured to pass through the other qubits except the first qubit in the projection trajectory of the bit layer 101, while the second frequency control line is configured to operate the second qubit, and the second control line passes through the first qubit in the projection trajectory of the bit layer 101.

[0082] In combination Figure 2 For the bit control line 2021 in Figure 3 the first chip 201 and the second chip 202 (the bit layer 101 and the wiring layer 102) are opposite to each other in the direction Figure 3 of the vertical direction in Figure 2 , the projection of the wiring two and the capacitor arm of the bit one in the same plane shows that they are perpendicular to each other, or intersect each other vertically and horizontally. In addition, in Figure 2 , the wiring one does not pass through the other qubits except the first qubit, while the wiring two passes through the first qubit.

[0083] In the crosstalk test structure described above, the bit control line 2021 is expected to be designed to operate the second qubit, not the first qubit. Meanwhile, it is expected that a read operation on the first qubit being operated is performed by the read structure to obtain read information, which is implemented by the control line corresponding to the first qubit. In order to implement effective quantum computing, it is desirable that the bit control line 2021 corresponding to the second qubit does not crosstalk to affect the first qubit, i.e., there is no crosstalk from the bit control line 2021 of the second qubit to the first qubit.

[0084] However, in some implementations, there can be a case where the bit control line 2021 corresponding to the second qubit crosstalks and affects the first qubit. Therefore, in order to determine whether such crosstalk exists, a test can be implemented based on the test structure. Correspondingly, in an example, a crosstalk test method for determining whether the bit control line 2021 of the second superconducting qubit crosstalks to the first superconducting qubit is proposed.

[0085] The crosstalk test method can be implemented using the crosstalk test structure described in the examples of the present application. In an example, the crosstalk test method mainly includes implementing a test using the crosstalk test structure. The test includes transmitting a control signal for operating the first superconducting qubit using the bit control line 2021 in the test structure, and performing a read operation on the first superconducting qubit through the read structure to obtain a read result; and then determining whether the bit control line 2021 crosstalks to the first superconducting qubit according to the read result (such as the frequency of the bit, the energy spectrum, the Rabi oscillation, etc.).

[0086] In other words, the bit control line 2021, which is expected to be designed to operate the second qubit, is used to transmit a control signal for operating the first qubit. The result of the read on the first qubit is evaluated to identify whether crosstalk exists. For example, if the read on the first qubit can obtain an expected read result, it indicates that the bit control line 2021 belonging to the second qubit can indeed implement the operation on the first qubit; the operation can be ineffective, thus representing crosstalk, or the operation can be effective, but this can not be the intended purpose of the design.

[0087] Since in the test structure, the bit control line 2021 passes through the first qubit, this indicates that the control line passing through the bit will affect the bit through which the line passes, such as signal crosstalk. Because the bit control line 2021 is expected to be designed to operate the second qubit, if it can operate the first qubit, it indicates that the signal of the bit control line 2021 has undesirably leaked to the first qubit and implemented an operation on the first qubit. Such signal leakage to the bit of the unintended operation can be identified as crosstalk.

[0088] When the above situation is identified, i.e. there is indeed crosstalk, it can be considered to change the position of the bit control line 2021, and then test again to determine whether the change of position can eliminate or weaken the crosstalk. Or in some structures, it can also be tried to weaken the crosstalk by setting a shielding structure (such as an air strip, an air bridge, etc. to be mentioned later).

[0089] In some other examples, the inventors also propose another crosstalk test structure. It includes a bit layer 101 and a line layer 102 opposite to each other.

[0090] Among them, the bit layer 101 has a first quantum bit, a second quantum bit, and a bit reading structure. The bit reading structure includes a function of reading the first quantum bit; further, the bit reading structure can also include a function of reading the second quantum bit.

[0091] Corresponding to the reading operation of the first bit, the bit reading structure for example includes a first bit reading resonant cavity. Corresponding to the reading operation of the second bit, the bit reading structure for example can also include a second bit reading resonant cavity.

[0092] In order to simplify the line and reduce the operation difficulty, for the scenario that the bit reading structure can read the first quantum bit and the second quantum bit respectively, the bit reading structure can also include a reading bus which is coupled with the reading resonant cavities corresponding to the two bits respectively. Therefore, by the difference of the reading signal transmitted by the reading bus, the independent reading operation of the first quantum bit or the second quantum bit can be realized on demand. Therefore, in such examples, the bit reading structure can include a reading bus and a reading resonant cavity. When it is needed to read two bits, the reading resonant cavity therein will include a first reading resonant cavity coupled with the first quantum bit, and a second reading resonant cavity coupled with the second quantum bit.

[0093] Based on this, a reading bus can be used to read different bits without the need to design corresponding reading lines for different bits. That is, the reading operation of multiple bits is completed, each bit has a corresponding reading resonant cavity, but it is not necessary to set a separate reading line for each bit, but a reading bus can be used. When actually performing the reading operation, the reading bus transmits a reading signal and acts on the reading resonant cavity, and then the reading resonant cavity acts on the bit, so that the bit can be read, for example, with dispersion.

[0094] Now turn to the line layer 102 of the test structure. In the line layer 102, there is a first control line 301 and a second control line (not shown). Among them, the first control line 301 is coupled with the first quantum bit and is expected to be designed to operate the first quantum bit; the second control line is coupled with the second quantum bit and is expected to be designed to operate the second quantum bit.

[0095] In addition, the first control line 301 and the second control line are respectively positioned such that the first control line 301 can operate the first qubit as intended. Meanwhile, the first control line 301 does not pass through other qubits except the first qubit in the projection trajectory of the bit layer 101; therefore, the first control line 301 does not operate the second qubit as intended. The second control line is configured to operate the second qubit, and the second control line passes through the first qubit in the projection trajectory of the bit layer 101.

[0096] As described above, the control line passing through the bit can cause crosstalk to the bit. Therefore, in this example, the second control line passes through the first qubit, and therefore, it can also have an impact on the first qubit.

[0097] Therefore, when a control signal corresponding to the first qubit is transmitted through the second control line, if the relevant information of the first qubit can be read through the reading structure, it also indicates that the configuration of the second control line passing through the first qubit can cause the adverse effect of crosstalk to the first qubit.

[0098] In the test structure described above, the first control line 301 and the second control line can be control lines in the form of operating bit transitions (such as xy control lines, or bit transition control lines), or can also be control lines in the form of operating bit frequencies (such as z control lines, or bit frequency control lines). The two control lines can be independently selected as any type of control line, and both can be the same type or different types. That is, the first control line 301 and the second control line can be configured in different ways in different examples.

[0099] In the case where the two control lines are of the same type, in some cases, the first control line 301 and the second control line are bit transition control lines; in other cases, the first control line 301 and the second control line are bit frequency control lines. For examples where the two control lines are of different types, in some cases, the first control line 301 is, for example, a bit frequency control line, and the second control line is, for example, a bit transition control line.

[0100] The above discusses that the control line type can have multiple configuration options, but the number of controls can also be configured as needed. Therefore, in addition to having the first and second control lines in the test structure, in other examples, a third control line 303 configured to operate the first qubit can also be provided in the wiring layer 102 according to actual needs; as Figure 4 shown.

[0101] Similar to the first control line 301, the third control line 303 is configured to operate the first qubit without passing through other qubits except the first qubit in the projection trajectory of the bit layer 101. Alternatively, in some examples, the second qubit can also be configured with an additional control line. Thus, the wiring layer 102 can further include a fourth control line configured to operate the second qubit; the fourth control line is configured to operate the second qubit without passing through other qubits except the second qubit in the projection trajectory of the bit layer 101.

[0102] As an example of the type of control line, the second control line and the fourth control line can be bit transition control lines, respectively, while the second control line and the fourth control line are coupled to the second qubit at different positions, respectively.

[0103] As an example of the type of control line, the second control line and the fourth control line can be bit transition control lines, respectively, while the second control line and the fourth control line are coupled to the second qubit at different positions, respectively. Figure 4 As an example of the type of control line, the second control line and the fourth control line can be bit transition control lines, respectively, while the second control line and the fourth control line are coupled to the second qubit at different positions, respectively.

[0104] In this way, the first control line 301 and the third control line 303 can be used to determine whether the operation of the control line at different positions of the bit on the qubit has the same or equivalent operation, and can be used to determine the crosstalk between the wiring and the bit, or between the wirings in other examples, thereby helping to study and optimize the wiring configuration in the bit expansion.

[0105] For the same bit, if the distance between the control line of the same structure at different positions (the first control line 301 and the third control line 303) and the bit arm is the same, for example, the distance between the first control line 301 and the first qubit is equal to the distance between the third control line 303 and the first qubit. Then the information obtained by the control line at different positions on the corresponding bit is expected to be the same. Therefore, in some examples, when the first control line 301 cannot be conveniently or without interference, the third control line 303 can be used instead of the first control line 301 to operate the corresponding bit.

[0106] The distance between the first control line and the first qubit can be defined by the vertical distance between the end of the projection of the first control line on the bit layer and the capacitor plate of the first qubit. Alternatively, the distance between the second control line and the first qubit can be defined by the vertical distance between the end of the projection of the second control line on the bit layer and the capacitor plate of the first qubit. In addition, in other examples, the distance between the control line and the bit can also be determined by the ground distance through the bit, because it can be relatively more convenient or direct to measure in some cases.

[0107] Alternatively, in other examples, the first control line 301 and the third control line 303 can be configured differently based on the needs, so that there is a difference in the results of the operation of the two control lines on the bit. Such a difference can be used to identify or identify the influence of control lines at different positions on the bit.

[0108] When the number of control lines has multiple control lines (these control lines have different or the same type), the distance between the control lines can also be considered in some examples, and the crosstalk test and judgment are made accordingly, and then the arrangement of the control lines can be optimized. Alternatively, the width of the control line and the influence of the crosstalk can also be further investigated.

[0109] For example, one control line has a large ground distance at the end, and the other control line has a small ground distance at the end; or one control line has a large width, and the other control line has a small width. For example, Figure 5 A, B and C in the table. Wherein A represents a control line distribution in which the control line has a first width and a first ground distance; wherein B represents a control line distribution in which the control line has a first width and a second ground distance greater than the first ground distance; and wherein C represents a control line distribution in which the control line has a third width greater than the first width and a third ground distance greater than the first ground distance.

[0110] Experiments show that by appropriately selecting and adjusting the width and ground distance of the control line, the crosstalk can be suppressed and weakened. This can be explained as:

[0111] From the perspective of electromagnetic radiation, charges are gathered at the top end of the control line and radiate outward. Then, as the ground distance of the control line increases, the positive and negative charges cannot form a loop due to the large distance; or only a small amount of positive and negative charges form a loop, while the vast majority of charges can only return along the original path (as designed), so the crosstalk is reduced.

[0112] In addition, the width of the control line (such as the xy line) is related to the number and energy of the charges, and the range of radiation can be determined at a certain width; and if the width of the control line increases, it will also cause the ground distance to increase, and the vast majority of charges can only return along the original path (as designed), so the crosstalk is reduced.

[0113] In addition to adjusting by the characteristics of the control lines themselves (width, distance to ground, etc.) to test or control crosstalk, the spatial arrangement of different control lines can also be used to test or control crosstalk. For example, the spacing between the xy control lines and the z control lines belonging to the same bit, or the distance between the xy lines of different bits, or the distance between the z lines of different bits, etc., can be used to test or verify whether the arrangement of the control lines (such as the distance between the control lines) has crosstalk, and if so, the strength of the crosstalk. For example, the distance between the first control line 301 of the first qubit and the second control line of the second qubit is not equal to the distance between the second control line of the second qubit and the third control line 303 of the first qubit.

[0114] In Figure 6 An example is shown in which one xy control line is arranged on each of the different capacitor arms in the same bit; meanwhile, each bit in this structure also has a z control line. L1 and L2 represent the distances between the two xy control lines and the z control line, respectively. In this example, neither the xy lines nor the z lines pass through other bits.

[0115] Therefore, by analyzing the different values of L1 and L2 and the corresponding bit read results, it can be obtained that in the same xy line distribution (width and distance to ground), the layout with different distances to the z line has crosstalk or not, and if so, the strength of the crosstalk. Through simulation data, it can be known that in some examples, when the distance between the control lines is greater than, for example, 80 microns, the crosstalk between these control lines can be ignored, i.e., it does not affect the normal bit operation expectation.

[0116] Through the above discussion, it can be known that by changing the width, distance to ground, whether the bit passes through the bit, and selective adjustment of the distance between the control lines of a single control line itself, the control of crosstalk can be achieved, so that it can be used to optimize the layout and wiring of the bit and the control line. It should be noted that although the foregoing is mainly based on the control line, in other examples, the idea of the foregoing scheme can also be extended to the read structure of the qubit or the influence of the spatial arrangement between the control line and the qubit on crosstalk.

[0117] In order to make it easier for those skilled in the art to implement the schemes of the examples of the present application, in the examples of the present application, a crosstalk test method for determining whether the control line of the first qubit has crosstalk on the control line of the second qubit is also proposed.

[0118] Referring to Figure 7 The test method comprises:

[0119] In step S101, a test structure is obtained.

[0120] The test structure has a first qubit and a first control line 301 and a read structure corresponding to the qubit, and a second qubit and a second control line corresponding to the qubit.

[0121] In which two bits are made of capacitors and Josephson structures respectively, and the control lines can be made of coplanar waveguide structures.

[0122] In which two bits are coplanarly distributed, and two control lines are also coplanarly distributed, but the bits and the control lines are out of plane; in specific implementation, they can be alternatively realized in flip-chip. In addition, the trace trajectory of the second control line, the projection in the plane where the bits are located, passes through the capacitor arm of the first qubit.

[0123] Step S102, respectively using the first control line 301 and the second control line to operate the first qubit, and obtaining a read result through the read structure.

[0124] Which includes: using the first control line 301 to transmit a first control signal for operating the first qubit, and performing an operation of reading the first qubit through the read structure to obtain a first read result; and using the second control line to transmit the first control signal, and performing an operation of reading the first qubit through the read structure to obtain a second read result.

[0125] Step S103, comparing the read results to determine the crosstalk situation

[0126] By comparing the first read result and the second read result, it is determined whether the second control line causes crosstalk to the first qubit.

[0127] For example, the first control line 301 is designed to operate the first qubit as expected, so that the bit operation implemented through the first control line 301 can obtain the corresponding read result through the read structure.

[0128] However, the second control line is designed to operate the second qubit as expected, so that the desired or expected result is that the second control line cannot operate the second qubit or cannot operate the second qubit in the expected manner. Then, if an attempt is made to use the second control line to operate the first qubit, and the corresponding or expected read result can also be obtained through the read result, it indicates that the second control line causes crosstalk to the first qubit.

[0129] Similarly, in other examples, different types of control lines for the same bit or the same type of control line can also be examined for whether there will be crosstalk.

[0130] Once crosstalk is confirmed through the above testing methods, appropriate actions can be taken to shield it. The crosstalk shielding scheme can be determined and designed based on how the crosstalk occurs. For example, if the crosstalk is caused by insufficient spacing between control lines, increasing the spacing between them can be considered. Similarly, if the crosstalk is caused by a control line passing through a bit, it can be made to bypass the bit.

[0131] In some examples, methods for masking crosstalk can be implemented, including:

[0132] Perform a crosstalk test method; and when crosstalk is determined to exist, configure a shielding structure between bit layer 101 and line layer 102, the shielding structure being suspended above the position where the projection trajectory of the second control line on bit layer 101 passes through the first qubit, the shielding structure including an air strip or an air bridge.

[0133] This crosstalk shielding scheme can be used in the following scenarios: in flip chips, where control lines and bits are spatially arranged in a non-planar manner, and the projection trajectory of the control lines on bit layer 101 passes through the capacitor plates (more specifically, their capacitor arms) of the bits. In such an example, the control lines generate crosstalk to the bits they pass through, which can be mitigated by... Figure 8 As shown, an air band is configured to shield crosstalk. This air band can be, for example, positioned in the bit layer 101 or the control line layer of the flip chip. Specifically, the air band is positioned to cover the area where the control lines pass through the capacitor arms of the bits, or the area where the two intersect.

[0134] The air band can be set along the routing path of the control line. Figure 8 In the example, the projection shape of the air band onto bit layer 101 is approximately rectangular. Its dimension along the control line trace is larger than the width of the capacitor plate of the corresponding bit. Figure 8 The horizontal dimension in the orientation; simultaneously, the width of the air band ( Figure 8 (Dimensions in the vertical direction of the orientation).

[0135] In other examples, crosstalk issues caused by small distances between control lines can be shielded by using air bridges, such as... Figure 9 As shown. Air bridges can be laid out along the trajectory of the control lines, and their number can be appropriately increased; the spacing between the air bridges is small to increase the ground plane.

[0136] The fabrication of the quantum bits, read structures, control lines, etc. provided by embodiments of the present application can require the deposition of one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the materials selected, deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), and epitaxy, among other deposition processes, can be used to deposit these materials. Illustratively, these include ion beam assisted deposition (IBAD), vacuum evaporation (Evaporation), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), chemical vapor deposition (CVD), sol-gel, and magnetron sputtering, among others.

[0137] Additionally, one or more materials can be removed from the device during the fabrication process. Depending on the material to be removed, the removal process can include, for example, a wet etching technique, a dry etching technique, or a lift-off process. The materials forming the circuit elements described herein can be patterned using known lithographic techniques (e.g., photolithography or e-beam lithography).

[0138] For the sake of brevity, conventional techniques related to semiconductor and / or superconductor devices and integrated circuit (IC) fabrication can or can not be described in detail herein. In addition, the various tasks and process steps described herein can be incorporated in more comprehensive procedures or processes having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor and / or superconductor devices and ICs based on semiconductors / superconductors are well known and so do not need to be described in detail here. Instead, only so much of such steps are

[0139] The embodiments described above by reference to the drawings are exemplary and are intended to explain the present application, and are not intended to limit the present application.

[0140] So that the manner in which the above recited features, advantages and objects of the present application are attained and can be understood in detail, a more particular description of one or more embodiments of the application, briefly summarized above, can be had by reference to the drawings.

[0141] It should be noted that the terms "first", "second", and the like, herein do not necessarily have an ordinal or chronological significance. Rather, these terms are used to distinguish different components or steps in the specification. It is to be understood that the terms "comprises", "comprising", "includes", "including" and the like, are not intended to exclude the presence of one or more other elements or steps. It will be apparent that systems and / or methods, described herein, can be implemented in various forms of hardware, software, or combinations thereof, for any of the embodiments. Favorable results are achieved when any of the systems and / or methods described herein are used to provide a system in which the described processes are performed.

[0142] In addition, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" another layer, region, pattern, or structure, it can be directly on the other layer or substrate, and / or there can also be one or more intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and / or there can also be one or more intervening layers. In addition, references in the various drawings to "the figure" are meant to be generic references to the various figures in the figure set.

[0143] The above detailed description of the embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the application be limited not with this detailed description, but rather by the claims appended hereto.

Claims

1. A crosstalk test structure, characterized by, The application relates to a quantum computer, comprising: a bit layer having a first quantum bit, a second quantum bit, and a bit read structure; a line layer opposite to the bit layer, having a first control line and a second control line respectively coupled with the first quantum bit and the second quantum bit; wherein the first control line and the second control line are respectively positioned so that the first control line is configured to operate the first quantum bit and the projection track of the bit layer does not pass through other quantum bits except the first quantum bit, and the second control line is configured to operate the second quantum bit and the projection track of the bit layer passes through the first quantum bit; the first control line is used for operating the first quantum bit to perform a read operation on the first quantum bit through the read structure to obtain a first read result; the second control line is used for operating the second quantum bit to perform a read operation on the first quantum bit through the read structure to obtain a second read result; the first read result and the second read result are used for comparison to determine whether the second control line has crosstalk to the first quantum bit.

2. The cross-talk test structure of claim 1, wherein, The first control line and the second control line are bit transition control lines or bit frequency control lines; and / or, the bit read structure comprises a read bus, a first read resonant cavity coupled with the first quantum bit, and a second read resonant cavity coupled with the second quantum bit, wherein the read bus is coupled with the first read resonant cavity and the second read resonant cavity respectively.

3. The cross-talk test structure of claim 1, wherein, The line layer further comprises a third control line configured to operate the first quantum bit, and the projection track of the bit layer does not pass through other quantum bits except the first quantum bit; the first control line and the third control line are respectively bit transition control lines, and the first control line and the third control line are respectively coupled with the first quantum bit at different positions.

4. The cross-talk test structure of claim 3, wherein, The distance between the first control line and the first quantum bit is equal to the distance between the third control line and the first quantum bit. and / or, the distance between the first control line and the second control line is not equal to the distance between the second control line and the third control line.

5. The cross-talk test structure of claim 4, wherein, The distance between the first control line and the first quantum bit is defined by the vertical distance between the end of the projection of the first control line on the bit layer and the capacitor plate of the first quantum bit. The distance between the second control line and the first quantum bit is defined by the vertical distance between the end of the projection of the second control line on the bit layer and the capacitor plate of the first quantum bit.

6. The cross-talk test structure of any of claims 1 to 5, wherein, The line layer further comprises a fourth control line configured to operate the second quantum bit, and the projection track of the bit layer does not pass through other quantum bits except the second quantum bit; the second control line and the fourth control line are respectively bit transition control lines, and the second control line and the fourth control line are respectively coupled with the second quantum bit at different positions.

7. The cross-talk test structure of claim 1, wherein, The first control line and the second control line are bit transition control lines, and the test structure further has a first frequency control line located in the wire layer and configured to correspondingly control the frequency of the first quantum bit, and a second frequency control line configured to control the frequency of the second quantum bit, wherein the first frequency control line does not pass through other quantum bits except the first quantum bit in the projection track of the bit layer, the second frequency control line is configured to operate the second quantum bit, and the second control line passes through the first quantum bit in the projection track of the bit layer.

8. A crosstalk test method of determining whether a control line of a first qubit has crosstalk to a control line of a second qubit, the method comprising: The method comprises: obtaining the test structure as claimed in any one of claims 1 to 7; transmitting a first control signal for operating the first quantum bit by using the first control line, and performing an operation of reading the first quantum bit by using the reading structure to obtain a first reading result; transmitting the first control signal by using the second control line, and performing an operation of reading the first quantum bit by using the reading structure to obtain a second reading result; comparing the first reading result and the second reading result to determine whether the second control line has crosstalk to the first quantum bit.

9. A method of crosstalk shielding, characterized by, The method comprises: performing the crosstalk test method as claimed in claim 8; when it is determined that there is crosstalk, configuring a shielding structure between the bit layer and the wire layer, the shielding structure over-arches the position where the projection track of the second control line passes through the first quantum bit in the bit layer, and the shielding structure comprises an air strip or an air bridge.

10. A crosstalk test structure, characterized by, The method comprises: a first chip configured with a first superconducting quantum bit and a second superconducting quantum bit, wherein the first superconducting quantum bit is coupled and configured with a reading structure; a second chip connected and supported to each other at a predetermined interval opposite to the first chip by an interconnection structure, and provided with a bit control line configured to cause the second superconducting quantum bit to transition or change frequency; wherein the bit control line passes through a capacitive arm of the first superconducting quantum bit in the first chip in the projection direction opposite to the chip; the bit control line is used to transmit a control signal for operating the first superconducting quantum bit, so as to perform an operation of reading the first superconducting quantum bit by using the reading structure to obtain a reading result; the reading result is used to determine whether the bit control line has crosstalk to the first superconducting quantum bit.

11. A crosstalk test method of determining whether a bit control line of a second superconducting qubit is crosstalking with a first superconducting qubit, the method comprising: The method comprises: obtaining the test structure as claimed in claim 10; transmitting a control signal for operating the first superconducting quantum bit by using the bit control line, and performing an operation of reading the first superconducting quantum bit by using the reading structure to obtain a reading result; determining whether the bit control line has crosstalk to the first superconducting quantum bit according to the reading result.

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