Pixel and display device for reducing static power consumption

Abstract

A pixel driving circuit according to the present disclosure includes a first circuit that, in a data writing mode, controls a signal related to driving one or more light emitting elements, and a second circuit that, in a driving mode, supplies power to the one or more light emitting elements based on a signal transmitted from the first circuit.

Description

Technical Field

[0001] The present invention relates to a pixel included in a display device, and more particularly to a pixel that reduces static power consumption. Background Technology

[0002] A typical display device includes multiple pixels and is configured to have M*N pixels. Each pixel may include more than one light-emitting element, and is typically composed of three light-emitting elements (red, green, and blue (R, G, B)). Each light-emitting element is called a sub-pixel.

[0003] Among the various methods for controlling driven sub-pixels, there is a PWM control method. This method stores the video data of the sub-frame to be controlled in its built-in memory during a single frame and controls the grayscale using a Pulse Width Modulation (PWM) signal. To control the PWM, the pixel driving circuit for each pixel can be implemented using transistors, but these can be categorized as digital circuits or analog circuits based on the transistor's operating region.

[0004] Digital circuits operate in the cutoff region, corresponding to on-off states, and in the non-saturated region to represent "0" and "1". Conversely, analog circuits (excluding analog switches), such as amplifier (AMP) circuits or bias (BIAS) circuits, operate in the saturation region, and therefore must continuously consume a specified current throughout the circuit's operating time. Since the power required may not always be the same depending on the display driving mode or the screen, a method is needed to reduce static power consumption in pixel driving circuits.

[0005] The background technology described above is technical information that the inventors possessed or obtained during the derivation of this invention, and is not necessarily publicly known technology disclosed to the general public before the application for this invention. Summary of the Invention The technical problem to be solved by the present invention

[0006] The purpose of this disclosure is to provide a low-power pixel driving circuit. The problems to be solved by this disclosure are not limited to those mentioned above; other problems and advantages of this disclosure not mentioned above can be understood through the following description and will become clearer through embodiments of this disclosure. Furthermore, it will be understood that the problems and advantages to be solved by this disclosure can be achieved through the solutions and combinations thereof described in the claims. Technical solution

[0007] The pixel driving circuit according to a first aspect of this disclosure includes: a first circuit, in a data writing mode, controlling signals related to driving one or more light-emitting elements; and a second circuit, in a driving mode, supplying power to the one or more light-emitting elements based on signals transmitted from the first circuit.

[0008] A display device according to a second aspect of this disclosure includes: a display panel including an arrangement of a plurality of pixel driving circuits forming rows and columns; a scan driving circuit that sequentially outputs row signals to the pixel driving circuits arranged in the row direction in the arrangement of the display panel; and a data driving circuit that outputs column signals related to driving light-emitting elements corresponding to each of the plurality of pixel driving circuits to the pixel driving circuits arranged in the column direction in the arrangement of the display panel; each of the plurality of pixel driving circuits is a pixel driving circuit according to the first aspect. Invention Effects

[0009] This invention can reduce the power consumed to drive pixels by reducing the number of times the capacitor is charged.

[0010] Furthermore, the present invention can reduce the power consumed for driving pixels by selectively providing the bias power required for charging the capacitor. Attached Figure Description

[0011] Figure 1 This is a display device including a plurality of pixel driving circuits according to an embodiment of the present disclosure.

[0012] Figure 2 This is a block diagram schematically illustrating a pixel driving circuit according to an embodiment of the present disclosure.

[0013] Figure 3 This is a schematic diagram illustrating the structure and operation of a drive unit according to an embodiment of the present disclosure.

[0014] Figure 4 This is a circuit diagram illustrating the configuration of a sub-driving unit according to an embodiment of the present disclosure.

[0015] Figure 5 This is an example diagram showing the number of times the capacitor section is charged based on capacitor data, according to an embodiment of this disclosure.

[0016] Figure 6 This is an example diagram illustrating whether or not the control bias unit is powered according to an embodiment of the present disclosure.

[0017] Figure 7This is an example diagram illustrating power supply control based on the control bias unit when the number of charging cycles is defined according to an embodiment of the present disclosure.

[0018] Figure 8 This is a circuit diagram of an electric power generation unit according to an embodiment of the present disclosure.

[0019] Figure 9 This is a timing diagram based on the power generation unit's use of row and column signals to output a reference voltage, as described in this specification.

[0020] Figure 10 This is a block diagram that schematically illustrates the configuration of a typical trigger.

[0021] Figure 11 This is a timing diagram of row and column signals in the video data reset interval according to an embodiment of the present disclosure.

[0022] Figure 12 This is an example diagram illustrating the writing of capacitor data and video data and the PWM drive range according to this specification. Detailed Implementation

[0023] The advantages and features of this disclosure, as well as methods for implementing them, will become apparent from the accompanying drawings and detailed description of the embodiments. However, it should be understood that this disclosure is not limited to the embodiments described below, but can be implemented in many different forms and includes all variations, equivalents, or substitutions falling within the spirit and technical scope of this disclosure. The embodiments described below are intended to complete this disclosure, and this disclosure is provided to fully inform those skilled in the art of the scope of the invention. In describing this disclosure, detailed descriptions of specific known techniques will be omitted if it is determined that such descriptions might obscure the gist of the disclosure.

[0024] The terminology used in the embodiments is selected as widely used and common as possible; however, these may be changed based on the intent or case of those skilled in the art, the emergence of new technologies, etc. Furthermore, in certain cases, terms may be arbitrarily chosen by the applicant; in such cases, their meanings will be detailed in the corresponding specification. Therefore, the terms used in this specification should be defined according to their meanings and the entirety of this specification, rather than based on their simple names.

[0025] The terminology used in this application is for illustrative purposes only and is not intended to limit this disclosure. Unless the context clearly specifies otherwise, singular expressions include plural expressions. In this application, terms such as "comprising" or "having" should be understood to specify the presence of features, numbers, steps, actions, elements, components, or combinations thereof as described in the specification, without precluding the presence or additional possibilities of one or more other features or numbers, steps, actions, elements, components, or combinations thereof.

[0026] The terms used in this specification, including ordinal numbers such as "first" or "second," may be used to describe various components, but the components should not be limited by these terms. These terms may be used for the purpose of distinguishing one component from another.

[0027] In the following embodiments, "ON" used in conjunction with a component state can refer to the active state of the component, and "OFF" can refer to the inactive state of the component. When used in association with a signal received by the component, "ON" can refer to a signal activating the component, and "OFF" can refer to a signal deactivating the component. Components can be activated by high or low voltages. For example, a P-type transistor can be activated by a low voltage. An N-type transistor is activated by a high voltage. Therefore, it should be understood that the "ON" voltages of P-type and N-type transistors are opposite (low to high) voltage levels.

[0028] When an element is referred to as being "connected to" another element, it includes all cases where it is directly connected to the other element or intervenes in the other element. Embodiments of the invention will be described in detail below with reference to the accompanying drawings.

[0029] Figure 1 This is a display device including a plurality of pixel driving circuits according to an embodiment of the present disclosure.

[0030] refer to Figure 1 According to an embodiment of the present disclosure, a display device 100 may include a display panel 110, a scanning drive circuit 120, a data drive circuit 130, and a control unit 140.

[0031] In this disclosure, the display panel 110 may include a plurality of pixels (PX). In one embodiment, the plurality of pixels (PX) may be configured as M*N (M and N are natural numbers) pixels arranged in a matrix, but the arrangement of the plurality of pixels (PX) may be arranged in various patterns such as a "Z" shape, depending on other embodiments.

[0032] In this disclosure, the display panel 110 can be implemented as one of the following: liquid crystal display (LCD), light emitting diode (LED) display, organic light emitting diode (OLED) display, active-matrix organic light emitting diode (AMOLED) display, electrochromic display (ECD), digital micromirror device (DMD), actuated mirror device (AMD), grating light valve (GLV), plasma display panel (PDP), electroluminescent display (ELD), or vacuum fluorescent display (VFD). Furthermore, it can be implemented as other types of flat panel displays or flexible displays. As an example, this disclosure will illustrate the display panel 110 as an LED display.

[0033] In this disclosure, each of a plurality of pixels PX may include more than one light-emitting element. In one embodiment, the light-emitting element may be a light-emitting diode (LED). The light-emitting diode may be a micro LED having a size of less than 80 μm. In one embodiment, a pixel PX may output multiple colors by using multiple light-emitting elements of different colors. As an example, a pixel PX may include red, green, and blue light-emitting elements. As another example, a pixel PX may also include a white light-emitting element, which may replace any one of the red, green, and blue light-emitting elements. As yet another example, a pixel PX may also consist of a single white light-emitting element. In embodiments where a pixel PX includes multiple light-emitting elements, each light-emitting element included in a pixel PX is referred to as a "subpixel".

[0034] In this disclosure, each pixel PX may include a pixel driving circuit for driving the light-emitting elements (i.e., sub-pixels) included in the pixel. In this disclosure, the pixel driving circuit can drive the sub-pixels to turn on or off using signals output from the scan driving circuit 120 and / or the data driving circuit 130. In one embodiment, the pixel driving circuit may include at least one transistor and at least one capacitor, etc. In one embodiment, the pixel driving circuit may be implemented using a stacked structure on a semiconductor wafer.

[0035] In this disclosure, the display panel 110 may include one or more scan lines SL1 to SL2 arranged along the row direction. m and one or more data lines DL1 to DL1 arranged along the column direction. n In this disclosure, pixel PX can be located on more than one scan line SL1 to SL2. m With one or more data lines DL1 to DL n At the intersection. Each pixel PX can be connected to any scan line SL. k and any data cable DL k More than one scan line SL1~SL m It can be connected to the scan drive circuit 120, and has more than one data line DL1 to DL2. n It can be connected to the data drive circuit 130.

[0036] In this disclosure, the scan drive circuit 120 can output an output for driving one or more scan lines SL1 to SL2. m The signal of one or more pixels of any scan line (hereinafter referred to as the row signal). Preferably, the scan drive circuit 120 can sequentially select one or more scan lines SL1 to SL2. m For example, pixels connected to the first scan line SL1 can be driven during the first scan drive, and pixels connected to the second scan line SL2 can be driven during the second scan drive. The operation of the scan drive circuit 120 of this disclosure will be described in detail later.

[0037] In this disclosure, the data drive circuit 130 can be driven by one or more data lines DL1 to DL2. n Each pixel outputs a grayscale-related signal (hereinafter referred to as a column signal). A data line is connected to more than one pixel in the vertical direction, but the grayscale-related signal can be input only to pixels connected to the scan line selected by the scan drive circuit 120. The operation of the data drive circuit 130 of this disclosure will be described in detail later.

[0038] In this disclosure, the control unit 140 can output control signals to execute the operation of the scan drive circuit 120 and the data drive circuit 130. The control unit 140 can output control signals corresponding to image data equivalent to an image frame to the scan drive circuit 120 or the data drive circuit 130.

[0039] Figure 2 This is a block diagram schematically illustrating a pixel driving circuit according to an embodiment of the present disclosure.

[0040] refer to Figure 2 The pixel driving circuit 200 of this disclosure may include a first circuit 210 and a second circuit 220. In this disclosure, the first circuit 210 may also be referred to as a digital circuit and can operate in data writing mode. In this disclosure, the second circuit 220 may also be referred to as an analog circuit and can operate in driving mode.

[0041] although Figure 2 As not shown, but will be readily understood by those skilled in the art, the pixel driving circuit 200 of this disclosure may include: terminals VCC and GND for receiving power, terminals R, G, and B for outputting light emission control signals to one or more light-emitting elements, terminal ROW for receiving row signals output from the scan driving circuit 120, and terminal COL for receiving column signals output from the data driving circuit 130; and may be configured with electrical connections to input and output power and signals through the aforementioned terminals.

[0042] In one embodiment, the first circuit 210 may include a control unit 211 and a memory 212. As described above, the first circuit 210 can operate in a data write mode.

[0043] In one embodiment, memory 212 may be configured to store data related to the control of pixels or light-emitting elements of this disclosure. In one embodiment, memory 212 may include a video memory (not shown) and a charging control memory (not shown). The video memory may store data related to the driving of one or more light-emitting elements, i.e., video data. The video data stored in the video memory may refer to data related to the grayscale of light emitted by the light-emitting elements within one frame or one PWM cycle. The charging control memory may store capacitor data related to the charging of capacitors included in the driving unit 222 described later. The operation of the memory of this disclosure will be described in detail later.

[0044] In one embodiment, the control unit 211 can control the operation of the capacitor included in the drive unit 222. In one embodiment, the control unit 211 can control whether or not to charge the capacitor based on capacitor data stored in the charging control memory. The operation of the capacitor of this disclosure will be described in detail later.

[0045] In one embodiment, the second circuit 220 may include a biasing section 221 and a driving section 222. As described above, the second circuit 220 can operate in a driving mode.

[0046] In one embodiment, the driving unit 222 can control the power supply to one or more light-emitting elements based on data stored in the memory 212. Specifically, the driving unit 222 can supply power to one or more light-emitting elements based on video data stored in the video memory. In one embodiment, the driving unit 222 can be configured to control the power supply to the light-emitting elements according to a PWM driving method. Since the PWM driving method is a well-known technology to those skilled in the art, its detailed description will be omitted.

[0047] In one embodiment, the biasing unit 221 may provide bias power to the driving unit 222. To supply bias power, the biasing unit 221 may be connected to a terminal VCC for receiving power. The operation of the biasing unit of this disclosure will be described in detail later.

[0048] The pixel driving circuit 200 of this disclosure may further include a power generation unit (not shown). The power generation unit can output a reference voltage VDD to the memory 212 based on the row signal output from the scan driving circuit 120 and the column signal output from the data driving circuit 130. The configuration and operation of the power generation unit of this disclosure will be described later.

[0049] The pixel driving circuit 200 of this disclosure may further include a reset unit (not shown), which outputs a reset signal RSTB to the memory 212 for initializing data stored in the memory 212. The configuration and operation of the reset unit of this disclosure will be described later.

[0050] Figure 3 This is a schematic diagram illustrating the structure and operation of a drive unit according to an embodiment of the present disclosure.

[0051] refer to Figure 3 The diagram shows a drive unit 330 including a control unit 310, a bias unit 320, and one or more sub-drive units 331. Figure 3 In the middle, the control unit 310 can be connected with... Figure 2 The configuration corresponding to the control unit 211, the bias unit 320 can be the same as... Figure 2 The configuration corresponding to the bias unit 221, the driver unit 330 can be the same as... Figure 2 The configuration corresponding to the driver unit 222.

[0052] In this disclosure, the driving unit 330 can control the power supply to one or more light-emitting elements. In one embodiment, the driving unit 330 may include one or more sub-driving units 331, each corresponding to one or more light-emitting elements. That is, a pixel in this disclosure may include one or more light-emitting elements, and a sub-driving unit 331 may be configured to correspond to one light-emitting element.

[0053] As described above, the driving unit 330 can control the power supply to one or more light-emitting elements based on data stored in the memory. Specifically, the sub-driving unit 331 can control the power supply to the light-emitting elements based on data stored in the memory. The sub-driving unit 331 can supply power to the light-emitting elements based on video data stored in the video memory. In one embodiment, the sub-driving unit 331 may include a capacitor unit for charging the power required to drive the light-emitting elements; the capacitor unit of this disclosure will be described in detail later.

[0054] In this disclosure, the bias unit 320 can supply bias power to the driving unit 330; specifically, the bias unit 320 can supply bias power to the sub-driving unit 331. The bias unit 320 can be connected to the VCC terminal of the pixel driving circuit to receive power, so as to supply bias power to the sub-driving unit 331.

[0055] In one embodiment, whether the bias unit 320 supplies power to the sub-drive unit 331 can be controlled by a control signal CTRL output from the control unit 310. In one embodiment, the control signal CTRL for controlling whether to supply power to the sub-drive unit 331 of the bias unit 320 can be output from the control unit 310. In one embodiment, the function of controlling the operation of the capacitor of the control unit 310 can be performed by a configuration different from that of the control unit 310, but is not limited thereto.

[0056] In one embodiment, the power supplied by the biasing unit 320 can be stored in a capacitor included in the sub-drive unit 331.

[0057] In one embodiment, the control unit 310 can control whether the capacitor is charged based on capacitor data stored in the memory. In other words, the control unit 310 can control whether to supply power to the bias unit 320 and whether to charge the capacitor by outputting a control signal CTRL based on the capacitor data stored in the memory.

[0058] Figure 4 This is a circuit diagram illustrating the configuration of a sub-driving unit according to an embodiment of the present disclosure.

[0059] refer to Figure 4According to one embodiment, the sub-driving unit 400 may include a capacitor unit 401, a charging unit 402, a discharging unit 403, and a switching unit SW. Figure 4 In the middle, the sub-drive unit 400 can be corresponding to Figure 3 The configuration of the sub-drive unit 331.

[0060] refer to Figure 4 The charging unit 402 can be connected between the pixel positive power supply and the pixel negative power supply. The discharging unit 403 can be connected between the pixel positive power supply and the pixel negative power supply. The capacitor unit 401 can be connected between the charging unit 402 and the discharging unit 403. The switch unit SW can be connected between the charging unit 402 and the capacitor unit 401. The switch unit SW can be turned on or off by the control signal CTRL output from the control unit.

[0061] Figure 4 The example shown is of capacitor section 401 consisting of two capacitors C1 and C2. The first capacitor C1 can be connected between the first connection line for connecting charging section 402 and discharging section 403 and the pixel negative power supply GND. The second capacitor C2 can be connected between the second connection line for connecting charging section 402 and discharging section 403 and the pixel negative power supply GND. In this case, charging section 402 may include a first charging transistor T connected between the pixel positive power supply and the pixel negative power supply, respectively, to the first capacitor C1 and the second capacitor C2. C1 Second charging transistor T C2 The discharge section 403 may include a first discharge transistor T connected between the pixel positive power supply and the pixel negative power supply, and respectively connected to the first capacitor C1 and the second capacitor C2. D1 Second discharge transistor T D2 The switching section SW may be included in the first charging transistor T. C1 The first switching element SW1 connected to the first capacitor C1 and the second charging transistor T C2 A second switching element SW2 is connected between the second capacitor C2. The switching unit SW may also include a third switching element SW3 connected between the first charging transistor TC1 and the second charging transistor TC2. The sub-driving unit 400 may further include a PWM switching element SW connected in series with the discharge unit 403 between the pixel positive power supply and the pixel negative power supply. PWM PWM switching element SW PWM It can be turned on or off based on the video data stored in the memory.

[0062] Figure 4 The sub-drive unit 400 is provided as an example, and the components included in the sub-drive unit 400 and the circuit structure according to the connection of the components can be compared with... Figure 4 The illustrated embodiments are configured differently. For example, in Figure 4 The diagram shows a sub-driving section 400 including transistors such as N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs). In another embodiment, the sub-driving section 400 may include transistors such as p-type field-effect transistors (PMOSFETs), and in such an embodiment, the first capacitor C1 and the second capacitor C2 may be connected to the terminal VCC for receiving power instead of the pixel negative power supply GND.

[0063] Figure 5 This is an example diagram showing the number of times a capacitor is charged based on capacitor data, according to an embodiment of the present disclosure.

[0064] refer to Figure 5 This illustrates an example where the capacitor data stored in memory is 3 bits and the video data is 12 bits.

[0065] In this disclosure, the capacitor data can correspond to the maximum number of times the capacitor can be charged within a period (i.e., a single frame). That is, the number of times the capacitor is charged within a single frame can be defined by the capacitor data.

[0066] refer to Figure 5 For example, when the capacitor data is <000> When the capacitor is charged, the control unit can output a control signal to charge the capacitor 12 times in one cycle. <001> When the capacitor data is... <010> When the capacitor data is... <011> At that time, the control unit can output a control signal to charge the capacitor three times in one cycle. That is, the value of the capacitor data stored in the memory is a value relating to the number of times the capacitor is charged within one cycle, and the control unit can output a control signal to control the charging of the capacitor based on the capacitor data stored in the memory. However, Figure 5 The example shown is for illustrative purposes only; the number of bits in the capacitor data and the number of times the capacitor data is charged can be set appropriately in any way.

[0067] Figure 6 This is an example diagram illustrating whether or not the control bias unit is powered according to an embodiment of the present disclosure.

[0068] In this disclosure, as described above, the control unit can control whether the bias unit is powered or not via a control signal.

[0069] In one embodiment, the control unit can control the bias unit so that the bias unit is powered only in drive mode. As described above, the pixel driving circuit of this disclosure can correspond to two modes, namely data writing mode or drive mode. Only when the pixel driving circuit is in drive mode, the control unit reduces power consumption by activating (turning on) the bias unit.

[0070] In one embodiment, after the capacitor is charged by the bias power supplied by the bias unit, the control unit controls the bias unit to interrupt the power supply to the bias unit. After the capacitor is charged, power consumption can be reduced by limiting the operation of the bias unit.

[0071] In one embodiment, after the capacitor is charged by the bias power supplied by the bias unit, the control unit can control the bias unit to interrupt the power supply. However, it can only control the bias unit to supply the bias power when the bit value of the video data is 1. In other words, in this embodiment, the control unit can read the video data stored in the memory and activate the bias unit only when the bit value of the video data is 1. After the capacitor is charged by the bias power supply, the operation of the bias unit can be limited. In this embodiment, the control unit can not activate the bias unit when the bit value of the video data is 0. When the value of the video data is 0, it is not necessary to drive the light-emitting element, and therefore it is not necessary to charge the capacitor. In this embodiment, by controlling the operation of the bias unit, if it is not necessary to charge the capacitor, the bias power supply is blocked, thereby reducing power consumption.

[0072] refer to Figure 6 The diagram illustrates a timing diagram of an embodiment in which the control unit controls the bias unit so that the bias unit supplies bias power only when the value of the video data is 1.

[0073] For example, refer to Figure 6 When the video data is (11111111111), since all the bit values ​​of the video data are 1, the control unit can start the bias unit corresponding to all the bits of the video data.

[0074] On the other hand, reference Figure 6 When the video data is (10101010101), the control unit activates the bias unit only when the bit value of the video data is 1. Conversely, when the bit value of the video data is 0, as described above, since it is not necessary to drive the light-emitting element, the capacitor is not charged. In this embodiment, the capacitor is prevented from being charged by blocking the bias power supply required for charging the capacitor.

[0075] refer to Figure 6 This shows that when the video data is (00000000111), the corresponding bit value of the video data is 0, and the capacitor is not charged.

[0076] On the other hand, reference Figure 6 When the video data is (00000000000), the value of all video data is 0. Therefore, the control unit can not activate the bias unit for all bits of the video data. As a result, the capacitor unit is not charged for all bits.

[0077] Figure 7 This is an example diagram illustrating the power supply when the number of charging cycles of the control bias unit according to an embodiment of the present disclosure is defined.

[0078] For reference Figure 5 The number of times the capacitor is charged within a single frame can be defined using capacitor data, and as referenced... Figure 6 The control unit may activate the bias unit only when the bit value of the video data is 1.

[0079] In one embodiment, when the number of charging cycles is defined, the control unit controls the bias unit to supply power only when the bit value of the video data is 1. After the capacitor is charged by the bias power supply, the control unit controls the bias unit to interrupt the power supply. Furthermore, the control unit can control the bias unit to supply the bias power supply as many times as the number of charging cycles within a single frame. Specifically, the control unit activates the bias unit only when the bit value of the video data is 1, and can limit the number of times the bias unit is activated within a single frame. That is, when the number of bits with a value of 1 in the video data within a single frame exceeds the number of charging cycles, the control unit can control the operation of the bias unit to charge the capacitor as many times as the number of charging cycles for the bits with a value of 1 in the video data, and will not charge the capacitor for the remaining cycles. Preferably, the bias unit is activated for the high-order bits corresponding to the bit value of 1, and after the number of times the bias unit is activated reaches the number of charging cycles defined within a single frame, the bias unit may not be activated for the low-order bits. In this embodiment, the control unit blocks the supply of the bias power supply for bits exceeding the number of charging cycles, thereby reducing power consumption.

[0080] refer to Figure 7 A timing diagram is shown to illustrate an embodiment of charging of a capacitor section according to multiple charging cycles when the video data is (10101010101).

[0081] refer to Figure 7The diagram illustrates an example where the number of charging cycles is undefined, or the total number of times (All times) is defined as the capacitor being charged for all bits of the video data with a bit value of 1 within a single frame. As shown, when the number of charging cycles is undefined, or defined as the capacitor being charged for all bits of the video data within a single frame, the control unit can control the capacitor to be charged in all cases where the corresponding bit value of the video data is 1. In other words, the control unit can control the bias unit to ensure that the bias power supply is provided in all cases where the corresponding bit value of the video data is 1 within a single frame.

[0082] refer to Figure 7 The figure illustrates an example where, when the number of charging cycles is defined as 1, the capacitor section is charged only for one bit of the video data with a bit value of 1 within a single frame. As shown, when the number of charging cycles is defined as 1, the control unit controls the capacitor section to be charged only for one bit of the video data with a bit value of 1. In other words, the control unit can control the bias unit so that the bias power supply is supplied only once within a single frame.

[0083] Similarly, refer to Figure 7 This illustrates an example where, when the number of charging cycles is defined as K, the capacitor is charged only for K bits of the video data whose bit value is 1 within a single frame. As shown in the figure, when the number of charging cycles is defined as K, the control unit controls the capacitor to be charged only for K bits of the video data whose bit value is 1. That is, in Figure 7 In the example shown, there are 6 bits with a value of 1 in the video data within a single frame. However, since the number of charging times is defined as K, the capacitor section only charges K bits out of the 6 bits, and the remaining bits may not be charged. In other words, the control section can control the bias section to supply bias power a maximum of K times within a single frame.

[0084] refer to Figure 7 ,exist Figure 7 In the example shown, since there are 6 bits with a value of 1 in the video data within a single frame, when the number of charging times is defined as a value of 6 or more, all bits with a value of 1 can be charged, and the capacitor will not be charged.

[0085] exist Figure 7 In the example shown, when the number of charging cycles is defined, the capacitor is charged only if the higher-order bits of the corresponding video data bits are 1. However, this is provided as an example and any suitable method can be applied.

[0086] Figure 7 The video data shown is provided as an example, and those skilled in the art will understand that the manner of this disclosure can be applied to video data including any number of bits, bit values, and the number of bits with a bit value of 1 within a single frame.

[0087] In one embodiment, the number of times the capacitor is charged within a single frame can be user-defined.

[0088] The following will describe a method for outputting a reference voltage to the memory of this disclosure and writing data into the memory.

[0089] Figure 8 This is a circuit diagram of an electric power generation unit according to an embodiment of the present disclosure.

[0090] As described above, a pixel driving circuit according to an embodiment of the present disclosure may include a power generation unit. The power generation unit can output a reference voltage to the memory using a row signal output from the scan driving circuit and a column signal output from the data driving circuit.

[0091] refer to Figure 8 The power generation unit 800 according to an embodiment of this specification may include a transistor 810, a NAND gate 820, and a delay element 830. The power generation unit 800 may be connected to the row signal input terminal ROW and the column signal input terminal COL to receive row and column signals. Furthermore, the power generation unit 800 may include a reference voltage output terminal that outputs a reference voltage VDD_INT to a memory.

[0092] Transistor 810 can be positioned between the input terminal ROW of the row signal and the output terminal of the reference voltage. According to one embodiment, transistor 810 can be a PMOSFET. The drain and source terminals of the PMOSFET can be connected to the input terminal ROW of the row signal and the output terminal of the reference voltage, and the gate terminal of the PMOSFET can be connected to the signal output terminal of a NAND gate. For reference, the PMOSFET is off when the signal input to the gate terminal is logic high ("1"), and on when the signal input to the gate terminal is logic low ("0").

[0093] The NAND gate 820 can be positioned between the middle terminal (gate terminal) of the transistor 810 and the column signal input terminal COL. As a logic circuit element, the NAND gate 820 can have two input terminals and one output terminal. The column signal can be input to one of the two input terminals of the NAND gate 820, while the delayed row signal is input to the other input terminal. For reference, the NAND gate 820 outputs a logic low level only when all inputs are logic high ([1, 1]), and outputs a logic high level in all other cases ([0, 0], [1, 0], [0, 1]).

[0094] The delay element 830 can be positioned between the input ROW of the row signal and the NAND gate 820. The delay element 830 can receive the row signal, delay it for a predetermined time, and output the delayed row signal to either of the inputs of the NAND gate 820. As an example, the delay time can be 0.5ns to 1ns.

[0095] Figure 9 This is a timing diagram based on the power generation unit's use of row and column signals to output a reference voltage, as described in this specification.

[0096] refer to Figure 9 "ROW" indicates that the row signal is input through the row signal input terminal, and "ROW_D" indicates that the row signal is input via a delay element (e.g., Figure 8 The delay element 830) delays the row signal, "COL" indicates the column signal input through the column signal input terminal, and "CTRL" indicates the signal from the NAND gate (e.g., Figure 8 The signal output by the NAND gate 820.

[0097] First, the row signal can transition from a logic high state to a logic low state, remain at the logic low state for a predetermined time, and then transition back to a logic high state. The column signal can also transition from a logic high state to a logic low state, remain at the logic low state for a predetermined time, and then transition back to a logic high state. In this case, the column signal can transition from a logic high state to a logic low state slightly earlier than the row signal transitions to a logic low state. Furthermore, when the data to be input into the memory is either a logic low level ("0") or a logic high level ("1"), the column signal can have a time difference in maintaining a logic low level. When corresponding to logic low level ("0") data, the column signal can transition from a logic low level to a logic high level after the row signal transitions to a logic high level (see reference). Figure 9 (a)). When corresponding to logic high ("1") data, the column signal can change from logic low to logic high before the row signal changes to logic high (see reference). Figure 9 (b)

[0098] Based on the timing of the delayed row and column signals, a NAND gate can transition from logic low to logic high and then back to logic low. As described above, a transistor (e.g., Figure 8 The transistor (810, PMOSFET) can be turned on (On) by a logic low level signal, turned off (Off) by a logic high level signal, and then turned on (On) again by a logic low level signal.

[0099] refer to Figure 9(c) When the row signal ROW is logic high, the transistor is on, thus the reference voltage VDD_INT can be output to the reference voltage output terminal. Conversely, when the row signal ROW is logic low, the transistor is off, thus maintaining the reference voltage VDD_INT at the reference voltage output terminal. For this purpose, the power generation unit (e.g., Figure 8 The power generation unit 800 may also include a capacitor disposed between the output terminal of the reference voltage and the circuit ground (e.g., Figure 8 (Capacitor 840). Since the transistor is in the off state, the capacitor can serve to maintain the reference voltage VDD_INT at the output of the reference voltage.

[0100] Figure 10 This is a block diagram that schematically illustrates the configuration of a typical trigger.

[0101] refer to Figure 10 The column signal can be input to the data signal input terminal D of the flip-flop FF, and the row signal can be input to the clock signal input terminal CLK. (Reference) Figure 9 In (a), when the column signal is at a logic low level at the rising edge (rising edge) of the instant the row signal changes from logic low to logic high, logic low-level data ("0") can be input to the flip-flop FF. Furthermore, refer to... Figure 9 (b) When the column signal is at a logic high level at the instant the row signal changes from logic low to logic high (rising edge), the logic high-level data ("1") can be input to the flip-flop FF. That is, in this disclosure, while outputting reference power from the power generation unit through the timing of the row and column signals, capacitor data or video data can be input using the same signal. In this disclosure, the memory can be illustrated by an example consisting of multiple flip-flops, but is not limited thereto.

[0102] On the other hand, as described above, the pixel driving circuit of this disclosure may also include a reset unit that outputs a reset signal RSTB, used to initialize data stored in the memory, to the memory.

[0103] Figure 11 This is a timing diagram of row and column signals in the video data reset interval according to an embodiment of the present disclosure.

[0104] refer to Figure 11The reset unit 1100 may have a data signal input terminal D for inputting row signals, a clock signal input terminal CLK for inputting column signals, and a signal output terminal Q for outputting a reset signal RSTB. In this case, the column signal input to the clock signal input terminal CLK can be input in a state where the column signal output from the data drive circuit is inverted. Therefore, the reset unit 1100 may also include an inverter (not shown) for inverting the signal input to the clock signal input terminal CLK to invert the column signal.

[0105] During the video data reset interval RESET, the scan drive circuit can output a row signal that remains low for a longer period than the reference interval. During the video data reset interval RESET, the data drive circuit can output a column signal that transitions from logic high to logic low while the row signal remains low. In this disclosure, the reset signal RSTB can initialize data stored in memory at a logic low level ("0"). Therefore, it should be understood that... Figure 11 The reset signal RSTB shown is the signal in the state where the column signal has not been inverted.

[0106] Figure 12 This is an example diagram illustrating the writing of capacitor data and video data and the PWM drive range according to this specification.

[0107] refer to Figure 12 In one embodiment, (a) the row signal and column signal can be signals that include a capacitor data write interval, a video data write interval, and a PWM drive interval for each cycle (1H). That is, new capacitor data can be input in each cycle.

[0108] refer to Figure 12 In another embodiment (b), the row and column signals may be signals that include a single capacitor data write interval, a video data write interval for each cycle (1H), and a PWM drive interval. That is, this embodiment relates to the case where the capacitor data is input only once and will not change without additional control.

[0109] refer to Figure 12 In another embodiment, (c) the row signal and column signal can be repeating signals that include a capacitor data write interval for each predetermined period, a video data write interval for each period (1H), and a PWM drive interval. That is, new capacitor data can be input at each predetermined interval.

[0110] In the above embodiments, the period H can correspond to a frame or a pre-divided interval within a frame.

[0111] The aforementioned scan drive circuit and data drive circuit may include processors, application-specific integrated circuits (ASICs), other chipsets, logic circuits, registers, communication modems, data processing devices, etc., known in the art to which this invention pertains, to execute the various control logics described above. Furthermore, when the control logic is implemented in software, the scan drive circuit and data drive circuit can be implemented through a collection of program modules. In this case, the program modules can be stored in a storage device and executed by the processor.

[0112] The program may include code encoded in computer languages ​​such as C / C++, C#, JAVA, Python, and machine language, which can be read by the computer's processor (CPU) through a computer device interface, allowing the computer to read and execute the methods implemented by the program. Such code may include functional code related to functions that define the necessary functionality for executing methods, and control code related to the executable program required by the computer processor to perform functions according to the prescribed program. Furthermore, this code may also include memory reference-related code regarding the location (address number) of additional information or media required by the computer processor to perform functions in the computer's internal or external memory. Additionally, if the computer processor needs to communicate with any other remote computer or server to perform functions, the code may also include communication-related code regarding how to use the computer's communication module to communicate with any other remote computer or server, and what information or media to send / receive during communication.

[0113] The storage medium for a stored program is not a short-term data storage medium such as registers or cache memory, but rather a medium that stores data semi-permanently and can be read by a device. Specifically, examples of storage media include, but are not limited to, read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disks, and optical data storage devices. That is, the program can be stored on multiple recording media on various servers accessible to the computer, or on multiple recording media on the user's computer. Furthermore, the storage media can be distributed across computer systems connected via a network, and computer-readable code can be stored in a distributed manner.

[0114] Those skilled in the art related to this embodiment will understand that it can be implemented in modified forms without departing from the essential characteristics described above. Therefore, the spirit of the invention should not be limited to the embodiments described above, and all scopes, not only the claims, but also those equivalent to or modified from those claims, fall within the spirit of the invention.

Claims

1. A pixel driving circuit, wherein, include: The first circuit, in data writing mode, controls the control signals related to driving one or more light-emitting elements; as well as In driving mode, the second circuit supplies power to the one or more light-emitting elements based on the control signal transmitted from the first circuit. The second circuit includes: A driving unit, configured to supply power to the one or more light-emitting elements, wherein the driving unit includes one or more capacitors for charging the power required to drive the one or more light-emitting elements; and The biasing unit is configured to provide bias power to the driving unit. The first circuit includes: A video memory configured to store bit values ​​of video data associated with driving the one or more light-emitting elements; A charging control memory configured to store capacitor data related to capacitor charging; and The control unit is configured to control the bias unit based on the video data, thereby controlling whether a bias power supply is supplied to the bias unit, and wherein the control unit is configured to control the bias unit to supply power only in response to a bit value of 1 in the video data. The first circuit is configured to store capacitor data related to the charging of the capacitor and output the control signal corresponding to the video data and the capacitor data.

2. The pixel driving circuit according to claim 1, wherein, The driving unit includes: one or more sub-driving units, each corresponding to one or more light-emitting elements; Wherein, each of the one or more sub-driving parts includes a capacitor; The control unit is configured to control whether to charge the capacitors included in the one or more sub-drive units based on the capacitor data.

3. The pixel driving circuit according to claim 1, wherein, The control unit is configured to control the bias unit such that the bias unit provides the bias power supply only in the drive mode.

4. The pixel driving circuit according to claim 1, wherein, After the capacitor is charged by the bias power supply, the control unit is configured to control the bias unit to interrupt the power supply to the bias unit.

5. The pixel driving circuit according to claim 1, wherein, When the number of charging cycles is defined as K, the control unit is configured to control the bias unit so that the bias power supply can achieve a maximum of K times within a single frame.

6. The pixel driving circuit according to claim 5, wherein, The number of charging cycles is user-defined.

7. A display device, wherein, The display device includes: The display panel includes an arrangement of multiple pixel driving circuits forming rows and columns. The scan driving circuit sequentially outputs row signals to the pixel driving circuits arranged along the row direction in the display panel, and... The data driving circuit outputs column signals related to driving the light-emitting elements corresponding to each of the plurality of pixel driving circuits to the pixel driving circuits arranged in the column direction in the display panel. Each of the plurality of pixel driving circuits is a pixel driving circuit according to any one of claims 1 to 6.

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