A shielded gate trench VDMOS device and its manufacturing method

Abstract

This invention discloses a shielded gate trench VDMOS device, comprising an N-drift region with a channel within it, and a gate polysilicon layer and a source polysilicon layer disposed within the channel. The gate polysilicon and source polysilicon are isolated by an interlayer oxide layer, and the gate polysilicon and N-drift region are isolated by a gate oxide layer. The thickness of the gate oxide layer near the edge of the interlayer oxide layer is not less than the thickness of the gate oxide layer away from the interlayer oxide layer. The manufacturing method includes the following steps: trench etching; thermal oxidation process to generate a field oxide layer; polysilicon deposition and reverse etching to form source polysilicon; oxide layer deposition to form an initial interlayer oxide layer; surface planarization and wet etching process to form an interlayer oxide layer; gate oxidation process to form a gate oxide layer; and polysilicon deposition and reverse etching to form a gate polysilicon layer. The gate oxide layer structure of this invention can effectively reduce the peak electric field at the bottom of the gate polysilicon layer, further enhancing device reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor devices, and particularly relates to a shielded gate trench VDMOS device. BACKGROUND

[0002] A shielded gate field effect transistor (SGFET) is a special type of field effect transistor (FET). It is composed of a metal gate, source, drain, and a shield layer. A general FET controls current flow by an insulating layer between the gate and the channel, but in an SGFET, a shield layer is introduced to improve device performance. The shield layer's role is to separate the electric field between the gate and the channel, reducing charge accumulation and leakage current, and reducing the capacitive coupling effect between the gate and the source, thereby improving the switching speed and stability of the transistor. Reducing leakage current: the shield layer effectively reduces the leakage current, improving the stability of the device. Due to its low on-resistance, high switching speed, and strong anti-interference ability, it is widely used in power devices and power supply fields.

[0003] However, the SGFET also has some limitations, and compared with traditional transistors, it is more complex in manufacturing and design, mainly because the formation process of the shield gate structure is relatively complex. For example, in the formation of the shield gate and the control trench gate two-layer polysilicon structure of the shield gate trench VDMOS, the isolation oxide layer structure needs to go through the oxide layer deposition process, CMP process, and wet etching process to form the isolation oxide layer. Due to the above-mentioned process, the formed isolation oxide layer structure is relatively flat, and the isolation oxide layer and the trench sidewall silicon form a 90-degree angle, as shown in FIG. 1, and in the subsequent gate oxidation process, due to the limitation of this right angle structure, and the thickness of the oxide layer generated in the gate oxidation process is not easy to control, the gate oxide layer at the bottom corner of the gate polysilicon layer is relatively thin, the anti-electric field breakdown ability is poor, and the product reliability is poor. Figure 5 SUMMARY

[0004] To overcome the defects of the above-mentioned shield gate field effect transistor and its manufacturing method, the technical problem to be solved by the present application is to provide a shield gate trench VDMOS device with uniform gate oxide layer thickness and strong anti-electric field breakdown ability and a manufacturing method thereof.

[0005] In terms of the shield gate trench VDMOS device, the shield gate trench VDMOS device for solving the technical problem of the present application comprises: an N-drift region, the drift region is provided with a channel, and the channel is provided with a gate polysilicon and a source polysilicon; the thickness of the gate oxide layer near the edge of the interlayer oxide layer is not less than the thickness of the gate oxide layer away from the edge of the interlayer oxide layer.

[0006] ​As an improvement of the shielding gate trench VDMOS device, the bottom wall of the gate polysilicon is connected to the side wall with a smooth transition, and the thickness of the gate oxide layer near the edge of the interlayer oxide layer gradually increases from the channel side wall to the direction away from the channel side wall.

[0007] As an improvement of the shielding gate trench VDMOS device, a thin film of silicon nitride is left between the side wall of the channel and the gate oxide layer.

[0008] Compared with the related art, the shielding gate VDMOS of the present application has a thicker gate oxide layer structure at the corner part of the trench, the gate oxide layer near the edge of the interlayer oxide layer has a circular arc structure, and the thickness of the bottom oxide layer is higher than that of the top gate oxide layer, thereby avoiding the unevenness of the oxide layer caused by the traditional process. Therefore, the gate oxide layer of the shielding gate VDMOS of the present application can effectively improve the ESD resistance (resistance to electrostatic discharge) and impact resistance (resistance to transient impact or pulse voltage) of the shielding gate VDMOS, and enhance the reliability of the device.

[0009] As for the manufacturing method of the shielding gate trench VDMOS device, the manufacturing method of the shielding gate trench VDMOS device for solving the technical problem comprises the following steps:

[0010] Trench etching is performed on the wafer surface;

[0011] A thermal oxidation process is performed to generate a field oxide layer in the trench;

[0012] Polysilicon deposition and reverse etching are performed to form a shielding layer source polysilicon in the field oxide layer;

[0013] Oxide layer deposition is performed to fill the trench and form an initial interlayer oxide layer above the shielding layer source polysilicon;

[0014] Oxide layer surface leveling treatment and wet etching treatment are performed on the initial interlayer oxide layer to make the upper surface of the initial interlayer oxide layer a certain depth away from the shielding layer source polysilicon, thereby forming an interlayer oxide layer;

[0015] A gate oxidation process is performed to form a gate oxide layer above the interlayer oxide layer;

[0016] Polysilicon deposition and reverse etching are performed to form a gate polysilicon layer in the gate oxide layer.

[0017] As an improvement of the manufacturing method of the shielding gate trench VDMOS device, the cross-sectional shape of the interlayer oxide layer is an arc structure with high sides and low middle.

[0018] As the improvement of the manufacturing method of the shield gate trench VDMOS device, the angle between the section of the upper surface of the interlayer oxide layer and the plane where the N-drift region sidewall is located is greater than 90°.

[0019] As the improvement of the manufacturing method of the shield gate trench VDMOS device, the angle between the section of the upper surface of the interlayer oxide layer and the plane where the N-drift region sidewall is located ranges from 160° to 180°.

[0020] As the improvement of the manufacturing method of the shield gate trench VDMOS device, the thickness of the gate oxide layer near the edge of the interlayer oxide layer is not less than the thickness of the gate oxide layer away from the edge of the interlayer oxide layer.

[0021] As the improvement of the manufacturing method of the shield gate trench VDMOS device, the bottom wall of the gate polysilicon is smoothly connected with the sidewall, and the thickness of the gate oxide layer near the edge of the interlayer oxide layer gradually increases from the direction of the channel sidewall to the direction away from the channel sidewall.

[0022] As the improvement of the manufacturing method of the shield gate trench VDMOS device, before forming the interlayer oxide layer,

[0023] SIN deposition and etching are performed to form a SIN layer on the sidewall of the trench.

[0024] As the improvement of the manufacturing method of the shield gate trench VDMOS device, a wet etching oxide layer process is further performed to form the interlayer oxide layer.

[0025] Compared with the related art, the manufacturing method of the shield gate trench VDMOS device can make the angle between the isolation oxide layer and the corner part of the trench of the device greater than 90° by preparing a bowl-shaped isolation oxide layer, so that the thermal oxidation rate of the corner part during the gate oxidation process is increased, thereby a thicker and more uniform gate oxide layer structure can be formed, and the problems of the thin gate oxide layer at the bottom corner of the gate polysilicon layer, poor anti-electric field breakdown capability, and poor product reliability caused by the traditional process are avoided. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a structural schematic diagram of a traditional shield gate VDMOS;

[0027] Figure 2 It is a structural schematic diagram after forming a trench on a wafer surface;

[0028] Figure 3 It is a structural schematic diagram of generating a field oxide layer in the trench;

[0029] Figure 4 It is a structural schematic diagram of forming a shield layer source polysilicon in the trench;

[0030] Figure 5 Structure schematic diagram for forming interlayer oxide layer in trench;

[0031] Figure 6 Structure schematic diagram for forming gate oxide layer in trench;

[0032] Figure 7 Structure schematic diagram for shield gate VDMOS structure according to embodiment of the present application;

[0033] Figure 8 Structure schematic diagram for forming second interlayer oxide layer in trench according to embodiment of the present application;

[0034] Figure 9 Structure schematic diagram for forming SIN layer according to embodiment of the present application;

[0035] Figure 10 Structure schematic diagram for forming third interlayer oxide layer according to embodiment of the present application;

[0036] Figure 11 Structure schematic diagram for forming second gate oxide layer according to embodiment of the present application.

[0037] Reference signs: N+ source region 101; N- drift region 102; field oxide layer 201; interlayer oxide layer 202; gate oxide layer 203; etching stop layer 204; second interlayer oxide layer 206; third interlayer oxide layer 207; second gate oxide layer 208; source polysilicon 301; gate polysilicon 302; SIN layer 401. DETAILED DESCRIPTION

[0038] In order to further clarify the technical means and effects of the present application for achieving the predetermined purposes, the present application is described in detail as follows in combination with the accompanying drawings and preferred embodiments.

[0039] The description of the method flow in the specification of the present application and the steps of the flow chart in the drawings of the present application do not necessarily strictly execute according to the step numbers. The method steps can change the execution order. Moreover, some steps can be omitted, a plurality of steps can be combined into one step for execution, and / or one step can be divided into a plurality of steps for execution.

[0040] Reference is made to Figure 1 , Figure 1 Structure schematic diagram for traditional shield gate VDMOS, such as Figure 1As shown, the structure of the conventional shield gate trench VDMOS includes: upper gate polysilicon 302: it is the control layer in the shield gate VDMOS device, used to control the charge density in the channel, thereby controlling the current flow; lower shield layer source polysilicon 301: it is the source layer in the shield gate VDMOS device, used to connect the drift region and the source; in the device structure, the upper gate polysilicon 302 and the lower shield layer source polysilicon 301 are isolated by the interlayer oxide layer 202, the lower shield layer source polysilicon 301 and the N-drift region 102 are isolated by the field oxide layer 201, and the upper gate polysilicon 302 and the N-drift region 102 are isolated by the gate oxide layer 203; N+ source region 101: used as an electrode or contact area, used to connect external circuits.

[0041] As shown in Figure 1 , the gate oxide layer 203 between the upper gate polysilicon 302 and the N-drift region 102 of the conventional shield gate VDMOS is thinned at the bottom corner position, the thickness of the gate oxide layer 203 is generally in the range of 30-100 nm, and the thickness of the corner position oxide layer is only 60%-80% of the normal value, the main reason is affected by the traditional manufacturing process, the main process flow of the conventional shield gate VDMOS is as follows:

[0042] 1. Trench etching is performed on the wafer surface, Figure 2 the structure schematic diagram after forming the trench on the wafer surface is shown in Figure 2 , the etching stop layer 204 can be used as a protective layer to protect the key layer or device structure below from being affected by etching, and plays a role in controlling and stopping etching during the etching process;

[0043] 2. Perform thermal oxidation process to generate field oxide layer 201, Figure 3 the structure schematic diagram of generating field oxide layer in the trench is shown in Figure 3 ;

[0044] 3. Polysilicon deposition and etching are performed to form shield layer source polysilicon 301, Figure 4 the structure schematic diagram of forming shield layer source polysilicon in the trench is shown in Figure 4 ;

[0045] 4. HDP (high-density plasma) oxide layer deposition is performed to fill the deep trench, then CMP (chemical mechanical polishing) process is performed to make the surface oxide layer flat, and finally wet etching of the oxide layer is performed to etch to a certain depth from the shield layer source polysilicon 301, forming an interlayer oxide layer 202, Figure 5 the structure schematic diagram of forming an interlayer oxide layer in the trench is shown in Figure 5 , the thickness of the interlayer oxide layer is generally 0.1-0.5um.

[0046] 5. Perform gate oxide process to form gate oxide layer 203, as shown in Figure 6 Figure 6 is a schematic diagram of the structure of the gate oxide layer formed in the trench. Generally, after cleaning and pretreatment, the device is placed in an oxidation furnace for oxidation treatment at high temperature. In this way, a SiO2 insulating layer with a thickness of about 100-1000 nanometers can be formed on the surface of the device.

[0047] 6. Finally, deposit and etch back the polysilicon to form the gate polysilicon layer 302, and the structure of the finally formed conventional shield gate VDMOS device is as shown in Figure 1

[0048] When the process flow reaches the gate oxide process of step 5, the interlayer oxide layer 202 and the N-drift region 102 form a 90-degree angle, which will affect the subsequent thermal oxidation rate at the corner position, resulting in a relatively thin oxide layer formed at this position, which reduces the reliability of the finally formed shield gate VDMOS device. The technical solution of the present application adopts a new manufacturing process flow, increases the thickness of the gate oxide layer 203 at the bottom corner of the gate polysilicon layer 302, improves the reliability of the device, and obtains a shield gate trench VDMOS device.

[0049] The exemplary embodiment of the present application provides a shield gate trench VDMOS device, comprising: an N-drift region, the drift region being provided with a channel, the channel being provided with a gate polysilicon and a source polysilicon;

[0050] The gate polysilicon and the source polysilicon are isolated by an interlayer oxide layer, and the gate polysilicon and the N-drift region are isolated by a gate oxide layer;

[0051] The thickness of the gate oxide layer near the edge of the interlayer oxide layer is not less than the thickness of the gate oxide layer away from the edge of the interlayer oxide layer.

[0052] The isolation oxide layer of the shield gate VDMOS has a relatively thick gate oxide layer structure at the corner position of the trench, the bottom of the gate oxide layer has a circular arc structure, and the thickness of the bottom oxide layer is higher than the thickness of the top gate oxide layer, thereby avoiding the uneven oxide layer defect caused by the conventional process. Therefore, the gate oxide layer of the shield gate VDMOS of the present application can effectively improve the ESD resistance (resistance to electrostatic discharge) and the impact resistance (resistance to transient impact or pulse voltage) of the shield gate VDMOS, and enhance the reliability of the device.

[0053] In specific implementation, refer to Figure 7 , Figure 7 is a schematic diagram of the shield gate VDMOS structure according to the embodiment of the present application, as shown in Figure 7 ​​As shown, the upper layer gate polysilicon 302 is isolated from the lower layer shielding layer source polysilicon 301 by the interlayer oxide layer 202, the lower layer shielding layer source polysilicon 301 is isolated from the N-drift region 102 by the field oxide layer 201, and the upper layer gate polysilicon 302 is isolated from the N-drift region 102 by the second gate oxide layer 208. Compared with the traditional shielding gate VDMOS structure, the bottom of the second gate oxide layer 208 of the shielding gate VDMOS of the embodiment of the present application is in a circular arc structure, and the thickness of the bottom oxide layer is higher than that of the top gate oxide layer, which can effectively improve the ESD resistance (resistance to electrostatic discharge) and impact resistance (resistance to transient impact or pulse voltage) of the shielding gate VDMOS, and enhance the reliability of the device.

[0054] The process flow of the shielding gate trench VDMOS device of the embodiment of the present application includes the following steps: performing trench etching on the wafer surface; performing a thermal oxidation process to generate a field oxide layer in the trench; performing polysilicon deposition and etching back to form a shielding layer source polysilicon in the field oxide layer; performing oxide layer deposition to fill the trench and form an initial interlayer oxide layer above the shielding layer source polysilicon; performing oxide layer surface flattening treatment and wet etching treatment on the initial interlayer oxide layer to make the upper surface of the initial interlayer oxide layer a certain depth away from the shielding layer source polysilicon, thereby forming an interlayer oxide layer; performing a gate oxidation process to form a gate oxide layer above the interlayer oxide layer; and performing polysilicon deposition and etching back to form a gate polysilicon layer in the gate oxide layer.

[0055] In the above or some embodiments, the cross-sectional shape of the interlayer oxide layer is an arc structure with high sides and a low middle.

[0056] The manufacturing method described above forms a bowl-shaped isolation oxide layer, makes the included angle between the isolation oxide layer and the corner part of the trench of the device much larger than 90°, and thus increases the thermal oxidation rate of the corner part when performing the gate oxidation process, so that a thicker and more uniform gate oxide layer structure can be formed, thereby avoiding the problems of a thin gate oxide layer at the bottom corner of the gate polysilicon layer, poor anti-electric field breakdown capability, and poor product reliability caused by the traditional process.

[0057] In specific implementation, taking an N-channel VDMOS device as an example, the method specifically includes the following steps:

[0058] Step 1: performing trench etching on the wafer surface, Figure 2 A structure diagram of the wafer surface after forming a trench is as shown in Figure 2As shown, the etching stop layer 204 can serve as a protective layer to protect the underlying key layer or device structure from etching, and can control and stop etching during the etching process. The etching stop layer 204 can be silicon dioxide, silicon nitride, or the like, and the depth of the trench can be 2-10 um, and the width of the trench can be 0.3-2 um.

[0059] Step 2: Perform a thermal oxidation process to generate a field oxide layer 201, Figure 3 A schematic diagram of the structure for generating the field oxide layer in the trench is shown in FIG. 2B. Figure 3 As shown, the thickness of the field oxide layer can be 1000-10000 A, which is mainly related to the breakdown voltage of the device.

[0060] Step 3: Perform a polysilicon deposition and etching back process to form a shield layer source polysilicon 301, Figure 4 A schematic diagram of the structure for forming the shield layer source polysilicon in the trench is shown in FIG. 3B. Figure 4 As shown, the shield layer source polysilicon 301 can be formed by the deposition and etching back process of the polysilicon.

[0061] Step 4: Perform an HDP (high-density plasma) oxide layer deposition to fill the deep trench, then perform a CMP (chemical mechanical polishing) process to make the surface oxide layer flat, and finally perform a wet etching process of the oxide layer to etch to a certain depth from the shield layer source polysilicon 301 to form a second interlayer oxide layer 206, as shown in FIG. 4B. Figure 8 Figure 8 A schematic diagram of the structure for forming the second interlayer oxide layer in the trench according to the embodiment of the present application is shown in FIG. 4B. The wet etching amount of this process can be 0.5-1 um.

[0062] Step 5: Perform a deposition of a layer of SIN and etch back, and the side wall will retain a SIN layer 401, as shown in FIG. 5B. Figure 9 Figure 9 A schematic diagram of the structure for forming the SIN layer according to the embodiment of the present application is shown in FIG. 5B. The SIN deposition technology is usually achieved by forming a thin film of silicon nitride (Si3N4) on the surface of silicon to increase the concentration of nitrogen (N) and silicon (Si) on the surface of silicon, thereby improving the performance and reliability of the device. It is worth noting that the material is not limited to SIN, and can be other dielectric materials such as silicon oxide, and the deposition thickness can be 0.1-0.5 um.

[0063] Step 6: Perform a wet etching oxide layer process again. Due to the isotropy of the wet etching, the wet etching amount is controlled to form a new third interlayer oxide layer 207, and the formed appearance is shown in FIG. 6B. Figure 10 Figure 10 ​​​The structure diagram of forming the third interlayer oxide layer according to the embodiment of the present application is in the shape of arc structure with both sides high and middle low, similar to the bowl structure. The wet etching amount of this step is 0.1-0.5um, and the key is to make the included angle between the third interlayer oxide layer 207 and the N-drift region 102 far greater than 90°, in the range of 160-180°, which helps to increase the thermal oxidation rate at the included angle position and improve the thickness of the oxide layer at the corner position.

[0064] Step 7: Perform the gate oxide process to form the second gate oxide layer 208 to isolate the gate and the drift region, avoid the leakage and drift of the electric charge, and form the second gate oxide layer 208 as shown in Figure 11 Figure 11 The structure diagram of forming the second gate oxide layer according to the embodiment of the present application is shown. The bottom of the second gate oxide layer 208 is in the circular arc structure, and the thickness of the bottom oxide layer is higher than that of the top gate oxide layer. The process is basically the same as the general process, that is, after cleaning and pretreatment, the device is put into the oxidation furnace to perform the oxidation treatment at high temperature. The difference is that the process is performed on the basis of the bowl-shaped third interlayer oxide layer 207 formed in step 6. Since the included angle between the third interlayer oxide layer 207 and the N-drift region 102 is far greater than 90°, the thermal oxidation rate at the corner position is improved, and a relatively thick gate oxide layer structure can be formed, thereby avoiding the defects caused by the traditional process.

[0065] Step 8: Finally, deposit and etch back the polysilicon to form the gate polysilicon layer 302, and the structure of the finally formed gate VDMOS device is shown in Figure 7 .

[0066] It is worth noting that the shielded gate trench VDMOS device proposed in the embodiment of the present application is described by taking the N-channel VDMOS device as an example. The technical solution of the present application is also suitable for the P-channel VDMOS device, and the corresponding N-type and P-type regions are opposite, which does not limit the present application.

[0067] The shielded gate trench VDMOS device proposed in the present application has the bowl-shaped structure of the new interlayer dielectric layer, the upper gate oxide layer is thin, and the bottom oxide layer is thick, which is just opposite to the traditional structure. This slope structure can effectively reduce the electric field peak value at the bottom of the gate polysilicon layer, and further enhance the reliability of the device.

[0068] Through the description of the specific embodiments, the technical means and effects taken by the present application to achieve the predetermined purpose can be understood more deeply and specifically. However, the accompanying drawings are provided for reference and illustration only, and are not used to limit the present application.​

Claims

1. A method of manufacturing a shielded gate trench VDMOS device, characterized by, The method comprises the following steps: performing trench etching on a wafer surface; performing a thermal oxidation process to form a field oxide layer in the trench; performing polysilicon deposition and etching back to form a shielded source polysilicon in the field oxide layer; performing oxide deposition to fill the trench and form an initial interlayer oxide layer above the shielded source polysilicon; performing oxide surface flattening and wet etching on the initial interlayer oxide layer to form an interlayer oxide layer with a preset depth from the shielded source polysilicon; performing a gate oxidation process to form a gate oxide layer above the interlayer oxide layer; performing polysilicon deposition and etching back to form a gate polysilicon layer in the gate oxide layer; the cross-sectional shape of the interlayer oxide layer is an arc structure with high sides and low middle; the bottom wall of the gate polysilicon is smoothly connected with the side wall, and the thickness of the gate oxide layer near the edge of the interlayer oxide layer is not less than the thickness of the gate oxide layer away from the edge of the interlayer oxide layer; the angle between the upper surface of the interlayer oxide layer and the part of the N-drift region side wall above the interlayer oxide layer is greater than 90°.

2. The manufacturing method of the shielded gate trench VDMOS device according to claim 1, wherein the angle between the upper surface of the interlayer oxide layer and the part of the N-drift region side wall above the interlayer oxide layer is within a range of 160-180°.

3. The manufacturing method of the shielded gate trench VDMOS device according to any one of claims 1-2, wherein before forming the interlayer oxide layer, SIN deposition and etching back are performed to form a SIN layer on the trench side wall.

4. The manufacturing method of the shielded gate trench VDMOS device according to claim 3, wherein based on the SIN layer, a wet etching oxide process is performed again to form the interlayer oxide layer. ​ ​ ​

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