A method for layer assignment based on via pillar and non-default rule line under slew constraint

Abstract

The application discloses a layer distribution method based on a through-hole column and a non-default rule line under slew constraint, which is divided into four stages: a pre-distribution stage, an edge capacity overflow elimination stage, a grid cell area overflow avoidance stage and a multi-refining stage. In the pre-distribution stage, a three-dimensional wiring scheme with ideal delay indicators is obtained. In the edge capacity overflow elimination stage, a track-aware method in a resource-aware strategy is adopted to comprehensively eliminate all conductor overflows. In the grid cell area overflow avoidance stage, an area-aware method in the resource-aware strategy is used to further reduce the grid cell area overflow under the condition that the edge capacity overflow is 0. In the multi-refining stage, the timing performance of the wiring scheme is further optimized without deteriorating the overflow.

Description

Technical Field

[0001] This invention belongs to the field of computer-aided design technology, specifically relating to a layer assignment method based on through-hole columns and non-default rule lines. Background Technology

[0002] Extensive research has been conducted on layer allocation to minimize overflow. Existing technologies have proposed methods for assessing congestion in overall routing via capacity, heuristic layer allocation algorithms that consider via capacity, layer allocation algorithms designed based on the negotiation concept to minimize via overflow, and a model that senses the impact of via size changes on congestion.

[0003] With the rapid development of VLSI, latency has become a crucial factor in evaluating chip timing characteristics, significantly impacting chip performance. Under multilayer routing models, existing technologies have proposed various latency optimization methods, but they do not consider the advanced manufacturing process of non-default regular lines. Based on this, a latency-driven layer allocation algorithm considering non-default regular lines and coupling effects is proposed, but it still has considerable room for further latency optimization. By introducing non-default regular lines, congestion is considered from multiple perspectives to further optimize latency. However, existing latency optimization layer allocation work focuses on optimizing conductor latency, without proposing specific optimization strategies for via latency. This paper introduces via pillars for the first time in the layer allocation stage to optimize latency.

[0004] Furthermore, slew violations are a significant factor affecting timing convergence. To ensure signal integrity and avoid signal distortion, existing routers focus on reducing slew violations. Introducing buffers reduces the number of slew violations, thereby optimizing timing characteristics; however, buffers undoubtedly consume limited routing resources. Another approach is to intelligently reclaim routing resources that cross IP blocks to improve slew violations, introducing slew constraints into the routing tree construction problem. An incremental layer allocation algorithm based on integer linear programming is proposed to reduce slew violations.

[0005] Although existing literature has proposed targeted algorithms for the impact of via size on congestion, latency optimization, and slew violation optimization based on other layer allocation algorithms, they are all not comprehensive enough. Specifically, they fail to consider the impact of non-default regular lines and via posts on congestion, and they also fail to consider timing optimization objectives; they only focus on latency optimization and ignore slew violations; and they do not utilize non-default regular lines and via post techniques to optimize slew violations, thus failing to obtain an ideal routing result. Summary of the Invention

[0006] To overcome the shortcomings of existing technologies, this invention provides a layer allocation method based on via pillars and non-default rule lines under Slew constraints, consisting of four stages: a pre-allocation stage, an edge capacity overflow elimination stage, a mesh cell area overflow avoidance stage, and a multi-refinement stage. In the pre-allocation stage, the aim is to obtain a 3D routing scheme with ideal latency performance. In the edge capacity overflow elimination stage, the track-aware method from the resource-aware strategy is used to completely eliminate all wire overflows. In the mesh cell area overflow avoidance stage, while ensuring that edge capacity overflow is zero, the area-aware method from the resource-aware strategy is used to further reduce mesh cell area overflow. In the multi-refinement stage, the timing performance of the obtained mesh is further optimized without worsening overflow.

[0007] The technical solution adopted by this invention to solve its technical problem includes the following steps:

[0008] Step 1: Define the objective function:

[0009]

[0010] Where cost(n) represents the total cost of the wire network, delay(n), via(n), cong(s), sv(n), and l(n) represent the delay cost, via cost, congestion cost, slew violation cost, and deviation cost, respectively; α, β, γ, λ, and δ are the delay weight, via weight, congestion weight, slew violation weight, and deviation weight, respectively.

[0011] Step 2: Pre-allocation phase;

[0012] Set initial values ​​for latency weight, via weight, congestion weight, slew violation weight, and deviation weight;

[0013] Step 3: Eliminating and avoiding overflow phase;

[0014] If the number of tracks used exceeds the grid edge capacity, an edge capacity overflow is determined to have occurred; if the area occupied by wires, vias, and obstacles in a grid cell is greater than the area of ​​the grid cell itself, a grid cell area overflow is determined to have occurred; a grid passing through an edge that has experienced edge capacity overflow or a grid passing through an edge that has experienced grid cell area overflow is defined as an illegal grid. The specific calculation formula is as follows:

[0015]

[0016]

[0017] Formula (2) is the method for calculating grid cell overflow, where of(g), dc(g), and tc(g) represent the number of overflowing grid cells, the area occupied by grid cells, and the total area of ​​grid cells, respectively; Formula (3) is the formula for calculating edge capacity overflow, where of(e), dc(e), and tc(e) represent the number of overflowing edges, the edge capacity, and the capacity used, respectively.

[0018] In the phase of eliminating edge capacity overflow, the track sensing method in the resource sensing strategy is adopted to completely eliminate all wire overflows;

[0019] In the stage of avoiding grid cell area overflow, while ensuring that the edge capacity overflow is 0, the area-aware method using the resource-aware strategy further reduces grid cell area overflow.

[0020] In the stages of eliminating edge capacity overflow and avoiding grid cell area overflow, the time delay weight, via weight, congestion weight, slew violation weight, and deviation weight are set to 0.1, 1, 1, 0.1, and 1, respectively.

[0021] Step 4: Multiple refining stages;

[0022] Without worsening overflow, the optimizable nets are de-wired and rewound multiple times, and the time delay weight and slew violation weight of the objective function are continuously adjusted in this process to obtain a layer allocation result; in addition, the via weight of the time-critical nets is increased.

[0023] A multi-refinement strategy is adopted, which optimizes latency and slew by repeatedly unwinding and rewinding the wires.

[0024] Set a refinement threshold and an optimizable candidate net set to avoid sacrificing too much runtime for timing performance optimization. End the multi-refinement strategy when the refinement threshold is reached or the optimizable candidate net set is empty. Increase the delay and slew weights during each de-route and re-route operation to make it easier to select layer allocation schemes with lower delay and slew for single-net layer assignment. Record the delay and slew violation counts of the original net for comparison with the re-route mesh. Remove the original net and reroute it. Compare the two nets and select the net with better timing performance as the final routing scheme. If the original net has better routing performance, it indicates that there is essentially no room for further optimization, so remove it from the selectable net set.

[0025] Finally, the latency weight, via weight, congestion weight, slew violation weight, and deviation weight were set to 0.1, 1, 1, 0.1, and 20, respectively.

[0026] Step 5: Slew hierarchical strategy;

[0027] Classify the wire networks according to the slew value of the signal receivers, and limit the wire networks at each level to the metal layers of the echelon; the non-timing critical wire networks are limited to the metal layers of the lower echelon;

[0028] Step 5-1: First, calculate the average slew value of the wire network. The calculation method is as follows:

[0029]

[0030] where avslew, P, and slew p represent the average slew value of the wire network, the set of signal receivers in the wire network, and the slew value of signal receiver p, respectively;

[0031] Step 5-2: According to the average slew value avslew of the wire network, the slew constraint value reslew, and the metal layer structure, divide the wire network into four levels. The specific division method is as follows:

[0032] (1) When the average slew value avslew of the wire network satisfies 0.00 < avslew <= 0.35 * reslew, the wire network is defined as a first-level wire network and can be assigned to the first echelon routing layer;

[0033] (2) When the average slew value avslew of the wire network satisfies 0.35 * reslew < avslew <= 1.00 * reslew, the wire network is defined as a second-level wire network and can be assigned to the second echelon routing layer;

[0034] (3) When the average slew value avslew of the wire network satisfies 1.00 * reslew < avslew <= 4.00 * reslew, the wire network is defined as a third-level wire network and can be assigned to the third echelon routing layer;

[0035] (4) When the average slew value avslew of the wire network satisfies avslew < 4.00 * reslew, the wire network is defined as a fourth-level wire network and there is no restriction on its routing layer;

[0036] Step 5-3: Calculate the deviation cost in the objective function to achieve the purpose of restricting wire networks at different levels to appropriate metal layers. The calculation formula for the deviation cost is as follows:

[0037] l(n) = μ × c(5)

[0038] where l(n) represents the deviation cost of wire network n, μ represents the user-defined parameter set to 0.75, and c is the deviation layer number, and its calculation method is as follows:

[0039]

[0040] Where S represents the set of conductor segments in the net n, hopes represents the metal layer that conductor segment s is expected to be assigned to, and actuals represents the metal layer that conductor segment s is actually assigned to.

[0041] Furthermore, the resource awareness strategy is specifically as follows:

[0042] Step 3-1: For the two overflow situations of edge capacity overflow and grid cell area overflow, resource-aware strategies are adopted at different stages to optimize the overflow; in the stage of eliminating edge capacity overflow, the resource-aware strategy is required to repair all edge capacity overflows; in the stage of avoiding grid cell area overflow, the resource-aware strategy is required to minimize grid cell area overflow when the edge overflow is 0, and the number of overflows reduced by 1% is required for each wire break and rewind.

[0043] Resource-aware strategies reduce overflow by updating the congestion cost in the objective function. The formula for calculating the congestion cost is as follows:

[0044] cong(s) = of(s) × p(s) (7)

[0045] Where cong(s), of(s), and p(s) represent congestion cost, overflow, and penalty, respectively;

[0046] In the edge overflow elimination stage, the orbit-aware method was used to repair all edge capacity overflows, and in the grid cell area overflow stage, the area-aware method was used to further reduce grid cell area overflow.

[0047] Step 3-2: Track sensing method;

[0048] During the edge overflow elimination phase, illegal wire networks with edge capacity overflow are repeatedly disassembled and rewound, and the congestion cost is continuously updated in the process to eliminate all edge capacity overflows. Since the track-aware method is dedicated to eliminating all edge capacity overflows, the overflow amount of(s) in the congestion cost is calculated using formula (2), and the penalty term p(s) in the congestion cost is calculated as follows:

[0049]

[0050] Where μ and ν are user-defined parameters, with μ taking the value of 0.25 and ν taking the value of 0.05; e s p(s), u(e) represent the grid edges e that the conductor segment s passes through. s ),c(e s ),times represent the penalty term for conductor segment s, the usage of grid edge e, the capacity of grid edge e, and the current number of times to unwrap and rewind the wire, respectively.

[0051] Step 3-3: Area sensing method;

[0052] The stage of avoiding grid cell area overflow will, while ensuring that no edge capacity overflow occurs, evaluate the current area usage of each grid cell to ensure that the overflow optimization ratio is greater than 1% after each illegal wire mesh is dismantled and rewound. Specifically, when each illegal wire mesh is dismantled and rewound, the area-aware method is continuously used to update the congestion cost to drive the single wire mesh layer allocation algorithm to find a wiring scheme with less overflow. Because the track-aware method is dedicated to reducing grid cell area overflow, the overflow amount of(s) in the congestion cost is calculated using formula (3). The penalty term p(s) in the congestion cost is calculated as follows:

[0053] p(s)=ε+u(g s )÷c(g s (9)

[0054] Among them, g s p(s), u(g) represent the grid edges traversed by conductor segment s; s ),c(g s ) represent the penalty term, the area occupied by grid cell g, and the total area of ​​grid cells, respectively; ε is a custom parameter, set to 1.

[0055] Furthermore, in step 2, the initial values ​​of the delay weight, via weight, congestion weight, slew violation weight, and deviation weight are set to 1, 0, 0.3, 0, and 1, respectively.

[0056] The beneficial effects of this invention are as follows:

[0057] This invention proposes for the first time an advanced technical node system that simultaneously optimizes latency and slew violations, and considers efficient layer allocation algorithms that take into account coupling effects, via count, wire size, via size, and overflow. Using the method of this invention, the total latency, critical net latency, via count, and number of iterations are all reduced. Attached Figure Description

[0058] Figure 1 This is a flowchart of the method of the present invention.

[0059] Figure 2 For different types of wires, (a) default regular line, (b) parallel line, and (c) wide line.

[0060] Figure 3 This is a comparison chart showing the wiring effects of through-hole posts and conventional through-holes. Detailed Implementation

[0061] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0062] To further optimize conductor delay and via delay, this invention uses non-default regular lines and via posts. Non-default regular lines have significant potential for optimizing conductor delay. Figure 2As shown, non-default rule lines come in two types: wide lines and parallel lines. Figure 2 As shown in (a), compared to non-default rule lines, default rule lines occupy only one track; wide lines optimize latency by increasing conductor size, occupying three tracks; parallel lines optimize latency by connecting conductors in parallel, occupying two tracks. Furthermore, via latency is a significant component of net latency. To effectively optimize via latency, the concept of via posts is proposed. For example... Figure 3 As shown, the conductors of adjacent routing layers on the right are connected via conventional vias, while the left side shows a via-pillar structure where conductors of adjacent routing layers are connected vias connected in parallel. A via-pillar consists of multiple closely spaced vias and conductor pairs, with the conductor pairs routed in the preferred direction for each layer. Via-pillars facilitate the transmission of electronic signals from lower to higher layers, thus leveraging the lower resistance of higher-layer conductors to optimize latency. Because a via-pillar is composed of multiple vias connected in parallel, via resistance is reduced, thereby reducing via latency. Furthermore, via-pillars improve yield and enhance reliability by preventing open circuits due to vias.

[0063] The purpose of this invention is to design an efficient layer assignment method using non-default rule lines and via pillars to simultaneously optimize latency, via count, overflow, and slew violations.

[0064] This invention is implemented using the following scheme: a layer allocation method based on through-hole pillars and non-default rule lines under Slew constraints, the flowchart of which is shown below. Figure 1 As shown.

[0065] This invention consists of four stages: a pre-allocation stage, an edge capacity overflow elimination stage, a mesh cell area overflow avoidance stage, and a multi-refinement stage. In the pre-allocation stage, the aim is to obtain a 3D routing scheme with ideal latency performance. In the edge capacity overflow elimination stage, the track-aware method within the resource-aware strategy is used to completely eliminate all wire overflows. In the mesh cell area overflow avoidance stage, while ensuring that edge capacity overflow is zero, the area-aware method within the resource-aware strategy is used to further reduce mesh cell area overflow. In the multi-refinement stage, the timing performance of the obtained net is further optimized without worsening overflow.

[0066] This invention specifically includes the following improvement strategies:

[0067] (1) Slew Classification Strategy. This invention quantitatively analyzes the slew values ​​of different pins and classifies different network structures into levels, which reduces the dependence of layer-by-layer allocation on routing order to a certain extent, thereby optimizing latency and the number of slew violations.

[0068] (2) Resource Awareness Strategy. After introducing non-default rule lines and via posts, this invention considers the impact of various types of conductor sizes and different via sizes on congestion, and adopts appropriate awareness methods at different stages to alleviate the congestion problem.

[0069] (3) Multiple Refinement Strategies. This invention strives to ensure that time-critical wires are allocated to higher layers to leverage the cabling advantages of higher layers, thereby optimizing latency and reducing slew violations. Specific implementation examples:

[0071] 1. Method and Flow

[0072] This invention is divided into four stages: pre-allocation stage, edge capacity overflow elimination stage, grid cell area overflow avoidance stage, and multi-refinement stage. Figure 1 This is a flowchart of the invention. The fundamental algorithm of this invention combines dynamic programming for single-line mesh layer allocation and a Slew hierarchical strategy. Based on this method, the invention utilizes different resource-aware strategies to minimize overflow during the edge capacity overflow elimination stage and the mesh cell area overflow avoidance stage. Finally, a multi-refinement strategy is employed in the post-optimization stage to further optimize the latency and Slew violations of the routing solution. To comprehensively optimize each objective, the invention uses the following objective function:

[0073]

[0074] Where cost(n) represents the total cost of the network, and delay(n), via(n), cong(s), sv(n), and l(n) represent the delay cost, via cost, congestion cost, slew violation cost, and deviation cost, respectively (see Section 3.3 for details). α, β, γ, λ, and δ are the delay weight, via weight, congestion weight, slew violation weight, and deviation weight, respectively. Since the optimization objectives differ at each stage, the weights also vary at each stage.

[0075] In the pre-allocation phase, this invention aims to obtain a 3D routing scheme with ideal latency performance, so the via weight and slew weight are set to 0. However, to avoid excessive overflow and increase the pressure on subsequent overflow repair stages, the congestion weight is set to a smaller value compared to later stages. Furthermore, to avoid consuming too many routing resources in the early stages, non-default rule lines and via posts are not allowed in this phase. In this phase, the latency weight, via weight, congestion weight, slew violation weight, and deviation weight are set to 1, 0, 0.3, 0, and 1, respectively.

[0076] In the congestion model of this invention, two overflow scenarios are considered: edge capacity overflow and grid cell area overflow. Each grid edge has a corresponding capacity (i.e., the number of tracks that can be used to place wires, vias, and obstacles on that grid edge). If the number of tracks used exceeds the grid edge capacity, edge capacity overflow is considered to have occurred. Furthermore, after restoring the grid cell size, each grid cell has a corresponding wiring area. If the area occupied by wires, vias, and obstacles in a grid cell is greater than the area of ​​the grid cell itself, grid cell area overflow occurs. A net passing through a grid edge that has experienced edge capacity overflow or a grid edge that has experienced grid cell area overflow is defined as an illegal net. The specific calculation formula is as follows:

[0077]

[0078]

[0079] Formula (1) is the method for calculating grid cell overflow, where of(g), dc(g), and tc(g) represent the number of overflowing grid cells, the area occupied by grid cells, and the total area of ​​grid cells, respectively. Formula (2) is the formula for calculating edge capacity overflow, where of(e), dc(e), and tc(e) represent the number of overflowing edges, the edge capacity, and the capacity used, respectively.

[0080] Because this invention considers two overflow scenarios, and the wire and via sizes are diverse, the overflow problem becomes more complex. Therefore, this invention will consider edge capacity overflow and mesh cell area overflow in the subsequent two stages respectively. In the edge capacity overflow elimination stage, this invention employs the track-aware method from the resource-aware strategy to comprehensively eliminate all wire overflows. This method ensures that all edge capacity overflows are successfully repaired after multiple wire unwinding and rewinding.

[0081] In the stage of avoiding grid cell area overflow, this invention further reduces grid cell area overflow by using an area-aware method with a resource-aware strategy, while ensuring that the edge capacity overflow is 0. After multiple experimental tests, the delay weight, via weight, congestion weight, slew violation weight, and deviation weight are set to 0.1, 1, 1, 0.1, and 1, respectively, in the stages of eliminating edge capacity overflow and avoiding grid cell area overflow.

[0082] In the multi-refinement stage, without deteriorating the overflows, the present invention rewires the obtained wire networks multiple times for the wire networks that can be optimized, and continuously adjusts the delay weight and slew weight of the objective function during this process to obtain an ideal layer assignment result. In addition, via delay is an important part of the wire network delay, and optimizing the delay has a positive impact on reducing slew violations. Therefore, considering the number of vias is beneficial to reducing via overflows and optimizing the delay and slew. Therefore, in order to further optimize, the via weight of the timing-critical wire networks is increased in this stage. After multiple experimental tests, in the multi-refinement stage, the delay weight, via weight, congestion weight, slew violation weight, and deviation weight are set to 0.1, 1, 1, 0.1, and 20 respectively.

[0083] 2 slew grading strategy

[0084] The per-net layer assignment algorithm is prone to falling into local optimality. The quality of its routing result depends greatly on the rationality of the routing order, but often a suitable routing order cannot be found, which reduces the performance of the routing result. At the same time, if only whether the pins have slew violations is judged and the slew values of the pins are not accurately calculated, it may cause the pins close to the slew constraint value to have slew violations again during the next rewire. Therefore, there is an urgent need to design a strategy to improve the above situation. The present invention grades the wire networks according to the slew values of the signal receivers, and restricts the wire networks at each level to the metal layers in the appropriate echelons. The non-timing-critical wire networks are restricted to the low-echelon metal layers, which not only reduces the number of vias but also reserves routing space for the timing-critical wire networks, enabling the timing-critical wire networks to give full play to the routing advantages of the high-echelon metal layers, thereby reducing the risk of falling into local optimality. In addition, reasonably restricting the wire networks prone to slew violations to the appropriate metal layers is beneficial to reducing slew violations.

[0085] First, it is necessary to calculate the average slew of the wire network, and the calculation method is as follows:

[0086]

[0087] where avslew, P, and slew p represent the average slew of the wire network, the set of signal receivers in the wire network, and the slew value of signal receiver p respectively.

[0088] Then, according to the average slew avslew of the wire network, the slew constraint value reslew, and the metal layer structure, the wire networks are divided into four levels, and the specific division method is as follows:

[0089] (1) When the average slew avslew of the wire network satisfies 0.00 < avslew <= 0.35 * reslew, the wire network is defined as a first-level wire network, and it is hoped that it can be assigned to the first-echelon routing layer;

[0090] (2) When the slew average value avslew of the wire net satisfies 0.35*reslew < avslew <= 1.00*reslew, the wire net is defined as a secondary wire net, and it is hoped that it can be assigned to the second-tier routing layer;

[0091] (3) When the slew average value avslew of the wire net satisfies 1.00*reslew < avslew <= 4.00*reslew, the wire net is defined as a tertiary wire net, and it is hoped that it can be assigned to the third-tier routing layer;

[0092] (4) When the slew average value avslew of the wire net satisfies avslew < 4.00*reslew, the wire net is defined as a quaternary wire net, and there is no restriction on its routing layer, giving it greater routing flexibility.

[0093] Finally, calculate the deviation cost in the objective function to achieve the purpose of restricting wire nets of different levels to appropriate metal layers. The calculation formula for the deviation cost is as follows:

[0094] l(n) = μ × c(5)

[0095] Among them, l(n) represents the deviation cost of wire net n. μ represents a user-defined parameter. We conducted multiple groups of experiments within the range of 0 - 2 with a gradient of 0.25, and finally set it to 0.75. c is the deviation layer number, and its calculation method is as follows:

[0096]

[0097] Among them, S represents the set of wire segments in wire net n, hopes represents the metal layer to which wire segment s is hoped to be assigned, and actuals represents the metal layer to which wire segment s is actually assigned.

[0098] 3 Resource Awareness Strategy

[0099] In the present invention, vias and grid cells are logically restored to rectangles with geometric shapes, thereby forming a more practical resource evaluation system that simultaneously considers wire dimensions, via dimensions, and obstacles, but also brings greater challenges to solving the congestion problem. At the same time, although non-default rule wires and via columns can effectively optimize delay and slew, they must be used reasonably, otherwise more serious overflows will occur. Therefore, there is an urgent need to design an efficient strategy to reduce overflows, regulate the use of non-default rule wires and via columns, so as to further enhance the routability of the routing scheme.

[0100] This invention addresses two overflow scenarios: edge capacity overflow and mesh cell area overflow. It employs a resource-aware strategy at different stages to optimize overflow. The pseudocode for the resource-aware strategy is as follows. Line 1 indicates that the resource-aware algorithm is executed when the expected optimization effect is not achieved. Specifically, in the edge capacity overflow elimination stage, this invention requires the resource-aware strategy to repair all edge capacity overflows; in the mesh cell area overflow avoidance stage, the resource-aware strategy is required to minimize mesh cell area overflows when edge overflows are zero, requiring each wire breakage and rewinding to reduce the number of overflows by at least 1%. Lines 2-5 count the nets with overflow problems and calculate their overflow amounts. Line 6 determines the routing order of the non-compliant nets. Lines 7-10 update the objective function of the non-compliant nets and then perform wire breakage and rewinding.

[0101] Algorithm 1. Resource-Aware Algorithm

[0102] Input: Routing scheme R1 before optimization.

[0103] Output: Optimized routing scheme R2.

[0104]

[0105] Resource-aware strategies reduce overflow by updating the congestion cost in the objective function. The formula for calculating the congestion cost is as follows:

[0106] cong(s) = of(s) × p(s) (7)

[0107] Here, cong(s), of(s), and p(s) represent congestion cost, overflow amount, and penalty term, respectively. The resource-aware strategy employs different methods to calculate overflow amount and penalty term in the edge capacity overflow elimination stage and the grid cell area overflow avoidance stage, thereby comprehensively reducing overflow. Specifically, in the edge overflow elimination stage, an orbit-aware method is used to repair all edge capacity overflows. In the grid cell area overflow avoidance stage, an area-aware method is used to further reduce grid cell area overflow.

[0108] 3.1 Track Sensing Method

[0109] To eliminate all edge capacity overflows, this invention proposes a novel track-aware method to optimize the timing characteristics and routeability of the routing scheme. In the edge overflow elimination phase, illegal networks with edge capacity overflows are repeatedly dismantled and rerouted, and the congestion cost is continuously updated during this process to eliminate all edge capacity overflows. Because the track-aware method aims to eliminate all edge capacity overflows, the overflow amount of(s) in the congestion cost is calculated using formula (2). The penalty term p(s) in the congestion cost is calculated as follows:

[0110]

[0111] Where μ and ν are user-defined parameters, after multiple experimental tests, the value of μ is 0.25 and the value of ν is 0.05. s p(s), u(e) represent the grid edge e traversed by conductor segment s. s ),c(e s ), and times represent the penalty term for conductor segment s, the usage of grid edge e, the capacity of grid edge e, and the current number of dismantling and rewinding operations, respectively. In the pre-allocated routing scheme, most conductors are distributed in high-metal layers, resulting in a high routing density of grid edges on these layers. During dismantling and rewinding, routing on high-metal layers with high routing density will be avoided as much as possible to optimize grid edge congestion. Simultaneously, after multiple dismantling and rewinding operations, the number of illegal nets decreases, the routing density of higher layers decreases, while the number of dismantling and rewinding operations increases. Considering the number of dismantling and rewinding operations can effectively prevent the congestion cost from becoming too small after multiple dismantling and rewinding operations, thus avoiding the inability to converge during the edge repair capacity overflow stage.

[0112] 3.2 Area Sensing Method

[0113] This invention restores the grid cell to a rectangle with area, while considering the different wire sizes of default regular lines, parallel lines, and wide lines, as well as the corresponding different via sizes. Therefore, it is necessary to consider not only edge capacity overflow but also grid cell area overflow. In order to minimize grid cell area overflow, this invention adopts an area-aware method in the grid cell area overflow avoidance stage to further enhance the routing feasibility of the routing method. In the grid cell area overflow avoidance stage, while ensuring that no edge capacity overflow occurs, the overflow optimization ratio is greater than 1% after each wire breakage and rewinding of illegal wire mesh by evaluating the current area usage of each grid cell. Specifically, when each wire breakage and rewinding of illegal wire mesh occurs, the area-aware method is continuously used to update the congestion cost to drive the single wire mesh layer allocation algorithm to find a routing scheme with less overflow. Because the track-aware method is committed to reducing grid cell area overflow, the overflow amount of(s) in the congestion cost is calculated using formula (3). The penalty term p(s) in the congestion cost is calculated as follows:

[0114] p(s)=ε+u(g s )÷c(g s (9)

[0115] Among them, g s p(s), u(g) represent the grid edges traversed by conductor segment s. s ),c(g s ) represent the penalty term, the area occupied by grid cell g, and the total area of ​​the grid cells, respectively. ε is a user-defined parameter, which is set to 1 in this work after multiple experiments.

[0116] 4. Refining Strategy

[0117] To prevent an overemphasis on overflow reduction targets from leading to suboptimal timing performance, this invention utilizes a multi-refinement strategy to fully leverage the timing optimization potential of non-default rule lines, vias, and high-layer routing resources, further optimizing the timing performance of the routing results. The pseudocode for the multi-refinement strategy is as follows:

[0118] Algorithm 2. Slew Refinement Strategy Algorithm

[0119] Input: Routing scheme R1 before optimization.

[0120] Output: Optimized routing scheme R2.

[0121]

[0122] The multi-refinement strategy optimizes latency and slew through multiple rewiring operations. Lines 1-2 set the refinement count threshold and the set of candidate nets for optimization to avoid sacrificing excessive runtime for timing performance. Lines 3-4 prepare for rewiring. Line 3 represents the condition for ending rewiring; specifically, the multi-refinement strategy ends when the refinement count threshold is reached or the set of candidate nets for optimization is empty. Line 4 increases the latency and slew weights during each rewiring operation, making it easier to select layer allocation schemes with lower latency and slew for single net layer allocation. Lines 5-11 detail the rewiring operations for each net. Line 6 records the latency and slew violation counts of the original net for comparison with the rewiring mesh. Line 7 removes the original net and reroutes. Lines 8-9 compare the merits of the two nets and select the net with better timing performance as the final routing scheme. If the original network cabling performance is better, it means that there is basically no room for further optimization, so it should be removed from the set of optional networks.

[0123] This invention compares with the layer allocation algorithm of the most advanced literature, both operating in the same experimental environment and using the same standard test circuit for DAC12 wireability drive. The DAC12 standard test circuit data originates from competition data at a top international design automation conference, and all designs are derived from modern industrial application-specific integrated circuits. Tables 1, 3, and 5 show the comparison results of latency, via count, and runtime before and after introducing different strategies. Here, "TD" and "MD" represent the total latency and maximum latency of the net, respectively; "0.5%", "1.0%", and "5.0%" correspond to the average latency of the top 0.5%, top 1.0%, and top 5.0% timing-critical nets in the test circuit sorted in descending order of net latency; "#vc" represents the via count; and "Runtime" represents the runtime. Tables 2, 4, and 6 show the comparison results of overflow count and slew violation count before and after introducing different strategies. Here, "#ov" represents the overflow count, "#sv" represents the slew violation count, and "ratio" represents the average optimization ratio.

[0124] Table 1 compares the latency, vias, and runtime results before and after introducing the Slew hierarchical strategy.

[0125]

[0126] As shown in Table 1, by introducing the Slew hierarchical strategy, different wireframe structures are distinguished, and the wireframes are hierarchically classified, thus confining different wireframes to the ideal metal layer. Therefore, compared to the case without the Slew hierarchical strategy, the total latency is optimized by 7%, 8%, 8%, and 7% for the first 0.5%, 1%, and 5% of the critical wireframes, respectively, and the number of vias is reduced by 5%. Simultaneously, due to the reduced number of iterations after introducing the Slew hierarchical strategy, the runtime is reduced by 10%.

[0127] Table 2 compares the overflow and Slew violation counts before and after introducing the Slew hierarchical strategy.

[0128]

[0129]

[0130] As shown in Table 2, the introduction of the slew hierarchical strategy, which restricts different levels of nets to different cabling layers, further alleviates the congestion problem. Therefore, compared to the case without the slew hierarchical strategy, the number of overflows decreased by 14%, and the number of slew violations decreased by 5%.

[0131] Table 3 compares latency, vias, and runtime before and after implementing the resource-aware strategy.

[0132]

[0133] As shown in Table 3, after introducing the resource-aware strategy, different appropriate methods were used to assess congestion at different stages. Therefore, compared with the case without the resource-aware strategy, the total latency was optimized by 4%, 15%, 14%, and 7% for the first 0.5%, 1%, and 5% of the critical network latency, respectively, while sacrificing a small amount of runtime.

[0134] Table 4 compares the number of overflows and Slew violations before and after the introduction of the resource-aware strategy.

[0135]

[0136] As shown in Table 4, by introducing the resource-aware strategy, the track-aware method is used in the stage of eliminating wire overflow, and the area-aware method is used in the stage of avoiding via overflow. Both overflow scenarios were calculated to optimize the wiring effect. Therefore, compared with the case without the resource-aware strategy, the number of overflows decreased by 11%, and the number of slew violations decreased by 5%.

[0137] Table 5 compares the latency, via throughput, and runtime results before and after introducing the multi-refining strategy.

[0138]

[0139] As shown in Table 5, the introduction of the multi-refinement strategy prevented the routing scheme from overemphasizing overflow targets while neglecting timing optimization targets. Therefore, compared to the case without the multi-refinement strategy, the total latency, maximum latency, and latency of the first 0.5%, 1%, and 5% of critical nets were optimized by 2% and 5%, respectively. The number of vias was optimized by 3%. Due to the multiple unwinding and rewinding operations, a small amount of runtime was inevitably consumed.

[0140] Table 6 compares the overflow and slew violation counts before and after introducing the multi-refinement strategy.

[0141]

[0142] As shown in Table 6, the advantages of the high routing layer were fully utilized after the introduction of the multi-refinement strategy. Therefore, compared with the case without the multi-refinement strategy, the number of overflows decreased by 6% and the number of slew violations decreased by 5%.

Claims

1. A layer assignment method based on through-hole pillars and non-default rule lines under Slew constraints, characterized in that, Includes the following steps: Step 1: Define the objective function: Where cost(n) represents the total cost of the wire network, delay(n), via(n), cong(s), sv(n), and l(n) represent the delay cost, via cost, congestion cost, slew violation cost, and deviation cost, respectively; α, β, γ, λ, and δ are the delay weight, via weight, congestion weight, slew violation weight, and deviation weight, respectively. Step 2: Pre-allocation phase; Set initial values ​​for latency weight, via weight, congestion weight, slew violation weight, and deviation weight; Step 3: Eliminating and avoiding overflow phase; If the number of tracks used exceeds the grid edge capacity, an edge capacity overflow is determined to have occurred; if the area occupied by wires, vias, and obstacles in a grid cell is greater than the area of ​​the grid cell itself, a grid cell area overflow is determined to have occurred; a grid passing through an edge that has experienced edge capacity overflow or a grid passing through an edge that has experienced grid cell area overflow is defined as an illegal grid; the specific calculation formula is as follows: Formula (2) is the method for calculating grid cell overflow, where of(g), dc(g), and tc(g) represent the number of overflowing grid cells, the area occupied by grid cells, and the total area of ​​grid cells, respectively; Formula (3) is the formula for calculating edge capacity overflow, where of(e), dc(e), and tc(e) represent the number of overflowing edges, the edge capacity, and the capacity used, respectively. In the phase of eliminating edge capacity overflow, the track sensing method in the resource sensing strategy is adopted to completely eliminate all wire overflows; In the stage of avoiding grid cell area overflow, while ensuring that the edge capacity overflow is 0, the area-aware method using the resource-aware strategy further reduces grid cell area overflow. In the stages of eliminating edge capacity overflow and avoiding grid cell area overflow, the time delay weight, via weight, congestion weight, slew violation weight, and deviation weight are set to 0.1, 1, 1, 0.1, and 1, respectively. Step 4: Multiple refining stages; Without worsening overflow, the optimizable nets are de-wired and rewound multiple times, and the time delay weight and slew violation weight of the objective function are continuously adjusted in this process to obtain a layer allocation result; in addition, the via weight of the time-critical nets is increased. A multi-refinement strategy is adopted, which optimizes latency and slew by repeatedly unwinding and rewinding the wires. Set a refinement threshold and an optimizable candidate net set to avoid sacrificing too much runtime for timing performance optimization. End the multi-refinement strategy when the refinement threshold is reached or the optimizable candidate net set is empty. Increase the delay and slew weights during each de-route and re-route operation to make it easier to select layer allocation schemes with lower delay and slew for single-net layer allocation. Record the delay and slew violation counts of the original net for comparison with the de-route and re-route mesh. Remove the original net and reroute it. Compare the two nets and select the net with better timing performance as the final routing scheme. If the original net has better routing performance, it indicates that there is essentially no room for further optimization, so remove it from the selectable net set. Finally, set the latency weight, via weight, congestion weight, slew violation weight, and deviation weight to 0.1, 1, 1, 0.1, and 20 respectively; Step 5: slew grading strategy; Classify the nets according to the slew value of the signal receiver, and limit the nets at each level to the metal layers of the echelon; the non-timing critical nets are restricted to the metal layers of the lower echelon; Step 5-1: First, calculate the average slew value of the net, and the calculation method is as follows: Among them, avslew,P,slew p These represent the average slew value of the wire mesh, the set of signal receivers in the wire mesh, and the slew value of signal receiver p, respectively. Step 5-2: According to the average slew value avslew of the net, the slew constraint value reslew, and the metal layer structure, divide the nets into four levels. The specific division method is as follows: (1) When the average slew value avslew of the net satisfies 0.00 < avslew <= 0.35 * reslew, the net is defined as a first-level net and can be assigned to the first echelon routing layer; (2) When the average slew value avslew of the net satisfies 0.35 * reslew < avslew <= 1.00 * reslew, the net is defined as a second-level net and can be assigned to the second echelon routing layer; (3) When the average slew value avslew of the net satisfies 1.00 * reslew < avslew <= 4.00 * reslew, the net is defined as a third-level net and can be assigned to the third echelon routing layer; (4) When the average slew value avslew of the net satisfies avslew < 4.00 * reslew, the net is defined as a fourth-level net and there is no restriction on its routing layer; Step 5-3: Calculate the deviation cost in the objective function to achieve the purpose of restricting nets at different levels to appropriate metal layers. The calculation formula of the deviation cost is as follows: l(n) = μ × c(5) Among them, l(n) represents the deviation cost of net n, μ represents the custom parameter set to 0.75, and c is the deviation layer number, and its calculation method is as follows: Among them, S represents the set of wire segments in net n, hopes represents the metal layer that wire segment s is expected to be assigned to, and actuals represents the metal layer that wire segment s is actually assigned to.

2. The layer assignment method based on through-hole pillars and non-default rule lines under Slew constraints according to claim 1, characterized in that, The resource awareness strategy is specifically as follows: Step 3-1: For the two overflow situations of edge capacity overflow and grid cell area overflow, adopt the resource awareness strategy at different stages to optimize the overflow; in the stage of eliminating edge capacity overflow, it is required that the resource awareness strategy repair all edge capacity overflows; in the stage of avoiding grid cell area overflow, it is required that the resource awareness strategy minimize the grid cell area overflow when the edge overflow is 0, and require that the number of overflows reduced by each wire removal and rerouting reaches 1%; The resource awareness strategy reduces the overflow by updating the congestion cost in the objective function. The calculation formula of the congestion cost is as follows: cong(s) = of(s) × p(s)(7) Among them, cong(s), of(s), and p(s) represent the congestion cost, overflow amount, and penalty term respectively; In the stage of eliminating edge overflow, the track awareness method is adopted to repair all edge capacity overflows, and in the stage of grid cell area overflow, the area awareness method is adopted to further reduce the grid cell area overflow; Step 3-2: Track awareness method; During the edge overflow elimination phase, illegal wire networks with edge capacity overflow are repeatedly disassembled and rewound, and the congestion cost is continuously updated in the process to eliminate all edge capacity overflows. Since the track-aware method is dedicated to eliminating all edge capacity overflows, the overflow amount of(s) in the congestion cost is calculated using formula (2), and the penalty term p(s) in the congestion cost is calculated as follows: Where μ and ν are user-defined parameters, μ takes a value of 0.25 and ν takes a value of 0.05; e s p(s), u(e) represent the grid edges e that the conductor segment s passes through. s ),c(e s ),times represent the penalty term for conductor segment s, the usage of grid edge e, the capacity of grid edge e, and the current number of times to unwrap and rewind the wire, respectively. Step 3-3: Area sensing method; The stage of avoiding grid cell area overflow will ensure that the overflow optimization ratio is greater than 1% after each illegal wire mesh is removed and rewound, while ensuring that no edge capacity overflow occurs. Specifically, the area-aware method is continuously used to update the congestion cost to drive the single wire mesh layer allocation algorithm to find a wiring scheme with less overflow when each illegal wire mesh is removed and rewound. Since the track-aware method is committed to reducing grid cell area overflow, the overflow amount of(s) in the congestion cost is calculated using formula (3). The penalty term p(s) in the congestion cost is calculated as follows: p(s)=ε+u(g s )÷c(g s )(9) Among them, g s p(s), u(g) represent the grid edges traversed by conductor segment s; s ),c(g s ) represent the penalty term, the area occupied by grid cell g, and the total area of ​​grid cells, respectively; ε is a custom parameter, set to 1.

3. The layer assignment method based on through-hole pillars and non-default rule lines under Slew constraints according to claim 1, characterized in that, In step 2, the initial values ​​of the delay weight, via weight, congestion weight, slew violation weight, and deviation weight are set to 1, 0, 0.3, 0, and 1, respectively.

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