A two-dimensional semiconductor transistor based on a gate sandwich structure and a method for manufacturing the same

Abstract

The present invention discloses a two-dimensional semiconductor transistor based on a gate sandwich structure and a method for fabricating the same. The transistor comprises a substrate, a first two-dimensional semiconductor layer, and a second two-dimensional semiconductor layer, arranged sequentially from bottom to top. A source electrode, a gate assembly, and a drain electrode are arranged horizontally between the first and second two-dimensional semiconductor layers. The remaining area between the first and second two-dimensional semiconductor layers is filled with a first passivation layer. The gate assembly comprises a first gate dielectric layer, a gate electrode, and a second gate dielectric layer, arranged sequentially from bottom to top. A second passivation layer is filled above the second two-dimensional semiconductor layer. This fabrication method is used to fabricate the aforementioned transistor. The present invention has the advantages of a simple structure, easy fabrication, and improved electrical property consistency.

Description

Technical Field

[0001] The present invention mainly relates to the field of semiconductor technology, and in particular to a two-dimensional semiconductor transistor based on a gate sandwich structure and a preparation method thereof. Background Art

[0002] With the rapid development of integrated circuit technology, transistors are becoming smaller, with higher performance and integration, and lower power consumption. However, the leakage current of transistor channels based on three-dimensional bulk semiconductor materials increases rapidly at the sub-10 nanometer scale, making further size reduction difficult. This creates bottlenecks in both improving performance and reducing power consumption. Two-dimensional semiconductor transistors constructed from two-dimensional semiconductor materials such as graphene and molybdenum disulfide can overcome short-channel and quantum effects, maintain a good switching frequency, and have the potential to further improve performance and reduce power consumption.

[0003] In the prior art, the typical two-dimensional semiconductor transistor structure is a top-gate structure, that is, the gate is located on the top of the two-dimensional semiconductor, such as Figure 1 As shown, the structure includes a substrate 1, a two-dimensional semiconductor layer 200, a gate dielectric layer 300, a gate 4, a source 5, a drain 6, and a passivation layer 700. The lower surface of the two-dimensional semiconductor layer 200 contacts the upper surface of the substrate 1, the lower surface of the gate dielectric layer 300 contacts the upper surface of the two-dimensional semiconductor layer 200, and the lower surface of the gate 4 contacts the upper surface of the gate dielectric layer 300. The source 5 and drain 6 are located on either side of the gate dielectric layer 300 and the gate 4, respectively, and their lower surfaces contact the upper surface of the two-dimensional semiconductor layer 200. The space above the substrate 1, excluding the structure already described, is filled with the passivation layer 700.

[0004] In the aforementioned structure, the channel of a two-dimensional semiconductor transistor consists of only a single layer of two-dimensional planar material. During the manufacturing process, the lattice is easily damaged by process steps such as doping and etching. Furthermore, during use, it is also highly susceptible to lattice defects caused by factors such as hot carriers, electromigration ions, and high-energy space radiation. Lattice defects can degrade the transistor's electrical characteristics and consistency, reducing its yield.

[0005] Therefore, improving the consistency of electrical characteristics is the bottleneck and key to achieving large-scale applications, and relevant practitioners have made great efforts. For example, a practitioner has proposed a Chinese invention patent with patent application number 201810014816.8, which discloses a method for preparing a two-dimensional semiconductor transistor with a top-gate structure and a polymer electrolyte dielectric layer. This technical solution uses a polymer electrolyte as the gate dielectric layer and a high-precision hard mask plate to achieve the top gate, reducing gate leakage current and increasing transistor switching speed, optimizing electrical characteristics, but does not improve the consistency of electrical characteristics.

[0006] Another practitioner has proposed a Chinese invention patent with Chinese patent application number 202011555330.9, which discloses a performance-controllable two-dimensional semiconductor transistor structure and its preparation method. In this technical solution, the electric dipole effect generated by the solid-phase diffusion reaction between the active metal and the gate dielectric layer is used instead of ion doping to achieve transistor electrical performance regulation, reducing the two-dimensional semiconductor lattice damage defects caused by ion doping, which is beneficial to improving the yield, but has limited effect on defect damage caused by other process steps such as etching.

[0007] Another practitioner has proposed a Chinese invention patent with Chinese patent application number 202211489343.X, which discloses a solid-state source doping method based on two-dimensional semiconductors and a two-dimensional semiconductor transistor. This technical solution is to evaporate a solid active source metal layer on the surface of the two-dimensional semiconductor layer and then evaporate a conventional metal layer thereon as the source and drain electrodes, thereby suppressing the Fermi pinning effect, reducing the resistance of the source and drain contact with the two-dimensional semiconductor layer, and improving the consistency of electrical characteristics to a certain extent. Although the above scheme can improve the consistency of the electrical characteristics of two-dimensional semiconductor transistors to a certain extent, its consistency has not yet met the requirements for large-scale application, and further exploration of new practical solutions is needed. Summary of the Invention

[0008] The technical problem to be solved by the present invention is: in response to the technical problems existing in the prior art, the present invention provides a two-dimensional semiconductor transistor based on a gate sandwich structure with a simple structure, convenient preparation, and better consistency of electrical characteristics, and a preparation method thereof.

[0009] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0010] A two-dimensional semiconductor transistor based on a gate sandwich structure includes a substrate, a first two-dimensional semiconductor layer and a second two-dimensional semiconductor layer arranged in sequence from bottom to top, a source, a gate assembly and a drain arranged in sequence along the horizontal direction between the first two-dimensional semiconductor layer and the second two-dimensional semiconductor layer, and other areas between the first two-dimensional semiconductor layer and the second two-dimensional semiconductor layer are filled with a first passivation layer; the gate assembly includes a first gate dielectric layer, a gate and a second gate dielectric layer arranged in sequence from bottom to top; and a second passivation layer is filled above the second two-dimensional semiconductor layer.

[0011] As a further improvement of the transistor of the present invention: the lower surface of the first two-dimensional semiconductor layer contacts the upper surface of the substrate, and the lower surface of the first gate dielectric layer contacts the upper surface of the first two-dimensional semiconductor layer.

[0012] As a further improvement of the transistor of the present invention: the lower surface of the gate contacts the upper surface of the first gate dielectric layer, and the lower surface of the second gate dielectric layer contacts the upper surface of the gate.

[0013] As a further improvement of the transistor of the present invention: the source and the drain are respectively located on both sides of the first gate dielectric layer and the gate, contacting the upper surface of the first two-dimensional semiconductor layer and the lower surface of the second two-dimensional semiconductor layer.

[0014] As a further improvement of the transistor of the present invention: the upper surface of the source electrode, the upper surface of the second gate dielectric layer and the upper surface of the drain electrode are located in the same plane and all contact the lower surface of the second two-dimensional semiconductor layer.

[0015] As a further improvement of the transistor of the present invention: the remaining space from below the plane to above the substrate is filled with a first passivation layer, and the remaining space above the plane except the second two-dimensional semiconductor layer is filled with a second passivation layer.

[0016] As a further improvement to the transistor of the present invention, the first two-dimensional semiconductor layer and the second two-dimensional semiconductor layer have the same thickness.

[0017] As a further improvement to the transistor of the present invention, the difference in thickness between the first two-dimensional semiconductor layer and the second two-dimensional semiconductor layer is less than 0.5 nanometers.

[0018] The present invention further provides a method for preparing a two-dimensional semiconductor transistor based on a gate sandwich structure, the steps comprising:

[0019] Step S1: preparing a two-dimensional semiconductor layer I on the substrate surface;

[0020] Step S2: preparing a first mask layer on the two-dimensional semiconductor layer I, exposing an area where the two-dimensional semiconductor layer is not required, and removing the two-dimensional semiconductor layer in the area to form a first two-dimensional semiconductor layer;

[0021] Step S3: removing the first mask layer and preparing a second mask layer to expose the areas where the first gate dielectric layer, the gate electrode and the second gate dielectric layer are located;

[0022] Step S4: preparing a first dielectric layer;

[0023] Step S5: preparing a first metal layer;

[0024] Step S6: preparing a second dielectric layer, the thickness of which is not less than that of the first dielectric layer;

[0025] Step S7: removing the second mask layer to form a first gate dielectric layer and a gate;

[0026] Step S8: preparing a third mask layer to expose the source and drain regions;

[0027] Step S9: preparing a second metal layer, the height of which should not be lower than that of the second dielectric layer;

[0028] Step S10: removing the third mask layer;

[0029] Step S11: preparing a passivation layer:

[0030] Step S12: polishing and thinning the upper surface of the passivation layer until the second metal layer and the second dielectric layer are exposed, and continuing polishing and thinning to form a first passivation layer, a second gate dielectric layer, a source electrode, and a drain electrode;

[0031] Step S13: preparing a two-dimensional semiconductor layer II;

[0032] Step S14: preparing a fourth mask layer on the two-dimensional semiconductor layer II to expose an area where the two-dimensional semiconductor layer is not required, and removing the two-dimensional semiconductor layer in the area to form a second two-dimensional semiconductor layer;

[0033] Step S15: removing the fourth mask layer;

[0034] Step S16: preparing a second passivation layer to form a two-dimensional semiconductor transistor based on a gate sandwich structure.

[0035] As a further improvement of the above method: in step S12, the thickness of the second dielectric layer is made the same as the thickness of the first gate dielectric layer, or the difference between the thickness of the second dielectric layer and the thickness of the first gate dielectric layer is made less than 0.5 nanometers.

[0036] Compared with the prior art, the advantages of the present invention are:

[0037] 1. The present invention discloses a two-dimensional semiconductor transistor based on a gate sandwich structure and a method for preparing the same, which has a simple structure and is easy to prepare. The present invention sandwiches the gate between two layers of two-dimensional semiconductor material to form two sets of vertically arranged identical transistor structures in parallel. This not only increases the on-current and enhances device performance, but also enables the characteristics of the two sets of identical transistors to complement and average each other, greatly enhancing the consistency of electrical characteristics.

[0038] 2. The present invention provides a two-dimensional semiconductor transistor based on a gate sandwich structure and a method for preparing the same, which uses two sets of identical transistor structures in a vertical layout, thereby enhancing device performance and consistency without increasing device area, and thus having a high cost advantage.

[0039] 3. The present invention provides a two-dimensional semiconductor transistor based on a gate sandwich structure and a method for preparing the same. Two sets of identical transistors are used to compensate for changes in the device's electrical characteristics caused by factors such as hot carriers, electromigration ions, and high-energy space rays during use, thereby improving reliability and life.

[0040] 4. The present invention provides a two-dimensional semiconductor transistor based on a gate sandwich structure and a preparation method thereof. To address the problem of low consistency in the electrical characteristics of current two-dimensional semiconductor transistors, a two-dimensional semiconductor transistor structure with better consistency in electrical characteristics and a preparation method thereof are proposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of a traditional two-dimensional semiconductor transistor structure in the prior art.

[0042] Figure 2 It is a schematic diagram of the structural principle of the transistor of the present invention in a specific application example.

[0043] Figure 3 It is a schematic diagram of the principle of step S1 in a specific application example of the preparation method of the present invention.

[0044] Figure 4 It is a schematic diagram of the principle of step S2 in a specific application example of the preparation method of the present invention.

[0045] Figure 5 It is a schematic diagram of the principle of step S3 in a specific application example of the preparation method of the present invention.

[0046] Figure 6 It is a schematic diagram of the principle of step S4 in a specific application example of the preparation method of the present invention.

[0047] Figure 7 It is a schematic diagram of the principle of step S5 in a specific application example of the preparation method of the present invention.

[0048] Figure 8 It is a schematic diagram of the principle of step S6 in a specific application example of the preparation method of the present invention.

[0049] Figure 9 It is a schematic diagram of the principle of step S7 in a specific application example of the preparation method of the present invention.

[0050] Figure 10 It is a schematic diagram of the principle of step S8 in a specific application example of the preparation method of the present invention.

[0051] Figure 11 It is a schematic diagram of the principle of step S9 in a specific application example of the preparation method of the present invention.

[0052] Figure 12 It is a schematic diagram of the principle of step S10 in a specific application example of the preparation method of the present invention.

[0053] Figure 13 It is a schematic diagram of the principle of step S11 in a specific application example of the preparation method of the present invention.

[0054] Figure 14 It is a schematic diagram of the principle of step S12 in a specific application example of the preparation method of the present invention.

[0055] Figure 15It is a schematic diagram of the principle of step S13 in a specific application example of the preparation method of the present invention.

[0056] Figure 16 It is a schematic diagram of the principle of step S14 in a specific application example of the preparation method of the present invention.

[0057] Figure 17 It is a schematic diagram of the principle of step S15 in a specific application example of the preparation method of the present invention.

[0058] Figure 18 It is a schematic diagram of the principle of step S16 in a specific application example of the preparation method of the present invention. DETAILED DESCRIPTION

[0059] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] In the description of this application, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0061] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0062] In this application, unless otherwise specified or limited, the terms "assemble," "connect," "connect," "fix," and the like should be understood in a broad sense. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0063] like Figure 2As shown, a two-dimensional semiconductor transistor based on a gate sandwich structure of the present invention includes a substrate 1, a first two-dimensional semiconductor layer 2 and a second two-dimensional semiconductor layer 9 arranged in sequence from bottom to top, a source 5, a gate assembly and a drain 6 are arranged in sequence along the horizontal direction between the first two-dimensional semiconductor layer 2 and the second two-dimensional semiconductor layer 9, and other areas between the first two-dimensional semiconductor layer 2 and the second two-dimensional semiconductor layer 9 are filled with a first passivation layer 7; the gate assembly includes a first gate dielectric layer 3, a gate 4 and a second gate dielectric layer 8 arranged in sequence from bottom to top; and a second passivation layer 10 is filled above the second two-dimensional semiconductor layer 9.

[0064] In a specific application example, the lower surface of the first two-dimensional semiconductor layer 2 contacts the upper surface of the substrate 1 , and the lower surface of the first gate dielectric layer 3 contacts the upper surface of the first two-dimensional semiconductor layer 2 .

[0065] In a specific application example, the lower surface of the gate 4 contacts the upper surface of the first gate dielectric layer 3 , and the lower surface of the second gate dielectric layer 8 contacts the upper surface of the gate 4 .

[0066] In a specific application example, the source electrode 5 and the drain electrode 6 are respectively located on both sides of the first gate dielectric layer 3 and the gate electrode 4 , contacting the upper surface of the first two-dimensional semiconductor layer 2 and the lower surface of the second two-dimensional semiconductor layer 9 .

[0067] In a specific application example, the upper surface of the source electrode 5 , the upper surface of the second gate dielectric layer 8 , and the upper surface of the drain electrode 6 are located in the same plane and all contact the lower surface of the second two-dimensional semiconductor layer 9 .

[0068] In a specific application example, the remaining space from below the plane to above the substrate 1 except the structure described above is filled with the first passivation layer 7 , and the remaining space above the plane except the second two-dimensional semiconductor layer 9 is filled with the second passivation layer 10 .

[0069] In a preferred embodiment, the thickness of the first two-dimensional semiconductor layer 2 and the second two-dimensional semiconductor layer 9 can be selected to be the same.

[0070] In another embodiment, according to actual needs, the thickness difference between the first two-dimensional semiconductor layer 2 and the second two-dimensional semiconductor layer 9 can be selected to be less than 0.5 nanometers.

[0071] like Figure 3-Figure 18 As shown, the present invention further provides a method for preparing a two-dimensional semiconductor transistor based on a gate sandwich structure, the steps comprising:

[0072] Step S1: Prepare a two-dimensional semiconductor layer I201 on the surface of substrate 1, such as Figure 3 As shown;

[0073] Step S2: Prepare a first mask layer 301 on the two-dimensional semiconductor layer I 201 to expose the area where the two-dimensional semiconductor layer is not required, and remove the two-dimensional semiconductor layer in the area to form a first two-dimensional semiconductor layer 2, such as Figure 4 As shown;

[0074] Step S3: remove the first mask layer 301 and prepare a second mask layer 302 to expose the area where the first gate dielectric layer 3, the gate electrode 4 and the second gate dielectric layer 8 are located. Figure 5 As shown;

[0075] Step S4: Prepare the first dielectric layer 401, such as Figure 6 As shown;

[0076] Step S5: Prepare the first metal layer 501, such as Figure 7 As shown;

[0077] Step S6: Prepare the second dielectric layer 402, the thickness of which is not less than the thickness of the first dielectric layer 401, such as Figure 8 As shown;

[0078] Step S7: remove the second mask layer 302 to form the first gate dielectric layer 3 and the gate 4. Figure 9 As shown;

[0079] Step S8: Prepare a third mask layer 303 to expose the area where the source 5 and the drain 6 are located, such as Figure 10 As shown;

[0080] Step S9: Prepare the second metal layer 502, the height of which should not be lower than the second dielectric layer 402, such as Figure 11 As shown;

[0081] Step S10: removing the third mask layer 303, such as Figure 12 As shown;

[0082] Step S11: Prepare a passivation layer 601, such as Figure 13 As shown:

[0083] Step S12: Polish and thin the upper surface of the passivation layer 601 until the second metal layer 502 and the second dielectric layer 402 are exposed, and continue polishing and thinning until the thickness of the second dielectric layer 402 is the same as that of the first gate dielectric layer 3, with a thickness difference of less than 0.5 nanometers, to form the first passivation layer 7, the second gate dielectric layer 8, the source 5 and the drain 6. Figure 14 As shown;

[0084] Step S13: Prepare a two-dimensional semiconductor layer II 202, such as Figure 15 As shown;

[0085] Step S14: Prepare a fourth mask layer 304 on the two-dimensional semiconductor layer II 202 to expose the area where the two-dimensional semiconductor layer is not required, and remove the two-dimensional semiconductor layer in the area to form a second two-dimensional semiconductor layer 9, such as Figure 16 As shown;

[0086] Step S15: remove the fourth mask layer 304, such as Figure 17 As shown;

[0087] Step S16: preparing a second passivation layer 10 to form a two-dimensional semiconductor transistor based on a gate sandwich structure, such as Figure 18 shown.

[0088] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the principles of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A method for preparing a two-dimensional semiconductor transistor based on a gate sandwich structure, characterized in that the steps include: Step S1: preparing a two-dimensional semiconductor layer I (201) on the surface of the substrate (1); Step S2: preparing a first mask layer (301) on the two-dimensional semiconductor layer I (201), exposing an area where the two-dimensional semiconductor layer is not required, and removing the two-dimensional semiconductor layer in the area to form a first two-dimensional semiconductor layer (2); Step S3: removing the first mask layer (301), preparing a second mask layer (302), and exposing the areas where the first gate dielectric layer (3), the gate electrode (4), and the second gate dielectric layer (8) are located; Step S4: preparing a first dielectric layer (401); Step S5: preparing a first metal layer (501); Step S6: preparing a second dielectric layer (402) having a thickness not less than that of the first dielectric layer (401); Step S7: removing the second mask layer (302) to form a first gate dielectric layer (3) and a gate (4); Step S8: preparing a third mask layer (303) to expose the areas where the source electrode (5) and the drain electrode (6) are located; Step S9: preparing a second metal layer (502), the height of which should not be lower than the second dielectric layer (402); Step S10: removing the third mask layer (303); Step S11: preparing a passivation layer (601): Step S12: polishing and thinning the upper surface of the passivation layer (601) until the second metal layer (502) and the second dielectric layer (402) are exposed, and continuing polishing and thinning to form a first passivation layer (7), a second gate dielectric layer (8), a source electrode (5), and a drain electrode (6); Step S13: preparing a two-dimensional semiconductor layer II (202); Step S14: preparing a fourth mask layer (304) on the two-dimensional semiconductor layer II (202), exposing an area where the two-dimensional semiconductor layer is not required, and removing the two-dimensional semiconductor layer in the area to form a second two-dimensional semiconductor layer (9); Step S15: removing the fourth mask layer (304); Step S16: preparing a second passivation layer (10) to form a two-dimensional semiconductor transistor based on a gate sandwich structure.

2. The method for preparing a two-dimensional semiconductor transistor based on a gate sandwich structure according to claim 1, characterized in that: In step S12, the thickness of the second dielectric layer (402) is the same as the thickness of the first gate dielectric layer (3), or the difference between the thickness of the second dielectric layer (402) and the thickness of the first gate dielectric layer (3) is less than 0.5 nanometers.

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