A reference clock detection circuit for use in a phase-locked loop circuit

Abstract

The application discloses a reference clock detection circuit used in a phase-locked loop circuit, comprising a counter sub-circuit, a first logic control sub-circuit, a second logic control sub-circuit and a sampling sub-circuit; the first logic control sub-circuit receives a reference clock and a phase-locked loop enable signal, and outputs a count reset signal to the counter sub-circuit; the counter sub-circuit receives a feedback clock signal and counts the feedback clock signal; the second logic control sub-circuit receives the feedback clock signal, a count signal output by the counter sub-circuit, the phase-locked loop enable signal and an indication signal output by the sampling sub-circuit; the sampling sub-circuit receives a sampling reset signal and a sampling clock signal, and outputs the indication signal to a subsequent circuit, so that the subsequent circuit receives an indication of normal operation / abnormal operation of the reference clock, and the indication signal is fed back to the second logic control sub-circuit. The application has the advantages of simple circuit, easy implementation and low cost.

Description

Technical Field

[0001] This invention relates to the field of CMOS integrated circuit design, and in particular to a reference clock detection circuit for use in a phase-locked loop circuit. Background Technology

[0002] As chip system applications become increasingly complex, signal interaction between clock systems faces various challenges. In practical applications of phase-locked loop (PLL) systems, situations may arise where the reference clock is abnormal or suddenly drops (e.g., due to factors such as crystal oscillator failure). However, because a PLL is a closed-loop system, even after the reference clock drops, the loop continues to operate, and the VCO (voltage-controlled oscillator) continues to oscillate. However, the output frequency becomes abnormal and inaccurate, which is highly detrimental to subsequent systems: the PLL output clock is unusable, but the PLL itself doesn't inform the subsequent system of the clock anomaly (it continues oscillating and outputting frequency), leading to malfunctions or even system crashes in the subsequent PLL systems. Summary of the Invention

[0003] The main objective of this invention is to provide a reference clock detection circuit for phase-locked loop circuits, which aims to prevent subsequent system malfunctions caused by the clock becoming unusable.

[0004] To achieve the above objectives, the present invention provides a reference clock detection circuit for a phase-locked loop circuit, comprising a counter sub-circuit, a first logic control sub-circuit, a second logic control sub-circuit, and a sampling sub-circuit; The first logic control sub-circuit receives a reference clock and a phase-locked loop enable signal. When the reference clock is valid, it outputs a count reset signal to the counter sub-circuit. The counter sub-circuit receives the feedback clock signal and counts the feedback clock signal. The counter sub-circuit is connected to the first logic control sub-circuit and is reset to zero according to the count reset signal. The second logic control sub-circuit receives the feedback clock signal, the counting signal output by the counter sub-circuit, the phase-locked loop enable signal, and the indication signal output by the sampling sub-circuit, and outputs a sampling reset signal and a sampling clock signal to the sampling sub-circuit; The sampling sub-circuit receives the sampling reset signal and the sampling clock signal and outputs an indication signal to the subsequent circuit so that the subsequent circuit receives an indication of whether the reference clock is working properly or not. At the same time, the indication signal is fed back to the second logic control sub-circuit.

[0005] Preferably, the first logic control sub-circuit includes a first NOT gate, a first NAND gate, and a second NOT gate. The input terminal of the first NOT gate receives the reference clock, and its output terminal is connected to the first input terminal of the first NAND gate. The second input terminal of the first NAND gate receives the phase-locked loop enable signal, and its output terminal is connected to the input terminal of the second NOT gate. The output terminal of the second NOT gate outputs the count reset signal to the counter circuit.

[0006] Preferably, the counter sub-circuit includes a first flip-flop and a second flip-flop. The clock input terminal of the first flip-flop receives the feedback clock signal, and its data input terminal is connected to its QN output terminal, which is also connected to the clock input terminal of the second flip-flop. The data input terminal of the second flip-flop is connected to its QN output terminal, and the Q output terminal of the second flip-flop outputs the counting signal of the counter sub-circuit. The reset terminals of both the first and second flip-flops are connected to the output terminal of the first logic control sub-circuit.

[0007] Preferably, the counter sub-circuit is used to count the feedback clock signal, and after counting four cycles of the feedback clock signal, it outputs a count signal to the second logic control sub-circuit.

[0008] Preferably, the second logic control sub-circuit includes a first NOR gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a second NOR gate, and an NMOS field-effect transistor; The input terminals of the first NOR gate are respectively connected to the output terminals of the counter sub-circuit and the sampling sub-circuit. The output terminal of the first NOR gate is connected to the input terminal of the third NOT gate. The input terminal of the fourth NOT gate receives the phase-locked loop enable signal input, and its output terminal is connected to the gate of the NMOS field-effect transistor. The source of the NMOS field-effect transistor is grounded, and its drain is connected to the output terminal of the third NOT gate, and it outputs the sampling reset signal to the sampling sub-circuit. The input terminal of the fifth NOT gate receives the reference clock, and its output terminal is connected to the input terminal of the second NOR gate. The other input terminal of the second NOR gate is connected to the output terminal of the sampling sub-circuit, and the second NOR gate outputs the sampling clock signal to the sampling sub-circuit.

[0009] Preferably, the sampling sub-circuit includes a third flip-flop, the clock input terminal of which receives the sampling clock signal, the data input terminal is connected to the power supply voltage, the reset terminal receives the sampling reset signal, and the Q output terminal outputs an indication signal to the subsequent circuit and feeds it back to the second logic control sub-circuit.

[0010] Preferably, all of the above triggers are D triggers.

[0011] The technical solution of this invention uses a counter sub-circuit, a first logic control sub-circuit, a second logic control sub-circuit, and a sampling sub-circuit. When the reference clock is normal, it outputs an indication signal to provide subsequent circuits with an indication that the reference clock is normal; when the reference clock is abnormal (dropped), it outputs an indication signal to provide subsequent circuits with an indication that the reference clock is abnormal, so as to avoid subsequent system malfunctions caused by the clock being unusable. The circuit of this invention is simple, easy to implement, and low in cost. Attached Figure Description

[0012] Figure 1 This is a timing diagram of the reference clock detection function in an embodiment of the present invention; Figure 2 This is a schematic diagram of the reference clock detection circuit used in a phase-locked loop circuit according to the present invention; Figure 3 This is a circuit diagram of the reference clock detection circuit used in a phase-locked loop circuit according to the present invention. Implementation

[0013] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0014] The invention will be further described below with reference to the accompanying drawings.

[0015] This invention provides a reference clock detection circuit for a phase-locked loop (PLL) circuit, used to detect whether the reference clock in the PLL system is working normally. In this embodiment, an abnormal state of the reference clock refers to the reference clock suddenly dropping during operation and remaining at a low level. Specifically, the function is as follows: when the PLL is enabled and the reference clock is normal, the detection circuit sends an indication signal CKIN_DOWN = "0", indicating that the reference clock has not dropped; when the reference clock suddenly drops, although the PLL loop is still working, the detection circuit sends an indication signal CKIN_DOWN = "1", indicating that the reference clock has dropped.

[0016] like Figure 2 As shown, the detection circuit includes a counter sub-circuit, a first logic control sub-circuit, a second logic control sub-circuit, and a sampling sub-circuit.

[0017] The first logic control subcircuit receives the reference clock CKIN and the phase-locked loop enable signal PLL_EN. When the reference clock CKIN is valid, it outputs the count reset signal RN1 to the counter subcircuit. When the reference clock CKIN is abnormal, the first logic control subcircuit outputs a count signal (the inverted version of the count reset signal RN1) to the counter subcircuit, causing the counter subcircuit to start counting. In other words, when the reference clock CKIN is valid, the first logic subcircuit outputs the count reset signal RN1 to the counter subcircuit, causing the counter subcircuit to continuously reset and clear to zero, preventing continuous counting. When the reference clock CKIN is abnormal or fails, the counter subcircuit stops clearing and counting, and can count normally.

[0018] Specifically, such as Figure 3 As shown, the first logic control sub-circuit includes a first NOT gate N1, a first NAND gate NAND1, and a second NOT gate N2. The input of the first NOT gate N1 receives the reference clock CKIN, and its output is connected to the first input of the first NAND gate NAND1. The second input of the first NAND gate NAND1 receives the phase-locked loop enable signal PLL_EN, and its output is connected to the input of the second NOT gate N2. The output of the second NOT gate N2 outputs a count reset signal RN1 to the counter circuit.

[0019] Specifically, when the phase-locked loop enable signal PLL_EN is low, the first logic control sub-circuit outputs a low level; when the phase-locked loop enable signal PLL_EN is high, the count reset signal RN1 output by the first logic control sub-circuit is the inverted version of the reference clock CKIN. That is, when the phase-locked loop enable signal PLL_EN is high and the reference clock CKIN is low, the first logic control sub-circuit outputs a high level, and when the phase-locked loop enable signal PLL_EN is high and the reference clock CKIN is high, the count reset signal RN1 is low.

[0020] The counter sub-circuit receives the feedback clock signal CKFB and counts the feedback clock signal CKFB. The counter sub-circuit is connected to the first logic control sub-circuit and is reset to zero according to the count reset signal RN1. When the reference clock CKIN is valid, the counter sub-circuit receives the count reset signal RN1 from the first logic control sub-circuit and continuously counts to zero. At this time, the output of the counter sub-circuit is low. When the reference clock CKIN fails abnormally, it starts counting continuously. When the count reaches a preset period, the output of the counter sub-circuit is high.

[0021] In a phase-locked loop (PLL) system, when the PLL starts running after receiving a reference clock, the feedback clock gradually approaches the reference clock, and its frequency and phase eventually become the same as the reference clock. At this point, the PLL is locked. If the reference clock is abnormal or suddenly drops (i.e., the reference clock input logic is "0"), the frequency of the feedback clock will gradually decrease until its frequency and phase become the same as the reference clock.

[0022] Specifically, such as Figure 3 As shown, the counter sub-circuit includes a first flip-flop C1 and a second flip-flop C2. The clock input terminal CK1 of the first flip-flop C1 receives the feedback clock signal CKFB, and its data input terminal D1 is connected to its QN output terminal QN1. Its QN output terminal QN1 is also connected to the clock input terminal CK2 of the second flip-flop C2. The data input terminal D2 of the second flip-flop C2 is connected to its QN output terminal QN2, and its Q output terminal Q2 outputs the counting signal Q of the counter sub-circuit. The reset terminals RN and RN′ of the first flip-flop C1 and the second flip-flop C2 are both connected to the output terminal of the first logic control sub-circuit.

[0023] Specifically, the counter sub-circuit is used to count the feedback clock signal CKFB. After counting four cycles of the feedback clock signal CKFB, it outputs a high level to the second logic control sub-circuit. When the counter is reset within four cycles of the feedback clock signal CKFB, the counter sub-circuit outputs a low level (i.e., no counting signal is output). In some embodiments, the counting period of the feedback clock signal CKFB can be customized according to factors such as the frequency and phase of the reference clock in the actual circuit.

[0024] Specifically, when the first logic control subcircuit outputs a low level, the counter subcircuit is reset and outputs a low level. When the first logic control subcircuit outputs a high level, the counter subcircuit starts counting the feedback clock signal CKFB. When it has counted four cycles of the feedback clock signal CKFB, the counter subcircuit outputs a high level. If the counter subcircuit receives a low level output from the first logic control subcircuit within four cycles of the feedback clock signal CKFB, the counter subcircuit is reset. When it receives a high level output from the first logic control subcircuit again, the counter subcircuit starts counting again.

[0025] The second logic control subcircuit receives the phase-locked loop enable signal PLL_EN, the count signal Q output from the counter subcircuit, and the indicator signal CKIN_DOWN output from the sampling subcircuit. It then outputs a sampling reset signal RN2 and a sampling clock signal CKFB_INT to the sampling subcircuit. The second logic control subcircuit is used to provide a reset signal to the sampling subcircuit.

[0026] Specifically, such as Figure 3As shown, the second logic control sub-circuit includes a first NOR gate NOR1, a third NOT gate N3, a fourth NOT gate N4, a fifth NOT gate N5, a second NOR gate NOR2, and an NMOS field-effect transistor. The input of the first NOR gate NOR1 is connected to the output of the counter sub-circuit and the output of the sampling sub-circuit, respectively. The output of the first NOR gate NOR1 is connected to the input of the third NOT gate N3. The input of the fourth NOT gate N4 receives the phase-locked loop enable signal PLL_EN, and its output is connected to the gate of the NMOS field-effect transistor. The source of the NMOS field-effect transistor is grounded to VSS, and its drain is connected to the output of the third NOT gate N3, and it outputs a sampling reset signal RN2 to the sampling sub-circuit. The input of the fifth NOT gate N5 receives the reference clock CKIN, and its output is connected to the input of the second NOR gate NOR2. The other input of the second NOR gate NOR2 is connected to the output of the sampling sub-circuit, and the second NOR gate NOR2 outputs a sampling clock to the sampling sub-circuit.

[0027] When both the counter subcircuit and the sampling subcircuit output a low level (i.e., the counter subcircuit is reset to zero, and the sampling subcircuit outputs the indicator signal CKIN_DOWN indicating that the reference clock CKIN is normal), the second logic control subcircuit outputs the sampling clock signal CKFB_INT as the reference clock CKIN and the sampling reset signal RN2 is low; at this time, the sampling subcircuit does not work. When the counter subcircuit outputs a high level (i.e., the reference clock CKIN input is low, and the counter subcircuit counts for four cycles of the feedback clock signal CKFB), the second logic control subcircuit outputs the sampling reset signal RN2 as high, and the sampling subcircuit starts working; when the sampling subcircuit outputs the indicator signal CKIN_DOWN as high (i.e., indicating that the reference clock CKIN is abnormal), the second logic control subcircuit outputs the sampling reset signal RN2 as high and the sampling clock signal CKFB_INT as low, and the sampling subcircuit stops working.

[0028] The sampling sub-circuit receives the sampling reset signal RN2 and the sampling clock signal CKFB_INT and outputs the indication signal CKIN_DOWN to the subsequent circuit so that the subsequent circuit receives an indication of whether the reference clock CKIN is working normally or not. At the same time, the indication signal CKIN_DOWN is fed back to the second logic control sub-circuit.

[0029] Specifically, such as Figure 3 As shown, the sampling sub-circuit includes a third flip-flop C3. The clock input terminal CK3 of the third flip-flop C3 receives the sampling clock signal CKFB_INT, the data input terminal D3 is connected to the power supply voltage VDD, the reset terminal RN″ receives the sampling reset signal RN2, and the Q output terminal Q3 outputs the indicator signal CKIN_DOWN to the subsequent circuit and feeds it back to the second logic control sub-circuit.

[0030] When the sampling reset signal RN2 is low, the third flip-flop C3 is reset, and the indicator signal CKIN_DOWN outputs a low level, indicating that the reference clock CKIN is working normally. When the sampling reset signal RN2 is high, the sampling sub-circuit starts working, the sampling clock signal CKFB_INT samples the power supply, and the indicator signal CKIN_DOWN outputs a high level, indicating that the reference clock CKIN is in an abnormal state.

[0031] In a specific embodiment, the first flip-flop C1, the second flip-flop C2, and the third flip-flop C3 are all D flip-flops.

[0032] The working principle of this invention embodiment is as follows: Combination Figure 1-3 In the reference clock detection circuit for a phase-locked loop circuit in this embodiment of the invention, when the initial phase-locked loop enable signal PLL_EN is in the "0" state, the sampling sub-circuit is reset and outputs "0". When the reference clock CKIN is input normally, the phase-locked loop enable signal PLL_EN rises. At this time, the sampling sub-circuit maintains its initial "0", and the indicator signal CKIN_DOWN of the sampling sub-circuit outputs "0". The counter sub-circuit receives the counting reset signal RN1 output by the first logic control sub-circuit, which is equal to the inverse of the reference clock CKIN and keeps toggling. Since the frequency of the feedback clock signal CKFB is always less than or equal to the reference clock CKIN, the counter sub-circuit keeps switching between counting and resetting, and the output Q of the counter sub-circuit always outputs "0". Because the indicator signal CKIN_DOWN is "0", after passing through the second logic control sub-circuit, the sampling clock signal CKFB_INT is equal to the feedback clock signal CKFB. And since the indicator signal CKIN_DOWN and the output Q of the counter sub-circuit are both in a logic "0" state at this time, after passing through the second logic control sub-circuit again, the sampling reset signal RN2 remains "0", so that the sampling sub-circuit always outputs "0". At this time, the entire reference clock detection circuit judges that the frequency of the reference clock CKIN is normal.

[0033] When the reference clock CKIN suddenly drops, the input to CKIN is "0". The first logic control sub-circuit outputs a count reset signal RN1 of "1". The counter sub-circuit, receiving a high-level count reset signal RN1, will not be reset to zero. After four cycles of the feedback clock signal CKFB, the output Q of the counter sub-circuit outputs "1". When the output Q of the counter sub-circuit is "1", the second logic control sub-circuit outputs a sampling reset signal RN2 of "1", and the sampling sub-circuit starts working. The sampling clock signal CKFB_INT samples the power supply VDD. After the first rising edge of the sampling clock signal CKFB_INT, the indicator signal CKIN_D is output. OWN is "1"; the indicator signal CKIN_DOWN is "1" and is then fed back to the second logic control sub-circuit. On one hand, it performs logic with the output Q of the counter sub-circuit, making the output sampling reset signal RN2 always "1". On the other hand, it performs inverse logic with the feedback clock signal CKFB, outputting the sampling clock signal CKFB_INT as "0". At this time, the sampling clock of the sampling sub-circuit is "0", and the sampling sub-circuit will no longer sample, and the output indicator signal CKIN_DOWN remains "1". At this time, the entire reference clock detection circuit determines that the reference clock CKIN frequency is in an abnormal state. When the subsequent circuit receives the indicator signal as "1", it performs corresponding actions such as shutting down the circuit.

[0034] It should be understood that the above are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A reference clock detection circuit for use in a phase-locked loop circuit, characterized in that, It includes a counter sub-circuit, a first logic control sub-circuit, a second logic control sub-circuit, and a sampling sub-circuit; The first logic control sub-circuit receives a reference clock and a phase-locked loop enable signal. When the reference clock is valid, it outputs a count reset signal to the counter sub-circuit. The counter sub-circuit receives the feedback clock signal and counts the feedback clock signal. The counter sub-circuit is connected to the first logic control sub-circuit and is reset to zero according to the count reset signal. The second logic control sub-circuit receives the feedback clock signal, the counting signal output by the counter sub-circuit, the phase-locked loop enable signal, and the indication signal output by the sampling sub-circuit, and outputs a sampling reset signal and a sampling clock signal to the sampling sub-circuit; The sampling sub-circuit receives the sampling reset signal and the sampling clock signal and outputs an indication signal to the subsequent circuit so that the subsequent circuit receives an indication of whether the reference clock is working normally or not. At the same time, the indication signal is fed back to the second logic control sub-circuit. The first logic control sub-circuit includes a first NOT gate, a first NAND gate, and a second NOT gate. The input terminal of the first NOT gate receives the reference clock, and its output terminal is connected to the first input terminal of the first NAND gate. The second input terminal of the first NAND gate receives the phase-locked loop enable signal, and its output terminal is connected to the input terminal of the second NOT gate. The output terminal of the second NOT gate outputs the count reset signal to the counter circuit.

2. The reference clock detection circuit for a phase-locked loop circuit according to claim 1, characterized in that, The counter sub-circuit includes a first flip-flop and a second flip-flop. The clock input terminal of the first flip-flop receives the feedback clock signal, and its data input terminal is connected to its QN output terminal. Its QN output terminal is also connected to the clock input terminal of the second flip-flop. The data input terminal of the second flip-flop is connected to its QN output terminal, and the Q output terminal of the second flip-flop outputs the counting signal of the counter sub-circuit. The reset terminals of both the first and second flip-flops are connected to the output terminal of the first logic control sub-circuit.

3. The reference clock detection circuit for a phase-locked loop circuit according to claim 2, characterized in that, The first flip-flop and the second flip-flop are D flip-flops.

4. The reference clock detection circuit for a phase-locked loop circuit according to claim 2, characterized in that, The counter sub-circuit is used to count the feedback clock signal. After counting four cycles of the feedback clock signal, it outputs a count signal to the second logic control sub-circuit.

5. The reference clock detection circuit for a phase-locked loop circuit according to claim 1, characterized in that, The second logic control sub-circuit includes a first NOR gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a second NOR gate, and an NMOS field-effect transistor; The input terminals of the first NOR gate are respectively connected to the output terminals of the counter sub-circuit and the sampling sub-circuit. The output terminal of the first NOR gate is connected to the input terminal of the third NOT gate. The input terminal of the fourth NOT gate receives the phase-locked loop enable signal input, and its output terminal is connected to the gate of the NMOS field-effect transistor. The source of the NMOS field-effect transistor is grounded, and its drain is connected to the output terminal of the third NOT gate, and it outputs the sampling reset signal to the sampling sub-circuit. The input terminal of the fifth NOT gate receives the reference clock, and its output terminal is connected to the input terminal of the second NOR gate. The other input terminal of the second NOR gate is connected to the output terminal of the sampling sub-circuit, and the second NOR gate outputs the sampling clock signal to the sampling sub-circuit.

6. The reference clock detection circuit for a phase-locked loop circuit according to claim 1, characterized in that, The sampling sub-circuit includes a third flip-flop. The clock input terminal of the third flip-flop receives the sampling clock signal, the data input terminal is connected to the power supply voltage, the reset terminal receives the sampling reset signal, and the Q output terminal outputs an indication signal to the subsequent circuit and feeds it back to the second logic control sub-circuit.

7. The reference clock detection circuit for a phase-locked loop circuit according to claim 6, characterized in that, The third trigger is a D trigger.

Images