A test structure layout processing method

Abstract

The present invention provides a method for processing a test structure layout, comprising selecting a target structure; automatically taking a screenshot of the layout; defining the layers included in the screenshot; naming the screenshot image with the name of the top-level unit of the target structure and annotating the screenshot name in the screenshot image; obtaining the pin name of the target structure and annotating it in the screenshot image; presetting a size threshold for evaluating the resolution of the screenshot image and completing the screenshot based on the threshold; and automatically generating a screenshot file for data analysis. A feasible automatic screenshot solution is provided, capable of providing test structure layout information. The screenshot image is directly used for data analysis, significantly improving analysis speed and accuracy, avoiding frequent queries of actual layout files, reducing time costs, improving work efficiency, and facilitating in-depth optimization of chip test process levels.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor design and production, and in particular relates to a test structure layout processing method. Background Art

[0002] Test structures are used to measure and monitor process parameters. They are essential in all stages of integrated circuit process development, including pre-, mid-, and post-process development, and are an important means of assisting process development. Test structure types include conventional test structure types and dedicated test structures based on product chips. The test structure based on product chips is a customized test chip used for product chip yield and performance diagnosis. It means that while ensuring that the front-end process layer of the product chip remains unchanged, the back-end process layer is changed and key components are directly connected to the PAD (pad), thereby achieving direct connection testing of key components of the product chip in a real physical environment.

[0003] After obtaining the measurement data of each test structure through testing, when analyzing the data of the test structure, it is necessary to conduct some targeted analysis in combination with the physical layout of the test structure. The test structure based on the product chip is a test structure with application advantages. However, the existing layout processing method is not perfect when it comes to the actual test application of the test structure based on the product chip. For example, the file size of the test chip based on the product is generally very large, which is not convenient to view. In addition, a more user-friendly analysis report process in actual application is expected to support the direct call and viewing of the layout structure of the corresponding test device during analysis, without the need to open the layout file of the test chip to re-search for the target structure, but the existing layout processing method does not provide a similar solution. The existing layout processing method has, to a certain extent, limited the test structure based on the product chip from fully exerting its advantages in test applications, and is not conducive to the further improvement of the test process.

[0004] It can be seen that there is an urgent need to develop a test structure layout processing method to further cooperate with the effective application of test structures based on product chips in testing work and provide practical solutions for the continuous optimization of testing processes. Summary of the Invention

[0005] The present invention is to solve all or part of the problems of the above-mentioned prior art. The present invention provides a test structure layout processing method, which processes the test structure layout to support data analysis software reading, and establishes a connection with the corresponding test structure to facilitate calling during analysis, and cooperate with the application requirements of the test structure based on the product chip in the testing work.

[0006] A test structure layout processing method of the present invention includes: reading an initial layout file and selecting a target structure; automatically taking a screenshot of the layout: defining the layers included in the screenshot; naming the screenshot image with the name of the top-level unit of the target structure, and marking the screenshot name in the screenshot image; obtaining the pin name of the target structure and marking it in the screenshot image; presetting a size threshold for evaluating the resolution of the screenshot image, and completing the screenshot based on the threshold; and automatically generating a screenshot file for data analysis.

[0007] By selecting the target structure in the layout file for automatic screenshot and marking the screenshot image, the correspondence between the screenshot image and the test structure can be established. The size threshold for evaluating the resolution of the screenshot image can be preset. The screenshot file can be automatically generated to save the layout of each test structure in the form of a clear and readable picture. It also supports data analysis software to read it and establish a connection with the corresponding test structure. It is convenient to call it during subsequent data analysis, meets the actual needs of the test work, improves the efficiency of the test work, and effectively guarantees the efficiency of using the test structure based on the product chip in the test application.

[0008] In general, selecting a target structure means selecting one or more target structures based on the type of the test structure. If multiple target structures are selected, the automatic screenshot process is performed in parallel for different target structures. Using a parallel implementation method for automatic screenshot operation is more efficient.

[0009] The method for defining the layers included in a screenshot includes: defaulting all layers included in the target structure as target layers, or defining user-defined layers as target layers; and displaying layers derived from the target layers in the generated screenshot image. In data analysis of test structures, different test structure types require different layers. Users can define or default the layers included in screenshots, making it more convenient and efficient to obtain screenshot images required for testing, more in line with the diversity of practical applications.

[0010] The method for obtaining the layer displayed in the generated screenshot image includes: defining a user-defined layer operation rule, and performing a Boolean operation on the target layer based on the layer operation rule to obtain an intermediate layer of the process node as the display layer. By performing the layer operation on the target layer, an intermediate layer of the process node that meets the user-defined process node can be automatically generated and displayed in the screenshot image, facilitating a clearer screenshot.

[0011] The method for defining the layers included in the screenshot also includes: the user adds a new layer included in the screenshot, which is defined as adding a layer.

[0012] The method for annotating a screenshot image includes: annotating the name of the top-level unit of the target structure as the screenshot name by default; obtaining the pin name and position of the target structure through a label in the layout, or identifying the pin name of the target structure through a pin definition, and annotating the pin name.

[0013] Labeling pin names refers to: obtaining the center position of each pin of the device included in the target structure; and adding labels in an image display area with the center position as the center point.

[0014] Based on the threshold, the method for completing the screenshot includes: comparing the size of the target structure with the threshold, and automatically determining whether the screenshot image is clear and readable; when the size of the target structure is greater than the threshold, generating a detailed screenshot of the target structure; wherein the method of capturing the detailed screenshot includes: based on the hierarchy of the target structure, finding the smallest repeating structure, and taking a screenshot of the smallest repeating structure; identifying the back-end layer connection, automatically identifying the connection port, and capturing the connection port.

[0015] The process of automatically taking a screenshot of the layout includes: step S1. obtaining the graphic frame where the selected target structure is located and the device inside the target structure; step S2. creating a new intermediate layout file, and setting the visible layer in the layout to the layer defined by the layer included in the screenshot; step S3. adding the target structure to the intermediate layout file; step S4. determining the positioning frame of the device, and obtaining the relevant elements in the initial layout file based on the positioning frame and adding them to the intermediate layout file; step S5. determining the image display area and size, and creating a screenshot image based on the intermediate layout file; step S6. adding a labeling layer to the screenshot image, marking the screenshot name and the pin name.

[0016] Before step S6, the display of the annotation layer is set, including setting the size and color of the annotation font.

[0017] After step S6, image rotation is further performed to adjust the viewing direction of the screenshot image.

[0018] The step S3 includes: adding the graphic frame and the device as reference structures to the intermediate layout file; and adding the winding structure and the mark layer frame generated during winding to the intermediate layout file.

[0019] The step S4 includes: step S4.1: determining the positioning point of the target structure; judging whether there is a wire winding on the pins in the device: if so, using the mark layer box generated during the wire winding as the positioning box; if not, using the minimum graphic box surrounding all pin polygons as the positioning box; step S4.2: obtaining the original layout area in the initial layout file that overlaps with the positioning box; step S4.3: creating a new layout unit structure, recorded as an intermediate layout unit structure; adding all elements in the layer contained in the screenshot in all the original layout areas obtained in step S4.2 as the related elements to the intermediate layout unit structure; step S4.4: adding the intermediate layout unit structure to the intermediate layout file.

[0020] The step S5 includes: step S5.1: obtaining all pins of the device; step S5.2: determining whether the pins are wound: if no winding exists, proceeding to step S5.3; if winding exists, obtaining the winding structure of the device, and selecting the graphic boundary box of the largest polygon in the winding structure as the image display area; step S5.3: presetting the zoom interval, denoted as ext; determining whether a detailed screenshot needs to be taken: if yes, proceeding to step S5.4; if not, proceeding to step S5.5; step S5.4: obtaining the device excluding the body potential (welltie) The smallest bounding box containing all other pins except the welltie, and the center coordinates of the bounding box; obtain all the through-hole layer polygons in the device, calculate the distance between the center of the through-hole layer polygon and the center coordinates, compare and obtain the through-hole layer polygon that is closest to the center of the bounding box, expand the graphic boundary box of the through-hole layer polygon to all sides ext, and obtain the image display area; step S5.5: obtain the smallest bounding box containing all other pins except the welltie in the device, expand the bounding box to all sides ext, and obtain the image display area.

[0021] In step S5.4 and step S5.5, the process of obtaining the image display area includes: presetting a width threshold in the horizontal direction of the image display area; obtaining the expanded graphic bounding box, and if the horizontal width of the graphic bounding box does not reach the width threshold, then continuing to expand outward from the center with a preset step size until the horizontal width of the obtained graphic bounding box is above the width threshold, and using the obtained graphic bounding box as the image display area.

[0022] Compared with the existing technology, the main benefits of the present invention are as follows: the test structure layout processing method of the present invention provides a solution for automatically capturing test structures for test chips, supports layer operations to help users obtain clearer layers required for testing, and can automatically mark test structure ports and test structure names in screenshots; supports screenshot size adjustment, which is particularly beneficial for processing large-scale test structures and obtaining detailed screenshots that meet application needs. Generating screenshot files can provide test structure layout information, which can be directly used for data analysis, significantly improving analysis speed and accuracy, avoiding the need to query actual layout files, reducing time costs, improving testing efficiency, and facilitating deeper optimization of chip testing process levels. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of a test structure layout processing method according to an embodiment of the present invention.

[0024] Figure 2 Schematic diagram of the automatic screenshot software interface according to an embodiment of the present invention.

[0025] Figure 3 A schematic diagram of a screenshot image of an embodiment of the invention.

[0026] Figure 4 Schematic diagram of the automatic screenshot process in an embodiment of the present invention.

[0027] Figure 5 Schematic diagram of a marking layer frame generated during winding in an embodiment of the present invention.

[0028] Figure 6 Schematic diagram of a graphic bounding box in an embodiment of the present invention.

[0029] Figure 7 A schematic diagram of the process of creating a screenshot according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the specific embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. In the following embodiments, the operation of the embodiments is described in a specific order. The description of this order is to better understand the details of the embodiments and to fully understand the present invention. However, the description of this order does not limit the scope of the present invention.

[0031] In an embodiment of the present invention, a test structure layout processing method is provided, including: reading an initial layout file and selecting a target structure; automatically taking a screenshot of the layout; defining the layers included in the screenshot; naming the screenshot image with the name of the top unit of the target structure and marking the screenshot name in the screenshot image; obtaining the pin name of the target structure and marking it in the screenshot image; presetting a size threshold for evaluating the resolution of the screenshot image, and completing the screenshot based on the threshold; and automatically generating a screenshot file for data analysis. Figure 1 As shown, it includes selecting test structure, defining layers, screenshot annotation, intelligent screenshot size recognition and automatic generation of screenshot images.

[0032] The example of selecting a test structure is to select a test structure as a target structure according to user needs. A single test structure can be selected as the target structure, or multiple different test structures can be selected to process multiple target structures. There is no limitation.

[0033] The definition layer of the example can be a user-defined layer, or the default layer can be all layers included in the test structure when the user does not define it, thereby completing the layer definition.

[0034] In the example, the methods for defining the layers included in the screenshot include: setting all layers included in the default target structure as target layers, or setting user-defined layers as target layers; and also including layers included in the user-added screenshot, which are defined as added layers. Figure 2 As shown, the main parameters in the automatic screenshot operation interface are Org Layers (target layer) and Add Layers (add layer).

[0035] In some better examples, layer operations are used to obtain intermediate layers and display them in the screenshot. This allows users to obtain clearer screenshots. For example, if a process has an M1 layer and an M1Cut layer, the user can define M1_cal = M1NOT M1Cut to obtain the M1 layer. Layer operations can include AND, OR, NOT, XOR, etc. The method for obtaining the layer displayed in the generated screenshot image based on the target layer includes: the user defines layer operation rules, and based on the layer operation rules, performs Boolean operations on the target layer to obtain the intermediate layer of the process node as the display layer.

[0036] The screenshot annotation method used in this example automatically uses the name of the top-level unit of the test structure as the screenshot name and annotates the name in the screenshot image. In a better example, the test structure pin names are also annotated in the screenshot image. Two specific examples include identifying the name and location through labels in the layout and identifying them through pin definitions.

[0037] An example of intelligent screenshot size recognition involves setting an upper limit for the screenshot resolution (e.g., 10μm). Based on the set threshold, the system automatically determines whether the screenshot of the test structure is clear and readable. In a more advanced example, if the test structure size exceeds the upper resolution limit, a detailed screenshot can be intelligently generated. This detailed screenshot can be captured in two ways: 1) by identifying the minimum repeating unit through the hierarchy of layout units and capturing the minimum repeating unit; 2) by identifying the backend layer connections, the connection ports can be automatically identified and captured.

[0038] In this embodiment, after the four steps above (test structure selection, layer definition, screenshot annotation, and intelligent screenshot size recognition) are completed, the information obtained from these four steps is integrated to automatically generate a screenshot file of the target test structure for subsequent data analysis. In a preferred example, parallel screenshots can be performed to more efficiently complete multiple screenshot operations.

[0039] To better understand the specific implementation of the present invention, the following example illustrates the process of automatically taking screenshots of a layout in an embodiment, but does not limit the scope of the present invention in any form. The screenshot implementation process can be completed by various computer codes and corresponding algorithms. For example, in terms of speed and efficiency, the code and algorithm can have corresponding specific designs, and the process of automatically taking screenshots of a layout can also have other specific steps, which are not limited to the specific situation here.

[0040] refer to Figure 4 As shown, the example process of automatically taking screenshots of the layout includes: step S1. obtaining the graphic frame where the selected target structure is located and the device inside the target structure; step S2. creating a new intermediate layout file and setting the visible layer in the layout to the layer defined by the layer included in the screenshot; step S3. adding the target structure to the intermediate layout file; step S4. determining the positioning frame of the device, obtaining the relevant elements in the initial layout file based on the positioning frame and adding them to the intermediate layout file; step S5. determining the image display area and size, and creating a screenshot image based on the intermediate layout file; step S6. adding a label layer to the screenshot image, labeling the screenshot name and pin name. Figure 4 In the example process, the display of the annotation layer is set before step S6, including setting the annotation font size and color. After step S6, the image is rotated to adjust the viewing direction of the screenshot image. In some embodiments, the annotation layer is not displayed, or the image is not rotated. The screenshot image is directly displayed as the screenshot image, which is not specified here.

[0041] In the example, the automatic screenshot process is realized by running the software. The example interface of the screenshot software is as follows: Figure 2 , combined with reference Figure 3The main parameters of the window are Org Layers, which represents the setting of the target layer; Add Layers, which represents the setting of adding layers; Size, which represents the option of determining the image display area. The example provides two options: by pins and by mark; Pin Ext, which represents the setting of the distance that the pin expands outward to form the graphic boundary box. This distance can be recorded as ext. Label represents the setting of the label font size. The example provides two options: default and large. Color represents the setting of the label color. Rotate represents the setting of the rotation angle. Four rotation angles of 0°, 90°, 180°, and 270° are provided for user definition. Zoom In represents whether to zoom in, that is, whether to take a detailed screenshot. Zoom Ext is zoom extents, which represents the setting of the zoom range when taking a detailed screenshot.

[0042] The layer definition option loads the default settings (all basic layers) from the extraction settings, allowing users to edit them based on the target structure type. Target layers include those defined in the extraction settings, and also support user-added layers.

[0043] Combined with reference Figure 5 and Figure 6 , in the options for determining the image display area and size, by pins is to set the image display area by pins, and the size of the area is determined by the smallest bounding box of all pins (i.e. Figure 5 The Bbox1 in the definition can define the distance of the surrounding extensions (i.e. the pin extension) of the left, right, top, and bottom (L, R, T, B). Figure 5 Bbox2 in the winding); by mark is the marker box of the marker layer generated by winding (defined in the winding settings, refer to Figure 6 Bbox3 in ). Figure 5 The figure below illustrates Bbox1, Bbox2, and Bbox3. Bbox1 is the smallest bounding box encompassing all pin polygons; Bbox2 is the bounding box generated by extending Bbox1 outward. The mark layer box generated during routing is generally larger, and is represented in this example by the outermost Bbox3. The "by pins" box, Bbox1, can be used as the positioning box, as can the "by mark" box, Bbox3. If the pins in the device do not have routing, Bbox3 generated by routing does not exist. The specific circumstances can vary and are not limited here.

[0044] The provided pin label option supports user-defined label color and size. In the case of the example, the screenshot image is named after the test structure. For some large test structures, the overall screenshot cannot show the details. In better examples, detailed screenshots (Zoom In snapshot) are also supported, and users can customize the Zoom In Window size (by setting Zoom Ext). The generated screenshot file supports the user to set the storage folder path. In better examples, separate subfolders can be set for each different target structure type (refer to Figure 2 , defined as yes through the window parameter Sub Dir). The screenshot image obtained by the example is as follows Figure 3 As shown, it should be noted that the screenshot image can be in color. Figure 3 This is for illustration only. The screenshots in this example are saved in Portable Network Graphics (PNG), a commonly used image file format. PNG provides lossless compression that's 30% smaller than GIF, supports 24-bit and 48-bit true color images, and offers numerous other technical advantages. Each screenshot can be as small as tens of kilobytes, making it easy to read.

[0045] Combined with reference Figure 4 The following is an example of the process of software implementing automatic screenshots, but does not limit the specific implementation process.

[0046] Step 1: Get the frame and device where the selected cell (target structure) is located; the test structure is the target of this snapshot, and it has only one device inside.

[0047] Step 2: Create a new gdsii (named newgdsii) layout file (i.e., the intermediate layout file).

[0048] Step 3: Add the relevant cellRef (i.e. the entire target structure mentioned above) to newgdsii: Step 3.1 Add the frame and all the devices in it as cellRef to newgdsii; in the case of pin routing, proceed as follows: Step 3.2 Add routingcell (winding structure, i.e. Figure 5 The polygons (rectangles) shown in the figure are used for wiring connections) and marklayer (see Figure 6 The outer contour box Bbox3) in is added to newgdsii as cellRef.

[0049] Step 4: merge Original gdsii (merge original layout area): Step 4.1 obtains all original gdsii (referring to the layout area in the original layout file) that overlap with Bbox3; Step 4.2 creates a new structure (named newcell), and adds all elements (elements, that is, polygons in each layer (rectangles for example)) in the target layer of all original gdsii in step 4.1 to newcell; Step 4.3 adds newcell to newgdsii (intermediate layout file).

[0050] Step 5: Create a snap shot image. Combined with reference Figure 5 and Figure 7 The process of creating a screenshot is illustrated. Step 5.1 Get all pins of the selected device; Step 5.2 Get the routing mark cell of the selected device; The software makes a judgment and executes accordingly: (1) If the routing mark cell exists, and the Size parameter value is set to: by mark. Then select the graphic bounding box of the largest polygon in the routing mark cell as the image display area, that is, use the Bbox3 as the image display area. (2) If the condition (1) is not met, and the parameter Zoom In is true, the Zoom Ext value is ext (a preset zoom range that can be customized). Get the smallest bounding box containing all other pins in the device except welltie, refer to Figure 6The smallest rectangular box Bbox1 in the device and the center coordinates of Bbox1; obtain all V0 polygons in the device (i.e., polygons in the V0 layer, V0 is the through-hole layer, used to connect M1 and AA), obtain the one with the smallest distance from the center of Bbηx1 in the V0 polygon; expand the selected polygon (polygon, the V0 polygon with the smallest distance from the center of Bbox1) to ext in all directions as the image display area. Some better examples also have a supplementary setting for when the expansion distance ext is too small to ensure that the image display area can be clear. If the horizontal width after expansion is not greater than 24, then take the center of the expanded graphic boundary box and expand it 12 outwards in all directions as the image display area. The specific width threshold and expansion step can be customized and are not limited. (3) If the conditions of (1) and (2) are not met, and the Size parameter value is: by pins, and the Pin Ext value is ext. Then obtain the smallest bounding box that includes all other pins except welltie (body potential), and expand Bbox1 to ext in all directions as the image display area. In some better examples, if the horizontal width after expansion is not greater than 24, then the center of the graphic boundary box after expansion ext is taken and expanded outward by 12 in all directions as the image display area.

[0051] In this embodiment, step 6 is performed after step 5: image annotation display: (1) if the value of the parameter Label is: default, no processing is performed; (2) if the value of the parameter Label is: large and the value of the parameter Color is value, the center position of each pin is obtained, and the pin annotation is added to the image display area with the point as the center point; step 7: image rotation; step 8: adding image annotation.

[0052] In order to facilitate the description of the present invention, some common English nouns or letters are used for illustrative reference only and are not intended to be restrictive or specific. The scope of protection of the present invention should not be limited by their possible Chinese translations or specific letters.

[0053] It is apparent to those skilled in the art that several improvements and modifications may be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A test structure layout processing method, characterized by: include: Read the initial layout file, select the target structure, and automatically take a screenshot of the layout: Define the layers included in the screenshot; Naming the screenshot image with the name of the top-level unit of the target structure, and marking the screenshot name in the screenshot image; Get the pin names of the target structure and mark them in the screenshot image; Preset a size threshold for evaluating the resolution of the screenshot image, and complete the screenshot based on the threshold; Automatically generate screenshot files for data analysis; The method for completing the screenshot based on the threshold includes: Comparing the size of the target structure with the threshold value, and automatically determining whether the screenshot image is clear and readable; When the size of the target structure is greater than the threshold, generating a detailed screenshot of the target structure; The methods for capturing detailed screenshots include:

1. Based on the hierarchy of the target structure, find the smallest repetitive structure and take a screenshot of the smallest repetitive structure; 2. Identify the backend layer connection, automatically identify the connection port, and intercept the connection port.

2. The test structure layout processing method according to claim 1, wherein: The method for defining the layers included in the screenshot includes: By default, all layers contained in the target structure are set as target layers, or user-defined layers are set as target layers; The generated screenshot image displays a layer obtained based on the target layer.

3. The test structure layout processing method according to claim 2, wherein: The method for obtaining the layer displayed in the generated screenshot image includes: The user defines a layer operation rule, and performs a Boolean operation on the target layer based on the layer operation rule to obtain an intermediate layer of the process node as the display layer.

4. The test structure layout processing method according to claim 2, wherein: The method for defining the layers included in the screenshot also includes: the user adds a new layer included in the screenshot, which is defined as adding a layer.

5. The test structure layout processing method according to claim 1, wherein: The method for annotating the screenshot image includes: By default, the name of the top-level unit of the target structure is marked as the screenshot name; The pin names and positions of the target structure are obtained through labels in the layout, or the pin names of the target structure are identified through pin definitions, and the pin names are marked.

6. The test structure layout processing method according to claim 5, characterized in that: Labeling pin names refers to: obtaining the center position of each pin of the device included in the target structure; and adding labels in an image display area with the center position as the center point.

7. The test structure layout processing method according to any one of claims 1 to 6, characterized in that: The process of automatically taking screenshots of the layout includes: Step S1. Obtain the graphic frame where the selected target structure is located and the devices inside the target structure; Step S2. Create a new intermediate layout file and set the visible layer in the layout to the layer defined by the layer included in the screenshot; Step S3. adding the target structure to the intermediate layout file; Step S4. Determine the positioning frame of the device, obtain relevant elements in the initial layout file based on the positioning frame, and add them to the intermediate layout file; Step S5. Determine the image display area and size, and create a screenshot image based on the intermediate layout file; Step S6: Add a labeling layer on the screenshot image, and label the screenshot name and the pin name.

8. The test structure layout processing method according to claim 7, characterized in that: Before step S6, the display of the annotation layer is set, including setting the size and color of the annotation font.

9. The test structure layout processing method according to claim 7, wherein: After step S6, image rotation is further performed to adjust the viewing direction of the screenshot image.

10. The test structure layout processing method according to claim 7, wherein: The step S3 includes: adding the graphic frame and the device as reference structures to the intermediate layout file; and adding the winding structure and the marker layer frame generated during winding to the intermediate layout file.

11. The test structure layout processing method according to claim 7, wherein: The step S4 comprises: Step S4.1: Determine the positioning point of the target structure; determine whether there is a wire routing for the pins in the device; if so, use the marking layer frame generated during the wire routing as the positioning frame; if not, use the minimum graphic frame surrounding all pin polygons as the positioning frame; Step S4.2: obtaining an original layout area in the initial layout file that overlaps with the positioning frame; Step S4.3: creating a new layout unit structure, recorded as an intermediate layout unit structure; adding all elements in the layers contained in the screenshot in all the original layout areas obtained in step S4.2 as the relevant elements to the intermediate layout unit structure; Step S4.4: Add the intermediate layout unit structure to the intermediate layout file.

12. The test structure layout processing method according to claim 7, wherein: The step S5 comprises: Step S5.1: Obtain all pins of the device; Step S5.2: Determine whether the pin has a winding: If no winding exists, proceed to step S5.3; if winding exists, obtain the winding structure of the device, and select the graphic bounding box of the largest polygon in the winding structure as the image display area; Step S5.3: Preset the zoom range, record it as ext; determine whether to capture the detailed screenshot: if yes, proceed to step S5.4; if not, proceed to step S5.5; Step S5.4: Obtain the smallest bounding box that includes all other pins in the device excluding the body potential, and the center coordinates of the bounding box; obtain all through-hole layer polygons in the device, calculate the distance between the center of the through-hole layer polygon and the center coordinates, compare and obtain the through-hole layer polygon that is closest to the center of the bounding box, and expand the graphic bounding box of the through-hole layer polygon to all sides ext to obtain the image display area; Step S5.5: Obtain the smallest bounding box of the device that excludes the body potential and includes all other pins, and expand the bounding box to all sides by ext to obtain the image display area.

13. The test structure layout processing method according to claim 12, wherein: In step S5.4 and step S5.5, the process of obtaining the image display area includes: Preset the width threshold of the image display area in the horizontal direction; Obtain the expanded graphic bounding box. If the horizontal width of the graphic bounding box does not reach the width threshold, continue to expand it outward from the center at a preset step size until the horizontal width of the obtained graphic bounding box exceeds the width threshold. Use the obtained graphic bounding box as the image display area.

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