Pixel circuit, driving method thereof, and display panel

Abstract

The present application discloses a pixel circuit and its driving method, and a display panel, wherein the pixel circuit at least includes: a driving module having a gate node and a source node; a first storage module coupled between the gate node and the source node; a data writing module coupled between a data line and the source node, and configured to, during a data writing phase, couple the data voltage on the data line to the gate node via the source node, and through the parasitic capacitance between the gate node and the source node in the driving module and the voltage division of the first storage module, so that during a light-emitting phase, the potential of the gate node is related to the data voltage, and the potential of the source node is the data voltage. In this way, the lighting current provided to the light-emitting module by the pixel circuit of the present application effectively avoids being controlled by the power supply of the pixel circuit, thereby avoiding the unstable state such as the voltage drop of the power supply from affecting the brightness uniformity and display effect of the display panel.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a pixel circuit and a driving method thereof, and a display panel. Background Art

[0002] Nowadays, in the pixel circuit of a display panel, the lighting current provided to the light-emitting module is usually controlled by the power supply of the pixel circuit. Therefore, when the power supply is unstable, such as in a voltage drop, it will inevitably cause problems such as brightness uniformity, ghosting, smearing, and poor display effect of the display panel. Summary of the Invention

[0003] In order to solve the above-mentioned technical problems and other problems, a technical solution adopted in the present application is: to provide a pixel circuit, wherein the pixel circuit at least includes: a driving module having a gate node and a source node; a first storage module coupled between the gate node and the source node; a data writing module coupled between the data line and the source node, and configured to, in the data writing stage, allow the data voltage on the data line to be coupled to the gate node via the source node, and through the parasitic capacitance between the gate node and the source node in the driving module and the voltage division of the first storage module, so that in the light-emitting stage, the potential of the gate node is related to the data voltage, and the potential of the source node is the data voltage.

[0004] The driving module further has a drain node, which is coupled to a first voltage source. The pixel circuit further includes a compensation module, wherein: the compensation module is coupled between the gate node and the drain node, and is configured to conduct the gate node and the drain node during the compensation phase so that the threshold voltage of the driving module is written into the first storage module; preferably, during the light-emitting phase, the potential of the gate node is related to the data voltage and the threshold voltage, and the potential of the source node is the data voltage.

[0005] The compensation phase does not overlap with the data writing phase; preferably, the compensation phase is executed before the data writing phase.

[0006] In which, the pixel circuit also includes a first initialization module, the first initialization module is coupled between the first reference voltage line and the source node, and the source node is coupled to the anode of the light-emitting module, wherein: the compensation stage is reused as the initialization stage, and the first initialization module is configured to write the first reference voltage on the first reference voltage line into the source node and the anode during the initialization stage.

[0007] In the data writing phase, the parasitic capacitor and the first storage module perform voltage division based on the voltage difference between the data voltage and the first reference voltage.

[0008] In which, the pixel circuit also includes a second storage module, which is coupled between the first voltage source and the drain node, wherein: the data writing module is further configured to couple the data voltage to the gate node via the source node and through the parasitic capacitance, the first storage module and the second storage module during the data writing stage.

[0009] wherein the source node is coupled to the anode of the light emitting module, wherein: in a light emitting phase, a potential difference between the gate node and the source node satisfies equation 1, and a current value of a driving current in the light emitting module is a function of a difference between equation 1 and a threshold voltage;

[0010] Formula 1: (Vref1-Vdata)(Cst2+Cgs) / (Cst1+Cst2+Cgs)+Vth; wherein Vref1 represents the first reference voltage, Vdata represents the data voltage, Cst1 represents the capacitance value of the first storage module, Cst2 represents the capacitance value of the second storage module, Cgs represents the parasitic capacitance, and Vth represents the threshold voltage.

[0011] The driving module further has a drain node, and the pixel circuit further includes a first light-emitting control module, the first light-emitting control module is coupled between the first voltage source and the drain node, and the source node is coupled to the anode of the light-emitting module, wherein: the first light-emitting control module is configured to, during the light-emitting phase, enable the first voltage source to drive the driving module via the drain node, so that the driving module is controlled by the potential of the gate node to generate a corresponding driving current, and the driving current is transmitted to the light-emitting module via the anode; preferably, the pixel circuit further includes an isolation module, the isolation module is coupled between the source node and the anode; wherein the isolation module is configured to avoid, during the data writing phase, The written data voltage affects the driving module; preferably, the pixel circuit also includes a second light-emitting control module, which is coupled between the source node and the anode, or the second light-emitting control module is coupled between the isolation module and the anode; wherein the second light-emitting control module is configured to avoid the written data voltage from affecting the light-emitting module during the data writing phase; preferably, the pixel circuit also includes a second initialization module, which is coupled between the second reference voltage line and the anode; the compensation phase is multiplexed as the initialization phase, and the second initialization module is configured to write the second reference voltage on the second reference voltage line to the anode during the initialization phase.

[0012] In order to solve the above-mentioned technical problems and other problems, another technical solution adopted in the present application is: to provide a driving method for a pixel circuit, which is applied to the pixel circuit as described above, wherein the driving method includes: in the data writing stage, the data writing module causes the data voltage on the data line to be coupled to the gate node via the source node and through the parasitic capacitance of the driving module and the voltage division of the first storage module; in the light-emitting stage, the driving module causes the potential of the gate node to be related to the data voltage, and the potential of the source node to be the data voltage.

[0013] The driving module further comprises a drain node coupled to a first voltage source, the pixel circuit further comprises a compensation module as claimed in claim 2, and the driving method further comprises: in a compensation phase, the gate node and the drain node are turned on so that the threshold voltage of the driving module is written into the first storage module; preferably, the compensation phase does not overlap with the data writing phase; preferably, the compensation phase is performed before the data writing phase.

[0014] The beneficial effect of the present application is as follows: different from the prior art, the driving module in the pixel circuit provided by the present application has a gate node and a source node, the first storage module is coupled between the gate node and the source node, the data writing module is coupled between the data line and the source node, and is configured to, in the data writing stage, allow the data voltage on the data line to be coupled to the gate node via the source node, and through the parasitic capacitance between the gate node and the source node in the driving module and the voltage division of the first storage module, so that in the light-emitting stage, the potential of the gate node is related to the data voltage, and the potential of the source node is the data voltage, and is not related to the power supply of the pixel circuit, thereby effectively avoiding the unstable state such as the voltage drop of the power supply affecting the brightness uniformity and display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0016] Figure 1 This is a schematic structural diagram of a first embodiment of a pixel circuit of the present application;

[0017] Figure 2 is a structural diagram of a second embodiment of a pixel circuit of the present application;

[0018] Figure 3 yes Figure 2 A structural diagram of a specific embodiment of a pixel circuit;

[0019] Figure 4 yes Figure 3 A timing diagram of the control signal corresponding to the driving method of the pixel circuit in FIG.

[0020] Figure 5 yes Figure 2 A schematic structural diagram of another specific embodiment of the pixel circuit;

[0021] Figure 6 yes Figure 5 A timing diagram of the control signal corresponding to the driving method of the pixel circuit in FIG.

[0022] Figure 7 It is a flowchart of an embodiment of a driving method of a pixel circuit of the present application. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0025] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0027] See also Figure 1 , Figure 1 FIG. 1 is a schematic structural diagram of a first embodiment of a pixel circuit of the present application. In this embodiment, the pixel circuit 10 at least includes: a driving module 11 , a first storage module 12 , and a data writing module 13 .

[0028] It should be noted that in the field of display technology, display panels typically utilize a system power supply to continuously supply current to a light-emitting module via a constant current source corresponding to the output of the pixel circuit 10. The magnitude of this current is specifically regulated by the voltage at the control terminal of the driver module 11 within the pixel circuit 10. This voltage at the control terminal of the driver module 11 is in turn written by a data signal provided by the display panel's driver circuit to the pixel circuit 10. This ensures that the light-emitting module can continuously emit light during a scan cycle of the driver circuit, thereby achieving corresponding image display.

[0029] Specifically, the driving module 11 may include a transistor, a thin film transistor, a field effect transistor or any other reasonable device with the same characteristics, and has a gate node and a source node, and the first storage module 12 is correspondingly coupled between the gate node and the source node.

[0030] The data writing module 13 is further coupled between the data line 101 and the source node of the driving module 11, and is configured to receive the data voltage on the data line 101 during the data writing phase of a display cycle of the pixel circuit 10, and write the data voltage on the data line 101 into the source node of the driving module 11, and then be coupled to the gate node of the driving module 11 through the parasitic capacitance between the gate node and the source node in the driving module 11 and the voltage division of the first storage module 12.

[0031] Furthermore, when the pixel circuit 10 is in the light-emitting stage, that is, the stage of lighting the light-emitting module in a display cycle, the data voltage coupled to the gate node of the driving module 11 through voltage division will make the potential of the gate node of the driving module 11 correspond to the data voltage, and the potential of the source node of the driving module 11 will be the data voltage, rather than being related to the power supply of the pixel circuit 10, so as to avoid being controlled by the power supply.

[0032] It is worth noting that the term "coupled" as used herein encompasses both direct and indirect connection methods. Therefore, if a first element is described as being coupled to a second element, this means that the first element may be directly connected to the second element via an electrical connection, a communication connection, wireless transmission, optical transmission, or other signal connection method, or may be indirectly connected to the second element electrically or by signal connection via other elements or connection methods.

[0033] Parasitic capacitance is the unavoidable and usually unwanted capacitance that exists between parts of an electronic component or circuit simply because they are in close proximity. When two electrical conductors with different voltages are brought together, the electric field between them causes charge to be stored on them; this effect is capacitance.

[0034] In the above scheme, during the data writing stage, the data voltage is coupled to the gate node of the driving module 11 via the source node of the driving module 11 and by utilizing the parasitic capacitance and the voltage division of the first storage module 12, so that the potential of the gate node is independent of the power supply of the pixel circuit 10, and the driving current of the light-emitting module is also independent of the power supply, thereby effectively avoiding the adverse effects of unstable conditions such as the voltage drop of the power supply on the brightness uniformity and display effect of the display panel.

[0035] See also Figure 2 , Figure 2 This is a schematic structural diagram of a second embodiment of a pixel circuit according to the present application. This embodiment is based on the first embodiment of a pixel circuit according to the present application, and the pixel circuit 20 further includes a compensation module 24 .

[0036] Specifically, the driving module 21 also has a drain node, which is coupled to the first voltage source 301 provided by the display panel system power supply, and the compensation module 24 is specifically coupled between the gate node and the drain node of the driving module 21, and is configured to turn on the gate node and the drain node of the driving module 21 during the compensation stage of a display cycle of the pixel circuit 20, so that the threshold voltage of the driving module 21 is written into the first storage module 22, and is used to compensate the threshold voltage of the driving module 21 during the light-emitting stage to offset the influence of the threshold voltage on the driving current in the light-emitting module 601.

[0037] Preferably, when the pixel circuit 20 includes the compensation module 24 , in the light emitting stage, the potential of the gate node of the driving module 21 is related to the data voltage and the threshold voltage, and the potential of the source node of the driving module 21 is the data voltage.

[0038] In one display cycle of the pixel circuit 20 , the compensation phase and the data writing phase do not overlap, thereby ensuring consistency in the grayscale compensation levels of the pixel circuit 20 and ensuring uniform brightness of the display panel and good display effects.

[0039] Preferably, the compensation phase is performed before the data writing phase.

[0040] In one embodiment, the pixel circuit 20 further includes a first initialization module 25 . The first initialization module 25 is specifically coupled between the first reference voltage line 501 and a source node, and the source node is coupled to the anode of the light emitting module 601 .

[0041] In which, in a display cycle of the pixel circuit 20, the compensation stage is reused as the initialization stage, and the first initialization module 25 is specifically configured to write the first reference voltage on the first reference voltage line 501 into the source node of the driving module 21, that is, one end of the first storage module 22, in the initialization stage to initialize the first storage module 22, and write the first reference voltage into the anode of the light-emitting module 601 to clear the signal residue that may exist in the first storage module 22 and the light-emitting module 601 in the previous display cycle.

[0042] In the data writing phase, the parasitic capacitance of the driving module 21 and the first storage module 22 are specifically divided based on the voltage difference between the data voltage and the first reference voltage.

[0043] In one embodiment, the driving module 21 further has a drain node. The pixel circuit 20 further includes a second storage module 26 . The second storage module 26 is coupled between the first voltage source 301 provided by the display panel system power supply and the drain node of the driving module 21 .

[0044] Among them, the data writing module 23 is further configured to write the data voltage on the data line 101 into the source node of the driving module 21 during the data writing phase, and be coupled to the gate node through the parasitic capacitance, the first storage module 22 and the voltage division of the second storage module 26, so as to effectively shorten the time consumption of the data writing phase and is suitable for high refresh and high resolution application scenarios.

[0045] In one embodiment, the pixel circuit 20 further includes a compensation module 24, which is coupled between the gate node and the drain node of the driving module 21 and is configured to turn on the gate node and the drain node of the driving module 21 during the compensation phase, so that the threshold voltage of the driving module 21 is written into the first storage module 22, and the source node is coupled to the anode of the light-emitting module 601.

[0046] In the light-emitting stage, the potential difference between the gate node and the source node of the driving module 21 satisfies equation 1, and the current value of the driving current in the light-emitting module 601 is a function of the difference between equation 1 and the threshold voltage;

[0047] Formula 1: (Vref1-Vdata)(Cst2+Cgs) / (Cst1+Cst2+Cgs)+Vth;

[0048] Wherein, Vref1 represents a first reference voltage, Vdata represents a data voltage, Cst1 represents a capacitance value of the first storage module 22, Cst2 represents a capacitance value of the second storage module 26, Cgs represents a parasitic capacitance, and Vth represents a threshold voltage.

[0049] In one embodiment, the driving module 21 also has a drain node, and the pixel circuit 20 specifically also includes a first light-emitting control module 27, the first light-emitting control module 27 is coupled between the first voltage source 301 provided by the display panel system power supply and the drain node of the driving module 21, and the source node of the driving module 21 is coupled to the anode of the light-emitting module 601.

[0050] Among them, the first light-emitting control module 27 is configured to enable the first voltage source 301 to drive the driving module 21 via the drain node of the driving module 21 during the light-emitting stage, so that the driving module 21 is controlled by the potential of its gate node to generate a corresponding driving current, and the driving current is transmitted to the light-emitting module 601 via the anode of the light-emitting module 601 to light up the light-emitting module 601 and display the corresponding picture.

[0051] In one embodiment, the pixel circuit 20 further includes an isolation module 28 , and the isolation module 28 is coupled between the source node of the driving module 21 and the anode of the light-emitting module 601 to separate the driving module 21 from the light-emitting module 601 .

[0052] The isolation module 28 is configured to be triggered to be cut off during the data writing phase to prevent the data voltage written by the data writing module 23 from affecting the driving module 21 .

[0053] In one embodiment, the pixel circuit 20 specifically also includes a second light-emitting control module 29, and the second light-emitting control module 29 is coupled between the source node of the driving module 21 and the anode of the light-emitting module 601; or, the second light-emitting control module 29 is correspondingly coupled between the isolation module 28 and the anode of the light-emitting module 601, and the second light-emitting control module 29 is specifically configured to trigger cutoff during the data writing stage to avoid the data voltage written by the data writing module 23 from affecting the anode of the light-emitting module 601.

[0054] In one embodiment, the pixel circuit 20 further includes a second initialization module 210 . The second initialization module 210 is coupled between the second reference voltage line 502 and the anode of the light emitting module 601 .

[0055] In which, in a display cycle of the pixel circuit 20, the compensation stage is reused as the initialization stage, and the second initialization module is configured to write the second reference voltage on the second reference voltage line 502 to the anode of the light-emitting module 601 during this initialization stage to initialize the light-emitting module 601 and clear the signal residue that may exist in the previous display cycle of the light-emitting module 601.

[0056] Optionally, the first reference voltage provided by the first reference voltage line 501 can be the same as or different from the second reference voltage provided by the second reference voltage line 502, and the second reference voltage is preferably smaller than the first reference voltage to optimize the required value of the data voltage provided by the data line 101. This application does not limit this.

[0057] In a specific embodiment, the first end of the data writing module 23 is coupled to the data line 101, the second end of the data writing module 23 is coupled to the second end of the first storage module 22, and the third end of the data writing module 23 is coupled to the second scan line 202; the first end of the compensation module 24 is coupled to the drain node of the driving module 21, the second end of the compensation module 24 is coupled to the gate node of the driving module 21, and the third end of the compensation module 24 is coupled to the first scan line 201; the first end of the first light-emitting control module 27 is coupled to the first voltage source 301, the second end of the first light-emitting control module 27 is coupled to the drain node of the driving module 21, and the third end of the first light-emitting control module 27 is coupled to the emission signal line 401; the first end of the isolation module 28 is coupled to the source node of the driving module 21, the second end of the second light-emitting control module 29 is coupled to the anode of the light-emitting module 601, and the second light-emitting control module 29 is coupled to the gate node of the driving module 21. The third end of the light control module 29 is coupled to the third scan line 203; the first end of the second light control module 29 is coupled to the second end of the second light control module 29, the second end of the second light control module 29 is coupled to the anode of the light emitting module 601, and the third end of the second light control module 29 is coupled to the third scan line 203; the first end of the first initialization module 25 is coupled to the first reference voltage line 501, the second end of the first initialization module 25 is coupled to the second end of the second storage module 26, and the third end of the first initialization module 25 is coupled to the fourth scan line 204; the first end of the second initialization module 210 is coupled to the second reference voltage line 502, the second end of the second initialization module 210 is coupled to the anode of the light emitting module 601, the third end of the second initialization module 210 is coupled to the second scan line 202, and the cathode of the light emitting module 601 is coupled to the second voltage source 302.

[0058] Optionally, the driving module 21, the data writing module 23, the compensation module 24, the first initialization module 25, the first light-emitting control module 27, the isolation module 28, the second light-emitting control module 29 and the second initialization module 210 can specifically be a transistor, a thin-film transistor or a field-effect transistor or any other reasonable device with the same characteristics, and this application does not limit this.

[0059] It is worth noting that, to distinguish the two ends of the driver module 21 other than the control end, one end is referred to as the first end and the other end is referred to as the second end. When the driver module 21 is a transistor, the control end can be specifically the base, the first end is the collector, and the second end is the emitter; alternatively, the control end can be specifically the base, the first end is the emitter, and the second end is the collector.

[0060] When the driving module 21 is a thin film transistor or a field effect transistor, the control end can be a gate, the first end can be a drain, and the second end can be a source; or, the control end can be a gate, the first end can be a source, and the second end can be a drain.

[0061] The first end, the second end, and the third end of each module except the driving module 21 correspond to the first end, the second end, and the control end of the driving module 21 respectively.

[0062] When each module is a thin film transistor or a field effect transistor, it may also be a composite transistor or a single transistor, which is not limited in this application.

[0063] For ease of understanding, taking the above modules as thin film transistors as an example, it can be seen that please refer to Figure 3 and Figure 4 , among which, the Figure 3 yes Figure 2 A schematic structural diagram of a specific embodiment of a pixel circuit is shown in FIG. Figure 4 yes Figure 3 A timing diagram of the control signals corresponding to the driving method of the pixel circuit in FIG.

[0064] It is understandable that, in this embodiment, Figure 3As shown, the driving module 21, the data writing module 23, the compensation module 24, the first initialization module 25, the first light-emitting control module 27, the isolation module 28, the second light-emitting control module 29 and the second initialization module 210 can specifically correspond to the first transistor T1, the third transistor T2, the fourth transistor T4, the second transistor T3, the fifth transistor T5, the seventh transistor T7, the sixth transistor T6 and the eighth transistor T8 respectively; and the first storage module 22 corresponds to the first capacitor Cst1, the second storage module 26 corresponds to the second capacitor Cst2, the light-emitting module 601 corresponds to the light-emitting device D1; and the data line 1 01, the first scan line 201, the second scan line 202, the third scan line 203, the fourth scan line 204, the emission signal line 401, the first reference voltage line 501 and the second reference voltage line 502 respectively correspond to the data line VDATA, the first scan line EMB, the second scan line Sn, the third scan line SnB, the fourth scan line RE, the emission signal line EM, the first reference voltage line VREF1 and the second reference voltage line VREF2; the first voltage source 301 and the second voltage source 302 respectively correspond to the first voltage source ELVDD and the second voltage source ELVSS; wherein the connection method of each of the above components is as follows: Figure 3 As shown, I will not go into details here.

[0065] From this we can see that if Figure 4 As shown, in the lighting stage, that is, in the t0 stage, the emission signal provided by the emission signal line EM and the third scanning signal provided by the third scanning line SnB are both in a high level state to control the first transistor T1, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 to be triggered and turned on to light up the light-emitting device D1.

[0066] It is worth noting that the t0 stage may specifically correspond to a light-emitting stage in a display cycle of the light-emitting device D1 ; and the emission signal line EM may specifically correspond to a scan line.

[0067] In the compensation stage, that is, the t1 stage, the compensation stage is multiplexed as the initialization stage. The fourth scan signal provided by the fourth scan line RE, the first scan signal provided by the first scan line EMB, and the third scan signal provided by the third scan line SnB are all in a high-level state to control the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 to be triggered and turned on, and the G point and the S point are reset, and the first capacitor Cst1 and the second capacitor Cst2 are also reset to clear the signal residue that may exist in the previous display cycle.

[0068] At this time, the current at point D will be coupled to the first reference voltage line VREF1 via the first transistor T1, the seventh transistor T7, and the third transistor T3, so that the voltage at point G gradually drops to Vref1+Vth, and the anode potential of the light-emitting device D1 corresponds to Vref1, so that the threshold voltage of the driving module is written into the first capacitor Cst1, and the potential difference on the second capacitor Cst2 is (Vref1+Vth)-VDD; wherein Vref1 is the first reference voltage provided by the first reference voltage line VREF1, Vth is the threshold voltage of the first transistor T1, and VDD is the output voltage of the first voltage source ELVDD.

[0069] In the data writing stage, that is, in the t2 stage, the second scanning signal provided by the second scanning line Sn and the first scanning signal provided by the first scanning line EMB are both in a high level state to control the second transistor T2, the fourth transistor T4 and the eighth transistor T8 to trigger conduction, and at this time the voltage at point S will jump from Vref1 to Vdata.

[0070] It can be understood that at stage t1, the charge on the first capacitor Cst1 is specifically Q1=C1*Vth, the charge on the second capacitor Cst2 is Q2=C2[(Vref1+Vth)-VDD], and the charge on the parasitic capacitor Cgs is Q3=Cgs*Vth;

[0071] In the t2 phase, the charge on the first capacitor Cst1 is Q11=C1(V G -Vdata), the charge on the second capacitor Cst2 is Q21=C2(V G -VDD), the charge on the parasitic capacitor Cgs is Q31=Cgs*(V G -Vref1);

[0072] According to the law of conservation of charge, we know that: Q = Q1 + Q2 + Q3 = Q11 + Q21 + Q31; that is,

[0073] C1*Vth+C2[(Vref1+Vth)-VDD]+Cgs*Vth=C1(V G -Vdata)+C2(V G -VD

[0074] D)+Cgs*(V G -Vref1);

[0075] Among them, the V G Specifically, Vdata is the potential of the point G at the end of the t2 phase, and Vdata is the voltage of the data signal provided by the data line VDATA.

[0076] Through the above calculation, we can get that in the t2 stage, VG =(C2*Vref1+C1*Vdata+Cgs*Vref1) / (C1+C2+Cgs)+Vth; accordingly, the voltage on the first capacitor Cst1 corresponds to V G -Vdata=(Cst2+Cgs)*(Vref1-Vdata) / (Cst1+Cst2+Cgs)+Vth; and the second reference voltage line VREF2 will reset the anode of the light-emitting device D1 through the eighth transistor T8 so that it corresponds to Vr2; wherein Cgs is the gate-source coupling capacitance of the first transistor T1, and Vr2 is the second reference voltage provided by the second reference voltage line VREF2.

[0077] During the light-emitting phase of the display cycle, i.e., phase t3, the emission signal provided by the emission signal line EM and the third scan signal provided by the third scan line SnB are both in a high-level state, thereby controlling the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 to be triggered and turned on, thereby lighting the light-emitting device D1. Furthermore, the lighting current of the light-emitting device D1 is controlled by the Vgs-Vth corresponding to the first transistor T1, and the Vgs-Vth corresponds to a function of (Cst2+Cgs)*(Vref1-Vdata) / (Cst1+Cst2+Cgs). This function does not include VDD, VSS, or Vth. Therefore, the pixel circuit effectively compensates for the IR drop (voltage drop) of VDD and VSS, as well as the Vth. Vgs is the voltage between the control terminal and the second terminal of the first transistor T1, i.e., the gate and source of the first transistor T1. VSS is the output voltage of the second voltage source ELVSS.

[0078] It can be understood that in this embodiment, Vref1 resets the first capacitor Cst1 while Vr2 resets the anode of the light-emitting device D1. Therefore, the voltage of Vr2 needs to be less than VSS+Voled, and Vdata is a negative voltage. In order to adapt to the driving control capability of the current driver chip, the potential of Vr2 can be made lower than the potential of Vref1; wherein Voled is the lighting voltage of the light-emitting device D1.

[0079] Through the above solution, the lighting current of the light-emitting device D1 will be controlled by Cst2*(Vref1-Vdata) / (Cst1+Cst2+Cgs). In this function, there is no VDD, VSS, or Vth, thereby effectively avoiding the influence of the IR drop of VDD and VSS on Vgs. The compensation degree is high, the ghosting problem can be significantly improved, and the IR drop of VDD and VSS is also compensated, so that the brightness uniformity of the display panel is better and the applicable refresh frequency range is also larger.

[0080] Please continue to refer to Figure 5 and Figure 6 , among which, the Figure 5 yes Figure 2 A schematic structural diagram of another specific embodiment of the pixel circuit is shown in FIG. Figure 6 yes Figure 5 A timing diagram of the control signals corresponding to the driving method of the pixel circuit in FIG.

[0081] It is understandable that, in another specific embodiment, the pixel circuit may further remove the eighth transistor T8 and the second reference voltage line VREF2.

[0082] Among them, such as Figure 6 As shown, in the lighting stage, that is, in the t0 stage, the emission signal provided by the emission signal line EM and the third scanning signal provided by the third scanning line SnB are both in a high level state to control the first transistor T1, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 to be triggered and turned on to light up the light-emitting device D1.

[0083] It is worth noting that the t0 stage may specifically correspond to a light-emitting stage in a display cycle of the light-emitting device D1 ; and the emission signal line EM may specifically correspond to a scan line.

[0084] Similarly, in the compensation stage, that is, in the t1 stage, the compensation stage is multiplexed as the initialization stage, and the fourth scanning signal provided by the fourth scanning line RE, the first scanning signal provided by the first scanning line EMB, and the third scanning signal provided by the third scanning line SnB are all in a high-level state to control the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 to be triggered to turn on, and the anode of the time point G, the point S, and the light-emitting device D1 are reset, and the first capacitor Cst1 and the second capacitor Cst2 are also reset to clear the signal residue that may exist in the previous display cycle.

[0085] At this time, the current at point D will flow through the first transistor T1, the seventh transistor T7, and the third transistor T3 in sequence to reach the first reference voltage line VREF1, so that the voltage at point G gradually drops to Vref1+Vth, and the anode potential of the light-emitting device D1 corresponds to Vref1, so that the threshold voltage of the driving module is written into the first capacitor Cst1, and the potential difference on the second capacitor Cst2 is (Vr1+Vth)-VDD.

[0086] In the data writing stage, that is, in the t2 stage, the second scanning signal provided by the second scanning line Sn and the first scanning signal provided by the first scanning line EMB are both in a high level state to control the second transistor T2 and the fourth transistor T4 to trigger conduction. At this time, the voltage at point S will jump from Vref1 to Vdata. Based on the law of conservation of charge, the voltage on the first capacitor Cst1 can also be obtained as (Cst2+Cgs)*(Vref1-Vdata) / (Cst1+Cst2+Cgs)+Vth.

[0087] During the light-emitting phase of the display cycle, i.e., phase t3, the emission signal provided by the emission signal line EM and the third scan signal provided by the third scan line SnB are both in a high-level state, thereby controlling the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 to be triggered and turned on, thereby lighting the light-emitting device D1. Furthermore, the lighting current of the light-emitting device D1 is controlled by the Vgs-Vth corresponding to the first transistor T1. The Vgs-Vth corresponds to a function of (Cst2+Cgs)*(Vref1-Vdata) / (Cst1+Cst2+Cgs). This function does not include VDD, VSS, or Vth. Therefore, the pixel circuit has a good compensation effect for the IR drop and Vth of VDD and VSS.

[0088] Through the above scheme, the pixel circuit 20 can effectively enhance the compensation effect on the threshold voltage Vth of the first transistor T1 and significantly improve the ghosting problem; it also compensates for the IR Drop of VDD and VSS to achieve higher uniformity of brightness; and the applicable refresh frequency range is also larger.

[0089] This application also provides a driving method for a pixel circuit, see Figure 7 , Figure 7 This is a flow chart of an embodiment of a driving method for a pixel circuit of the present application. Specifically, it may include the following steps:

[0090] S31: In the data writing phase, the data writing module couples the data voltage on the data line to the gate node via the source node, the parasitic capacitance of the driving module, and the voltage division of the first storage module.

[0091] It is understandable that the driving method in this embodiment is specifically that the driving circuit in the corresponding display panel is Figure 2 For details on the method of driving the pixel circuit shown in FIG. Figure 2 and Figure 6 And the related text content will not be repeated here.

[0092] Specifically, if Figure 4As shown, in the data writing stage, that is, in the t2 stage, the second scanning signal corresponding to the second scanning line and the first scanning signal corresponding to the first scanning line are both in a high-level state, so as to control the data writing module to be turned on, so that the data writing module writes the data voltage provided on the data line to the second end of the first storage module, that is, the gate node of the driving module, so as to couple the written data voltage to the gate node of the driving module via the source node and through the parasitic capacitance of the driving module and the voltage divider of the first storage module.

[0093] S32: In the light emitting stage, the driving module makes the potential of the gate node correlate with the data voltage, and the potential of the source node is the data voltage.

[0094] Specifically, in the light-emitting stage within the display cycle, that is, in the t3 stage, the emission signal provided by the emission signal line and the third scanning signal provided by the third scanning line are both in a high-level state, so as to be able to control the first light-emitting control module to be turned on, so that the driving module drives the light-emitting module to emit light according to the voltage of the gate node and the source node.

[0095] The potential of the gate node is specifically related to the data voltage, and the potential of the source node is the data voltage.

[0096] Furthermore, in one embodiment, the driving module further has a drain node, which is coupled to the first voltage source. Before the above S31, the process may further include: in the compensation phase, the gate node and the drain node are turned on so that the threshold voltage of the driving module is written into the first storage module.

[0097] Among them, such as Figure 4 As shown, in the compensation stage, that is, in the t1 stage, the fourth scanning signal corresponding to the fourth scanning line, the first scanning signal corresponding to the first scanning line, and the third scanning signal corresponding to the third scanning line are all in a high-level state, so as to be able to control the first initialization module and the compensation module to be triggered and turned on, so that the first initialization module writes the first reference voltage into the first end of the first storage module and the light-emitting module, and the gate node and the drain node of the driving module are turned on, so that the threshold voltage of the driving module is written into the first storage module to compensate for the threshold voltage of the driving module.

[0098] Preferably, the compensation phase does not overlap with the data writing phase, so as to ensure consistency of the compensation degree of each grayscale of the pixel circuit, thereby ensuring uniform brightness of the display panel and good display effect.

[0099] Preferably, the compensation phase is performed before the data writing phase.

[0100] It is understandable that in some other embodiments, the pixel circuit further includes some other more specific features to enable corresponding implementation of some other more specific driving methods. For details, please refer to Figure 2-Figure 6 And the related text content will not be repeated here.

[0101] The beneficial effects of the present application are as follows: different from the prior art, the driving module in the pixel circuit provided by the present application has a gate node and a source node, the first storage module is coupled between the gate node and the source node, the data writing module is coupled between the data line and the source node, and is configured to, in the data writing stage, allow the data voltage on the data line to be coupled to the gate node via the source node and through the parasitic capacitance of the driving module and the voltage division of the first storage module, so that in the light-emitting stage, the potential of the gate node is related to the data voltage, and the potential of the source node is the data voltage, and is not related to the power supply of the pixel circuit, thereby effectively avoiding the unstable state such as the voltage drop of the power supply affecting the brightness uniformity and display effect of the display panel.

[0102] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A pixel circuit, characterized in that: At least: A driving module having a gate node, a drain node and a source node, wherein the drain node is coupled to a first voltage source, and the source node is coupled to an anode of the light emitting module; a first storage module coupled between the gate node and the source node; a data writing module coupled between the data line and the source node and configured to, during a data writing phase, couple the data voltage on the data line to the gate node via the source node and through the parasitic capacitance between the gate node and the source node in the driving module and the voltage division of the first storage module, so that, during a light emitting phase, the potential of the gate node is correlated with the data voltage and the potential of the source node is the data voltage; a compensation module, coupled between the gate node and the drain node, and configured to conduct the gate node and the drain node during a compensation phase so that the threshold voltage of the driving module is written into the first storage module; a first initialization module coupled between a first reference voltage line and the source node, wherein the compensation phase is multiplexed into an initialization phase, and the first initialization module is configured to write a first reference voltage on the first reference voltage line into the source node and the anode during the initialization phase; a second storage module coupled between the first voltage source and the drain node; The compensation phase does not overlap with the data writing phase, and the compensation phase is performed before the data writing phase. In the light-emitting phase, the potential of the gate node is related to the data voltage and the threshold voltage, and the potential of the source node is the data voltage.

2. The pixel circuit according to claim 1, wherein: In the data writing phase, the parasitic capacitor and the first storage module perform the voltage division based on a voltage difference between the data voltage and the first reference voltage.

3. The pixel circuit according to claim 1, wherein: The data writing module is further configured to couple the data voltage to the gate node via the source node and through voltage division of the parasitic capacitance, the first storage module, and the second storage module during the data writing phase.

4. The pixel circuit according to claim 3, wherein: The source node is coupled to the anode of the light emitting module, wherein: In the light-emitting stage, the potential difference between the gate node and the source node satisfies Formula 1, and the current value of the driving current in the light-emitting module is a function of the difference between Formula 1 and the threshold voltage; Formula 1: (Vref1-Vdata)(Cst2+Cgs) / (Cst1+Cst2+Cgs)+Vth; Wherein, Vref1 represents the first reference voltage, Vdata represents the data voltage, Cst1 represents the capacitance value of the first storage module, Cst2 represents the capacitance value of the second storage module, Cgs represents the parasitic capacitance, and Vth represents the threshold voltage.

5. The pixel circuit according to claim 1, wherein: The driving module further has a drain node, and the pixel circuit further includes a first light-emitting control module, wherein the first light-emitting control module is coupled between a first voltage source and the drain node, and the source node is coupled to an anode of the light-emitting module, wherein: The first light-emitting control module is configured to, during the light-emitting phase, enable the first voltage source to drive the driving module via the drain node, so that the driving module is controlled by the potential of the gate node to generate a corresponding driving current, and the driving current is transmitted to the light-emitting module via the anode.

6. The pixel circuit according to claim 1, wherein: The pixel circuit further includes an isolation module coupled between the source node and the anode; wherein the isolation module is configured to prevent the written data voltage from affecting the driving module during the data writing phase.

7. The pixel circuit according to claim 6, wherein: The pixel circuit also includes a second light-emitting control module, which is coupled between the source node and the anode, or the second light-emitting control module is coupled between the isolation module and the anode; wherein the second light-emitting control module is configured to prevent the written data voltage from affecting the light-emitting module during the data writing phase.

8. The pixel circuit according to claim 1, wherein: The pixel circuit also includes a second initialization module, which is coupled between the second reference voltage line and the anode; the compensation phase is multiplexed as an initialization phase, and the second initialization module is configured to write the second reference voltage on the second reference voltage line into the anode during the initialization phase.

9. A method for driving a pixel circuit, characterized in that: As used in the pixel circuit according to any one of claims 1 to 8, comprising: In the data writing phase, the data writing module couples the data voltage on the data line to the gate node via the source node and through the parasitic capacitance of the driving module and the voltage division of the first storage module; In the light emitting stage, the driving module makes the potential of the gate node correlate with the data voltage, and the potential of the source node is the data voltage.

10. The driving method according to claim 9, wherein: The driving method further includes: In the compensation phase, the gate node and the drain node are turned on, so that the threshold voltage of the driving module is written into the first storage module.

11. The driving method according to claim 10, wherein: The compensation phase does not overlap with the data writing phase.

12. The driving method according to claim 10, wherein: The compensation phase is performed before the data writing phase.

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